; -------------------------------------------------------------------------------- ; @Title: AM263x On-Chip Peripherals ; @Props: Released ; @Author: KRZ ; @Changelog: 2025-02-14 KRZ ; @Manufacturer: TI - Texas Instruments ; @Doc: Generated (TRACE32, build: 176904.), based on: AM263x.xml (CCS 20.0.0) ; @Core: Cortex-R5F, Cortex-M4 ; @Chip: AM2631, AM2632, AM2634 ; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: peram263x.per 19100 2025-02-24 14:34:34Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 sif (CORENAME()=="CORTEXR5F") tree "Core Registers (Cortex-R5F)" AUTOINDENT.PUSH AUTOINDENT.OFF width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup.long c15:0x00++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" textline " " bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup.long c15:0x400--0x400 line.long 0x0 "MPUIR,MPU type register" hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions" bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated" rgroup.long c15:0x500++0x00 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system" textline " " hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2" hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1" hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0" textline " " rgroup.long c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " SL ,Number of Shareability levels implemented" "1,?..." bitfld.long 0x00 8.--11. " OS ,Outermost Shareability domain support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c15:0x020++0x00 line.long 0x00 "ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x120++0x00 line.long 0x00 "ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x220++0x00 line.long 0x00 "ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x320++0x00 line.long 0x00 "ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x420++0x00 line.long 0x00 "ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)" rgroup.long c15:0x0620++0x00 line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)" rgroup.long c15:0x0720++0x00 line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)" rgroup.long c15:0x010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." textline " " rgroup.long c15:0x210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c15:0x310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c15:0x02f++0x00 line.long 0x00 "BO1R,Build Options 1 Register" hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR ,Default high address for the TCM" bitfld.long 0x00 1. " FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented" textline " " bitfld.long 0x00 0. " PP_BUS_ECC ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented" group.long c15:0x12f++0x00 line.long 0x00 "BO2R,Build Options 2 Register" bitfld.long 0x00 31. " NUM_CPU ,Number of CPUs" "1,2" bitfld.long 0x00 30. " LOCK_STEP ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included" textline " " bitfld.long 0x00 29. " NO_ICACHE ,Indicate whether the CPU contains instruction cache" "Yes,No" bitfld.long 0x00 28. " NO_DCACHE ,Indicate whether the CPU contains data cache" "Yes,No" textline " " bitfld.long 0x00 26.--27. " ATCM_ES ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection" bitfld.long 0x00 23.--25. " BTCM_ES ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..." textline " " bitfld.long 0x00 23. " NO_IE ,Indicate whether the processor supports big-endian instructions" "Yes,No" bitfld.long 0x00 22. " NO_FPU ,Indicate whether the CPU contains a floating point unit" "Yes,No" textline " " bitfld.long 0x00 20.--21. " MPU_REGIONS ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions" bitfld.long 0x00 17.--19. " BREAK_POINTS ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 14.--16. " WATCH_POINTS ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " NO_A_TCM_INF ,Indicate whether the CPUs contain ATCM ports" "Yes,No" textline " " bitfld.long 0x00 12. " NO_B0_TCM_INF ,Indicate whether the CPUs contain B0TCM ports" "Yes,No" bitfld.long 0x00 11. " NO_B1_TCM_INF ,Indicate whether the CPUs contain B1TCM ports" "Yes,No" textline " " bitfld.long 0x00 10. " TCMBUSPARITY ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes" bitfld.long 0x00 9. " NO_SLAVE ,Indicate whether the CPU contains an AXI slave port" "Yes,No" textline " " bitfld.long 0x00 7.--8. " ICACHE_ES ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC" bitfld.long 0x00 5.--6. " DCACHE_ES ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..." textline " " bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No" bitfld.long 0x00 3. " AXI_BUS_ECC ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes" textline " " bitfld.long 0x00 2. " SL ,Indicate whether the processor has been built with split/lock logic" "No,Yes" bitfld.long 0x00 1. " AHB_PP ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes" textline " " bitfld.long 0x00 0. " MICRO_SCU ,Indicate whether the processor contain an ACP interface" "No,Yes" group.long c15:0x72f++0x00 line.long 0x00 "POR,Pin Options Register" bitfld.long 0x00 4. " DBGNOCLKSTOP ,Value of the DBGNOCLKSTOP pin" "Low,High" bitfld.long 0x00 3. " INTSYNCEN ,Value of the INTSYNCEN pin" "Low,High" textline " " bitfld.long 0x00 2. " IRQADDRVSYNCEN ,Value of the IRQADDRVSYNCEN pin" "Low,High" bitfld.long 0x00 1. " SLBTCMSB ,Value of the SLBTCMSBm pin" "Low,High" textline " " bitfld.long 0x00 0. " PARITYLEVEL ,Value of the PARITYLEVEL pin" "Low,High" tree.end width 0x8 tree "System Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x101++0x00 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable" bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable" bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable" bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" textline " " bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable" bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable" textline " " bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Enable,Disable" bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Enable,Disable" bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable" textline " " bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable" bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable" bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..." textline " " bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable" bitfld.long 0x00 13. " DLFO ,Disable linefill optimization in the AXI master" "Enable,Disable" bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable" textline " " bitfld.long 0x00 11. " DNCH ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable" bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced" bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced" textline " " bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced" bitfld.long 0x00 7. " SMOV ,sMOV disabled" "Enabled,Disabled" bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable" textline " " bitfld.long 0x00 3.--5. " CEC ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..." textline " " bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable" bitfld.long 0x00 1. " B0TCMECEN ,B0TCM external error enable" "Disable,Enable" bitfld.long 0x00 0. " ATCMECEN ,ATCM external error enable" "Disable,Enable" textline " " group.long c15:0x0f++0x00 line.long 0x00 "SACTLR,Secondary Auxiliary Control Register" bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable" bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable" bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable" bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable" bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable" textline " " bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable" bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate" bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate" bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate" bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate" bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable" bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable" textline " " bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable" bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable" textline " " group.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes" textline " " bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group.long c15:0x000b++0x00 line.long 0x00 "SPCR,Slave Port Control Register" bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only" bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled" tree.end width 0x8 tree "MPU Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x05++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x15++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x06++0x00 line.long 0x00 "DFAR,Data Fault Address Register" textline " " group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" textline " " group.long c15:0x0016++0x00 line.long 0x00 "RBAR,Region Base Address Register" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group.long c15:0x0216++0x00 line.long 0x00 "RSER,Region Size and Enable Register" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group.long c15:0x0416++0x00 line.long 0x00 "RACR,Region Access Control Register" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" group.long c15:0x0026++0x00 line.long 0x00 "MRNR,Memory Region Number Register" bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " group.long c15:0x010d++0x00 line.long 0x00 "CIDR,Context ID Register" group.long c15:0x20d++0x00 line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register" group.long c15:0x30d++0x00 line.long 0x00 "TIDRURO,User read only Thread and Process ID Register" group.long c15:0x40d++0x00 line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register" width 0x08 tree "MPU regions" group c15:0x0016++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RBAR0,Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RSER0,Region Size and Enable Register 0" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RACR0,Region Access Control Register 0" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RBAR1,Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RSER1,Region Size and Enable Register 1" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RACR1,Region Access Control Register 1" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RBAR2,Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RSER2,Region Size and Enable Register 2" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RACR2,Region Access Control Register 2" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RBAR3,Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RSER3,Region Size and Enable Register 3" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RACR3,Region Access Control Register 3" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RBAR4,Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RSER4,Region Size and Enable Register 4" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RACR4,Region Access Control Register 4" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RBAR5,Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RSER5,Region Size and Enable Register 5" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RACR5,Region Access Control Register 5" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RBAR6,Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RSER6,Region Size and Enable Register 6" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RACR6,Region Access Control Register 6" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RBAR7,Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RSER7,Region Size and Enable Register 7" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RACR7,Region Access Control Register 7" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RBAR8,Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RSER8,Region Size and Enable Register 8" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RACR8,Region Access Control Register 8" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RBAR9,Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RSER9,Region Size and Enable Register 9" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RACR9,Region Access Control Register 9" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RBAR10,Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RSER10,Region Size and Enable Register 10" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RACR10,Region Access Control Register 10" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RBAR11,Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RSER11,Region Size and Enable Register 11" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RACR11,Region Access Control Register 11" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RBAR12,Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RSER12,Region Size and Enable Register 12" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RACR12,Region Access Control Register 12" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RBAR13,Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RSER13,Region Size and Enable Register 13" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RACR13,Region Access Control Register 13" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RBAR14,Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RSER14,Region Size and Enable Register 14" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RACR14,Region Access Control Register 14" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RBAR15,Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RSER15,Region Size and Enable Register 15" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RACR15,Region Access Control Register 15" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " tree.end tree.end width 0x9 tree "TCM Control and Configuration" rgroup.long c15:0x200++0x00 line.long 0x00 "TCMTR,TCM Type Register" bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7" group.long c15:0x019++0x00 line.long 0x00 "BTCMRR,BTCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" group.long c15:0x119++0x00 line.long 0x00 "ATCMRR,ATCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" rgroup.long c15:0x29++0x00 line.long 0x00 "TCMSEL,TCM Selection Register" textline " " group.long c15:0x10f++0x00 line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x20f++0x00 line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x30f++0x00 line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" tree.end width 0xC tree "Cache Control and Configuration" rgroup.long c15:0x1100++0x00 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7" rgroup.long c15:0x1700++0x00 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets" hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity" textline " " bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7" group.long c15:0x2000++0x00 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Cache level to select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " IND ,Instruction or data or unified cache to use" "Data/unified,Instruction" group.long c15:0x03f++0x00 line.long 0x00 "CFLR,Correctable Fault Location Register" bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred" bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP" group.long c15:0x5f++0x00 line.long 0x00 "IADCR,Invalidate All Data Cache Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" group.long c15:0xef++0x00 line.long 0x00 "CSOR,Cache Size Override Register" bitfld.long 0x00 4.--7. " Dcache ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" bitfld.long 0x00 0.--3. " Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" tree.end width 12. tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x00 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable PMCCNTR when prohibited" "No,Yes" textline " " bitfld.long 0x00 4. " X ,Export enable" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock counter reset" "No action,Reset" bitfld.long 0x00 1. " P ,Event counter reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Enable" "Disabled,Enabled" group.long c15:0x1c9++0x00 line.long 0x00 "PMCNTENSET,Count Enable Set Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x0 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x0 "PMOVSR,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x0 "PMSWINC,Software Increment Register" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Event Type Selection Register" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected" group.long c15:0x02d9++0x00 line.long 0x00 "PMXEVCNTR,Event Count Register" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Counter Selection Register" bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Cycle Count Register" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "ESR0,Event Selection Register 0" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "PMCR0,Performance Monitor Count Register 0" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "ESR1,Event Selection Register 1" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "PMCR1,Performance Monitor Count Register 1" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "ESR2,Event Selection Register 2" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "PMCR2,Performance Monitor Count Register 2" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,User Enable Register" bitfld.long 0x00 0. " EN ,User mode access to performance monitor and validation registers" "Not allowed,Allowed" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Interrupt Enable Set Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" tree "Validation Registers" group.long c15:0x01f++0x00 line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x11f++0x00 line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x21f++0x00 line.long 0x00 "RESR,nVAL Reset Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x31f++0x00 line.long 0x00 "RESR,VAL Debug Request Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" group.long c15:0x41f++0x00 line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x51f++0x00 line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x61f++0x00 line.long 0x00 "RECR,nVAL Reset Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x71f++0x00 line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" tree.end tree.end width 11. width 18. tree "Debug Registers" tree "Processor Identifier Registers" rgroup.long c14:832.++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup.long c14:833.++0x00 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup.long c14:834.++0x00 line.long 0x00 "TCMTR,TCM Type Register" group.long c14:835.++0x00 line.long 0x00 "AMIDR,Alias of MIDR" rgroup.long c14:836.++0x00 line.long 0x00 "MPUTR,MPU Type Register" rgroup.long c14:837.++0x00 line.long 0x00 "MPIDR,Multiprocessor Affinity Register" group.long c14:838.++0x00 line.long 0x00 "AMIDR0,Alias of MIDR" group.long c14:839.++0x00 line.long 0x00 "AMIDR1,Alias of MIDR" rgroup.long c14:840.++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c14:841.++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c14:842.++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c14:843.++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c14:844.++0x00 line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c14:845.++0x00 line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c14:846.++0x00 line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c14:847.++0x00 line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c14:848.++0x00 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:849.++0x00 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c14:850.++0x00 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:851.++0x00 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c14:852.++0x00 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c14:853.++0x00 line.long 0x00 "ID_ISAR5,ISA Feature Register 5" tree.end width 15. tree "Coresight Management Registers" group.long c14:960.++0x00 line.long 0x00 "DBGITCTRL,Integration Mode Control Register" bitfld.long 0x00 0. " INTMODE ,Processor integration mode" "Normal,Integration" group.long c14:1000.++0x00 line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register" hexmask.long.byte 0x00 0.--7. 1. " CTS ,Claim tag set" group.long c14:1001.++0x00 line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register" hexmask.long.byte 0x00 0.--7. 1. " CTC ,Claim tag clear" wgroup.long c14:1004.++0x00 line.long 0x00 "DBGLAR,Lock Access Register" rgroup.long c14:1005.++0x00 line.long 0x00 "DBGLSR,Lock Status Register" bitfld.long 0x00 2. " 32BA ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes" textline " " bitfld.long 0x00 1. " LB ,Lock bit" "Not locked,Locked" bitfld.long 0x00 0. " LIB ,Lock implemented bit" "Not locked,Locked" rgroup.long c14:1006.++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register" bitfld.long 0x00 7. " SNDFI ,Secure non-invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 6. " SNDFE ,Secure non-invasive debug features enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SIDFI ,Secure invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 4. " SIDFE ,Secure invasive debug features enabled" "Disabled,Enabled" rgroup.long c14:1011.++0x00 line.long 0x00 "DBGDEVTYPE,Device Type Register" hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype" hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class" tree.end textline " " width 12. rgroup.long c14:0.++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version" textline " " bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High" bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Low,High" textline " " bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Low,High" bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Low,High" textline " " hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number" hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number" group.long c14:34.++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" textline " " bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" group.long c14:0x7++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 7. " FIQVCE_S ,FIQ vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IRQVCE_S ,IRQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. " DAVCE_S ,Data Abort vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PAVCE_S ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 2. " SVCVCE_S ,SVC vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " UIVCE_S ,Undefined instruction vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 0. " RVCE ,Reset vector catch enable" "Disabled,Enabled" hgroup.long c14:32.++0x0 hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register" in group.long c14:35.++0x00 line.long 0x0 "DTRTX,Host -> Target Data Transfer Register" hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data" group.long c14:10.++0x0 line.long 0x00 "DBGDSCCR,Debug State Cache Control Register" bitfld.long 0x00 2. " NWT ,Write through disable" "No,Yes" bitfld.long 0x00 1. " NIL ,L1 instruction cache line-fills disable" "No,Yes" textline " " bitfld.long 0x00 0. " NDL ,L1 data cache line-fills disable" "No,Yes" wgroup.long c14:33.++0x0 line.long 0x00 "DBGITR,Instruction Transfer Register" wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 4. " CMR ,Cancel memory requests" "Not cancel,Cancel" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" textline " " bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart" textline " " bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt" textline " " rgroup.long c14:193.++0x0 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented" group.long c14:196.++0x0 line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register" bitfld.long 0x00 2. " HCWR ,Hold core warm reset" "Not held,Held" textline " " bitfld.long 0x00 1. " CWRR ,Reset reguest" "Not requested,Requested" bitfld.long 0x00 0. " CORENPDRQ ,Core no powerdown request" "Power-down,Emulate" rgroup.long c14:197.++0x0 line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register" bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset" bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset" textline " " bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset" bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up" tree.end width 7. tree "Breakpoint Registers" group.long c14:64.++0x0 line.long 0x00 "BVR0,Breakpoint Value 0 Register" hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0" group.long c14:80.++0x0 line.long 0x00 "BCR0,Breakpoint Control 0 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:65.++0x0 line.long 0x00 "BVR1,Breakpoint Value 1 Register" hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1" group.long c14:81.++0x0 line.long 0x00 "BCR1,Breakpoint Control 1 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:66.++0x0 line.long 0x00 "BVR2,Breakpoint Value 2 Register" hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2" group.long c14:82.++0x0 line.long 0x00 "BCR2,Breakpoint Control 2 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:67.++0x0 line.long 0x00 "BVR3,Breakpoint Value 3 Register" hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3" group.long c14:83.++0x0 line.long 0x00 "BCR3,Breakpoint Control 3 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:68.++0x0 line.long 0x00 "BVR4,Breakpoint Value 4 Register" hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4" group.long c14:84.++0x0 line.long 0x00 "BCR4,Breakpoint Control 4 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:69.++0x0 line.long 0x00 "BVR5,Breakpoint Value 5 Register" hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5" group.long c14:85.++0x0 line.long 0x00 "BCR5,Breakpoint Control 5 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:70.++0x0 line.long 0x00 "BVR6,Breakpoint Value 6 Register" hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6" group.long c14:86.++0x0 line.long 0x00 "BCR6,Breakpoint Control 6 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:71.++0x0 line.long 0x00 "BVR7,Breakpoint Value 7 Register" hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7" group.long c14:87.++0x0 line.long 0x00 "BCR7,Breakpoint Control 7 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end tree "Watchpoint Control Registers" group.long c14:96.++0x0 line.long 0x00 "WVR0,Watchpoint Value 0 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:112.++0x0 line.long 0x00 "WCR0,Watchpoint Control 0 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:97.++0x0 line.long 0x00 "WVR1,Watchpoint Value 1 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:113.++0x0 line.long 0x00 "WCR1,Watchpoint Control 1 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:98.++0x0 line.long 0x00 "WVR2,Watchpoint Value 2 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:114.++0x0 line.long 0x00 "WCR2,Watchpoint Control 2 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:99.++0x0 line.long 0x00 "WVR3,Watchpoint Value 3 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:115.++0x0 line.long 0x00 "WCR3,Watchpoint Control 3 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:100.++0x0 line.long 0x00 "WVR4,Watchpoint Value 4 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:116.++0x0 line.long 0x00 "WCR4,Watchpoint Control 4 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:101.++0x0 line.long 0x00 "WVR5,Watchpoint Value 5 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:117.++0x0 line.long 0x00 "WCR5,Watchpoint Control 5 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:102.++0x0 line.long 0x00 "WVR6,Watchpoint Value 6 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:118.++0x0 line.long 0x00 "WCR6,Watchpoint Control 6 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:103.++0x0 line.long 0x00 "WVR7,Watchpoint Value 7 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:119.++0x0 line.long 0x00 "WCR7,Watchpoint Control 7 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:6.++0x0 line.long 0x00 "WFAR ,Watchpoint Fault Address Register" hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction" tree.end width 11. AUTOINDENT.POP tree.end endif sif (CORENAME()=="CORTEXM4") tree.close "Core Registers (Cortex-M4)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited" bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15" bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,ARMv7-M" newline abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC24=Cortex-M4" bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif tree "CONTROLSS" base ad:0x0 tree "ADC" tree "ADC0_CFG" base ad:0x502C0000 group.word 0x0++0x5 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCCTL1" rbitfld.word 0x0 13. "ADCBSY,ADC Busy. Set when ADC SOC is generated cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy.." "0,1" hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel. Set when an ADC Start of Conversion (SOC) is generated. When ADCBSY=0: holds the value of the last converted SOC When ADCBSY=1: reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC.." bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down (active low). This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up" "0,1" bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion (at the end of the acquisition window) plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse.." "0,1" line.word 0x2 "CONTROLSS_ADC0_CFG_ADCCTL2" bitfld.word 0x2 7. "SIGNALMODE,SOC Signaling Mode. Selects the input mode of the converter. Use the AdcSetMode function to change the signal mode. 0 Single-ended 1 Differential" "0,1" bitfld.word 0x2 6. "RESOLUTION,SOC Conversion Resolution. Selects the resolution of the converter. Use the AdcSetMode function to change the resolution. 0 12-bit resolution 1 16-bit resolution" "0,1" hexmask.word.byte 0x2 0.--3. 1. "PRESCALE,ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 Invalid 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock /.." line.word 0x4 "CONTROLSS_ADC0_CFG_ADCBURSTCTL" bitfld.word 0x4 15. "BURSTEN,SOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation. 0 Burst mode is disabled. 1 Burst mode is enabled." "0,1" hexmask.word.byte 0x4 8.--11. 1. "BURSTSIZE,SOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer which is advanced as each SOC is converted. 0h 1 SOC.." hexmask.word.byte 0x4 0.--6. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence. 00h - 7Fh: See AM602 spec. for trigger defintion" rgroup.word 0x6++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCINTFLG" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" group.word 0x8++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCINTFLGCLR" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT4 and ADCINT4RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT3 and ADCINT3RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT2 and ADCINT2RESULT flags in the ADCINTFLG register. . If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT1 and ADCINT1RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" rgroup.word 0xA++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCINTOVF" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" group.word 0xC++0xB line.word 0x0 "CONTROLSS_ADC0_CFG_ADCINTOVFCLR" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" line.word 0x2 "CONTROLSS_ADC0_CFG_ADCINTSEL1N2" bitfld.word 0x2 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode 0 No further ADCINT2 pulses are generated until ADCINT2 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" bitfld.word 0x2 13. "INT2E,ADCINT2 Interrupt Enable 0 ADCINT2 is disabled 1 ADCINT2 is enabled" "0,1" hexmask.word.byte 0x2 8.--11. 1. "INT2SEL,ADCINT2 EOC Source Select 0h EOC0 is trigger for ADCINT2 1h EOC1 is trigger for ADCINT2 2h EOC2 is trigger for ADCINT2 3h EOC3 is trigger for ADCINT2 4h EOC4 is trigger for ADCINT2 5h EOC5 is trigger for ADCINT2 6h EOC6 is.." bitfld.word 0x2 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode 0 No further ADCINT1 pulses are generated until ADCINT1 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 5. "INT1E,ADCINT1 Interrupt Enable 0 ADCINT1 is disabled 1 ADCINT1 is enabled" "0,1" hexmask.word.byte 0x2 0.--3. 1. "INT1SEL,ADCINT1 EOC Source Select 0h EOC0 is trigger for ADCINT1 1h EOC1 is trigger for ADCINT1 2h EOC2 is trigger for ADCINT1 3h EOC3 is trigger for ADCINT1 4h EOC4 is trigger for ADCINT1 5h EOC5 is trigger for ADCINT1 6h EOC6 is.." line.word 0x4 "CONTROLSS_ADC0_CFG_ADCINTSEL3N4" bitfld.word 0x4 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode 0 No further ADCINT4 pulses are generated until ADCINT4 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" bitfld.word 0x4 13. "INT4E,ADCINT4 Interrupt Enable 0 ADCINT4 is disabled 1 ADCINT4 is enabled" "0,1" hexmask.word.byte 0x4 8.--11. 1. "INT4SEL,ADCINT4 EOC Source Select 0h EOC0 is trigger for ADCINT4 1h EOC1 is trigger for ADCINT4 2h EOC2 is trigger for ADCINT4 3h EOC3 is trigger for ADCINT4 4h EOC4 is trigger for ADCINT4 5h EOC5 is trigger for ADCINT4 6h EOC6 is.." bitfld.word 0x4 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode 0 No further ADCINT3 pulses are generated until ADCINT3 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 5. "INT3E,ADCINT3 Interrupt Enable 0 ADCINT3 is disabled 1 ADCINT3 is enabled" "0,1" hexmask.word.byte 0x4 0.--3. 1. "INT3SEL,ADCINT3 EOC Source Select 0h EOC0 is trigger for ADCINT3 1h EOC1 is trigger for ADCINT3 2h EOC2 is trigger for ADCINT3 3h EOC3 is trigger for ADCINT3 4h EOC4 is trigger for ADCINT3 5h EOC5 is trigger for ADCINT3 6h EOC6 is.." line.word 0x6 "CONTROLSS_ADC0_CFG_ADCSOCPRICTL" hexmask.word.byte 0x6 5.--9. 1. "RRPOINTER,Round Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions. 00h SOC0 was last round robin SOC to convert SOC1 is highest round robin priority. 01h.." hexmask.word.byte 0x6 0.--4. 1. "SOCPRIORITY,SOC Priority Determines the cutoff point for priority mode and round robin arbitration for SOCx 00h SOC priority is handled in round robin mode for all channels. 01h SOC0 is high priority rest of channels are in round robin mode. 02h.." line.word 0x8 "CONTROLSS_ADC0_CFG_ADCINTSOCSEL1" bitfld.word 0x8 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0.." "0,1,2,3" line.word 0xA "CONTROLSS_ADC0_CFG_ADCINTSOCSEL2" bitfld.word 0xA 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC15. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC14. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC13. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC12. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC11. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC10. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0xA 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC0.." "0,1,2,3" rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCSOCFLG1" bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions. 0 No sample pending for SOC15. 1 Trigger has been received and sample is pending for SOC15. This bit will be automatically cleared when the SOC15 conversion is.." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions. 0 No sample pending for SOC14. 1 Trigger has been received and sample is pending for SOC14. This bit will be automatically cleared when the SOC14 conversion is.." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions. 0 No sample pending for SOC13. 1 Trigger has been received and sample is pending for SOC13. This bit will be automatically cleared when the SOC13 conversion is.." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions. 0 No sample pending for SOC12. 1 Trigger has been received and sample is pending for SOC12. This bit will be automatically cleared when the SOC12 conversion is.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions. 0 No sample pending for SOC11. 1 Trigger has been received and sample is pending for SOC11. This bit will be automatically cleared when the SOC11 conversion is.." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions. 0 No sample pending for SOC10. 1 Trigger has been received and sample is pending for SOC10. This bit will be automatically cleared when the SOC10 conversion is.." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions. 0 No sample pending for SOC9. 1 Trigger has been received and sample is pending for SOC9. This bit will be automatically cleared when the SOC9 conversion is started. If.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions. 0 No sample pending for SOC8. 1 Trigger has been received and sample is pending for SOC8. This bit will be automatically cleared when the SOC8 conversion is started. If.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions. 0 No sample pending for SOC7. 1 Trigger has been received and sample is pending for SOC7. This bit will be automatically cleared when the SOC7 conversion is started. If.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions. 0 No sample pending for SOC6. 1 Trigger has been received and sample is pending for SOC6. This bit will be automatically cleared when the SOC6 conversion is started. If.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions. 0 No sample pending for SOC5. 1 Trigger has been received and sample is pending for SOC5. This bit will be automatically cleared when the SOC5 conversion is started. If.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions. 0 No sample pending for SOC4. 1 Trigger has been received and sample is pending for SOC4. This bit will be automatically cleared when the SOC4 conversion is started. If.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions. 0 No sample pending for SOC3. 1 Trigger has been received and sample is pending for SOC3. This bit will be automatically cleared when the SOC3 conversion is started. If.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions. 0 No sample pending for SOC2. 1 Trigger has been received and sample is pending for SOC2. This bit will be automatically cleared when the SOC2 conversion is started. If.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions. 0 No sample pending for SOC1. 1 Trigger has been received and sample is pending for SOC1. This bit will be automatically cleared when the SOC1 conversion is started. If.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions. 0 No sample pending for SOC0. 1 Trigger has been received and sample is pending for SOC0. This bit will be automatically cleared when the SOC0 conversion is started. If.." "0,1" group.word 0x1A++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCSOCFRC1" bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" rgroup.word 0x1C++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCSOCOVF1" bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending. 0 No SOC15 event overflow. 1 SOC15 event overflow. An overflow condition does not stop SOC15.." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending. 0 No SOC14 event overflow. 1 SOC14 event overflow. An overflow condition does not stop SOC14.." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending. 0 No SOC13 event overflow. 1 SOC13 event overflow. An overflow condition does not stop SOC13.." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending. 0 No SOC12 event overflow. 1 SOC12 event overflow. An overflow condition does not stop SOC12.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending. 0 No SOC11 event overflow. 1 SOC11 event overflow. An overflow condition does not stop SOC11.." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending. 0 No SOC10 event overflow. 1 SOC10 event overflow. An overflow condition does not stop SOC10.." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending. 0 No SOC9 event overflow. 1 SOC9 event overflow. An overflow condition does not stop SOC9 events from.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending. 0 No SOC8 event overflow. 1 SOC8 event overflow. An overflow condition does not stop SOC8 events from.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending. 0 No SOC7 event overflow. 1 SOC7 event overflow. An overflow condition does not stop SOC7 events from.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending. 0 No SOC6 event overflow. 1 SOC6 event overflow. An overflow condition does not stop SOC6 events from.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending. 0 No SOC5 event overflow. 1 SOC5 event overflow. An overflow condition does not stop SOC5 events from.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending. 0 No SOC4 event overflow. 1 SOC4 event overflow. An overflow condition does not stop SOC4 events from.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending. 0 No SOC3 event overflow. 1 SOC3 event overflow. An overflow condition does not stop SOC3 events from.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending. 0 No SOC2 event overflow. 1 SOC2 event overflow. An overflow condition does not stop SOC2 events from.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending. 0 No SOC1 event overflow. 1 SOC1 event overflow. An overflow condition does not stop SOC1 events from.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending. 0 No SOC0 event overflow. 1 SOC0 event overflow. An overflow condition does not stop SOC0 events from.." "0,1" group.word 0x1E++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCSOCOVFCLR1" bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC15 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC14 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC13 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC12 overflow flag. If software tries to.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC11 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC10 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC9 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC8 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC7 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC6 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC5 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC4 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC3 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC2 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC1 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC0 overflow flag. If software tries to set.." "0,1" group.long 0x20++0x3F line.long 0x0 "CONTROLSS_ADC0_CFG_ADCSOC0CTL" hexmask.long.byte 0x0 20.--26. 1. "TRIGSEL,SOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x0 15.--19. 1. "CHSEL,SOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x4 "CONTROLSS_ADC0_CFG_ADCSOC1CTL" hexmask.long.byte 0x4 20.--26. 1. "TRIGSEL,SOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x4 15.--19. 1. "CHSEL,SOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x8 "CONTROLSS_ADC0_CFG_ADCSOC2CTL" hexmask.long.byte 0x8 20.--26. 1. "TRIGSEL,SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x8 15.--19. 1. "CHSEL,SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0xC "CONTROLSS_ADC0_CFG_ADCSOC3CTL" hexmask.long.byte 0xC 20.--26. 1. "TRIGSEL,SOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0xC 15.--19. 1. "CHSEL,SOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x10 "CONTROLSS_ADC0_CFG_ADCSOC4CTL" hexmask.long.byte 0x10 20.--26. 1. "TRIGSEL,SOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x10 15.--19. 1. "CHSEL,SOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x14 "CONTROLSS_ADC0_CFG_ADCSOC5CTL" hexmask.long.byte 0x14 20.--26. 1. "TRIGSEL,SOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x14 15.--19. 1. "CHSEL,SOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x18 "CONTROLSS_ADC0_CFG_ADCSOC6CTL" hexmask.long.byte 0x18 20.--26. 1. "TRIGSEL,SOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x18 15.--19. 1. "CHSEL,SOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x1C "CONTROLSS_ADC0_CFG_ADCSOC7CTL" hexmask.long.byte 0x1C 20.--26. 1. "TRIGSEL,SOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x1C 15.--19. 1. "CHSEL,SOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x20 "CONTROLSS_ADC0_CFG_ADCSOC8CTL" hexmask.long.byte 0x20 20.--26. 1. "TRIGSEL,SOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x20 15.--19. 1. "CHSEL,SOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x20 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x24 "CONTROLSS_ADC0_CFG_ADCSOC9CTL" hexmask.long.byte 0x24 20.--26. 1. "TRIGSEL,SOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x24 15.--19. 1. "CHSEL,SOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x24 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x28 "CONTROLSS_ADC0_CFG_ADCSOC10CTL" hexmask.long.byte 0x28 20.--26. 1. "TRIGSEL,SOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x28 15.--19. 1. "CHSEL,SOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x28 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x2C "CONTROLSS_ADC0_CFG_ADCSOC11CTL" hexmask.long.byte 0x2C 20.--26. 1. "TRIGSEL,SOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x2C 15.--19. 1. "CHSEL,SOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x2C 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x30 "CONTROLSS_ADC0_CFG_ADCSOC12CTL" hexmask.long.byte 0x30 20.--26. 1. "TRIGSEL,SOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x30 15.--19. 1. "CHSEL,SOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x30 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x34 "CONTROLSS_ADC0_CFG_ADCSOC13CTL" hexmask.long.byte 0x34 20.--26. 1. "TRIGSEL,SOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x34 15.--19. 1. "CHSEL,SOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x34 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x38 "CONTROLSS_ADC0_CFG_ADCSOC14CTL" hexmask.long.byte 0x38 20.--26. 1. "TRIGSEL,SOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x38 15.--19. 1. "CHSEL,SOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x38 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x3C "CONTROLSS_ADC0_CFG_ADCSOC15CTL" hexmask.long.byte 0x3C 20.--26. 1. "TRIGSEL,SOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x3C 15.--19. 1. "CHSEL,SOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x3C 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." rgroup.word 0x60++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCEVTSTAT" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" group.word 0x64++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCEVTCLR" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" group.word 0x68++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCEVTSEL" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" group.word 0x6C++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCEVTINTSEL" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" group.word 0x70++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCOSDETECT" bitfld.word 0x0 0.--2. "DETECTCFG,ADC Opens and Shorts Detect Configuration. This bit field defines the open/shorts detection circuit state. 0h Open/Shorts detection circuit is disabled. 1h Open/Shorts detection circuit is enabled at zero scale. 2h Open/Shorts.." "0,1,2,3,4,5,6,7" rgroup.word 0x72++0x3 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCCOUNTER" hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value. This bit field reflects the status of the free running ADC counter." line.word 0x2 "CONTROLSS_ADC0_CFG_ADCREV" hexmask.word.byte 0x2 8.--15. 1. "REV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h." hexmask.word.byte 0x2 0.--7. 1. "TYPE,ADC Type. Always set to 5 for this ADC." group.word 0x76++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCOFFTRIM" hexmask.word.byte 0x0 0.--7. 1. "OFFTRIM,ADC Offset Trim Adjusts the conversion results of the converter up or down to account for offset error in the ADC. A factory trim setting will be loaded during device boot. Offset can be corrected in the range of +7 to -8 LSBs. Value is.." group.long 0x7C++0x3 line.long 0x0 "CONTROLSS_ADC0_CFG_ADCCONFIG" hexmask.long 0x0 0.--31. 1. "CONFIG,ADC Configuration. This bit field is used for TI internal testing/debugging." group.word 0x80++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCPPB1CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 1 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0x82++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCPPB1STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x84++0x3 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCPPB1OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC0_CFG_ADCPPB1OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x88++0x7 line.long 0x0 "CONTROLSS_ADC0_CFG_ADCPPB1TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC0_CFG_ADCPPB1TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits 12:0.." group.word 0x90++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCPPB2CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 2 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0x92++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCPPB2STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x94++0x3 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCPPB2OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC0_CFG_ADCPPB2OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x98++0x7 line.long 0x0 "CONTROLSS_ADC0_CFG_ADCPPB2TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC0_CFG_ADCPPB2TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits 12:0.." group.word 0xA0++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCPPB3CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 3 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0xA2++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCPPB3STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xA4++0x3 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCPPB3OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC0_CFG_ADCPPB3OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xA8++0x7 line.long 0x0 "CONTROLSS_ADC0_CFG_ADCPPB3TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC0_CFG_ADCPPB3TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits 12:0.." group.word 0xB0++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCPPB4CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 4 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0xB2++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCPPB4STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xB4++0x3 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCPPB4OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 4 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC0_CFG_ADCPPB4OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xB8++0x7 line.long 0x0 "CONTROLSS_ADC0_CFG_ADCPPB4TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC0_CFG_ADCPPB4TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits 12:0.." group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_ADC0_CFG_ADCINTCYCLE" hexmask.word 0x0 0.--15. 1. "DELAY,ADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles for the interrupt to be generated." group.long 0xE0++0x17 line.long 0x0 "CONTROLSS_ADC0_CFG_ADCINLTRIM1" hexmask.long 0x0 0.--31. 1. "INLTRIM31TO0,ADC Linearity Trim Bits 31-0. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x4 "CONTROLSS_ADC0_CFG_ADCINLTRIM2" hexmask.long 0x4 0.--31. 1. "INLTRIM63TO32,ADC Linearity Trim Bits 63-32. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x8 "CONTROLSS_ADC0_CFG_ADCINLTRIM3" hexmask.long 0x8 0.--31. 1. "INLTRIM95TO64,ADC Linearity Trim Bits 95-64. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0xC "CONTROLSS_ADC0_CFG_ADCINLTRIM4" hexmask.long 0xC 0.--31. 1. "INLTRIM127TO96,ADC Linearity Trim Bits 127-96. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x10 "CONTROLSS_ADC0_CFG_ADCINLTRIM5" hexmask.long 0x10 0.--31. 1. "INLTRIM159TO128,ADC Linearity Trim Bits 159-128. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x14 "CONTROLSS_ADC0_CFG_ADCINLTRIM6" hexmask.long 0x14 0.--31. 1. "INLTRIM191TO160,ADC Linearity Trim Bits 191-160. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." group.long 0xFC++0x3 line.long 0x0 "CONTROLSS_ADC0_CFG_ADCINLTRIMCTL" hexmask.long.word 0x0 16.--31. 1. "KEY,ADC Linearity Trim Control Write Key. Any write to this register must contain the value 0xA5A5 in these bit locations. If a write request attempts to load any other value into these bits the write for the entire register is ignored. These bits.." hexmask.long.byte 0x0 1.--5. 1. "CALIBSTEP,ADC Linearity Calibration Step. Defines which of the 24 steps of calibration is to be executed. Never set this bit field while the ADC SELFTRIM is in progress. The R-M-W operation could unintentionally set the CALIBMODE bit again." bitfld.long 0x0 0. "CALIBMODE,ADC Linearity Calibration Mode." "0,1" tree.end tree "ADC0_RESULT" base ad:0x50100000 rgroup.word 0x0++0x1F line.word 0x0 "CONTROLSS_ADC0_RESULT_ADCRESULT0" hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result 0 16-bit ADC result. After the ADC completes a conversion of SOC0 the digital result is placed in this bit field." line.word 0x2 "CONTROLSS_ADC0_RESULT_ADCRESULT1" hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result 1 16-bit ADC result. After the ADC completes a conversion of SOC1 the digital result is placed in this bit field." line.word 0x4 "CONTROLSS_ADC0_RESULT_ADCRESULT2" hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result 2 16-bit ADC result. After the ADC completes a conversion of SOC2 the digital result is placed in this bit field." line.word 0x6 "CONTROLSS_ADC0_RESULT_ADCRESULT3" hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result 3 16-bit ADC result. After the ADC completes a conversion of SOC3 the digital result is placed in this bit field." line.word 0x8 "CONTROLSS_ADC0_RESULT_ADCRESULT4" hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result 4 16-bit ADC result. After the ADC completes a conversion of SOC4 the digital result is placed in this bit field." line.word 0xA "CONTROLSS_ADC0_RESULT_ADCRESULT5" hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result 5 16-bit ADC result. After the ADC completes a conversion of SOC5 the digital result is placed in this bit field." line.word 0xC "CONTROLSS_ADC0_RESULT_ADCRESULT6" hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result 6 16-bit ADC result. After the ADC completes a conversion of SOC6 the digital result is placed in this bit field." line.word 0xE "CONTROLSS_ADC0_RESULT_ADCRESULT7" hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result 7 16-bit ADC result. After the ADC completes a conversion of SOC7 the digital result is placed in this bit field." line.word 0x10 "CONTROLSS_ADC0_RESULT_ADCRESULT8" hexmask.word 0x10 0.--15. 1. "RESULT,ADC Result 8 16-bit ADC result. After the ADC completes a conversion of SOC8 the digital result is placed in this bit field." line.word 0x12 "CONTROLSS_ADC0_RESULT_ADCRESULT9" hexmask.word 0x12 0.--15. 1. "RESULT,ADC Result 9 16-bit ADC result. After the ADC completes a conversion of SOC9 the digital result is placed in this bit field." line.word 0x14 "CONTROLSS_ADC0_RESULT_ADCRESULT10" hexmask.word 0x14 0.--15. 1. "RESULT,ADC Result 10 16-bit ADC result. After the ADC completes a conversion of SOC10 the digital result is placed in this bit field." line.word 0x16 "CONTROLSS_ADC0_RESULT_ADCRESULT11" hexmask.word 0x16 0.--15. 1. "RESULT,ADC Result 11 16-bit ADC result. After the ADC completes a conversion of SOC11 the digital result is placed in this bit field." line.word 0x18 "CONTROLSS_ADC0_RESULT_ADCRESULT12" hexmask.word 0x18 0.--15. 1. "RESULT,ADC Result 12 16-bit ADC result. After the ADC completes a conversion of SOC12 the digital result is placed in this bit field." line.word 0x1A "CONTROLSS_ADC0_RESULT_ADCRESULT13" hexmask.word 0x1A 0.--15. 1. "RESULT,ADC Result 13 16-bit ADC result. After the ADC completes a conversion of SOC13 the digital result is placed in this bit field." line.word 0x1C "CONTROLSS_ADC0_RESULT_ADCRESULT14" hexmask.word 0x1C 0.--15. 1. "RESULT,ADC Result 14 16-bit ADC result. After the ADC completes a conversion of SOC14 the digital result is placed in this bit field." line.word 0x1E "CONTROLSS_ADC0_RESULT_ADCRESULT15" hexmask.word 0x1E 0.--15. 1. "RESULT,ADC Result 15 16-bit ADC result. After the ADC completes a conversion of SOC15 the digital result is placed in this bit field." rgroup.long 0x20++0xF line.long 0x0 "CONTROLSS_ADC0_RESULT_ADCPPB1RESULT" hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 1 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." line.long 0x4 "CONTROLSS_ADC0_RESULT_ADCPPB2RESULT" hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 2 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." line.long 0x8 "CONTROLSS_ADC0_RESULT_ADCPPB3RESULT" hexmask.long.word 0x8 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x8 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 3 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." line.long 0xC "CONTROLSS_ADC0_RESULT_ADCPPB4RESULT" hexmask.long.word 0xC 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0xC 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 4 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." tree.end tree "ADC1_CFG" base ad:0x502C1000 group.word 0x0++0x5 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCCTL1" rbitfld.word 0x0 13. "ADCBSY,ADC Busy. Set when ADC SOC is generated cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy.." "0,1" hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel. Set when an ADC Start of Conversion (SOC) is generated. When ADCBSY=0: holds the value of the last converted SOC When ADCBSY=1: reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC.." bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down (active low). This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up" "0,1" bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion (at the end of the acquisition window) plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse.." "0,1" line.word 0x2 "CONTROLSS_ADC1_CFG_ADCCTL2" bitfld.word 0x2 7. "SIGNALMODE,SOC Signaling Mode. Selects the input mode of the converter. Use the AdcSetMode function to change the signal mode. 0 Single-ended 1 Differential" "0,1" bitfld.word 0x2 6. "RESOLUTION,SOC Conversion Resolution. Selects the resolution of the converter. Use the AdcSetMode function to change the resolution. 0 12-bit resolution 1 16-bit resolution" "0,1" hexmask.word.byte 0x2 0.--3. 1. "PRESCALE,ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 Invalid 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock /.." line.word 0x4 "CONTROLSS_ADC1_CFG_ADCBURSTCTL" bitfld.word 0x4 15. "BURSTEN,SOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation. 0 Burst mode is disabled. 1 Burst mode is enabled." "0,1" hexmask.word.byte 0x4 8.--11. 1. "BURSTSIZE,SOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer which is advanced as each SOC is converted. 0h 1 SOC.." hexmask.word.byte 0x4 0.--6. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence. 00h - 7Fh: See AM602 spec. for trigger defintion" rgroup.word 0x6++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCINTFLG" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" group.word 0x8++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCINTFLGCLR" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT4 and ADCINT4RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT3 and ADCINT3RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT2 and ADCINT2RESULT flags in the ADCINTFLG register. . If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT1 and ADCINT1RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" rgroup.word 0xA++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCINTOVF" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" group.word 0xC++0xB line.word 0x0 "CONTROLSS_ADC1_CFG_ADCINTOVFCLR" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" line.word 0x2 "CONTROLSS_ADC1_CFG_ADCINTSEL1N2" bitfld.word 0x2 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode 0 No further ADCINT2 pulses are generated until ADCINT2 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" bitfld.word 0x2 13. "INT2E,ADCINT2 Interrupt Enable 0 ADCINT2 is disabled 1 ADCINT2 is enabled" "0,1" hexmask.word.byte 0x2 8.--11. 1. "INT2SEL,ADCINT2 EOC Source Select 0h EOC0 is trigger for ADCINT2 1h EOC1 is trigger for ADCINT2 2h EOC2 is trigger for ADCINT2 3h EOC3 is trigger for ADCINT2 4h EOC4 is trigger for ADCINT2 5h EOC5 is trigger for ADCINT2 6h EOC6 is.." bitfld.word 0x2 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode 0 No further ADCINT1 pulses are generated until ADCINT1 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 5. "INT1E,ADCINT1 Interrupt Enable 0 ADCINT1 is disabled 1 ADCINT1 is enabled" "0,1" hexmask.word.byte 0x2 0.--3. 1. "INT1SEL,ADCINT1 EOC Source Select 0h EOC0 is trigger for ADCINT1 1h EOC1 is trigger for ADCINT1 2h EOC2 is trigger for ADCINT1 3h EOC3 is trigger for ADCINT1 4h EOC4 is trigger for ADCINT1 5h EOC5 is trigger for ADCINT1 6h EOC6 is.." line.word 0x4 "CONTROLSS_ADC1_CFG_ADCINTSEL3N4" bitfld.word 0x4 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode 0 No further ADCINT4 pulses are generated until ADCINT4 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" bitfld.word 0x4 13. "INT4E,ADCINT4 Interrupt Enable 0 ADCINT4 is disabled 1 ADCINT4 is enabled" "0,1" hexmask.word.byte 0x4 8.--11. 1. "INT4SEL,ADCINT4 EOC Source Select 0h EOC0 is trigger for ADCINT4 1h EOC1 is trigger for ADCINT4 2h EOC2 is trigger for ADCINT4 3h EOC3 is trigger for ADCINT4 4h EOC4 is trigger for ADCINT4 5h EOC5 is trigger for ADCINT4 6h EOC6 is.." bitfld.word 0x4 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode 0 No further ADCINT3 pulses are generated until ADCINT3 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 5. "INT3E,ADCINT3 Interrupt Enable 0 ADCINT3 is disabled 1 ADCINT3 is enabled" "0,1" hexmask.word.byte 0x4 0.--3. 1. "INT3SEL,ADCINT3 EOC Source Select 0h EOC0 is trigger for ADCINT3 1h EOC1 is trigger for ADCINT3 2h EOC2 is trigger for ADCINT3 3h EOC3 is trigger for ADCINT3 4h EOC4 is trigger for ADCINT3 5h EOC5 is trigger for ADCINT3 6h EOC6 is.." line.word 0x6 "CONTROLSS_ADC1_CFG_ADCSOCPRICTL" hexmask.word.byte 0x6 5.--9. 1. "RRPOINTER,Round Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions. 00h SOC0 was last round robin SOC to convert SOC1 is highest round robin priority. 01h.." hexmask.word.byte 0x6 0.--4. 1. "SOCPRIORITY,SOC Priority Determines the cutoff point for priority mode and round robin arbitration for SOCx 00h SOC priority is handled in round robin mode for all channels. 01h SOC0 is high priority rest of channels are in round robin mode. 02h.." line.word 0x8 "CONTROLSS_ADC1_CFG_ADCINTSOCSEL1" bitfld.word 0x8 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0.." "0,1,2,3" line.word 0xA "CONTROLSS_ADC1_CFG_ADCINTSOCSEL2" bitfld.word 0xA 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC15. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC14. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC13. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC12. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC11. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC10. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0xA 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC0.." "0,1,2,3" rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCSOCFLG1" bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions. 0 No sample pending for SOC15. 1 Trigger has been received and sample is pending for SOC15. This bit will be automatically cleared when the SOC15 conversion is.." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions. 0 No sample pending for SOC14. 1 Trigger has been received and sample is pending for SOC14. This bit will be automatically cleared when the SOC14 conversion is.." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions. 0 No sample pending for SOC13. 1 Trigger has been received and sample is pending for SOC13. This bit will be automatically cleared when the SOC13 conversion is.." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions. 0 No sample pending for SOC12. 1 Trigger has been received and sample is pending for SOC12. This bit will be automatically cleared when the SOC12 conversion is.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions. 0 No sample pending for SOC11. 1 Trigger has been received and sample is pending for SOC11. This bit will be automatically cleared when the SOC11 conversion is.." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions. 0 No sample pending for SOC10. 1 Trigger has been received and sample is pending for SOC10. This bit will be automatically cleared when the SOC10 conversion is.." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions. 0 No sample pending for SOC9. 1 Trigger has been received and sample is pending for SOC9. This bit will be automatically cleared when the SOC9 conversion is started. If.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions. 0 No sample pending for SOC8. 1 Trigger has been received and sample is pending for SOC8. This bit will be automatically cleared when the SOC8 conversion is started. If.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions. 0 No sample pending for SOC7. 1 Trigger has been received and sample is pending for SOC7. This bit will be automatically cleared when the SOC7 conversion is started. If.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions. 0 No sample pending for SOC6. 1 Trigger has been received and sample is pending for SOC6. This bit will be automatically cleared when the SOC6 conversion is started. If.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions. 0 No sample pending for SOC5. 1 Trigger has been received and sample is pending for SOC5. This bit will be automatically cleared when the SOC5 conversion is started. If.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions. 0 No sample pending for SOC4. 1 Trigger has been received and sample is pending for SOC4. This bit will be automatically cleared when the SOC4 conversion is started. If.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions. 0 No sample pending for SOC3. 1 Trigger has been received and sample is pending for SOC3. This bit will be automatically cleared when the SOC3 conversion is started. If.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions. 0 No sample pending for SOC2. 1 Trigger has been received and sample is pending for SOC2. This bit will be automatically cleared when the SOC2 conversion is started. If.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions. 0 No sample pending for SOC1. 1 Trigger has been received and sample is pending for SOC1. This bit will be automatically cleared when the SOC1 conversion is started. If.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions. 0 No sample pending for SOC0. 1 Trigger has been received and sample is pending for SOC0. This bit will be automatically cleared when the SOC0 conversion is started. If.." "0,1" group.word 0x1A++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCSOCFRC1" bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" rgroup.word 0x1C++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCSOCOVF1" bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending. 0 No SOC15 event overflow. 1 SOC15 event overflow. An overflow condition does not stop SOC15.." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending. 0 No SOC14 event overflow. 1 SOC14 event overflow. An overflow condition does not stop SOC14.." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending. 0 No SOC13 event overflow. 1 SOC13 event overflow. An overflow condition does not stop SOC13.." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending. 0 No SOC12 event overflow. 1 SOC12 event overflow. An overflow condition does not stop SOC12.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending. 0 No SOC11 event overflow. 1 SOC11 event overflow. An overflow condition does not stop SOC11.." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending. 0 No SOC10 event overflow. 1 SOC10 event overflow. An overflow condition does not stop SOC10.." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending. 0 No SOC9 event overflow. 1 SOC9 event overflow. An overflow condition does not stop SOC9 events from.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending. 0 No SOC8 event overflow. 1 SOC8 event overflow. An overflow condition does not stop SOC8 events from.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending. 0 No SOC7 event overflow. 1 SOC7 event overflow. An overflow condition does not stop SOC7 events from.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending. 0 No SOC6 event overflow. 1 SOC6 event overflow. An overflow condition does not stop SOC6 events from.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending. 0 No SOC5 event overflow. 1 SOC5 event overflow. An overflow condition does not stop SOC5 events from.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending. 0 No SOC4 event overflow. 1 SOC4 event overflow. An overflow condition does not stop SOC4 events from.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending. 0 No SOC3 event overflow. 1 SOC3 event overflow. An overflow condition does not stop SOC3 events from.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending. 0 No SOC2 event overflow. 1 SOC2 event overflow. An overflow condition does not stop SOC2 events from.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending. 0 No SOC1 event overflow. 1 SOC1 event overflow. An overflow condition does not stop SOC1 events from.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending. 0 No SOC0 event overflow. 1 SOC0 event overflow. An overflow condition does not stop SOC0 events from.." "0,1" group.word 0x1E++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCSOCOVFCLR1" bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC15 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC14 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC13 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC12 overflow flag. If software tries to.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC11 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC10 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC9 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC8 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC7 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC6 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC5 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC4 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC3 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC2 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC1 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC0 overflow flag. If software tries to set.." "0,1" group.long 0x20++0x3F line.long 0x0 "CONTROLSS_ADC1_CFG_ADCSOC0CTL" hexmask.long.byte 0x0 20.--26. 1. "TRIGSEL,SOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x0 15.--19. 1. "CHSEL,SOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x4 "CONTROLSS_ADC1_CFG_ADCSOC1CTL" hexmask.long.byte 0x4 20.--26. 1. "TRIGSEL,SOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x4 15.--19. 1. "CHSEL,SOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x8 "CONTROLSS_ADC1_CFG_ADCSOC2CTL" hexmask.long.byte 0x8 20.--26. 1. "TRIGSEL,SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x8 15.--19. 1. "CHSEL,SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0xC "CONTROLSS_ADC1_CFG_ADCSOC3CTL" hexmask.long.byte 0xC 20.--26. 1. "TRIGSEL,SOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0xC 15.--19. 1. "CHSEL,SOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x10 "CONTROLSS_ADC1_CFG_ADCSOC4CTL" hexmask.long.byte 0x10 20.--26. 1. "TRIGSEL,SOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x10 15.--19. 1. "CHSEL,SOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x14 "CONTROLSS_ADC1_CFG_ADCSOC5CTL" hexmask.long.byte 0x14 20.--26. 1. "TRIGSEL,SOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x14 15.--19. 1. "CHSEL,SOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x18 "CONTROLSS_ADC1_CFG_ADCSOC6CTL" hexmask.long.byte 0x18 20.--26. 1. "TRIGSEL,SOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x18 15.--19. 1. "CHSEL,SOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x1C "CONTROLSS_ADC1_CFG_ADCSOC7CTL" hexmask.long.byte 0x1C 20.--26. 1. "TRIGSEL,SOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x1C 15.--19. 1. "CHSEL,SOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x20 "CONTROLSS_ADC1_CFG_ADCSOC8CTL" hexmask.long.byte 0x20 20.--26. 1. "TRIGSEL,SOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x20 15.--19. 1. "CHSEL,SOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x20 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x24 "CONTROLSS_ADC1_CFG_ADCSOC9CTL" hexmask.long.byte 0x24 20.--26. 1. "TRIGSEL,SOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x24 15.--19. 1. "CHSEL,SOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x24 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x28 "CONTROLSS_ADC1_CFG_ADCSOC10CTL" hexmask.long.byte 0x28 20.--26. 1. "TRIGSEL,SOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x28 15.--19. 1. "CHSEL,SOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x28 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x2C "CONTROLSS_ADC1_CFG_ADCSOC11CTL" hexmask.long.byte 0x2C 20.--26. 1. "TRIGSEL,SOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x2C 15.--19. 1. "CHSEL,SOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x2C 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x30 "CONTROLSS_ADC1_CFG_ADCSOC12CTL" hexmask.long.byte 0x30 20.--26. 1. "TRIGSEL,SOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x30 15.--19. 1. "CHSEL,SOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x30 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x34 "CONTROLSS_ADC1_CFG_ADCSOC13CTL" hexmask.long.byte 0x34 20.--26. 1. "TRIGSEL,SOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x34 15.--19. 1. "CHSEL,SOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x34 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x38 "CONTROLSS_ADC1_CFG_ADCSOC14CTL" hexmask.long.byte 0x38 20.--26. 1. "TRIGSEL,SOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x38 15.--19. 1. "CHSEL,SOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x38 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x3C "CONTROLSS_ADC1_CFG_ADCSOC15CTL" hexmask.long.byte 0x3C 20.--26. 1. "TRIGSEL,SOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x3C 15.--19. 1. "CHSEL,SOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x3C 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." rgroup.word 0x60++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCEVTSTAT" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" group.word 0x64++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCEVTCLR" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" group.word 0x68++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCEVTSEL" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" group.word 0x6C++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCEVTINTSEL" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" group.word 0x70++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCOSDETECT" bitfld.word 0x0 0.--2. "DETECTCFG,ADC Opens and Shorts Detect Configuration. This bit field defines the open/shorts detection circuit state. 0h Open/Shorts detection circuit is disabled. 1h Open/Shorts detection circuit is enabled at zero scale. 2h Open/Shorts.." "0,1,2,3,4,5,6,7" rgroup.word 0x72++0x3 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCCOUNTER" hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value. This bit field reflects the status of the free running ADC counter." line.word 0x2 "CONTROLSS_ADC1_CFG_ADCREV" hexmask.word.byte 0x2 8.--15. 1. "REV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h." hexmask.word.byte 0x2 0.--7. 1. "TYPE,ADC Type. Always set to 5 for this ADC." group.word 0x76++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCOFFTRIM" hexmask.word.byte 0x0 0.--7. 1. "OFFTRIM,ADC Offset Trim Adjusts the conversion results of the converter up or down to account for offset error in the ADC. A factory trim setting will be loaded during device boot. Offset can be corrected in the range of +7 to -8 LSBs. Value is.." group.long 0x7C++0x3 line.long 0x0 "CONTROLSS_ADC1_CFG_ADCCONFIG" hexmask.long 0x0 0.--31. 1. "CONFIG,ADC Configuration. This bit field is used for TI internal testing/debugging." group.word 0x80++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCPPB1CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 1 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0x82++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCPPB1STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x84++0x3 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCPPB1OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC1_CFG_ADCPPB1OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x88++0x7 line.long 0x0 "CONTROLSS_ADC1_CFG_ADCPPB1TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC1_CFG_ADCPPB1TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits 12:0.." group.word 0x90++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCPPB2CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 2 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0x92++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCPPB2STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x94++0x3 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCPPB2OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC1_CFG_ADCPPB2OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x98++0x7 line.long 0x0 "CONTROLSS_ADC1_CFG_ADCPPB2TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC1_CFG_ADCPPB2TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits 12:0.." group.word 0xA0++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCPPB3CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 3 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0xA2++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCPPB3STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xA4++0x3 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCPPB3OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC1_CFG_ADCPPB3OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xA8++0x7 line.long 0x0 "CONTROLSS_ADC1_CFG_ADCPPB3TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC1_CFG_ADCPPB3TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits 12:0.." group.word 0xB0++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCPPB4CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 4 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0xB2++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCPPB4STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xB4++0x3 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCPPB4OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 4 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC1_CFG_ADCPPB4OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xB8++0x7 line.long 0x0 "CONTROLSS_ADC1_CFG_ADCPPB4TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC1_CFG_ADCPPB4TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits 12:0.." group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_ADC1_CFG_ADCINTCYCLE" hexmask.word 0x0 0.--15. 1. "DELAY,ADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles for the interrupt to be generated." group.long 0xE0++0x17 line.long 0x0 "CONTROLSS_ADC1_CFG_ADCINLTRIM1" hexmask.long 0x0 0.--31. 1. "INLTRIM31TO0,ADC Linearity Trim Bits 31-0. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x4 "CONTROLSS_ADC1_CFG_ADCINLTRIM2" hexmask.long 0x4 0.--31. 1. "INLTRIM63TO32,ADC Linearity Trim Bits 63-32. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x8 "CONTROLSS_ADC1_CFG_ADCINLTRIM3" hexmask.long 0x8 0.--31. 1. "INLTRIM95TO64,ADC Linearity Trim Bits 95-64. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0xC "CONTROLSS_ADC1_CFG_ADCINLTRIM4" hexmask.long 0xC 0.--31. 1. "INLTRIM127TO96,ADC Linearity Trim Bits 127-96. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x10 "CONTROLSS_ADC1_CFG_ADCINLTRIM5" hexmask.long 0x10 0.--31. 1. "INLTRIM159TO128,ADC Linearity Trim Bits 159-128. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x14 "CONTROLSS_ADC1_CFG_ADCINLTRIM6" hexmask.long 0x14 0.--31. 1. "INLTRIM191TO160,ADC Linearity Trim Bits 191-160. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." group.long 0xFC++0x3 line.long 0x0 "CONTROLSS_ADC1_CFG_ADCINLTRIMCTL" hexmask.long.word 0x0 16.--31. 1. "KEY,ADC Linearity Trim Control Write Key. Any write to this register must contain the value 0xA5A5 in these bit locations. If a write request attempts to load any other value into these bits the write for the entire register is ignored. These bits.." hexmask.long.byte 0x0 1.--5. 1. "CALIBSTEP,ADC Linearity Calibration Step. Defines which of the 24 steps of calibration is to be executed. Never set this bit field while the ADC SELFTRIM is in progress. The R-M-W operation could unintentionally set the CALIBMODE bit again." bitfld.long 0x0 0. "CALIBMODE,ADC Linearity Calibration Mode." "0,1" tree.end tree "ADC1_RESULT" base ad:0x50101000 rgroup.word 0x0++0x1F line.word 0x0 "CONTROLSS_ADC1_RESULT_ADCRESULT0" hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result 0 16-bit ADC result. After the ADC completes a conversion of SOC0 the digital result is placed in this bit field." line.word 0x2 "CONTROLSS_ADC1_RESULT_ADCRESULT1" hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result 1 16-bit ADC result. After the ADC completes a conversion of SOC1 the digital result is placed in this bit field." line.word 0x4 "CONTROLSS_ADC1_RESULT_ADCRESULT2" hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result 2 16-bit ADC result. After the ADC completes a conversion of SOC2 the digital result is placed in this bit field." line.word 0x6 "CONTROLSS_ADC1_RESULT_ADCRESULT3" hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result 3 16-bit ADC result. After the ADC completes a conversion of SOC3 the digital result is placed in this bit field." line.word 0x8 "CONTROLSS_ADC1_RESULT_ADCRESULT4" hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result 4 16-bit ADC result. After the ADC completes a conversion of SOC4 the digital result is placed in this bit field." line.word 0xA "CONTROLSS_ADC1_RESULT_ADCRESULT5" hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result 5 16-bit ADC result. After the ADC completes a conversion of SOC5 the digital result is placed in this bit field." line.word 0xC "CONTROLSS_ADC1_RESULT_ADCRESULT6" hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result 6 16-bit ADC result. After the ADC completes a conversion of SOC6 the digital result is placed in this bit field." line.word 0xE "CONTROLSS_ADC1_RESULT_ADCRESULT7" hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result 7 16-bit ADC result. After the ADC completes a conversion of SOC7 the digital result is placed in this bit field." line.word 0x10 "CONTROLSS_ADC1_RESULT_ADCRESULT8" hexmask.word 0x10 0.--15. 1. "RESULT,ADC Result 8 16-bit ADC result. After the ADC completes a conversion of SOC8 the digital result is placed in this bit field." line.word 0x12 "CONTROLSS_ADC1_RESULT_ADCRESULT9" hexmask.word 0x12 0.--15. 1. "RESULT,ADC Result 9 16-bit ADC result. After the ADC completes a conversion of SOC9 the digital result is placed in this bit field." line.word 0x14 "CONTROLSS_ADC1_RESULT_ADCRESULT10" hexmask.word 0x14 0.--15. 1. "RESULT,ADC Result 10 16-bit ADC result. After the ADC completes a conversion of SOC10 the digital result is placed in this bit field." line.word 0x16 "CONTROLSS_ADC1_RESULT_ADCRESULT11" hexmask.word 0x16 0.--15. 1. "RESULT,ADC Result 11 16-bit ADC result. After the ADC completes a conversion of SOC11 the digital result is placed in this bit field." line.word 0x18 "CONTROLSS_ADC1_RESULT_ADCRESULT12" hexmask.word 0x18 0.--15. 1. "RESULT,ADC Result 12 16-bit ADC result. After the ADC completes a conversion of SOC12 the digital result is placed in this bit field." line.word 0x1A "CONTROLSS_ADC1_RESULT_ADCRESULT13" hexmask.word 0x1A 0.--15. 1. "RESULT,ADC Result 13 16-bit ADC result. After the ADC completes a conversion of SOC13 the digital result is placed in this bit field." line.word 0x1C "CONTROLSS_ADC1_RESULT_ADCRESULT14" hexmask.word 0x1C 0.--15. 1. "RESULT,ADC Result 14 16-bit ADC result. After the ADC completes a conversion of SOC14 the digital result is placed in this bit field." line.word 0x1E "CONTROLSS_ADC1_RESULT_ADCRESULT15" hexmask.word 0x1E 0.--15. 1. "RESULT,ADC Result 15 16-bit ADC result. After the ADC completes a conversion of SOC15 the digital result is placed in this bit field." rgroup.long 0x20++0xF line.long 0x0 "CONTROLSS_ADC1_RESULT_ADCPPB1RESULT" hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 1 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." line.long 0x4 "CONTROLSS_ADC1_RESULT_ADCPPB2RESULT" hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 2 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." line.long 0x8 "CONTROLSS_ADC1_RESULT_ADCPPB3RESULT" hexmask.long.word 0x8 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x8 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 3 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." line.long 0xC "CONTROLSS_ADC1_RESULT_ADCPPB4RESULT" hexmask.long.word 0xC 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0xC 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 4 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." tree.end tree "ADC2_CFG" base ad:0x502C2000 group.word 0x0++0x5 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCCTL1" rbitfld.word 0x0 13. "ADCBSY,ADC Busy. Set when ADC SOC is generated cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy.." "0,1" hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel. Set when an ADC Start of Conversion (SOC) is generated. When ADCBSY=0: holds the value of the last converted SOC When ADCBSY=1: reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC.." bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down (active low). This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up" "0,1" bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion (at the end of the acquisition window) plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse.." "0,1" line.word 0x2 "CONTROLSS_ADC2_CFG_ADCCTL2" bitfld.word 0x2 7. "SIGNALMODE,SOC Signaling Mode. Selects the input mode of the converter. Use the AdcSetMode function to change the signal mode. 0 Single-ended 1 Differential" "0,1" bitfld.word 0x2 6. "RESOLUTION,SOC Conversion Resolution. Selects the resolution of the converter. Use the AdcSetMode function to change the resolution. 0 12-bit resolution 1 16-bit resolution" "0,1" hexmask.word.byte 0x2 0.--3. 1. "PRESCALE,ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 Invalid 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock /.." line.word 0x4 "CONTROLSS_ADC2_CFG_ADCBURSTCTL" bitfld.word 0x4 15. "BURSTEN,SOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation. 0 Burst mode is disabled. 1 Burst mode is enabled." "0,1" hexmask.word.byte 0x4 8.--11. 1. "BURSTSIZE,SOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer which is advanced as each SOC is converted. 0h 1 SOC.." hexmask.word.byte 0x4 0.--6. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence. 00h - 7Fh: See AM602 spec. for trigger defintion" rgroup.word 0x6++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCINTFLG" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" group.word 0x8++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCINTFLGCLR" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT4 and ADCINT4RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT3 and ADCINT3RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT2 and ADCINT2RESULT flags in the ADCINTFLG register. . If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT1 and ADCINT1RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" rgroup.word 0xA++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCINTOVF" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" group.word 0xC++0xB line.word 0x0 "CONTROLSS_ADC2_CFG_ADCINTOVFCLR" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" line.word 0x2 "CONTROLSS_ADC2_CFG_ADCINTSEL1N2" bitfld.word 0x2 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode 0 No further ADCINT2 pulses are generated until ADCINT2 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" bitfld.word 0x2 13. "INT2E,ADCINT2 Interrupt Enable 0 ADCINT2 is disabled 1 ADCINT2 is enabled" "0,1" hexmask.word.byte 0x2 8.--11. 1. "INT2SEL,ADCINT2 EOC Source Select 0h EOC0 is trigger for ADCINT2 1h EOC1 is trigger for ADCINT2 2h EOC2 is trigger for ADCINT2 3h EOC3 is trigger for ADCINT2 4h EOC4 is trigger for ADCINT2 5h EOC5 is trigger for ADCINT2 6h EOC6 is.." bitfld.word 0x2 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode 0 No further ADCINT1 pulses are generated until ADCINT1 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 5. "INT1E,ADCINT1 Interrupt Enable 0 ADCINT1 is disabled 1 ADCINT1 is enabled" "0,1" hexmask.word.byte 0x2 0.--3. 1. "INT1SEL,ADCINT1 EOC Source Select 0h EOC0 is trigger for ADCINT1 1h EOC1 is trigger for ADCINT1 2h EOC2 is trigger for ADCINT1 3h EOC3 is trigger for ADCINT1 4h EOC4 is trigger for ADCINT1 5h EOC5 is trigger for ADCINT1 6h EOC6 is.." line.word 0x4 "CONTROLSS_ADC2_CFG_ADCINTSEL3N4" bitfld.word 0x4 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode 0 No further ADCINT4 pulses are generated until ADCINT4 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" bitfld.word 0x4 13. "INT4E,ADCINT4 Interrupt Enable 0 ADCINT4 is disabled 1 ADCINT4 is enabled" "0,1" hexmask.word.byte 0x4 8.--11. 1. "INT4SEL,ADCINT4 EOC Source Select 0h EOC0 is trigger for ADCINT4 1h EOC1 is trigger for ADCINT4 2h EOC2 is trigger for ADCINT4 3h EOC3 is trigger for ADCINT4 4h EOC4 is trigger for ADCINT4 5h EOC5 is trigger for ADCINT4 6h EOC6 is.." bitfld.word 0x4 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode 0 No further ADCINT3 pulses are generated until ADCINT3 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 5. "INT3E,ADCINT3 Interrupt Enable 0 ADCINT3 is disabled 1 ADCINT3 is enabled" "0,1" hexmask.word.byte 0x4 0.--3. 1. "INT3SEL,ADCINT3 EOC Source Select 0h EOC0 is trigger for ADCINT3 1h EOC1 is trigger for ADCINT3 2h EOC2 is trigger for ADCINT3 3h EOC3 is trigger for ADCINT3 4h EOC4 is trigger for ADCINT3 5h EOC5 is trigger for ADCINT3 6h EOC6 is.." line.word 0x6 "CONTROLSS_ADC2_CFG_ADCSOCPRICTL" hexmask.word.byte 0x6 5.--9. 1. "RRPOINTER,Round Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions. 00h SOC0 was last round robin SOC to convert SOC1 is highest round robin priority. 01h.." hexmask.word.byte 0x6 0.--4. 1. "SOCPRIORITY,SOC Priority Determines the cutoff point for priority mode and round robin arbitration for SOCx 00h SOC priority is handled in round robin mode for all channels. 01h SOC0 is high priority rest of channels are in round robin mode. 02h.." line.word 0x8 "CONTROLSS_ADC2_CFG_ADCINTSOCSEL1" bitfld.word 0x8 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0.." "0,1,2,3" line.word 0xA "CONTROLSS_ADC2_CFG_ADCINTSOCSEL2" bitfld.word 0xA 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC15. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC14. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC13. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC12. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC11. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC10. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0xA 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC0.." "0,1,2,3" rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCSOCFLG1" bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions. 0 No sample pending for SOC15. 1 Trigger has been received and sample is pending for SOC15. This bit will be automatically cleared when the SOC15 conversion is.." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions. 0 No sample pending for SOC14. 1 Trigger has been received and sample is pending for SOC14. This bit will be automatically cleared when the SOC14 conversion is.." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions. 0 No sample pending for SOC13. 1 Trigger has been received and sample is pending for SOC13. This bit will be automatically cleared when the SOC13 conversion is.." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions. 0 No sample pending for SOC12. 1 Trigger has been received and sample is pending for SOC12. This bit will be automatically cleared when the SOC12 conversion is.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions. 0 No sample pending for SOC11. 1 Trigger has been received and sample is pending for SOC11. This bit will be automatically cleared when the SOC11 conversion is.." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions. 0 No sample pending for SOC10. 1 Trigger has been received and sample is pending for SOC10. This bit will be automatically cleared when the SOC10 conversion is.." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions. 0 No sample pending for SOC9. 1 Trigger has been received and sample is pending for SOC9. This bit will be automatically cleared when the SOC9 conversion is started. If.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions. 0 No sample pending for SOC8. 1 Trigger has been received and sample is pending for SOC8. This bit will be automatically cleared when the SOC8 conversion is started. If.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions. 0 No sample pending for SOC7. 1 Trigger has been received and sample is pending for SOC7. This bit will be automatically cleared when the SOC7 conversion is started. If.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions. 0 No sample pending for SOC6. 1 Trigger has been received and sample is pending for SOC6. This bit will be automatically cleared when the SOC6 conversion is started. If.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions. 0 No sample pending for SOC5. 1 Trigger has been received and sample is pending for SOC5. This bit will be automatically cleared when the SOC5 conversion is started. If.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions. 0 No sample pending for SOC4. 1 Trigger has been received and sample is pending for SOC4. This bit will be automatically cleared when the SOC4 conversion is started. If.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions. 0 No sample pending for SOC3. 1 Trigger has been received and sample is pending for SOC3. This bit will be automatically cleared when the SOC3 conversion is started. If.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions. 0 No sample pending for SOC2. 1 Trigger has been received and sample is pending for SOC2. This bit will be automatically cleared when the SOC2 conversion is started. If.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions. 0 No sample pending for SOC1. 1 Trigger has been received and sample is pending for SOC1. This bit will be automatically cleared when the SOC1 conversion is started. If.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions. 0 No sample pending for SOC0. 1 Trigger has been received and sample is pending for SOC0. This bit will be automatically cleared when the SOC0 conversion is started. If.." "0,1" group.word 0x1A++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCSOCFRC1" bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" rgroup.word 0x1C++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCSOCOVF1" bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending. 0 No SOC15 event overflow. 1 SOC15 event overflow. An overflow condition does not stop SOC15.." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending. 0 No SOC14 event overflow. 1 SOC14 event overflow. An overflow condition does not stop SOC14.." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending. 0 No SOC13 event overflow. 1 SOC13 event overflow. An overflow condition does not stop SOC13.." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending. 0 No SOC12 event overflow. 1 SOC12 event overflow. An overflow condition does not stop SOC12.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending. 0 No SOC11 event overflow. 1 SOC11 event overflow. An overflow condition does not stop SOC11.." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending. 0 No SOC10 event overflow. 1 SOC10 event overflow. An overflow condition does not stop SOC10.." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending. 0 No SOC9 event overflow. 1 SOC9 event overflow. An overflow condition does not stop SOC9 events from.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending. 0 No SOC8 event overflow. 1 SOC8 event overflow. An overflow condition does not stop SOC8 events from.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending. 0 No SOC7 event overflow. 1 SOC7 event overflow. An overflow condition does not stop SOC7 events from.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending. 0 No SOC6 event overflow. 1 SOC6 event overflow. An overflow condition does not stop SOC6 events from.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending. 0 No SOC5 event overflow. 1 SOC5 event overflow. An overflow condition does not stop SOC5 events from.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending. 0 No SOC4 event overflow. 1 SOC4 event overflow. An overflow condition does not stop SOC4 events from.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending. 0 No SOC3 event overflow. 1 SOC3 event overflow. An overflow condition does not stop SOC3 events from.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending. 0 No SOC2 event overflow. 1 SOC2 event overflow. An overflow condition does not stop SOC2 events from.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending. 0 No SOC1 event overflow. 1 SOC1 event overflow. An overflow condition does not stop SOC1 events from.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending. 0 No SOC0 event overflow. 1 SOC0 event overflow. An overflow condition does not stop SOC0 events from.." "0,1" group.word 0x1E++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCSOCOVFCLR1" bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC15 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC14 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC13 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC12 overflow flag. If software tries to.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC11 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC10 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC9 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC8 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC7 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC6 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC5 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC4 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC3 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC2 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC1 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC0 overflow flag. If software tries to set.." "0,1" group.long 0x20++0x3F line.long 0x0 "CONTROLSS_ADC2_CFG_ADCSOC0CTL" hexmask.long.byte 0x0 20.--26. 1. "TRIGSEL,SOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x0 15.--19. 1. "CHSEL,SOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x4 "CONTROLSS_ADC2_CFG_ADCSOC1CTL" hexmask.long.byte 0x4 20.--26. 1. "TRIGSEL,SOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x4 15.--19. 1. "CHSEL,SOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x8 "CONTROLSS_ADC2_CFG_ADCSOC2CTL" hexmask.long.byte 0x8 20.--26. 1. "TRIGSEL,SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x8 15.--19. 1. "CHSEL,SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0xC "CONTROLSS_ADC2_CFG_ADCSOC3CTL" hexmask.long.byte 0xC 20.--26. 1. "TRIGSEL,SOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0xC 15.--19. 1. "CHSEL,SOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x10 "CONTROLSS_ADC2_CFG_ADCSOC4CTL" hexmask.long.byte 0x10 20.--26. 1. "TRIGSEL,SOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x10 15.--19. 1. "CHSEL,SOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x14 "CONTROLSS_ADC2_CFG_ADCSOC5CTL" hexmask.long.byte 0x14 20.--26. 1. "TRIGSEL,SOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x14 15.--19. 1. "CHSEL,SOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x18 "CONTROLSS_ADC2_CFG_ADCSOC6CTL" hexmask.long.byte 0x18 20.--26. 1. "TRIGSEL,SOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x18 15.--19. 1. "CHSEL,SOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x1C "CONTROLSS_ADC2_CFG_ADCSOC7CTL" hexmask.long.byte 0x1C 20.--26. 1. "TRIGSEL,SOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x1C 15.--19. 1. "CHSEL,SOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x20 "CONTROLSS_ADC2_CFG_ADCSOC8CTL" hexmask.long.byte 0x20 20.--26. 1. "TRIGSEL,SOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x20 15.--19. 1. "CHSEL,SOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x20 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x24 "CONTROLSS_ADC2_CFG_ADCSOC9CTL" hexmask.long.byte 0x24 20.--26. 1. "TRIGSEL,SOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x24 15.--19. 1. "CHSEL,SOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x24 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x28 "CONTROLSS_ADC2_CFG_ADCSOC10CTL" hexmask.long.byte 0x28 20.--26. 1. "TRIGSEL,SOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x28 15.--19. 1. "CHSEL,SOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x28 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x2C "CONTROLSS_ADC2_CFG_ADCSOC11CTL" hexmask.long.byte 0x2C 20.--26. 1. "TRIGSEL,SOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x2C 15.--19. 1. "CHSEL,SOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x2C 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x30 "CONTROLSS_ADC2_CFG_ADCSOC12CTL" hexmask.long.byte 0x30 20.--26. 1. "TRIGSEL,SOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x30 15.--19. 1. "CHSEL,SOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x30 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x34 "CONTROLSS_ADC2_CFG_ADCSOC13CTL" hexmask.long.byte 0x34 20.--26. 1. "TRIGSEL,SOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x34 15.--19. 1. "CHSEL,SOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x34 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x38 "CONTROLSS_ADC2_CFG_ADCSOC14CTL" hexmask.long.byte 0x38 20.--26. 1. "TRIGSEL,SOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x38 15.--19. 1. "CHSEL,SOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x38 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x3C "CONTROLSS_ADC2_CFG_ADCSOC15CTL" hexmask.long.byte 0x3C 20.--26. 1. "TRIGSEL,SOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x3C 15.--19. 1. "CHSEL,SOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x3C 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." rgroup.word 0x60++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCEVTSTAT" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" group.word 0x64++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCEVTCLR" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" group.word 0x68++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCEVTSEL" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" group.word 0x6C++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCEVTINTSEL" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" group.word 0x70++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCOSDETECT" bitfld.word 0x0 0.--2. "DETECTCFG,ADC Opens and Shorts Detect Configuration. This bit field defines the open/shorts detection circuit state. 0h Open/Shorts detection circuit is disabled. 1h Open/Shorts detection circuit is enabled at zero scale. 2h Open/Shorts.." "0,1,2,3,4,5,6,7" rgroup.word 0x72++0x3 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCCOUNTER" hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value. This bit field reflects the status of the free running ADC counter." line.word 0x2 "CONTROLSS_ADC2_CFG_ADCREV" hexmask.word.byte 0x2 8.--15. 1. "REV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h." hexmask.word.byte 0x2 0.--7. 1. "TYPE,ADC Type. Always set to 5 for this ADC." group.word 0x76++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCOFFTRIM" hexmask.word.byte 0x0 0.--7. 1. "OFFTRIM,ADC Offset Trim Adjusts the conversion results of the converter up or down to account for offset error in the ADC. A factory trim setting will be loaded during device boot. Offset can be corrected in the range of +7 to -8 LSBs. Value is.." group.long 0x7C++0x3 line.long 0x0 "CONTROLSS_ADC2_CFG_ADCCONFIG" hexmask.long 0x0 0.--31. 1. "CONFIG,ADC Configuration. This bit field is used for TI internal testing/debugging." group.word 0x80++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCPPB1CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 1 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0x82++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCPPB1STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x84++0x3 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCPPB1OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC2_CFG_ADCPPB1OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x88++0x7 line.long 0x0 "CONTROLSS_ADC2_CFG_ADCPPB1TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC2_CFG_ADCPPB1TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits 12:0.." group.word 0x90++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCPPB2CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 2 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0x92++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCPPB2STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x94++0x3 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCPPB2OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC2_CFG_ADCPPB2OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x98++0x7 line.long 0x0 "CONTROLSS_ADC2_CFG_ADCPPB2TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC2_CFG_ADCPPB2TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits 12:0.." group.word 0xA0++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCPPB3CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 3 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0xA2++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCPPB3STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xA4++0x3 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCPPB3OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC2_CFG_ADCPPB3OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xA8++0x7 line.long 0x0 "CONTROLSS_ADC2_CFG_ADCPPB3TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC2_CFG_ADCPPB3TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits 12:0.." group.word 0xB0++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCPPB4CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 4 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0xB2++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCPPB4STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xB4++0x3 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCPPB4OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 4 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC2_CFG_ADCPPB4OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xB8++0x7 line.long 0x0 "CONTROLSS_ADC2_CFG_ADCPPB4TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC2_CFG_ADCPPB4TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits 12:0.." group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_ADC2_CFG_ADCINTCYCLE" hexmask.word 0x0 0.--15. 1. "DELAY,ADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles for the interrupt to be generated." group.long 0xE0++0x17 line.long 0x0 "CONTROLSS_ADC2_CFG_ADCINLTRIM1" hexmask.long 0x0 0.--31. 1. "INLTRIM31TO0,ADC Linearity Trim Bits 31-0. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x4 "CONTROLSS_ADC2_CFG_ADCINLTRIM2" hexmask.long 0x4 0.--31. 1. "INLTRIM63TO32,ADC Linearity Trim Bits 63-32. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x8 "CONTROLSS_ADC2_CFG_ADCINLTRIM3" hexmask.long 0x8 0.--31. 1. "INLTRIM95TO64,ADC Linearity Trim Bits 95-64. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0xC "CONTROLSS_ADC2_CFG_ADCINLTRIM4" hexmask.long 0xC 0.--31. 1. "INLTRIM127TO96,ADC Linearity Trim Bits 127-96. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x10 "CONTROLSS_ADC2_CFG_ADCINLTRIM5" hexmask.long 0x10 0.--31. 1. "INLTRIM159TO128,ADC Linearity Trim Bits 159-128. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x14 "CONTROLSS_ADC2_CFG_ADCINLTRIM6" hexmask.long 0x14 0.--31. 1. "INLTRIM191TO160,ADC Linearity Trim Bits 191-160. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." group.long 0xFC++0x3 line.long 0x0 "CONTROLSS_ADC2_CFG_ADCINLTRIMCTL" hexmask.long.word 0x0 16.--31. 1. "KEY,ADC Linearity Trim Control Write Key. Any write to this register must contain the value 0xA5A5 in these bit locations. If a write request attempts to load any other value into these bits the write for the entire register is ignored. These bits.." hexmask.long.byte 0x0 1.--5. 1. "CALIBSTEP,ADC Linearity Calibration Step. Defines which of the 24 steps of calibration is to be executed. Never set this bit field while the ADC SELFTRIM is in progress. The R-M-W operation could unintentionally set the CALIBMODE bit again." bitfld.long 0x0 0. "CALIBMODE,ADC Linearity Calibration Mode." "0,1" tree.end tree "ADC2_RESULT" base ad:0x50102000 rgroup.word 0x0++0x1F line.word 0x0 "CONTROLSS_ADC2_RESULT_ADCRESULT0" hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result 0 16-bit ADC result. After the ADC completes a conversion of SOC0 the digital result is placed in this bit field." line.word 0x2 "CONTROLSS_ADC2_RESULT_ADCRESULT1" hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result 1 16-bit ADC result. After the ADC completes a conversion of SOC1 the digital result is placed in this bit field." line.word 0x4 "CONTROLSS_ADC2_RESULT_ADCRESULT2" hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result 2 16-bit ADC result. After the ADC completes a conversion of SOC2 the digital result is placed in this bit field." line.word 0x6 "CONTROLSS_ADC2_RESULT_ADCRESULT3" hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result 3 16-bit ADC result. After the ADC completes a conversion of SOC3 the digital result is placed in this bit field." line.word 0x8 "CONTROLSS_ADC2_RESULT_ADCRESULT4" hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result 4 16-bit ADC result. After the ADC completes a conversion of SOC4 the digital result is placed in this bit field." line.word 0xA "CONTROLSS_ADC2_RESULT_ADCRESULT5" hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result 5 16-bit ADC result. After the ADC completes a conversion of SOC5 the digital result is placed in this bit field." line.word 0xC "CONTROLSS_ADC2_RESULT_ADCRESULT6" hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result 6 16-bit ADC result. After the ADC completes a conversion of SOC6 the digital result is placed in this bit field." line.word 0xE "CONTROLSS_ADC2_RESULT_ADCRESULT7" hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result 7 16-bit ADC result. After the ADC completes a conversion of SOC7 the digital result is placed in this bit field." line.word 0x10 "CONTROLSS_ADC2_RESULT_ADCRESULT8" hexmask.word 0x10 0.--15. 1. "RESULT,ADC Result 8 16-bit ADC result. After the ADC completes a conversion of SOC8 the digital result is placed in this bit field." line.word 0x12 "CONTROLSS_ADC2_RESULT_ADCRESULT9" hexmask.word 0x12 0.--15. 1. "RESULT,ADC Result 9 16-bit ADC result. After the ADC completes a conversion of SOC9 the digital result is placed in this bit field." line.word 0x14 "CONTROLSS_ADC2_RESULT_ADCRESULT10" hexmask.word 0x14 0.--15. 1. "RESULT,ADC Result 10 16-bit ADC result. After the ADC completes a conversion of SOC10 the digital result is placed in this bit field." line.word 0x16 "CONTROLSS_ADC2_RESULT_ADCRESULT11" hexmask.word 0x16 0.--15. 1. "RESULT,ADC Result 11 16-bit ADC result. After the ADC completes a conversion of SOC11 the digital result is placed in this bit field." line.word 0x18 "CONTROLSS_ADC2_RESULT_ADCRESULT12" hexmask.word 0x18 0.--15. 1. "RESULT,ADC Result 12 16-bit ADC result. After the ADC completes a conversion of SOC12 the digital result is placed in this bit field." line.word 0x1A "CONTROLSS_ADC2_RESULT_ADCRESULT13" hexmask.word 0x1A 0.--15. 1. "RESULT,ADC Result 13 16-bit ADC result. After the ADC completes a conversion of SOC13 the digital result is placed in this bit field." line.word 0x1C "CONTROLSS_ADC2_RESULT_ADCRESULT14" hexmask.word 0x1C 0.--15. 1. "RESULT,ADC Result 14 16-bit ADC result. After the ADC completes a conversion of SOC14 the digital result is placed in this bit field." line.word 0x1E "CONTROLSS_ADC2_RESULT_ADCRESULT15" hexmask.word 0x1E 0.--15. 1. "RESULT,ADC Result 15 16-bit ADC result. After the ADC completes a conversion of SOC15 the digital result is placed in this bit field." rgroup.long 0x20++0xF line.long 0x0 "CONTROLSS_ADC2_RESULT_ADCPPB1RESULT" hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 1 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." line.long 0x4 "CONTROLSS_ADC2_RESULT_ADCPPB2RESULT" hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 2 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." line.long 0x8 "CONTROLSS_ADC2_RESULT_ADCPPB3RESULT" hexmask.long.word 0x8 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x8 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 3 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." line.long 0xC "CONTROLSS_ADC2_RESULT_ADCPPB4RESULT" hexmask.long.word 0xC 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0xC 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 4 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." tree.end tree "ADC3_CFG" base ad:0x502C3000 group.word 0x0++0x5 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCCTL1" rbitfld.word 0x0 13. "ADCBSY,ADC Busy. Set when ADC SOC is generated cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy.." "0,1" hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel. Set when an ADC Start of Conversion (SOC) is generated. When ADCBSY=0: holds the value of the last converted SOC When ADCBSY=1: reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC.." bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down (active low). This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up" "0,1" bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion (at the end of the acquisition window) plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse.." "0,1" line.word 0x2 "CONTROLSS_ADC3_CFG_ADCCTL2" bitfld.word 0x2 7. "SIGNALMODE,SOC Signaling Mode. Selects the input mode of the converter. Use the AdcSetMode function to change the signal mode. 0 Single-ended 1 Differential" "0,1" bitfld.word 0x2 6. "RESOLUTION,SOC Conversion Resolution. Selects the resolution of the converter. Use the AdcSetMode function to change the resolution. 0 12-bit resolution 1 16-bit resolution" "0,1" hexmask.word.byte 0x2 0.--3. 1. "PRESCALE,ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 Invalid 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock /.." line.word 0x4 "CONTROLSS_ADC3_CFG_ADCBURSTCTL" bitfld.word 0x4 15. "BURSTEN,SOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation. 0 Burst mode is disabled. 1 Burst mode is enabled." "0,1" hexmask.word.byte 0x4 8.--11. 1. "BURSTSIZE,SOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer which is advanced as each SOC is converted. 0h 1 SOC.." hexmask.word.byte 0x4 0.--6. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence. 00h - 7Fh: See AM602 spec. for trigger defintion" rgroup.word 0x6++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCINTFLG" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" group.word 0x8++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCINTFLGCLR" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT4 and ADCINT4RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT3 and ADCINT3RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT2 and ADCINT2RESULT flags in the ADCINTFLG register. . If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT1 and ADCINT1RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" rgroup.word 0xA++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCINTOVF" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" group.word 0xC++0xB line.word 0x0 "CONTROLSS_ADC3_CFG_ADCINTOVFCLR" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" line.word 0x2 "CONTROLSS_ADC3_CFG_ADCINTSEL1N2" bitfld.word 0x2 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode 0 No further ADCINT2 pulses are generated until ADCINT2 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" bitfld.word 0x2 13. "INT2E,ADCINT2 Interrupt Enable 0 ADCINT2 is disabled 1 ADCINT2 is enabled" "0,1" hexmask.word.byte 0x2 8.--11. 1. "INT2SEL,ADCINT2 EOC Source Select 0h EOC0 is trigger for ADCINT2 1h EOC1 is trigger for ADCINT2 2h EOC2 is trigger for ADCINT2 3h EOC3 is trigger for ADCINT2 4h EOC4 is trigger for ADCINT2 5h EOC5 is trigger for ADCINT2 6h EOC6 is.." bitfld.word 0x2 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode 0 No further ADCINT1 pulses are generated until ADCINT1 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 5. "INT1E,ADCINT1 Interrupt Enable 0 ADCINT1 is disabled 1 ADCINT1 is enabled" "0,1" hexmask.word.byte 0x2 0.--3. 1. "INT1SEL,ADCINT1 EOC Source Select 0h EOC0 is trigger for ADCINT1 1h EOC1 is trigger for ADCINT1 2h EOC2 is trigger for ADCINT1 3h EOC3 is trigger for ADCINT1 4h EOC4 is trigger for ADCINT1 5h EOC5 is trigger for ADCINT1 6h EOC6 is.." line.word 0x4 "CONTROLSS_ADC3_CFG_ADCINTSEL3N4" bitfld.word 0x4 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode 0 No further ADCINT4 pulses are generated until ADCINT4 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" bitfld.word 0x4 13. "INT4E,ADCINT4 Interrupt Enable 0 ADCINT4 is disabled 1 ADCINT4 is enabled" "0,1" hexmask.word.byte 0x4 8.--11. 1. "INT4SEL,ADCINT4 EOC Source Select 0h EOC0 is trigger for ADCINT4 1h EOC1 is trigger for ADCINT4 2h EOC2 is trigger for ADCINT4 3h EOC3 is trigger for ADCINT4 4h EOC4 is trigger for ADCINT4 5h EOC5 is trigger for ADCINT4 6h EOC6 is.." bitfld.word 0x4 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode 0 No further ADCINT3 pulses are generated until ADCINT3 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 5. "INT3E,ADCINT3 Interrupt Enable 0 ADCINT3 is disabled 1 ADCINT3 is enabled" "0,1" hexmask.word.byte 0x4 0.--3. 1. "INT3SEL,ADCINT3 EOC Source Select 0h EOC0 is trigger for ADCINT3 1h EOC1 is trigger for ADCINT3 2h EOC2 is trigger for ADCINT3 3h EOC3 is trigger for ADCINT3 4h EOC4 is trigger for ADCINT3 5h EOC5 is trigger for ADCINT3 6h EOC6 is.." line.word 0x6 "CONTROLSS_ADC3_CFG_ADCSOCPRICTL" hexmask.word.byte 0x6 5.--9. 1. "RRPOINTER,Round Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions. 00h SOC0 was last round robin SOC to convert SOC1 is highest round robin priority. 01h.." hexmask.word.byte 0x6 0.--4. 1. "SOCPRIORITY,SOC Priority Determines the cutoff point for priority mode and round robin arbitration for SOCx 00h SOC priority is handled in round robin mode for all channels. 01h SOC0 is high priority rest of channels are in round robin mode. 02h.." line.word 0x8 "CONTROLSS_ADC3_CFG_ADCINTSOCSEL1" bitfld.word 0x8 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0.." "0,1,2,3" line.word 0xA "CONTROLSS_ADC3_CFG_ADCINTSOCSEL2" bitfld.word 0xA 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC15. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC14. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC13. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC12. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC11. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC10. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0xA 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC0.." "0,1,2,3" rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCSOCFLG1" bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions. 0 No sample pending for SOC15. 1 Trigger has been received and sample is pending for SOC15. This bit will be automatically cleared when the SOC15 conversion is.." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions. 0 No sample pending for SOC14. 1 Trigger has been received and sample is pending for SOC14. This bit will be automatically cleared when the SOC14 conversion is.." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions. 0 No sample pending for SOC13. 1 Trigger has been received and sample is pending for SOC13. This bit will be automatically cleared when the SOC13 conversion is.." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions. 0 No sample pending for SOC12. 1 Trigger has been received and sample is pending for SOC12. This bit will be automatically cleared when the SOC12 conversion is.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions. 0 No sample pending for SOC11. 1 Trigger has been received and sample is pending for SOC11. This bit will be automatically cleared when the SOC11 conversion is.." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions. 0 No sample pending for SOC10. 1 Trigger has been received and sample is pending for SOC10. This bit will be automatically cleared when the SOC10 conversion is.." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions. 0 No sample pending for SOC9. 1 Trigger has been received and sample is pending for SOC9. This bit will be automatically cleared when the SOC9 conversion is started. If.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions. 0 No sample pending for SOC8. 1 Trigger has been received and sample is pending for SOC8. This bit will be automatically cleared when the SOC8 conversion is started. If.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions. 0 No sample pending for SOC7. 1 Trigger has been received and sample is pending for SOC7. This bit will be automatically cleared when the SOC7 conversion is started. If.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions. 0 No sample pending for SOC6. 1 Trigger has been received and sample is pending for SOC6. This bit will be automatically cleared when the SOC6 conversion is started. If.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions. 0 No sample pending for SOC5. 1 Trigger has been received and sample is pending for SOC5. This bit will be automatically cleared when the SOC5 conversion is started. If.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions. 0 No sample pending for SOC4. 1 Trigger has been received and sample is pending for SOC4. This bit will be automatically cleared when the SOC4 conversion is started. If.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions. 0 No sample pending for SOC3. 1 Trigger has been received and sample is pending for SOC3. This bit will be automatically cleared when the SOC3 conversion is started. If.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions. 0 No sample pending for SOC2. 1 Trigger has been received and sample is pending for SOC2. This bit will be automatically cleared when the SOC2 conversion is started. If.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions. 0 No sample pending for SOC1. 1 Trigger has been received and sample is pending for SOC1. This bit will be automatically cleared when the SOC1 conversion is started. If.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions. 0 No sample pending for SOC0. 1 Trigger has been received and sample is pending for SOC0. This bit will be automatically cleared when the SOC0 conversion is started. If.." "0,1" group.word 0x1A++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCSOCFRC1" bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" rgroup.word 0x1C++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCSOCOVF1" bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending. 0 No SOC15 event overflow. 1 SOC15 event overflow. An overflow condition does not stop SOC15.." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending. 0 No SOC14 event overflow. 1 SOC14 event overflow. An overflow condition does not stop SOC14.." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending. 0 No SOC13 event overflow. 1 SOC13 event overflow. An overflow condition does not stop SOC13.." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending. 0 No SOC12 event overflow. 1 SOC12 event overflow. An overflow condition does not stop SOC12.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending. 0 No SOC11 event overflow. 1 SOC11 event overflow. An overflow condition does not stop SOC11.." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending. 0 No SOC10 event overflow. 1 SOC10 event overflow. An overflow condition does not stop SOC10.." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending. 0 No SOC9 event overflow. 1 SOC9 event overflow. An overflow condition does not stop SOC9 events from.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending. 0 No SOC8 event overflow. 1 SOC8 event overflow. An overflow condition does not stop SOC8 events from.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending. 0 No SOC7 event overflow. 1 SOC7 event overflow. An overflow condition does not stop SOC7 events from.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending. 0 No SOC6 event overflow. 1 SOC6 event overflow. An overflow condition does not stop SOC6 events from.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending. 0 No SOC5 event overflow. 1 SOC5 event overflow. An overflow condition does not stop SOC5 events from.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending. 0 No SOC4 event overflow. 1 SOC4 event overflow. An overflow condition does not stop SOC4 events from.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending. 0 No SOC3 event overflow. 1 SOC3 event overflow. An overflow condition does not stop SOC3 events from.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending. 0 No SOC2 event overflow. 1 SOC2 event overflow. An overflow condition does not stop SOC2 events from.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending. 0 No SOC1 event overflow. 1 SOC1 event overflow. An overflow condition does not stop SOC1 events from.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending. 0 No SOC0 event overflow. 1 SOC0 event overflow. An overflow condition does not stop SOC0 events from.." "0,1" group.word 0x1E++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCSOCOVFCLR1" bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC15 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC14 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC13 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC12 overflow flag. If software tries to.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC11 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC10 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC9 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC8 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC7 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC6 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC5 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC4 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC3 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC2 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC1 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC0 overflow flag. If software tries to set.." "0,1" group.long 0x20++0x3F line.long 0x0 "CONTROLSS_ADC3_CFG_ADCSOC0CTL" hexmask.long.byte 0x0 20.--26. 1. "TRIGSEL,SOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x0 15.--19. 1. "CHSEL,SOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x4 "CONTROLSS_ADC3_CFG_ADCSOC1CTL" hexmask.long.byte 0x4 20.--26. 1. "TRIGSEL,SOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x4 15.--19. 1. "CHSEL,SOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x8 "CONTROLSS_ADC3_CFG_ADCSOC2CTL" hexmask.long.byte 0x8 20.--26. 1. "TRIGSEL,SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x8 15.--19. 1. "CHSEL,SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0xC "CONTROLSS_ADC3_CFG_ADCSOC3CTL" hexmask.long.byte 0xC 20.--26. 1. "TRIGSEL,SOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0xC 15.--19. 1. "CHSEL,SOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x10 "CONTROLSS_ADC3_CFG_ADCSOC4CTL" hexmask.long.byte 0x10 20.--26. 1. "TRIGSEL,SOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x10 15.--19. 1. "CHSEL,SOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x14 "CONTROLSS_ADC3_CFG_ADCSOC5CTL" hexmask.long.byte 0x14 20.--26. 1. "TRIGSEL,SOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x14 15.--19. 1. "CHSEL,SOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x18 "CONTROLSS_ADC3_CFG_ADCSOC6CTL" hexmask.long.byte 0x18 20.--26. 1. "TRIGSEL,SOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x18 15.--19. 1. "CHSEL,SOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x1C "CONTROLSS_ADC3_CFG_ADCSOC7CTL" hexmask.long.byte 0x1C 20.--26. 1. "TRIGSEL,SOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x1C 15.--19. 1. "CHSEL,SOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x20 "CONTROLSS_ADC3_CFG_ADCSOC8CTL" hexmask.long.byte 0x20 20.--26. 1. "TRIGSEL,SOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x20 15.--19. 1. "CHSEL,SOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x20 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x24 "CONTROLSS_ADC3_CFG_ADCSOC9CTL" hexmask.long.byte 0x24 20.--26. 1. "TRIGSEL,SOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x24 15.--19. 1. "CHSEL,SOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x24 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x28 "CONTROLSS_ADC3_CFG_ADCSOC10CTL" hexmask.long.byte 0x28 20.--26. 1. "TRIGSEL,SOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x28 15.--19. 1. "CHSEL,SOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x28 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x2C "CONTROLSS_ADC3_CFG_ADCSOC11CTL" hexmask.long.byte 0x2C 20.--26. 1. "TRIGSEL,SOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x2C 15.--19. 1. "CHSEL,SOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x2C 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x30 "CONTROLSS_ADC3_CFG_ADCSOC12CTL" hexmask.long.byte 0x30 20.--26. 1. "TRIGSEL,SOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x30 15.--19. 1. "CHSEL,SOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x30 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x34 "CONTROLSS_ADC3_CFG_ADCSOC13CTL" hexmask.long.byte 0x34 20.--26. 1. "TRIGSEL,SOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x34 15.--19. 1. "CHSEL,SOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x34 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x38 "CONTROLSS_ADC3_CFG_ADCSOC14CTL" hexmask.long.byte 0x38 20.--26. 1. "TRIGSEL,SOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x38 15.--19. 1. "CHSEL,SOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x38 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x3C "CONTROLSS_ADC3_CFG_ADCSOC15CTL" hexmask.long.byte 0x3C 20.--26. 1. "TRIGSEL,SOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x3C 15.--19. 1. "CHSEL,SOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x3C 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." rgroup.word 0x60++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCEVTSTAT" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" group.word 0x64++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCEVTCLR" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" group.word 0x68++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCEVTSEL" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" group.word 0x6C++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCEVTINTSEL" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" group.word 0x70++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCOSDETECT" bitfld.word 0x0 0.--2. "DETECTCFG,ADC Opens and Shorts Detect Configuration. This bit field defines the open/shorts detection circuit state. 0h Open/Shorts detection circuit is disabled. 1h Open/Shorts detection circuit is enabled at zero scale. 2h Open/Shorts.." "0,1,2,3,4,5,6,7" rgroup.word 0x72++0x3 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCCOUNTER" hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value. This bit field reflects the status of the free running ADC counter." line.word 0x2 "CONTROLSS_ADC3_CFG_ADCREV" hexmask.word.byte 0x2 8.--15. 1. "REV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h." hexmask.word.byte 0x2 0.--7. 1. "TYPE,ADC Type. Always set to 5 for this ADC." group.word 0x76++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCOFFTRIM" hexmask.word.byte 0x0 0.--7. 1. "OFFTRIM,ADC Offset Trim Adjusts the conversion results of the converter up or down to account for offset error in the ADC. A factory trim setting will be loaded during device boot. Offset can be corrected in the range of +7 to -8 LSBs. Value is.." group.long 0x7C++0x3 line.long 0x0 "CONTROLSS_ADC3_CFG_ADCCONFIG" hexmask.long 0x0 0.--31. 1. "CONFIG,ADC Configuration. This bit field is used for TI internal testing/debugging." group.word 0x80++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCPPB1CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 1 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0x82++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCPPB1STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x84++0x3 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCPPB1OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC3_CFG_ADCPPB1OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x88++0x7 line.long 0x0 "CONTROLSS_ADC3_CFG_ADCPPB1TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC3_CFG_ADCPPB1TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits 12:0.." group.word 0x90++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCPPB2CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 2 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0x92++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCPPB2STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x94++0x3 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCPPB2OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC3_CFG_ADCPPB2OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x98++0x7 line.long 0x0 "CONTROLSS_ADC3_CFG_ADCPPB2TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC3_CFG_ADCPPB2TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits 12:0.." group.word 0xA0++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCPPB3CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 3 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0xA2++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCPPB3STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xA4++0x3 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCPPB3OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC3_CFG_ADCPPB3OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xA8++0x7 line.long 0x0 "CONTROLSS_ADC3_CFG_ADCPPB3TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC3_CFG_ADCPPB3TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits 12:0.." group.word 0xB0++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCPPB4CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 4 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0xB2++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCPPB4STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xB4++0x3 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCPPB4OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 4 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC3_CFG_ADCPPB4OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xB8++0x7 line.long 0x0 "CONTROLSS_ADC3_CFG_ADCPPB4TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC3_CFG_ADCPPB4TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits 12:0.." group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_ADC3_CFG_ADCINTCYCLE" hexmask.word 0x0 0.--15. 1. "DELAY,ADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles for the interrupt to be generated." group.long 0xE0++0x17 line.long 0x0 "CONTROLSS_ADC3_CFG_ADCINLTRIM1" hexmask.long 0x0 0.--31. 1. "INLTRIM31TO0,ADC Linearity Trim Bits 31-0. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x4 "CONTROLSS_ADC3_CFG_ADCINLTRIM2" hexmask.long 0x4 0.--31. 1. "INLTRIM63TO32,ADC Linearity Trim Bits 63-32. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x8 "CONTROLSS_ADC3_CFG_ADCINLTRIM3" hexmask.long 0x8 0.--31. 1. "INLTRIM95TO64,ADC Linearity Trim Bits 95-64. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0xC "CONTROLSS_ADC3_CFG_ADCINLTRIM4" hexmask.long 0xC 0.--31. 1. "INLTRIM127TO96,ADC Linearity Trim Bits 127-96. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x10 "CONTROLSS_ADC3_CFG_ADCINLTRIM5" hexmask.long 0x10 0.--31. 1. "INLTRIM159TO128,ADC Linearity Trim Bits 159-128. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x14 "CONTROLSS_ADC3_CFG_ADCINLTRIM6" hexmask.long 0x14 0.--31. 1. "INLTRIM191TO160,ADC Linearity Trim Bits 191-160. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." group.long 0xFC++0x3 line.long 0x0 "CONTROLSS_ADC3_CFG_ADCINLTRIMCTL" hexmask.long.word 0x0 16.--31. 1. "KEY,ADC Linearity Trim Control Write Key. Any write to this register must contain the value 0xA5A5 in these bit locations. If a write request attempts to load any other value into these bits the write for the entire register is ignored. These bits.." hexmask.long.byte 0x0 1.--5. 1. "CALIBSTEP,ADC Linearity Calibration Step. Defines which of the 24 steps of calibration is to be executed. Never set this bit field while the ADC SELFTRIM is in progress. The R-M-W operation could unintentionally set the CALIBMODE bit again." bitfld.long 0x0 0. "CALIBMODE,ADC Linearity Calibration Mode." "0,1" tree.end tree "ADC3_RESULT" base ad:0x50103000 rgroup.word 0x0++0x1F line.word 0x0 "CONTROLSS_ADC3_RESULT_ADCRESULT0" hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result 0 16-bit ADC result. After the ADC completes a conversion of SOC0 the digital result is placed in this bit field." line.word 0x2 "CONTROLSS_ADC3_RESULT_ADCRESULT1" hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result 1 16-bit ADC result. After the ADC completes a conversion of SOC1 the digital result is placed in this bit field." line.word 0x4 "CONTROLSS_ADC3_RESULT_ADCRESULT2" hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result 2 16-bit ADC result. After the ADC completes a conversion of SOC2 the digital result is placed in this bit field." line.word 0x6 "CONTROLSS_ADC3_RESULT_ADCRESULT3" hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result 3 16-bit ADC result. After the ADC completes a conversion of SOC3 the digital result is placed in this bit field." line.word 0x8 "CONTROLSS_ADC3_RESULT_ADCRESULT4" hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result 4 16-bit ADC result. After the ADC completes a conversion of SOC4 the digital result is placed in this bit field." line.word 0xA "CONTROLSS_ADC3_RESULT_ADCRESULT5" hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result 5 16-bit ADC result. After the ADC completes a conversion of SOC5 the digital result is placed in this bit field." line.word 0xC "CONTROLSS_ADC3_RESULT_ADCRESULT6" hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result 6 16-bit ADC result. After the ADC completes a conversion of SOC6 the digital result is placed in this bit field." line.word 0xE "CONTROLSS_ADC3_RESULT_ADCRESULT7" hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result 7 16-bit ADC result. After the ADC completes a conversion of SOC7 the digital result is placed in this bit field." line.word 0x10 "CONTROLSS_ADC3_RESULT_ADCRESULT8" hexmask.word 0x10 0.--15. 1. "RESULT,ADC Result 8 16-bit ADC result. After the ADC completes a conversion of SOC8 the digital result is placed in this bit field." line.word 0x12 "CONTROLSS_ADC3_RESULT_ADCRESULT9" hexmask.word 0x12 0.--15. 1. "RESULT,ADC Result 9 16-bit ADC result. After the ADC completes a conversion of SOC9 the digital result is placed in this bit field." line.word 0x14 "CONTROLSS_ADC3_RESULT_ADCRESULT10" hexmask.word 0x14 0.--15. 1. "RESULT,ADC Result 10 16-bit ADC result. After the ADC completes a conversion of SOC10 the digital result is placed in this bit field." line.word 0x16 "CONTROLSS_ADC3_RESULT_ADCRESULT11" hexmask.word 0x16 0.--15. 1. "RESULT,ADC Result 11 16-bit ADC result. After the ADC completes a conversion of SOC11 the digital result is placed in this bit field." line.word 0x18 "CONTROLSS_ADC3_RESULT_ADCRESULT12" hexmask.word 0x18 0.--15. 1. "RESULT,ADC Result 12 16-bit ADC result. After the ADC completes a conversion of SOC12 the digital result is placed in this bit field." line.word 0x1A "CONTROLSS_ADC3_RESULT_ADCRESULT13" hexmask.word 0x1A 0.--15. 1. "RESULT,ADC Result 13 16-bit ADC result. After the ADC completes a conversion of SOC13 the digital result is placed in this bit field." line.word 0x1C "CONTROLSS_ADC3_RESULT_ADCRESULT14" hexmask.word 0x1C 0.--15. 1. "RESULT,ADC Result 14 16-bit ADC result. After the ADC completes a conversion of SOC14 the digital result is placed in this bit field." line.word 0x1E "CONTROLSS_ADC3_RESULT_ADCRESULT15" hexmask.word 0x1E 0.--15. 1. "RESULT,ADC Result 15 16-bit ADC result. After the ADC completes a conversion of SOC15 the digital result is placed in this bit field." rgroup.long 0x20++0xF line.long 0x0 "CONTROLSS_ADC3_RESULT_ADCPPB1RESULT" hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 1 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." line.long 0x4 "CONTROLSS_ADC3_RESULT_ADCPPB2RESULT" hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 2 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." line.long 0x8 "CONTROLSS_ADC3_RESULT_ADCPPB3RESULT" hexmask.long.word 0x8 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x8 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 3 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." line.long 0xC "CONTROLSS_ADC3_RESULT_ADCPPB4RESULT" hexmask.long.word 0xC 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0xC 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 4 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." tree.end tree "ADC4_CFG" base ad:0x502C4000 group.word 0x0++0x5 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCCTL1" rbitfld.word 0x0 13. "ADCBSY,ADC Busy. Set when ADC SOC is generated cleared by hardware four ADC clocks after negative edge of S/H pulse. Used by the ADC state machine to determine if ADC is available to sample. 0 ADC is available to sample next channel 1 ADC is busy.." "0,1" hexmask.word.byte 0x0 8.--11. 1. "ADCBSYCHN,ADC Busy Channel. Set when an ADC Start of Conversion (SOC) is generated. When ADCBSY=0: holds the value of the last converted SOC When ADCBSY=1: reflects the SOC currently being processed 0h SOC0 is currently processing or was last SOC.." bitfld.word 0x0 7. "ADCPWDNZ,ADC Power Down (active low). This bit controls the power up and power down of all the analog circuitry inside the analog core. 0 All analog circuitry inside the core is powered down 1 All analog circuitry inside the core is powered up" "0,1" bitfld.word 0x0 2. "INTPULSEPOS,ADC Interrupt Pulse Position. 0 Interrupt pulse generation occurs when ADC begins conversion (at the end of the acquisition window) plus a number of SYSCLK cycles as specified in the ADCINTCYCLE.OFFSET register. 1 Interrupt pulse.." "0,1" line.word 0x2 "CONTROLSS_ADC4_CFG_ADCCTL2" bitfld.word 0x2 7. "SIGNALMODE,SOC Signaling Mode. Selects the input mode of the converter. Use the AdcSetMode function to change the signal mode. 0 Single-ended 1 Differential" "0,1" bitfld.word 0x2 6. "RESOLUTION,SOC Conversion Resolution. Selects the resolution of the converter. Use the AdcSetMode function to change the resolution. 0 12-bit resolution 1 16-bit resolution" "0,1" hexmask.word.byte 0x2 0.--3. 1. "PRESCALE,ADC Clock Prescaler. 0000 ADCCLK = Input Clock / 1.0 0001 Invalid 0010 ADCCLK = Input Clock / 2.0 0011 ADCCLK = Input Clock / 2.5 0100 ADCCLK = Input Clock / 3.0 0101 ADCCLK = Input Clock / 3.5 0110 ADCCLK = Input Clock /.." line.word 0x4 "CONTROLSS_ADC4_CFG_ADCBURSTCTL" bitfld.word 0x4 15. "BURSTEN,SOC Burst Mode Enable. This bit enables the SOC Burst Mode of operation. 0 Burst mode is disabled. 1 Burst mode is enabled." "0,1" hexmask.word.byte 0x4 8.--11. 1. "BURSTSIZE,SOC Burst Size Select. This bit field determines how many SOCs are converted when a burst conversion sequence is started. The first SOC converted is defined by the round robin pointer which is advanced as each SOC is converted. 0h 1 SOC.." hexmask.word.byte 0x4 0.--6. 1. "BURSTTRIGSEL,SOC Burst Trigger Source Select. Configures which trigger will start a burst conversion sequence. 00h - 7Fh: See AM602 spec. for trigger defintion" rgroup.word 0x6++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCINTFLG" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag. Reading these flags indicates if the associated ADCINT pulse was generated since the last clear. 0 No ADC interrupt pulse generated 1 ADC interrupt pulse generated If the ADC interrupt is placed in continue to.." "0,1" group.word 0x8++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCINTFLGCLR" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT4 and ADCINT4RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT3 and ADCINT3RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT2 and ADCINT2RESULT flags in the ADCINTFLG register. . If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Flag Clear. Reads return 0. 0 No action 1 Clears ADCINT1 and ADCINT1RESULT flags in the ADCINTFLG register. If software sets the clear bit on the same cycle that hardware is trying to set the flag bit then hardware has.." "0,1" rgroup.word 0xA++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCINTOVF" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated then an overflow condition occurs. 0 No ADC interrupt.." "0,1" group.word 0xC++0xB line.word 0x0 "CONTROLSS_ADC4_CFG_ADCINTOVFCLR" bitfld.word 0x0 3. "ADCINT4,ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" bitfld.word 0x0 2. "ADCINT3,ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" bitfld.word 0x0 1. "ADCINT2,ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" bitfld.word 0x0 0. "ADCINT1,ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF.." "0,1" line.word 0x2 "CONTROLSS_ADC4_CFG_ADCINTSEL1N2" bitfld.word 0x2 14. "INT2CONT,ADCINT2 Continue to Interrupt Mode 0 No further ADCINT2 pulses are generated until ADCINT2 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT2 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" bitfld.word 0x2 13. "INT2E,ADCINT2 Interrupt Enable 0 ADCINT2 is disabled 1 ADCINT2 is enabled" "0,1" hexmask.word.byte 0x2 8.--11. 1. "INT2SEL,ADCINT2 EOC Source Select 0h EOC0 is trigger for ADCINT2 1h EOC1 is trigger for ADCINT2 2h EOC2 is trigger for ADCINT2 3h EOC3 is trigger for ADCINT2 4h EOC4 is trigger for ADCINT2 5h EOC5 is trigger for ADCINT2 6h EOC6 is.." bitfld.word 0x2 6. "INT1CONT,ADCINT1 Continue to Interrupt Mode 0 No further ADCINT1 pulses are generated until ADCINT1 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT1 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x2 5. "INT1E,ADCINT1 Interrupt Enable 0 ADCINT1 is disabled 1 ADCINT1 is enabled" "0,1" hexmask.word.byte 0x2 0.--3. 1. "INT1SEL,ADCINT1 EOC Source Select 0h EOC0 is trigger for ADCINT1 1h EOC1 is trigger for ADCINT1 2h EOC2 is trigger for ADCINT1 3h EOC3 is trigger for ADCINT1 4h EOC4 is trigger for ADCINT1 5h EOC5 is trigger for ADCINT1 6h EOC6 is.." line.word 0x4 "CONTROLSS_ADC4_CFG_ADCINTSEL3N4" bitfld.word 0x4 14. "INT4CONT,ADCINT4 Continue to Interrupt Mode 0 No further ADCINT4 pulses are generated until ADCINT4 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT4 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" bitfld.word 0x4 13. "INT4E,ADCINT4 Interrupt Enable 0 ADCINT4 is disabled 1 ADCINT4 is enabled" "0,1" hexmask.word.byte 0x4 8.--11. 1. "INT4SEL,ADCINT4 EOC Source Select 0h EOC0 is trigger for ADCINT4 1h EOC1 is trigger for ADCINT4 2h EOC2 is trigger for ADCINT4 3h EOC3 is trigger for ADCINT4 4h EOC4 is trigger for ADCINT4 5h EOC5 is trigger for ADCINT4 6h EOC6 is.." bitfld.word 0x4 6. "INT3CONT,ADCINT3 Continue to Interrupt Mode 0 No further ADCINT3 pulses are generated until ADCINT3 flag (in ADCINTFLG register) is cleared by user. 1 ADCINT3 pulses are generated whenever an EOC pulse is generated irrespective of whether the flag.." "0,1" newline bitfld.word 0x4 5. "INT3E,ADCINT3 Interrupt Enable 0 ADCINT3 is disabled 1 ADCINT3 is enabled" "0,1" hexmask.word.byte 0x4 0.--3. 1. "INT3SEL,ADCINT3 EOC Source Select 0h EOC0 is trigger for ADCINT3 1h EOC1 is trigger for ADCINT3 2h EOC2 is trigger for ADCINT3 3h EOC3 is trigger for ADCINT3 4h EOC4 is trigger for ADCINT3 5h EOC5 is trigger for ADCINT3 6h EOC6 is.." line.word 0x6 "CONTROLSS_ADC4_CFG_ADCSOCPRICTL" hexmask.word.byte 0x6 5.--9. 1. "RRPOINTER,Round Robin Pointer. Holds the value of the last converted round robin SOCx to be used by the round robin scheme to determine order of conversions. 00h SOC0 was last round robin SOC to convert SOC1 is highest round robin priority. 01h.." hexmask.word.byte 0x6 0.--4. 1. "SOCPRIORITY,SOC Priority Determines the cutoff point for priority mode and round robin arbitration for SOCx 00h SOC priority is handled in round robin mode for all channels. 01h SOC0 is high priority rest of channels are in round robin mode. 02h.." line.word 0x8 "CONTROLSS_ADC4_CFG_ADCINTSOCSEL1" bitfld.word 0x8 14.--15. "SOC7,SOC7 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC7. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC7. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 12.--13. "SOC6,SOC6 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC6. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC6. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 10.--11. "SOC5,SOC5 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC5. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC5. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 8.--9. "SOC4,SOC4 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC4. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC4. TRIGSEL field alone determines SOC0.." "0,1,2,3" newline bitfld.word 0x8 6.--7. "SOC3,SOC3 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC3. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC3. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 4.--5. "SOC2,SOC2 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC2. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC2. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 2.--3. "SOC1,SOC1 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC1. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC1. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0x8 0.--1. "SOC0,SOC0 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC0. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC0. TRIGSEL field alone determines SOC0.." "0,1,2,3" line.word 0xA "CONTROLSS_ADC4_CFG_ADCINTSOCSEL2" bitfld.word 0xA 14.--15. "SOC15,SOC15 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC15. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC15. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 12.--13. "SOC14,SOC14 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC14. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC14. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 10.--11. "SOC13,SOC13 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC13. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC13. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 8.--9. "SOC12,SOC12 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC12. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC12. TRIGSEL field alone determines.." "0,1,2,3" newline bitfld.word 0xA 6.--7. "SOC11,SOC11 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC11. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC11. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 4.--5. "SOC10,SOC10 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC10. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC10. TRIGSEL field alone determines.." "0,1,2,3" bitfld.word 0xA 2.--3. "SOC9,SOC9 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC9. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC9. TRIGSEL field alone determines SOC0.." "0,1,2,3" bitfld.word 0xA 0.--1. "SOC8,SOC8 ADC Interrupt Trigger Select. Selects which if any ADCINT triggers SOC8. The trigger selected in this field is in addition to the TRIGSEL field in the ADCSOCxCTL register. 00 No ADCINT will trigger SOC8. TRIGSEL field alone determines SOC0.." "0,1,2,3" rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCSOCFLG1" bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Flag. Indicates the state of SOC15 conversions. 0 No sample pending for SOC15. 1 Trigger has been received and sample is pending for SOC15. This bit will be automatically cleared when the SOC15 conversion is.." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Flag. Indicates the state of SOC14 conversions. 0 No sample pending for SOC14. 1 Trigger has been received and sample is pending for SOC14. This bit will be automatically cleared when the SOC14 conversion is.." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Flag. Indicates the state of SOC13 conversions. 0 No sample pending for SOC13. 1 Trigger has been received and sample is pending for SOC13. This bit will be automatically cleared when the SOC13 conversion is.." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Flag. Indicates the state of SOC12 conversions. 0 No sample pending for SOC12. 1 Trigger has been received and sample is pending for SOC12. This bit will be automatically cleared when the SOC12 conversion is.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Flag. Indicates the state of SOC11 conversions. 0 No sample pending for SOC11. 1 Trigger has been received and sample is pending for SOC11. This bit will be automatically cleared when the SOC11 conversion is.." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Flag. Indicates the state of SOC10 conversions. 0 No sample pending for SOC10. 1 Trigger has been received and sample is pending for SOC10. This bit will be automatically cleared when the SOC10 conversion is.." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Flag. Indicates the state of SOC9 conversions. 0 No sample pending for SOC9. 1 Trigger has been received and sample is pending for SOC9. This bit will be automatically cleared when the SOC9 conversion is started. If.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Flag. Indicates the state of SOC8 conversions. 0 No sample pending for SOC8. 1 Trigger has been received and sample is pending for SOC8. This bit will be automatically cleared when the SOC8 conversion is started. If.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Flag. Indicates the state of SOC7 conversions. 0 No sample pending for SOC7. 1 Trigger has been received and sample is pending for SOC7. This bit will be automatically cleared when the SOC7 conversion is started. If.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Flag. Indicates the state of SOC6 conversions. 0 No sample pending for SOC6. 1 Trigger has been received and sample is pending for SOC6. This bit will be automatically cleared when the SOC6 conversion is started. If.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Flag. Indicates the state of SOC5 conversions. 0 No sample pending for SOC5. 1 Trigger has been received and sample is pending for SOC5. This bit will be automatically cleared when the SOC5 conversion is started. If.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Flag. Indicates the state of SOC4 conversions. 0 No sample pending for SOC4. 1 Trigger has been received and sample is pending for SOC4. This bit will be automatically cleared when the SOC4 conversion is started. If.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Flag. Indicates the state of SOC3 conversions. 0 No sample pending for SOC3. 1 Trigger has been received and sample is pending for SOC3. This bit will be automatically cleared when the SOC3 conversion is started. If.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Flag. Indicates the state of SOC2 conversions. 0 No sample pending for SOC2. 1 Trigger has been received and sample is pending for SOC2. This bit will be automatically cleared when the SOC2 conversion is started. If.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Flag. Indicates the state of SOC1 conversions. 0 No sample pending for SOC1. 1 Trigger has been received and sample is pending for SOC1. This bit will be automatically cleared when the SOC1 conversion is started. If.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Flag. Indicates the state of SOC0 conversions. 0 No sample pending for SOC0. 1 Trigger has been received and sample is pending for SOC0. This bit will be automatically cleared when the SOC0 conversion is started. If.." "0,1" group.word 0x1A++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCSOCFRC1" bitfld.word 0x0 15. "SOC15,SOC15 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC15 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC14 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC13 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC12 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC11 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC10 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC9 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC8 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC7 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC6 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC5 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC4 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC3 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC2 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC1 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Force Start of Conversion Bit. Writing a 1 will force to 1 the SOC0 flag in the ADCSOCFLG1 register. This can be used to initiate a software initiated conversion. Writes of 0 are ignored. This bit will always read as a 0. 0 No action. 1.." "0,1" rgroup.word 0x1C++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCSOCOVF1" bitfld.word 0x0 15. "SOC15,SOC15 Start of Conversion Overflow Flag. Indicates an SOC15 event was generated in hardware while an existing SOC15 event was already pending. 0 No SOC15 event overflow. 1 SOC15 event overflow. An overflow condition does not stop SOC15.." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Start of Conversion Overflow Flag. Indicates an SOC14 event was generated in hardware while an existing SOC14 event was already pending. 0 No SOC14 event overflow. 1 SOC14 event overflow. An overflow condition does not stop SOC14.." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Start of Conversion Overflow Flag. Indicates an SOC13 event was generated in hardware while an existing SOC13 event was already pending. 0 No SOC13 event overflow. 1 SOC13 event overflow. An overflow condition does not stop SOC13.." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Start of Conversion Overflow Flag. Indicates an SOC12 event was generated in hardware while an existing SOC12 event was already pending. 0 No SOC12 event overflow. 1 SOC12 event overflow. An overflow condition does not stop SOC12.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Start of Conversion Overflow Flag. Indicates an SOC11 event was generated in hardware while an existing SOC11 event was already pending. 0 No SOC11 event overflow. 1 SOC11 event overflow. An overflow condition does not stop SOC11.." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Start of Conversion Overflow Flag. Indicates an SOC10 event was generated in hardware while an existing SOC10 event was already pending. 0 No SOC10 event overflow. 1 SOC10 event overflow. An overflow condition does not stop SOC10.." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Start of Conversion Overflow Flag. Indicates an SOC9 event was generated in hardware while an existing SOC9 event was already pending. 0 No SOC9 event overflow. 1 SOC9 event overflow. An overflow condition does not stop SOC9 events from.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Start of Conversion Overflow Flag. Indicates an SOC8 event was generated in hardware while an existing SOC8 event was already pending. 0 No SOC8 event overflow. 1 SOC8 event overflow. An overflow condition does not stop SOC8 events from.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Start of Conversion Overflow Flag. Indicates an SOC7 event was generated in hardware while an existing SOC7 event was already pending. 0 No SOC7 event overflow. 1 SOC7 event overflow. An overflow condition does not stop SOC7 events from.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Start of Conversion Overflow Flag. Indicates an SOC6 event was generated in hardware while an existing SOC6 event was already pending. 0 No SOC6 event overflow. 1 SOC6 event overflow. An overflow condition does not stop SOC6 events from.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Start of Conversion Overflow Flag. Indicates an SOC5 event was generated in hardware while an existing SOC5 event was already pending. 0 No SOC5 event overflow. 1 SOC5 event overflow. An overflow condition does not stop SOC5 events from.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Start of Conversion Overflow Flag. Indicates an SOC4 event was generated in hardware while an existing SOC4 event was already pending. 0 No SOC4 event overflow. 1 SOC4 event overflow. An overflow condition does not stop SOC4 events from.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Start of Conversion Overflow Flag. Indicates an SOC3 event was generated in hardware while an existing SOC3 event was already pending. 0 No SOC3 event overflow. 1 SOC3 event overflow. An overflow condition does not stop SOC3 events from.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Start of Conversion Overflow Flag. Indicates an SOC2 event was generated in hardware while an existing SOC2 event was already pending. 0 No SOC2 event overflow. 1 SOC2 event overflow. An overflow condition does not stop SOC2 events from.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Start of Conversion Overflow Flag. Indicates an SOC1 event was generated in hardware while an existing SOC1 event was already pending. 0 No SOC1 event overflow. 1 SOC1 event overflow. An overflow condition does not stop SOC1 events from.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Start of Conversion Overflow Flag. Indicates an SOC0 event was generated in hardware while an existing SOC0 event was already pending. 0 No SOC0 event overflow. 1 SOC0 event overflow. An overflow condition does not stop SOC0 events from.." "0,1" group.word 0x1E++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCSOCOVFCLR1" bitfld.word 0x0 15. "SOC15,SOC15 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC15 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC15 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 14. "SOC14,SOC14 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC14 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC14 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 13. "SOC13,SOC13 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC13 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC13 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 12. "SOC12,SOC12 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC12 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC12 overflow flag. If software tries to.." "0,1" newline bitfld.word 0x0 11. "SOC11,SOC11 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC11 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC11 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 10. "SOC10,SOC10 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC10 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC10 overflow flag. If software tries to.." "0,1" bitfld.word 0x0 9. "SOC9,SOC9 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC9 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC9 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 8. "SOC8,SOC8 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC8 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC8 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 7. "SOC7,SOC7 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC7 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC7 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 6. "SOC6,SOC6 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC6 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC6 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 5. "SOC5,SOC5 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC5 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC5 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 4. "SOC4,SOC4 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC4 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC4 overflow flag. If software tries to set.." "0,1" newline bitfld.word 0x0 3. "SOC3,SOC3 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC3 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC3 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 2. "SOC2,SOC2 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC2 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC2 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 1. "SOC1,SOC1 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC1 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC1 overflow flag. If software tries to set.." "0,1" bitfld.word 0x0 0. "SOC0,SOC0 Clear Start of Conversion Overflow Bit. Writing a 1 will clear the SOC0 overflow flag in the ADCSOCOVF1 register. Writes of 0 are ignored. Reads will always return a 0. 0 No action. 1 Clear SOC0 overflow flag. If software tries to set.." "0,1" group.long 0x20++0x3F line.long 0x0 "CONTROLSS_ADC4_CFG_ADCSOC0CTL" hexmask.long.byte 0x0 20.--26. 1. "TRIGSEL,SOC0 Trigger Source Select. Along with the SOC0 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC0 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x0 15.--19. 1. "CHSEL,SOC0 Channel Select. Selects the channel to be converted when SOC0 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x0 0.--8. 1. "ACQPS,SOC0 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x4 "CONTROLSS_ADC4_CFG_ADCSOC1CTL" hexmask.long.byte 0x4 20.--26. 1. "TRIGSEL,SOC1 Trigger Source Select. Along with the SOC1 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC1 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x4 15.--19. 1. "CHSEL,SOC1 Channel Select. Selects the channel to be converted when SOC1 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x4 0.--8. 1. "ACQPS,SOC1 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x8 "CONTROLSS_ADC4_CFG_ADCSOC2CTL" hexmask.long.byte 0x8 20.--26. 1. "TRIGSEL,SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x8 15.--19. 1. "CHSEL,SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x8 0.--8. 1. "ACQPS,SOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0xC "CONTROLSS_ADC4_CFG_ADCSOC3CTL" hexmask.long.byte 0xC 20.--26. 1. "TRIGSEL,SOC3 Trigger Source Select. Along with the SOC3 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC3 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0xC 15.--19. 1. "CHSEL,SOC3 Channel Select. Selects the channel to be converted when SOC3 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0xC 0.--8. 1. "ACQPS,SOC3 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x10 "CONTROLSS_ADC4_CFG_ADCSOC4CTL" hexmask.long.byte 0x10 20.--26. 1. "TRIGSEL,SOC4 Trigger Source Select. Along with the SOC4 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC4 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x10 15.--19. 1. "CHSEL,SOC4 Channel Select. Selects the channel to be converted when SOC4 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x10 0.--8. 1. "ACQPS,SOC4 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x14 "CONTROLSS_ADC4_CFG_ADCSOC5CTL" hexmask.long.byte 0x14 20.--26. 1. "TRIGSEL,SOC5 Trigger Source Select. Along with the SOC5 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC5 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x14 15.--19. 1. "CHSEL,SOC5 Channel Select. Selects the channel to be converted when SOC5 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x14 0.--8. 1. "ACQPS,SOC5 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x18 "CONTROLSS_ADC4_CFG_ADCSOC6CTL" hexmask.long.byte 0x18 20.--26. 1. "TRIGSEL,SOC6 Trigger Source Select. Along with the SOC6 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC6 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x18 15.--19. 1. "CHSEL,SOC6 Channel Select. Selects the channel to be converted when SOC6 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x18 0.--8. 1. "ACQPS,SOC6 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x1C "CONTROLSS_ADC4_CFG_ADCSOC7CTL" hexmask.long.byte 0x1C 20.--26. 1. "TRIGSEL,SOC7 Trigger Source Select. Along with the SOC7 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC7 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x1C 15.--19. 1. "CHSEL,SOC7 Channel Select. Selects the channel to be converted when SOC7 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x1C 0.--8. 1. "ACQPS,SOC7 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x20 "CONTROLSS_ADC4_CFG_ADCSOC8CTL" hexmask.long.byte 0x20 20.--26. 1. "TRIGSEL,SOC8 Trigger Source Select. Along with the SOC8 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC8 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x20 15.--19. 1. "CHSEL,SOC8 Channel Select. Selects the channel to be converted when SOC8 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x20 0.--8. 1. "ACQPS,SOC8 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x24 "CONTROLSS_ADC4_CFG_ADCSOC9CTL" hexmask.long.byte 0x24 20.--26. 1. "TRIGSEL,SOC9 Trigger Source Select. Along with the SOC9 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC9 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. 00h -.." hexmask.long.byte 0x24 15.--19. 1. "CHSEL,SOC9 Channel Select. Selects the channel to be converted when SOC9 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x24 0.--8. 1. "ACQPS,SOC9 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x28 "CONTROLSS_ADC4_CFG_ADCSOC10CTL" hexmask.long.byte 0x28 20.--26. 1. "TRIGSEL,SOC10 Trigger Source Select. Along with the SOC10 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC10 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x28 15.--19. 1. "CHSEL,SOC10 Channel Select. Selects the channel to be converted when SOC10 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x28 0.--8. 1. "ACQPS,SOC10 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x2C "CONTROLSS_ADC4_CFG_ADCSOC11CTL" hexmask.long.byte 0x2C 20.--26. 1. "TRIGSEL,SOC11 Trigger Source Select. Along with the SOC11 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC11 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x2C 15.--19. 1. "CHSEL,SOC11 Channel Select. Selects the channel to be converted when SOC11 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x2C 0.--8. 1. "ACQPS,SOC11 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x30 "CONTROLSS_ADC4_CFG_ADCSOC12CTL" hexmask.long.byte 0x30 20.--26. 1. "TRIGSEL,SOC12 Trigger Source Select. Along with the SOC12 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC12 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x30 15.--19. 1. "CHSEL,SOC12 Channel Select. Selects the channel to be converted when SOC12 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x30 0.--8. 1. "ACQPS,SOC12 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x34 "CONTROLSS_ADC4_CFG_ADCSOC13CTL" hexmask.long.byte 0x34 20.--26. 1. "TRIGSEL,SOC13 Trigger Source Select. Along with the SOC13 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC13 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x34 15.--19. 1. "CHSEL,SOC13 Channel Select. Selects the channel to be converted when SOC13 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x34 0.--8. 1. "ACQPS,SOC13 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x38 "CONTROLSS_ADC4_CFG_ADCSOC14CTL" hexmask.long.byte 0x38 20.--26. 1. "TRIGSEL,SOC14 Trigger Source Select. Along with the SOC14 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC14 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x38 15.--19. 1. "CHSEL,SOC14 Channel Select. Selects the channel to be converted when SOC14 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x38 0.--8. 1. "ACQPS,SOC14 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." line.long 0x3C "CONTROLSS_ADC4_CFG_ADCSOC15CTL" hexmask.long.byte 0x3C 20.--26. 1. "TRIGSEL,SOC15 Trigger Source Select. Along with the SOC15 field in the ADCINTSOCSEL1 register this bit field configures which trigger will set the SOC15 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it." hexmask.long.byte 0x3C 15.--19. 1. "CHSEL,SOC15 Channel Select. Selects the channel to be converted when SOC15 is received by the ADC. 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31" hexmask.long.word 0x3C 0.--8. 1. "ACQPS,SOC15 Acquisition Prescale. Controls the sample and hold window for this SOC. The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The device datasheet will also specify a minimum sample and hold.." rgroup.word 0x60++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCEVTSTAT" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Flag. When set indicates the ADCPPB4RESULT register has changed sign. This bit is gated by EOC signal." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Flag. When set indicates the ADCPPB3RESULT register has changed sign. This bit is gated by EOC signal." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Flag. When set indicates the ADCPPB2RESULT register has changed sign. This bit is gated by EOC signal." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Flag. When set indicates the ADCPPB1RESULT register has changed sign. This bit is gated by EOC signal." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Flag. When set indicates a digital compare trip low event has occurred." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Flag. When set indicates a digital compare trip high event has occurred." "0,1" group.word 0x64++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCEVTCLR" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Clear. Clears the corresponding zero crossing flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Clear. Clears the corresponding trip low flag in the ADCEVTSTAT register." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Clear. Clears the corresponding trip high flag in the ADCEVTSTAT register." "0,1" group.word 0x68++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCEVTSEL" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Event Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM.." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Event Enable. Setting this bit allows the corresponding rising trip low flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Event Enable. Setting this bit allows the corresponding rising trip high flag to activate the event signal to the PWM blocks. The flag must be cleared before it can produce additional events to the PWM blocks." "0,1" group.word 0x6C++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCEVTINTSEL" bitfld.word 0x0 14. "PPB4ZERO,Post Processing Block 4 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" bitfld.word 0x0 13. "PPB4TRIPLO,Post Processing Block 4 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" bitfld.word 0x0 12. "PPB4TRIPHI,Post Processing Block 4 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" bitfld.word 0x0 10. "PPB3ZERO,Post Processing Block 3 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" newline bitfld.word 0x0 9. "PPB3TRIPLO,Post Processing Block 3 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" bitfld.word 0x0 8. "PPB3TRIPHI,Post Processing Block 3 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" bitfld.word 0x0 6. "PPB2ZERO,Post Processing Block 2 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" bitfld.word 0x0 5. "PPB2TRIPLO,Post Processing Block 2 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" newline bitfld.word 0x0 4. "PPB2TRIPHI,Post Processing Block 2 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" bitfld.word 0x0 2. "PPB1ZERO,Post Processing Block 1 Zero Crossing Interrupt Enable. Setting this bit allows the corresponding rising zero crossing flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts.." "0,1" bitfld.word 0x0 1. "PPB1TRIPLO,Post Processing Block 1 Trip Low Interrupt Enable. Setting this bit allows the corresponding rising trip low flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the PIE." "0,1" bitfld.word 0x0 0. "PPB1TRIPHI,Post Processing Block 1 Trip High Interrupt Enable. Setting this bit allows the corresponding rising trip high flag to activate the event interrupt signal to the PIE. The flag must be cleared before it can produce additional interrupts to the.." "0,1" group.word 0x70++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCOSDETECT" bitfld.word 0x0 0.--2. "DETECTCFG,ADC Opens and Shorts Detect Configuration. This bit field defines the open/shorts detection circuit state. 0h Open/Shorts detection circuit is disabled. 1h Open/Shorts detection circuit is enabled at zero scale. 2h Open/Shorts.." "0,1,2,3,4,5,6,7" rgroup.word 0x72++0x3 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCCOUNTER" hexmask.word 0x0 0.--11. 1. "FREECOUNT,ADC Free Running Counter Value. This bit field reflects the status of the free running ADC counter." line.word 0x2 "CONTROLSS_ADC4_CFG_ADCREV" hexmask.word.byte 0x2 8.--15. 1. "REV,ADC Revision. To allow documentation of differences between revisions. First version is labeled as 00h." hexmask.word.byte 0x2 0.--7. 1. "TYPE,ADC Type. Always set to 5 for this ADC." group.word 0x76++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCOFFTRIM" hexmask.word.byte 0x0 0.--7. 1. "OFFTRIM,ADC Offset Trim Adjusts the conversion results of the converter up or down to account for offset error in the ADC. A factory trim setting will be loaded during device boot. Offset can be corrected in the range of +7 to -8 LSBs. Value is.." group.long 0x7C++0x3 line.long 0x0 "CONTROLSS_ADC4_CFG_ADCCONFIG" hexmask.long 0x0 0.--31. 1. "CONFIG,ADC Configuration. This bit field is used for TI internal testing/debugging." group.word 0x80++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCPPB1CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 1 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 1 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 1 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0x82++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCPPB1STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 1 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x84++0x3 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCPPB1OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 1 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC4_CFG_ADCPPB1OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 1 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x88++0x7 line.long 0x0 "CONTROLSS_ADC4_CFG_ADCPPB1TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 1 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC4_CFG_ADCPPB1TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 1 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 1 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB1RESULT register. In 12-bit mode bits 12:0.." group.word 0x90++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCPPB2CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 2 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 2 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 2 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0x92++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCPPB2STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 2 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0x94++0x3 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCPPB2OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 2 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC4_CFG_ADCPPB2OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 2 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0x98++0x7 line.long 0x0 "CONTROLSS_ADC4_CFG_ADCPPB2TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 2 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC4_CFG_ADCPPB2TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 2 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 2 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB2RESULT register. In 12-bit mode bits 12:0.." group.word 0xA0++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCPPB3CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 3 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 3 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 3 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0xA2++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCPPB3STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 3 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xA4++0x3 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCPPB3OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 3 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC4_CFG_ADCPPB3OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 3 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xA8++0x7 line.long 0x0 "CONTROLSS_ADC4_CFG_ADCPPB3TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 3 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC4_CFG_ADCPPB3TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 3 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 3 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB3RESULT register. In 12-bit mode bits 12:0.." group.word 0xB0++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCPPB4CONFIG" bitfld.word 0x0 5. "CBCEN,ADC Post Processing Block Cycle By Cycle Enable. When set this bit enables the post conversion hardware processing circuit to automatically clear the ADCEVTSTAT on a conversion if the event condition is no longer present." "0,1" bitfld.word 0x0 4. "TWOSCOMPEN,ADC Post Processing Block 4 Two's Complement Enable. When set this bit enables the post conversion hardware processing circuit that performs a two's complement on the output of the offset/reference subtraction unit before storing the result in.." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CONFIG,ADC Post Processing Block 4 Configuration. This bit field defines which SOC/EOC/RESULT is assocatied with this post processing block. 0000 SOC0/EOC0/RESULT0 is associated with post processing block 4 0001 SOC1/EOC1/RESULT1 is associated.." rgroup.word 0xB2++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCPPB4STAMP" hexmask.word 0x0 0.--11. 1. "DLYSTAMP,ADC Post Processing Block 4 Delay Time Stamp. When an SOC starts sampling the value contained in REQSTAMP is subtracted from the value in ADCCOUNTER.FREECOUNT and loaded into this bit field thereby giving the number of system clock cycles delay.." group.word 0xB4++0x3 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCPPB4OFFCAL" hexmask.word 0x0 0.--9. 1. "OFFCAL,ADC Post Processing Block 4 Offset Correction. This bit field can be used to digitally remove any system level offset inherent in the ADCIN circuit. This 10-bit signed value is subtracted from the ADC output before being stored in the ADCRESULT.." line.word 0x2 "CONTROLSS_ADC4_CFG_ADCPPB4OFFREF" hexmask.word 0x2 0.--15. 1. "OFFREF,ADC Post Processing Block 4 Offset Correction. This bit field can be used to either calculate the feedback error or convert a unipolar signal to bipolar by subtracting a reference value. This 16-bit unsigned value is subtracted from the ADCRESULT.." group.long 0xB8++0x7 line.long 0x0 "CONTROLSS_ADC4_CFG_ADCPPB4TRIPHI" bitfld.long 0x0 16. "HSIGN,High Limit Sign Bit. This is the sign bit (17th bit) to the LIMITHI bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x0 0.--15. 1. "LIMITHI,ADC Post Processing Block 4 Trip High Limit. This value sets the digital comparator trip high limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits.." line.long 0x4 "CONTROLSS_ADC4_CFG_ADCPPB4TRIPLO" hexmask.long.word 0x4 20.--31. 1. "REQSTAMP,ADC Post Processing Block 4 Request Time Stamp. When a trigger sets the associated SOC flag in the ADCSOCFLG1 register the value of ADCCOUNTER.FREECOUNT is loaded into this bit field." bitfld.long 0x4 16. "LSIGN,Low Limit Sign Bit. This is the sign bit (17th bit) to the LIMITLO bit field when in 16-bit ADC mode." "0,1" hexmask.long.word 0x4 0.--15. 1. "LIMITLO,ADC Post Processing Block 4 Trip Low Limit. This value sets the digital comparator trip low limit. In 16-bit mode all 17 bits will be compared against the 17 bits of the PPBRESULT bit field of the ADCPPB4RESULT register. In 12-bit mode bits 12:0.." group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_ADC4_CFG_ADCINTCYCLE" hexmask.word 0x0 0.--15. 1. "DELAY,ADC Early Interrupt Generation Cycle Delay: Defines the delay from the fall edge of ADCSOC in terms of system clock cycles for the interrupt to be generated." group.long 0xE0++0x17 line.long 0x0 "CONTROLSS_ADC4_CFG_ADCINLTRIM1" hexmask.long 0x0 0.--31. 1. "INLTRIM31TO0,ADC Linearity Trim Bits 31-0. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x4 "CONTROLSS_ADC4_CFG_ADCINLTRIM2" hexmask.long 0x4 0.--31. 1. "INLTRIM63TO32,ADC Linearity Trim Bits 63-32. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x8 "CONTROLSS_ADC4_CFG_ADCINLTRIM3" hexmask.long 0x8 0.--31. 1. "INLTRIM95TO64,ADC Linearity Trim Bits 95-64. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0xC "CONTROLSS_ADC4_CFG_ADCINLTRIM4" hexmask.long 0xC 0.--31. 1. "INLTRIM127TO96,ADC Linearity Trim Bits 127-96. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x10 "CONTROLSS_ADC4_CFG_ADCINLTRIM5" hexmask.long 0x10 0.--31. 1. "INLTRIM159TO128,ADC Linearity Trim Bits 159-128. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." line.long 0x14 "CONTROLSS_ADC4_CFG_ADCINLTRIM6" hexmask.long 0x14 0.--31. 1. "INLTRIM191TO160,ADC Linearity Trim Bits 191-160. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet.." group.long 0xFC++0x3 line.long 0x0 "CONTROLSS_ADC4_CFG_ADCINLTRIMCTL" hexmask.long.word 0x0 16.--31. 1. "KEY,ADC Linearity Trim Control Write Key. Any write to this register must contain the value 0xA5A5 in these bit locations. If a write request attempts to load any other value into these bits the write for the entire register is ignored. These bits.." hexmask.long.byte 0x0 1.--5. 1. "CALIBSTEP,ADC Linearity Calibration Step. Defines which of the 24 steps of calibration is to be executed. Never set this bit field while the ADC SELFTRIM is in progress. The R-M-W operation could unintentionally set the CALIBMODE bit again." bitfld.long 0x0 0. "CALIBMODE,ADC Linearity Calibration Mode." "0,1" tree.end tree "ADC4_RESULT" base ad:0x50104000 rgroup.word 0x0++0x1F line.word 0x0 "CONTROLSS_ADC4_RESULT_ADCRESULT0" hexmask.word 0x0 0.--15. 1. "RESULT,ADC Result 0 16-bit ADC result. After the ADC completes a conversion of SOC0 the digital result is placed in this bit field." line.word 0x2 "CONTROLSS_ADC4_RESULT_ADCRESULT1" hexmask.word 0x2 0.--15. 1. "RESULT,ADC Result 1 16-bit ADC result. After the ADC completes a conversion of SOC1 the digital result is placed in this bit field." line.word 0x4 "CONTROLSS_ADC4_RESULT_ADCRESULT2" hexmask.word 0x4 0.--15. 1. "RESULT,ADC Result 2 16-bit ADC result. After the ADC completes a conversion of SOC2 the digital result is placed in this bit field." line.word 0x6 "CONTROLSS_ADC4_RESULT_ADCRESULT3" hexmask.word 0x6 0.--15. 1. "RESULT,ADC Result 3 16-bit ADC result. After the ADC completes a conversion of SOC3 the digital result is placed in this bit field." line.word 0x8 "CONTROLSS_ADC4_RESULT_ADCRESULT4" hexmask.word 0x8 0.--15. 1. "RESULT,ADC Result 4 16-bit ADC result. After the ADC completes a conversion of SOC4 the digital result is placed in this bit field." line.word 0xA "CONTROLSS_ADC4_RESULT_ADCRESULT5" hexmask.word 0xA 0.--15. 1. "RESULT,ADC Result 5 16-bit ADC result. After the ADC completes a conversion of SOC5 the digital result is placed in this bit field." line.word 0xC "CONTROLSS_ADC4_RESULT_ADCRESULT6" hexmask.word 0xC 0.--15. 1. "RESULT,ADC Result 6 16-bit ADC result. After the ADC completes a conversion of SOC6 the digital result is placed in this bit field." line.word 0xE "CONTROLSS_ADC4_RESULT_ADCRESULT7" hexmask.word 0xE 0.--15. 1. "RESULT,ADC Result 7 16-bit ADC result. After the ADC completes a conversion of SOC7 the digital result is placed in this bit field." line.word 0x10 "CONTROLSS_ADC4_RESULT_ADCRESULT8" hexmask.word 0x10 0.--15. 1. "RESULT,ADC Result 8 16-bit ADC result. After the ADC completes a conversion of SOC8 the digital result is placed in this bit field." line.word 0x12 "CONTROLSS_ADC4_RESULT_ADCRESULT9" hexmask.word 0x12 0.--15. 1. "RESULT,ADC Result 9 16-bit ADC result. After the ADC completes a conversion of SOC9 the digital result is placed in this bit field." line.word 0x14 "CONTROLSS_ADC4_RESULT_ADCRESULT10" hexmask.word 0x14 0.--15. 1. "RESULT,ADC Result 10 16-bit ADC result. After the ADC completes a conversion of SOC10 the digital result is placed in this bit field." line.word 0x16 "CONTROLSS_ADC4_RESULT_ADCRESULT11" hexmask.word 0x16 0.--15. 1. "RESULT,ADC Result 11 16-bit ADC result. After the ADC completes a conversion of SOC11 the digital result is placed in this bit field." line.word 0x18 "CONTROLSS_ADC4_RESULT_ADCRESULT12" hexmask.word 0x18 0.--15. 1. "RESULT,ADC Result 12 16-bit ADC result. After the ADC completes a conversion of SOC12 the digital result is placed in this bit field." line.word 0x1A "CONTROLSS_ADC4_RESULT_ADCRESULT13" hexmask.word 0x1A 0.--15. 1. "RESULT,ADC Result 13 16-bit ADC result. After the ADC completes a conversion of SOC13 the digital result is placed in this bit field." line.word 0x1C "CONTROLSS_ADC4_RESULT_ADCRESULT14" hexmask.word 0x1C 0.--15. 1. "RESULT,ADC Result 14 16-bit ADC result. After the ADC completes a conversion of SOC14 the digital result is placed in this bit field." line.word 0x1E "CONTROLSS_ADC4_RESULT_ADCRESULT15" hexmask.word 0x1E 0.--15. 1. "RESULT,ADC Result 15 16-bit ADC result. After the ADC completes a conversion of SOC15 the digital result is placed in this bit field." rgroup.long 0x20++0xF line.long 0x0 "CONTROLSS_ADC4_RESULT_ADCPPB1RESULT" hexmask.long.word 0x0 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x0 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 1 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." line.long 0x4 "CONTROLSS_ADC4_RESULT_ADCPPB2RESULT" hexmask.long.word 0x4 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x4 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 2 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." line.long 0x8 "CONTROLSS_ADC4_RESULT_ADCPPB3RESULT" hexmask.long.word 0x8 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0x8 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 3 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." line.long 0xC "CONTROLSS_ADC4_RESULT_ADCPPB4RESULT" hexmask.long.word 0xC 16.--31. 1. "SIGN,Sign Extended Bits. These bits reflect the same value as bit 16. NOTE: If the conversion associated with this Post Processing Block is a 12-bit conversion the SIGN bits extend down to bit 12 and all reflect the same value as bit 12." hexmask.long.word 0xC 0.--15. 1. "PPBRESULT,ADC Post Processing Block Result 4 The result of the offset/reference subtraction post conversion processing is stored in this register. If ADCINTFLG is polled in reading PPBRESULT user needs to add a NOP instruction to ensure that post.." tree.end tree.end tree "CMPSSA" tree "CMPSSA0" base ad:0x50200000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSA0_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage (default)1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage (default)1 negative mux selects INL_3p3v" "0,1" line.word 0x2 "CONTROLSS_CMPSSA0_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSA0_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSA0_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSA0_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSA0_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSA0_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSA0_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSA0_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSA0_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSA0_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSA0_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSA0_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSA0_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSA0_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSA0_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSA0_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSA0_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSA0_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSA0_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSA0_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSA0_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSA0_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSA0_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSA0_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSA1" base ad:0x50201000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSA1_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage (default)1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage (default)1 negative mux selects INL_3p3v" "0,1" line.word 0x2 "CONTROLSS_CMPSSA1_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSA1_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSA1_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSA1_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSA1_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSA1_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSA1_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSA1_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSA1_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSA1_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSA1_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSA1_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSA1_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSA1_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSA1_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSA1_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSA1_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSA1_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSA1_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSA1_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSA1_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSA1_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSA1_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSA1_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSA2" base ad:0x50202000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSA2_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage (default)1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage (default)1 negative mux selects INL_3p3v" "0,1" line.word 0x2 "CONTROLSS_CMPSSA2_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSA2_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSA2_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSA2_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSA2_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSA2_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSA2_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSA2_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSA2_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSA2_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSA2_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSA2_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSA2_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSA2_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSA2_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSA2_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSA2_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSA2_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSA2_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSA2_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSA2_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSA2_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSA2_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSA2_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSA3" base ad:0x50203000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSA3_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage (default)1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage (default)1 negative mux selects INL_3p3v" "0,1" line.word 0x2 "CONTROLSS_CMPSSA3_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSA3_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSA3_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSA3_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSA3_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSA3_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSA3_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSA3_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSA3_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSA3_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSA3_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSA3_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSA3_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSA3_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSA3_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSA3_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSA3_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSA3_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSA3_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSA3_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSA3_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSA3_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSA3_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSA3_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSA4" base ad:0x50204000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSA4_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage (default)1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage (default)1 negative mux selects INL_3p3v" "0,1" line.word 0x2 "CONTROLSS_CMPSSA4_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSA4_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSA4_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSA4_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSA4_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSA4_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSA4_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSA4_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSA4_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSA4_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSA4_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSA4_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSA4_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSA4_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSA4_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSA4_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSA4_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSA4_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSA4_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSA4_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSA4_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSA4_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSA4_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSA4_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSA5" base ad:0x50205000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSA5_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage (default)1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage (default)1 negative mux selects INL_3p3v" "0,1" line.word 0x2 "CONTROLSS_CMPSSA5_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSA5_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSA5_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSA5_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSA5_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSA5_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSA5_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSA5_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSA5_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSA5_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSA5_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSA5_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSA5_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSA5_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSA5_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSA5_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSA5_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSA5_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSA5_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSA5_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSA5_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSA5_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSA5_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSA5_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSA6" base ad:0x50206000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSA6_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage (default)1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage (default)1 negative mux selects INL_3p3v" "0,1" line.word 0x2 "CONTROLSS_CMPSSA6_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSA6_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSA6_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSA6_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSA6_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSA6_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSA6_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSA6_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSA6_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSA6_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSA6_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSA6_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSA6_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSA6_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSA6_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSA6_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSA6_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSA6_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSA6_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSA6_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSA6_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSA6_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSA6_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSA6_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSA7" base ad:0x50207000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSA7_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage (default)1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage (default)1 negative mux selects INL_3p3v" "0,1" line.word 0x2 "CONTROLSS_CMPSSA7_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSA7_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSA7_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSA7_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSA7_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSA7_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSA7_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSA7_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSA7_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSA7_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSA7_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSA7_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSA7_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSA7_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSA7_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSA7_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSA7_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSA7_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSA7_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSA7_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSA7_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSA7_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSA7_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSA7_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSA8" base ad:0x50208000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSA8_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage (default)1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage (default)1 negative mux selects INL_3p3v" "0,1" line.word 0x2 "CONTROLSS_CMPSSA8_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSA8_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSA8_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSA8_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSA8_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSA8_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSA8_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSA8_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSA8_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSA8_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSA8_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSA8_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSA8_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSA8_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSA8_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSA8_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSA8_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSA8_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSA8_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSA8_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSA8_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSA8_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSA8_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSA8_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSA9" base ad:0x50209000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSA9_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "COMPLSOURCE,CompL Pos Mux Select0 positive mux selects INL_3p3v voltage (default)1 postive mux selects INH_3p3v" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "COMPHSOURCE,CompH neg Mux slect0 negative mux selects DAC voltage (default)1 negative mux selects INL_3p3v" "0,1" line.word 0x2 "CONTROLSS_CMPSSA9_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSA9_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSA9_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSA9_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSA9_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSA9_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSA9_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSA9_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSA9_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSA9_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSA9_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSA9_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSA9_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSA9_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSA9_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSA9_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSA9_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSA9_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSA9_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSA9_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSA9_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSA9_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSA9_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSA9_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree.end tree "CMPSSB" tree "CMPSSB0" base ad:0x50220000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSB0_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "RESERVED,Reserved for CMPSSB" "0,1" line.word 0x2 "CONTROLSS_CMPSSB0_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSB0_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSB0_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSB0_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSB0_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSB0_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSB0_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSB0_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSB0_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSB0_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSB0_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSB0_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSB0_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSB0_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSB0_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSB0_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSB0_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSB0_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSB0_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSB0_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSB0_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSB0_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSB0_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSB0_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSB1" base ad:0x50221000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSB1_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "RESERVED,Reserved for CMPSSB" "0,1" line.word 0x2 "CONTROLSS_CMPSSB1_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSB1_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSB1_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSB1_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSB1_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSB1_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSB1_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSB1_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSB1_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSB1_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSB1_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSB1_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSB1_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSB1_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSB1_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSB1_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSB1_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSB1_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSB1_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSB1_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSB1_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSB1_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSB1_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSB1_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSB2" base ad:0x50222000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSB2_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "RESERVED,Reserved for CMPSSB" "0,1" line.word 0x2 "CONTROLSS_CMPSSB2_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSB2_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSB2_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSB2_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSB2_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSB2_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSB2_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSB2_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSB2_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSB2_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSB2_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSB2_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSB2_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSB2_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSB2_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSB2_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSB2_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSB2_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSB2_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSB2_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSB2_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSB2_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSB2_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSB2_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSB3" base ad:0x50223000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSB3_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "RESERVED,Reserved for CMPSSB" "0,1" line.word 0x2 "CONTROLSS_CMPSSB3_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSB3_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSB3_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSB3_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSB3_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSB3_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSB3_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSB3_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSB3_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSB3_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSB3_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSB3_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSB3_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSB3_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSB3_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSB3_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSB3_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSB3_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSB3_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSB3_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSB3_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSB3_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSB3_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSB3_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSB4" base ad:0x50224000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSB4_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "RESERVED,Reserved for CMPSSB" "0,1" line.word 0x2 "CONTROLSS_CMPSSB4_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSB4_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSB4_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSB4_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSB4_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSB4_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSB4_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSB4_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSB4_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSB4_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSB4_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSB4_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSB4_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSB4_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSB4_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSB4_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSB4_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSB4_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSB4_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSB4_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSB4_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSB4_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSB4_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSB4_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSB5" base ad:0x50225000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSB5_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "RESERVED,Reserved for CMPSSB" "0,1" line.word 0x2 "CONTROLSS_CMPSSB5_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSB5_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSB5_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSB5_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSB5_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSB5_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSB5_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSB5_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSB5_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSB5_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSB5_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSB5_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSB5_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSB5_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSB5_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSB5_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSB5_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSB5_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSB5_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSB5_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSB5_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSB5_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSB5_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSB5_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSB6" base ad:0x50226000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSB6_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "RESERVED,Reserved for CMPSSB" "0,1" line.word 0x2 "CONTROLSS_CMPSSB6_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSB6_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSB6_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSB6_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSB6_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSB6_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSB6_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSB6_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSB6_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSB6_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSB6_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSB6_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSB6_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSB6_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSB6_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSB6_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSB6_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSB6_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSB6_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSB6_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSB6_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSB6_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSB6_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSB6_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSB7" base ad:0x50227000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSB7_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "RESERVED,Reserved for CMPSSB" "0,1" line.word 0x2 "CONTROLSS_CMPSSB7_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSB7_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSB7_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSB7_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSB7_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSB7_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSB7_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSB7_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSB7_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSB7_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSB7_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSB7_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSB7_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSB7_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSB7_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSB7_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSB7_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSB7_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSB7_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSB7_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSB7_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSB7_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSB7_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSB7_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSB8" base ad:0x50228000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSB8_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "RESERVED,Reserved for CMPSSB" "0,1" line.word 0x2 "CONTROLSS_CMPSSB8_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSB8_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSB8_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSB8_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSB8_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSB8_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSB8_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSB8_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSB8_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSB8_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSB8_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSB8_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSB8_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSB8_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSB8_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSB8_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSB8_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSB8_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSB8_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSB8_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSB8_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSB8_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSB8_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSB8_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree "CMPSSB9" base ad:0x50229000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_CMPSSB9_COMPCTL" bitfld.word 0x0 15. "COMPDACE,Comparator/DAC enable. 0 Comparator/DAC disabled 1 Comparator/DAC enabled" "0,1" bitfld.word 0x0 14. "ASYNCLEN,Low comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPLSEL=3 or CTRIPOUTLSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" newline bitfld.word 0x0 12.--13. "CTRIPOUTLSEL,Low comparator CTRIPOUTL source select. 0 Asynchronous comparator output drives CTRIPOUTL 1 Synchronous comparator output drives CTRIPOUTL 2 Output of digital filter drives CTRIPOUTL 3 Latched output of digital filter drives.." "0,1,2,3" bitfld.word 0x0 10.--11. "CTRIPLSEL,Low comparator CTRIPL source select. 0 Asynchronous comparator output drives CTRIPL 1 Synchronous comparator output drives CTRIPL 2 Output of digital filter drives CTRIPL 3 Latched output of digital filter drives CTRIPL" "0,1,2,3" newline bitfld.word 0x0 9. "COMPLINV,Low comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" bitfld.word 0x0 8. "RESERVED,Reserved for CMPSSB" "0,1" newline bitfld.word 0x0 6. "ASYNCHEN,High comparator asynchronous path enable. Allows asynchronous comparator output to feed into OR gate with latched digital filter signal when CTRIPHSEL=3 or CTRIPOUTHSEL=3. 0 Asynchronous comparator output does not feed into OR gate with.." "0,1" bitfld.word 0x0 4.--5. "CTRIPOUTHSEL,High comparator CTRIPOUTH source select. 0 Asynchronous comparator output drives CTRIPOUTH 1 Synchronous comparator output drives CTRIPOUTH 2 Output of digital filter drives CTRIPOUTH 3 Latched output of digital filter drives.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTRIPHSEL,High comparator CTRIPH source select. 0 Asynchronous comparator output drives CTRIPH 1 Synchronous comparator output drives CTRIPH 2 Output of digital filter drives CTRIPH 3 Latched output of digital filter drives CTRIPH" "0,1,2,3" bitfld.word 0x0 1. "COMPHINV,High comparator output invert. 0 Output of comparator is not inverted 1 Output of comparator is inverted" "0,1" newline bitfld.word 0x0 0. "RESERVED,Reserved for CMPSSB" "0,1" line.word 0x2 "CONTROLSS_CMPSSB9_COMPHYSCTL" hexmask.word.byte 0x2 0.--3. 1. "COMPHYS,Comparator hysteresis. Sets the amount of hysteresis on the comparator inputs. 0 None 1 Set to typical hysteresis 2 Set to 2x of typical hysteresis 3 Set to 3x of typical hysteresis 4 Set to 4x of typical hysteresis others :.." rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_CMPSSB9_COMPSTS" bitfld.word 0x0 9. "COMPLLATCH,Latched value of low comparator digital filter output" "0,1" bitfld.word 0x0 8. "COMPLSTS,Low comparator digital filter output" "0,1" newline bitfld.word 0x0 1. "COMPHLATCH,Latched value of high comparator digital filter output" "0,1" bitfld.word 0x0 0. "COMPHSTS,High comparator digital filter output" "0,1" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_CMPSSB9_COMPSTSCLR" bitfld.word 0x0 10. "LSYNCCLREN,Low comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 9. "LLATCHCLR,Low comparator latch software clear. Perform software reset of low comparator digital filter output latch COMPSTS[COMPLLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPLLATCH]" "0,1" newline bitfld.word 0x0 2. "HSYNCCLREN,High comparator latch EPWMSYNCPER clear. Enable EPWMSYNCPER reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. 0 EPWMSYNCPER will not reset latch 1 EPWMSYNCPER will reset latch" "0,1" bitfld.word 0x0 1. "HLATCHCLR,High comparator latch software clear. Perform software reset of high comparator digital filter output latch COMPSTS[COMPHLATCH]. Reads always return 0. 0 No effect 1 Generate a single pulse of latch reset signal for COMPSTS[COMPHLATCH]" "0,1" line.word 0x2 "CONTROLSS_CMPSSB9_COMPDACCTL" bitfld.word 0x2 14.--15. "FREESOFT,Free-run or software-run emulation behavior. Behavior of the ramp generator during emulation suspend. 00b Ramp generator stops immediately during emulation suspend 01b Ramp generator completes current ramp and stops at next EPWMSYNCPER.." "0,1,2,3" bitfld.word 0x2 12. "BLANKEN,EPWMBLANK enable. This bit enables the EPWMBLANK signal. 0 EPWMBLANK signal is disabled. 1 EPWMBLANK signal is enabled." "0,1" newline hexmask.word.byte 0x2 8.--11. 1. "BLANKSOURCE,EPWMBLANK source select. This bit field determines which EPWMnBLANK is passed on as the EPWMBLANK signal. Where n represents the maximum number of EPWMBLANK signals available on the device: 0 EPWM1BLANK 1 EPWM2BLANK 2 EPWM3BLANK.." bitfld.word 0x2 7. "SWLOADSEL,Software load select. Determines whether DACxVALA is updated from DACxVALS on SYSCLK or EPWMSYNCPER. 0 DACxVALA is updated from DACxVALS on SYSCLK 1 DACxVALA is updated from DACxVALS on EPWMSYNCPER" "0,1" newline bitfld.word 0x2 6. "RAMPLOADSEL,Ramp load select. Determines whether RAMPSTS is updated from RAMPMAXREFA or RAMPMAXREFS when COMPSTS[COMPHSTS] is triggered. 0 RAMPSTS is loaded from RAMPMAXREFA 1 RAMPSTS is loaded from RAMPMAXREFS" "0,1" bitfld.word 0x2 5. "SELREF,CMPSS reference select0 vref_1p8v as reference voltage (default)1 vdd_1p8v as reference voltage" "0,1" newline hexmask.word.byte 0x2 1.--4. 1. "RAMPSOURCE,EPWMSYNCPER source select. Determines which EPWMnSYNCPER signal is used within the CMPSS module. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2.." bitfld.word 0x2 0. "DACSOURCE,DAC source select. Determines whether DACHVALA is updated from DACHVALS or from the ramp generator. 0 DACHVALA is updated from DACHVALS 1 DACHVALA is updated from the ramp generator" "0,1" line.word 0x4 "CONTROLSS_CMPSSB9_COMPDACCTL2" bitfld.word 0x4 10. "RAMPSOURCEUSEL,0: Selects EPWM0 to 15 as RAMP source 1: Selects EPWM16 to 31 as RAMP source" "0: Selects EPWM0 to 15 as RAMP source,1: Selects EPWM16 to 31 as RAMP source" bitfld.word 0x4 8. "BLANKSOURCEUSEL,0: Selects EPWM0 to 15 as blank source 1: Selects EPWM16 to 31 as blank source" "0: Selects EPWM0 to 15 as blank source,1: Selects EPWM16 to 31 as blank source" newline hexmask.word.byte 0x4 1.--5. 1. "DEACTIVESEL,DEACTIVE source select: 0x0 : EPWM1.DEACTIVE 0x1 : EPWM2.DEACTIVE 0x2 : EPWM3.DEACTIVE 0x3 : EPWM4.DEACTIVE . . 0x31 : EPWM32.DEACTIVE" bitfld.word 0x4 0. "DEENABLE,DE mode enable. 0 DE mode features disabled. 1 DE mode features enabled." "0,1" line.word 0x6 "CONTROLSS_CMPSSB9_DACHVALS" hexmask.word 0x6 0.--11. 1. "DACVAL,High DAC shadow value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS is loaded into DACHVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0xE++0x3 line.word 0x0 "CONTROLSS_CMPSSB9_DACHVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC active value. Value that is actively driven by the high DAC." line.word 0x2 "CONTROLSS_CMPSSB9_RAMPMAXREFA" hexmask.word 0x2 0.--15. 1. "RAMPMAXREF,Ramp maximum reference active value. Latched value to be loaded into ramp generator RAMPSTS." group.word 0x14++0x1 line.word 0x0 "CONTROLSS_CMPSSB9_RAMPMAXREFS" hexmask.word 0x0 0.--15. 1. "RAMPMAXREF,Ramp maximum reference shadow. Unlatched value to be loaded into ramp generator RAMPSTS." rgroup.word 0x18++0x1 line.word 0x0 "CONTROLSS_CMPSSB9_RAMPDECVALA" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value active. Latched value that will be subtracted from RAMPSTS." group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_CMPSSB9_RAMPDECVALS" hexmask.word 0x0 0.--15. 1. "RAMPDECVAL,Ramp decrement value shadow. Unlatched value to be loaded into RAMPDECVALA." rgroup.word 0x20++0x1 line.word 0x0 "CONTROLSS_CMPSSB9_RAMPSTS" hexmask.word 0x0 0.--15. 1. "RAMPVALUE,Ramp value. Present value of ramp generator." group.word 0x24++0x1 line.word 0x0 "CONTROLSS_CMPSSB9_DACLVALS" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC shadow value. value to be loaded into DACLVALA on the trigger signal selected by COMPDACCTL[SWLOADSEL]." rgroup.word 0x26++0x3 line.word 0x0 "CONTROLSS_CMPSSB9_DACLVALA" hexmask.word 0x0 0.--11. 1. "DACVAL,Low DAC active value. Value that is actively driven by the low DAC." line.word 0x2 "CONTROLSS_CMPSSB9_RAMPDLYA" hexmask.word 0x2 0.--12. 1. "DELAY,Ramp delay active value. Latched value of the number of cycles to delay the start of the ramp generator decrementer after a EPWMSYNCPER is received." group.word 0x2A++0xB line.word 0x0 "CONTROLSS_CMPSSB9_RAMPDLYS" hexmask.word 0x0 0.--12. 1. "DELAY,Ramp delay shadow value. Unlatched value to be loaded into RAMPDLYA." line.word 0x2 "CONTROLSS_CMPSSB9_CTRIPLFILCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_CMPSSB9_CTRIPLFILCLKCTL" hexmask.word 0x4 0.--15. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0x6 "CONTROLSS_CMPSSB9_CTRIPHFILCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state. Threshold used is THRESH+1." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_CMPSSB9_CTRIPHFILCLKCTL" hexmask.word 0x8 0.--15. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples is CLKPRESCALE+1." line.word 0xA "CONTROLSS_CMPSSB9_COMPLOCK" bitfld.word 0xA 4. "TEST,TEST Lock. This bit when set will prevent any further writes to the any undocumented registers that may affect the performance/behavior of this block. Once set this bit can only be cleared by a reset." "0,1" bitfld.word 0xA 3. "CTRIP,Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system.." "0,1" newline bitfld.word 0xA 2. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0xA 1. "COMPHYSCTL,Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit." "0,1" newline bitfld.word 0xA 0. "COMPCTL,Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit." "0,1" group.word 0x38++0x5 line.word 0x0 "CONTROLSS_CMPSSB9_DACHVALS2" hexmask.word 0x0 0.--11. 1. "DACVAL,High DAC shadow register2 value. When COMPDACCTL[DACSOURCE]=0 the value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x2 "CONTROLSS_CMPSSB9_DACLVALS2" hexmask.word 0x2 0.--11. 1. "DACVAL,Low DAC shadow register2 value. Value of DACHVALS2 is loaded into DACHVALA when DE mode is enabled and selected DEACTIVE input is asserted." line.word 0x4 "CONTROLSS_CMPSSB9_CONFIG1" hexmask.word.byte 0x4 8.--15. 1. "SPARE,SPARE" hexmask.word.byte 0x4 4.--7. 1. "COMPLHYS,compL Hysterisishystl_1p1v[3] = reservedhystl_1p1v[2] = control which comparator output value the hysteresis is applied tohystl_1p1v[1:0] = hysteresis value00 0 LSB01 17.5 LSB10 35 LSB11 52.5 LSB" newline hexmask.word.byte 0x4 0.--3. 1. "COMPHHYS,CompH Hysteresishysth_1p1v[3] = reservedhysth_1p1v[2] 0 comparator hysteresis is applied when the comparator output is 1'b11 comparator hysteresis is applied when the comparator output is 1'b0hysth_1p1v[1:0] = hysteresis value00 0 LSB01 17.5.." tree.end tree.end tree "CTRL" base ad:0x502F0000 rgroup.long 0x0++0x3 line.long 0x0 "CONTROLSS_CTRL_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,Not Defined" newline hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,Not Defined" newline bitfld.long 0x0 8.--10. "PID_MAJOR,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM,Not Defined" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,Not Defined" group.long 0x4++0x7 line.long 0x0 "CONTROLSS_CTRL_EPWM_STATICXBAR_SEL0" bitfld.long 0x0 30.--31. "ETPWM15,ETPWM15 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x0 28.--29. "ETPWM14,ETPWM14 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x0 26.--27. "ETPWM13,ETPWM13 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x0 24.--25. "ETPWM12,ETPWM12 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x0 22.--23. "ETPWM11,ETPWM11 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x0 20.--21. "ETPWM10,ETPWM10 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x0 18.--19. "ETPWM9,ETPWM9 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x0 16.--17. "ETPWM8,ETPWM8 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x0 14.--15. "ETPWM7,ETPWM7 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x0 12.--13. "ETPWM6,ETPWM6 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x0 10.--11. "ETPWM5,ETPWM5 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x0 8.--9. "ETPWM4,ETPWM4 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x0 6.--7. "ETPWM3,ETPWM3 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x0 4.--5. "ETPWM2,ETPWM2 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x0 2.--3. "ETPWM1,ETPWM1 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x0 0.--1. "ETPWM0,ETPWM0 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" line.long 0x4 "CONTROLSS_CTRL_EPWM_STATICXBAR_SEL1" bitfld.long 0x4 30.--31. "ETPWM31,ETPWM31 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x4 28.--29. "ETPWM30,ETPWM30 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x4 26.--27. "ETPWM29,ETPWM29 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x4 24.--25. "ETPWM28,ETPWM28 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x4 22.--23. "ETPWM27,ETPWM27 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x4 20.--21. "ETPWM26,ETPWM26 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x4 18.--19. "ETPWM25,ETPWM25 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x4 16.--17. "ETPWM24,ETPWM24 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x4 14.--15. "ETPWM23,ETPWM23 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x4 12.--13. "ETPWM22,ETPWM22 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x4 10.--11. "ETPWM21,ETPWM21 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x4 8.--9. "ETPWM20,ETPWM20 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x4 6.--7. "ETPWM19,ETPWM19 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x4 4.--5. "ETPWM18,ETPWM18 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x4 2.--3. "ETPWM17,ETPWM17 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" newline bitfld.long 0x4 0.--1. "ETPWM16,ETPWM16 access from PCR grouping - 00 = G0 01 = G1 01 = G2 11 = G3" "0: G0,1: G2,?,?" group.long 0x10++0x3 line.long 0x0 "CONTROLSS_CTRL_EPWM_CLKSYNC" hexmask.long 0x0 0.--31. 1. "BIT,ETPWM clock sync for each EPWM instance1: will allow CLK SYNC when GBCLKSYNC is written in0: No CLK SYNC when GBCLKSYNC is written in" group.byte 0x18++0x0 line.byte 0x0 "CONTROLSS_CTRL_SDFM1_CLK0_SEL" bitfld.byte 0x0 0. "SEL,SDFM1 clock CK0 select0: source is SDFM1 CK0 from Pinmux1: source is SDFM0 CK0 from Pinmux" "0,1" group.byte 0x20++0x0 line.byte 0x0 "CONTROLSS_CTRL_EMUSTOPN_MASK" bitfld.byte 0x0 3. "CR5B1,Bit-mask for debug suspend cpu cores to EPWM0: CR5B1 enabled to control EMUSTOPn1: CR5B1 disabled to control EMUSTOPn" "0,1" newline bitfld.byte 0x0 2. "CR5A1,Bit-mask for debug suspend cpu cores to EPWM0: CR5A1 enabled to control EMUSTOPn1: CR5A1 disabled to control EMUSTOPn" "0,1" newline bitfld.byte 0x0 1. "CR5B0,Bit-mask for debug suspend cpu cores to EPWM0: CR5B0 enabled to control EMUSTOPn1: CR5B0 disabled to control EMUSTOPn" "0,1" newline bitfld.byte 0x0 0. "CR5A0,Bit-mask for debug suspend cpu cores to EPWM0: CR5A0 enabled to control EMUSTOPn1: CR5A0 disabled to control EMUSTOPn" "0,1" group.long 0x28++0x3 line.long 0x0 "CONTROLSS_CTRL_CLB_AQ_EN0" hexmask.long 0x0 0.--31. 1. "ENABLE,Enable ICCS control to CLB_AQ signal of PWM[15:0]" group.long 0x30++0x3 line.long 0x0 "CONTROLSS_CTRL_CLB_AQ_EN1" hexmask.long 0x0 0.--31. 1. "ENABLE,Enable ICCS control to CLB_AQ signal of PWM[31:16]" group.long 0x38++0x3 line.long 0x0 "CONTROLSS_CTRL_CLB_DB_EN0" hexmask.long 0x0 0.--31. 1. "ENABLE,Enable ICCS control to CLB_DB signal of PWM[15:0]" group.long 0x40++0x3 line.long 0x0 "CONTROLSS_CTRL_CLB_DB_EN1" hexmask.long 0x0 0.--31. 1. "ENABLE,Enable ICCS control to CLB_DB signal of PWM[31:16]" group.byte 0x100++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM0_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x104++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM1_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x108++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM2_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x10C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM3_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x110++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM4_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x114++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM5_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x118++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM6_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x11C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM7_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x120++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM8_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x124++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM9_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x128++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM10_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x12C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM11_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x130++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM12_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x134++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM13_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x138++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM14_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x13C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM15_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x140++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM16_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x144++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM17_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x148++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM18_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x14C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM19_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x150++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM20_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x154++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM21_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x158++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM22_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x15C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM23_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x160++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM24_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x164++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM25_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x168++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM26_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x16C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM27_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x170++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM28_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x174++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM29_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x178++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM30_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x17C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM31_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x180++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_TX0_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding fsi_tx" "0,1,2,3,4,5,6,7" group.byte 0x184++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_TX1_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding fsi_tx" "0,1,2,3,4,5,6,7" group.byte 0x188++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_TX2_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding fsi_tx" "0,1,2,3,4,5,6,7" group.byte 0x18C++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_TX3_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding fsi_tx" "0,1,2,3,4,5,6,7" group.byte 0x190++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_RX0_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding fsi_rx" "0,1,2,3,4,5,6,7" group.byte 0x194++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_RX1_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding fsi_rx" "0,1,2,3,4,5,6,7" group.byte 0x198++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_RX2_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding fsi_rx" "0,1,2,3,4,5,6,7" group.byte 0x19C++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_RX3_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding fsi_rx" "0,1,2,3,4,5,6,7" group.byte 0x1A0++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA0_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x1A4++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA1_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x1A8++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA2_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x1AC++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA3_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x1B0++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA4_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x1B4++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA5_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x1B8++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA6_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x1BC++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA7_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x1C0++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA8_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x1C4++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA9_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x1D0++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB0_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x1D4++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB1_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x1D8++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB2_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x1DC++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB3_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x1E0++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB4_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x1E4++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB5_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x1E8++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB6_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x1EC++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB7_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x1F0++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB8_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x1F4++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB9_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x200++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP0_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x204++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP1_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x208++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP2_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x20C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP3_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x210++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP4_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x214++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP5_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x218++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP6_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x21C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP7_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x220++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP8_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x224++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP9_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x240++0x0 line.byte 0x0 "CONTROLSS_CTRL_EQEP0_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding eqep" "0,1,2,3,4,5,6,7" group.byte 0x244++0x0 line.byte 0x0 "CONTROLSS_CTRL_EQEP1_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding eqep" "0,1,2,3,4,5,6,7" group.byte 0x248++0x0 line.byte 0x0 "CONTROLSS_CTRL_EQEP2_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding eqep" "0,1,2,3,4,5,6,7" group.byte 0x250++0x0 line.byte 0x0 "CONTROLSS_CTRL_SDFM0_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding sdfm" "0,1,2,3,4,5,6,7" group.byte 0x254++0x0 line.byte 0x0 "CONTROLSS_CTRL_SDFM1_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding sdfm" "0,1,2,3,4,5,6,7" group.byte 0x258++0x0 line.byte 0x0 "CONTROLSS_CTRL_DAC_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for dac" "0,1,2,3,4,5,6,7" group.byte 0x25C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ADC0_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding adc" "0,1,2,3,4,5,6,7" group.byte 0x260++0x0 line.byte 0x0 "CONTROLSS_CTRL_ADC1_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding adc" "0,1,2,3,4,5,6,7" group.byte 0x264++0x0 line.byte 0x0 "CONTROLSS_CTRL_ADC2_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding adc" "0,1,2,3,4,5,6,7" group.byte 0x268++0x0 line.byte 0x0 "CONTROLSS_CTRL_ADC3_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding adc" "0,1,2,3,4,5,6,7" group.byte 0x26C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ADC4_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding adc" "0,1,2,3,4,5,6,7" group.byte 0x270++0x0 line.byte 0x0 "CONTROLSS_CTRL_OTTO0_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding otto" "0,1,2,3,4,5,6,7" group.byte 0x274++0x0 line.byte 0x0 "CONTROLSS_CTRL_OTTO1_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding otto" "0,1,2,3,4,5,6,7" group.byte 0x278++0x0 line.byte 0x0 "CONTROLSS_CTRL_OTTO2_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding otto" "0,1,2,3,4,5,6,7" group.byte 0x27C++0x0 line.byte 0x0 "CONTROLSS_CTRL_OTTO3_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding otto" "0,1,2,3,4,5,6,7" group.byte 0x280++0x0 line.byte 0x0 "CONTROLSS_CTRL_SDFM0_PLL_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding sdfm pll clock" "0,1,2,3,4,5,6,7" group.byte 0x284++0x0 line.byte 0x0 "CONTROLSS_CTRL_SDFM1_PLL_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding sdfm pll clock" "0,1,2,3,4,5,6,7" group.byte 0x288++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_TX0_PLL_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding fsi rx pll clock" "0,1,2,3,4,5,6,7" group.byte 0x28C++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_TX1_PLL_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding fsi rx pll clock" "0,1,2,3,4,5,6,7" group.byte 0x290++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_TX2_PLL_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding fsi rx pll clock" "0,1,2,3,4,5,6,7" group.byte 0x294++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_TX3_PLL_CLK_GATE" bitfld.byte 0x0 0.--2. "CLK_GATE,writing '111' will gate clock for corresponding fsi rx pll clock" "0,1,2,3,4,5,6,7" group.byte 0x300++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM0_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x304++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM1_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x308++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM2_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x30C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM3_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x310++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM4_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x314++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM5_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x318++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM6_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x31C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM7_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x320++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM8_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x324++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM9_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x328++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM10_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x32C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM11_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x330++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM12_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x334++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM13_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x338++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM14_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x33C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM15_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x340++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM16_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x344++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM17_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x348++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM18_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x34C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM19_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x350++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM20_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x354++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM21_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x358++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM22_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x35C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM23_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x360++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM24_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x364++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM25_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x368++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM26_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x36C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM27_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x370++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM28_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x374++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM29_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x378++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM30_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x37C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ETPWM31_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding etpwm" "0,1,2,3,4,5,6,7" group.byte 0x380++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_TX0_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding fsi_tx" "0,1,2,3,4,5,6,7" group.byte 0x384++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_TX1_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding fsi_tx" "0,1,2,3,4,5,6,7" group.byte 0x388++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_TX2_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding fsi_tx" "0,1,2,3,4,5,6,7" group.byte 0x38C++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_TX3_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding fsi_tx" "0,1,2,3,4,5,6,7" group.byte 0x390++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_RX0_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding fsi_rx" "0,1,2,3,4,5,6,7" group.byte 0x394++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_RX1_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding fsi_rx" "0,1,2,3,4,5,6,7" group.byte 0x398++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_RX2_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding fsi_rx" "0,1,2,3,4,5,6,7" group.byte 0x39C++0x0 line.byte 0x0 "CONTROLSS_CTRL_FSI_RX3_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding fsi_rx" "0,1,2,3,4,5,6,7" group.byte 0x3A0++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA0_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x3A4++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA1_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x3A8++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA2_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x3AC++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA3_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x3B0++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA4_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x3B4++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA5_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x3B8++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA6_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x3BC++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA7_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x3C0++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA8_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x3C4++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA9_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss12b" "0,1,2,3,4,5,6,7" group.byte 0x3D0++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB0_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x3D4++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB1_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x3D8++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB2_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x3DC++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB3_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x3E0++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB4_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x3E4++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB5_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x3E8++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB6_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x3EC++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB7_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x3F0++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB8_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x3F4++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB9_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding cmpss8b" "0,1,2,3,4,5,6,7" group.byte 0x400++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP0_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x404++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP1_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x408++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP2_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x40C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP3_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x410++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP4_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x414++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP5_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x418++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP6_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x41C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP7_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x420++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP8_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x424++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP9_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding ecap" "0,1,2,3,4,5,6,7" group.byte 0x440++0x0 line.byte 0x0 "CONTROLSS_CTRL_EQEP0_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding eqep" "0,1,2,3,4,5,6,7" group.byte 0x444++0x0 line.byte 0x0 "CONTROLSS_CTRL_EQEP1_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding eqep" "0,1,2,3,4,5,6,7" group.byte 0x448++0x0 line.byte 0x0 "CONTROLSS_CTRL_EQEP2_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding eqep" "0,1,2,3,4,5,6,7" group.byte 0x450++0x0 line.byte 0x0 "CONTROLSS_CTRL_SDFM0_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding sdfm" "0,1,2,3,4,5,6,7" group.byte 0x454++0x0 line.byte 0x0 "CONTROLSS_CTRL_SDFM1_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding sdfm" "0,1,2,3,4,5,6,7" group.byte 0x458++0x0 line.byte 0x0 "CONTROLSS_CTRL_DAC_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for dac" "0,1,2,3,4,5,6,7" group.byte 0x45C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ADC0_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding adc" "0,1,2,3,4,5,6,7" group.byte 0x460++0x0 line.byte 0x0 "CONTROLSS_CTRL_ADC1_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding adc" "0,1,2,3,4,5,6,7" group.byte 0x464++0x0 line.byte 0x0 "CONTROLSS_CTRL_ADC2_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding adc" "0,1,2,3,4,5,6,7" group.byte 0x468++0x0 line.byte 0x0 "CONTROLSS_CTRL_ADC3_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding adc" "0,1,2,3,4,5,6,7" group.byte 0x46C++0x0 line.byte 0x0 "CONTROLSS_CTRL_ADC4_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding adc" "0,1,2,3,4,5,6,7" group.byte 0x470++0x0 line.byte 0x0 "CONTROLSS_CTRL_OTTO0_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding otto" "0,1,2,3,4,5,6,7" group.byte 0x474++0x0 line.byte 0x0 "CONTROLSS_CTRL_OTTO1_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding otto" "0,1,2,3,4,5,6,7" group.byte 0x478++0x0 line.byte 0x0 "CONTROLSS_CTRL_OTTO2_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding otto" "0,1,2,3,4,5,6,7" group.byte 0x47C++0x0 line.byte 0x0 "CONTROLSS_CTRL_OTTO3_RST" bitfld.byte 0x0 0.--2. "RST,writing '111' will generate reset for corresponding otto" "0,1,2,3,4,5,6,7" group.byte 0x500++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM0_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x504++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM1_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x508++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM2_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x50C++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM3_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x510++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM4_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x514++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM5_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x518++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM6_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x51C++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM7_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x520++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM8_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x524++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM9_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x528++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM10_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x52C++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM11_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x530++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM12_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x534++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM13_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x538++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM14_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x53C++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM15_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x540++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM16_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x544++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM17_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x548++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM18_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x54C++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM19_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x550++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM20_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x554++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM21_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x558++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM22_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x55C++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM23_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x560++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM24_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x564++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM25_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x568++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM26_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x56C++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM27_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x570++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM28_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x574++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM29_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x578++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM30_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x57C++0x0 line.byte 0x0 "CONTROLSS_CTRL_EPWM31_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x580++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA0_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x584++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA1_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x588++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA2_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x58C++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA3_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x590++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA4_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x594++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA5_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x598++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA6_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x59C++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA7_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5A0++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA8_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5A4++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSA9_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5A8++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB0_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5AC++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB1_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5B0++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB2_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5B4++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB3_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5B8++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB4_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5BC++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB5_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5C0++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB6_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5C4++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB7_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5C8++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB8_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5CC++0x0 line.byte 0x0 "CONTROLSS_CTRL_CMPSSB9_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5D0++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP0_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5D4++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP1_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5D8++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP2_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5DC++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP3_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5E0++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP4_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5E4++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP5_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5E8++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP6_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5EC++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP7_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5F0++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP8_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5F4++0x0 line.byte 0x0 "CONTROLSS_CTRL_ECAP9_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5F8++0x0 line.byte 0x0 "CONTROLSS_CTRL_EQEP0_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x5FC++0x0 line.byte 0x0 "CONTROLSS_CTRL_EQEP1_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x600++0x0 line.byte 0x0 "CONTROLSS_CTRL_EQEP2_HALTEN" bitfld.byte 0x0 3. "CR5B1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.long 0x1008++0x7 line.long 0x0 "CONTROLSS_CTRL_LOCK0_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "CONTROLSS_CTRL_LOCK0_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" group.byte 0x1010++0x0 line.byte 0x0 "CONTROLSS_CTRL_INTR_RAW_STATUS" bitfld.byte 0x0 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" group.byte 0x1014++0x0 line.byte 0x0 "CONTROLSS_CTRL_INTR_ENABLED_STATUS_CLEAR" bitfld.byte 0x0 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" group.byte 0x1018++0x0 line.byte 0x0 "CONTROLSS_CTRL_INTR_ENABLE" bitfld.byte 0x0 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" group.byte 0x101C++0x0 line.byte 0x0 "CONTROLSS_CTRL_INTR_ENABLE_CLEAR" bitfld.byte 0x0 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.byte 0x1020++0x0 line.byte 0x0 "CONTROLSS_CTRL_EOI" hexmask.byte 0x0 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0x3 line.long 0x0 "CONTROLSS_CTRL_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." rgroup.byte 0x1028++0x0 line.byte 0x0 "CONTROLSS_CTRL_FAULT_TYPE_STATUS" bitfld.byte 0x0 6. "FAULT_NS,Non-secure access." "0,1" newline hexmask.byte 0x0 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1.." rgroup.long 0x102C++0x3 line.long 0x0 "CONTROLSS_CTRL_FAULT_ATTR_STATUS" hexmask.long.word 0x0 20.--31. 1. "FAULT_XID,XID." newline hexmask.long.word 0x0 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x0 0.--7. 1. "FAULT_PRIVID,Privilege ID." wgroup.byte 0x1030++0x0 line.byte 0x0 "CONTROLSS_CTRL_FAULT_CLEAR" bitfld.byte 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" tree.end tree "DAC" base ad:0x50260000 rgroup.word 0x0++0x1 line.word 0x0 "CONTROLSS_DAC0_DACREV" hexmask.word.byte 0x0 0.--7. 1. "REV,DAC Revision" group.word 0x2++0x1 line.word 0x0 "CONTROLSS_DAC0_DACCTL_ALT2_" hexmask.word.byte 0x0 4.--8. 1. "SYNCSEL,DAC EPWMSYNCPER select. Determines which EPWMSYNCPER signal will update the DACVALA register. Where n represents the maximum number of EPWMSYNCPER signals available on the device: 0 EPWM1SYNCPER 1 EPWM2SYNCPER 2 EPWM3SYNCPER ..." bitfld.word 0x0 2. "LOADMODE,DACVALA load mode. Determines when the DACVALA register is updated with the value from DACVALS. 0 Load on next SYSCLK 1 Load on next EPWMSYNCPER specified by SYNCSEL" "0,1" bitfld.word 0x0 1. "MODE,DAC gain mode select. Selects the gain mode for the buffered output. The MODE value is only used when DACREFSEL=1 and internal ADC reference mode is selected. 0 Gain is 1 1 Gain is 2" "0,1" bitfld.word 0x0 0. "DACREFSEL,DAC reference select. Selects which voltage references are used by the DAC. 0 VDAC/VSSA are the reference voltages 1 ADC VREFHI/VSSA are the reference voltages" "0,1" rgroup.word 0x4++0x1 line.word 0x0 "CONTROLSS_DAC0_DACVALA" hexmask.word 0x0 0.--11. 1. "DACVALA,Active output code currently driven by the DAC" group.word 0x6++0x7 line.word 0x0 "CONTROLSS_DAC0_DACVALS" hexmask.word 0x0 0.--11. 1. "DACVALS,Shadow output code to be loaded into DACVALA" line.word 0x2 "CONTROLSS_DAC0_DACOUTEN" bitfld.word 0x2 0. "DACOUTEN,DAC output enable 0 DAC output is disabled 1 DAC output is enabled" "0,1" line.word 0x4 "CONTROLSS_DAC0_DACLOCK" hexmask.word.byte 0x4 12.--15. 1. "KEY,Writes to this register succeed only if this field is written with a value of 0xA. Only 16-bit writes will succeed (provided the KEY matches). Read-modify-writes to individual bits in this register will be ignored." bitfld.word 0x4 2. "DACOUTEN,Lock write-access to the DACOUTEN register. 0 DACOUTEN register is not locked. Write 0 to this bit has no effect. 1 DACOUTEN register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0x4 1. "DACVAL,Lock write-access to the DACVALS register. 0 DACVALS register is not locked. Write 0 to this bit has no effect. 1 DACVALS register is locked. Only a system reset can clear this bit." "0,1" bitfld.word 0x4 0. "DACCTL,Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit." "0,1" line.word 0x6 "CONTROLSS_DAC0_DACTRIM" hexmask.word.byte 0x6 8.--11. 1. "RESERVED,DAC Gain Trim. This signed (two's complement) bit field is used to adjust the gain of the DAC. This register will be written with a factory set value during the device boot procedure. 1000 Gain is increased by the equivalent of 0.8% ..." hexmask.word.byte 0x6 0.--7. 1. "OFFSET_TRIM,DAC Offset Trim. This register should not be modified unless specifically indicated by TI Errata or other documentation. Modifying the contents of this register could cause this module to operate outside of datasheet specifications." tree.end tree "DMAXBAR" base ad:0x502D6000 rgroup.long 0x0++0x3 line.long 0x0 "CONTROLSS_DMAXBAR_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,Not Defined" hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,Not Defined" bitfld.long 0x0 8.--10. "PID_MAJOR,Not Defined" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "PID_CUSTOM,Not Defined" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,Not Defined" group.byte 0x100++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR0_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x104++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR0_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x108++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR0_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x10C++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR0_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x110++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR0_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x114++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR0_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x118++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR0_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" group.byte 0x140++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR1_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x144++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR1_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x148++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR1_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x14C++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR1_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x150++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR1_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x154++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR1_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x158++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR1_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" group.byte 0x180++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR2_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x184++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR2_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x188++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR2_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x18C++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR2_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x190++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR2_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x194++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR2_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x198++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR2_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" group.byte 0x1C0++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR3_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x1C4++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR3_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x1C8++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR3_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x1CC++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR3_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x1D0++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR3_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x1D4++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR3_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x1D8++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR3_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" group.byte 0x200++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR4_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x204++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR4_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x208++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR4_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x20C++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR4_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x210++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR4_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x214++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR4_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x218++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR4_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" group.byte 0x240++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR5_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x244++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR5_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x248++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR5_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x24C++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR5_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x250++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR5_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x254++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR5_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x258++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR5_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" group.byte 0x280++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR6_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x284++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR6_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x288++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR6_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x28C++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR6_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x290++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR6_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x294++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR6_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x298++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR6_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" group.byte 0x2C0++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR7_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x2C4++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR7_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x2C8++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR7_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x2CC++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR7_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x2D0++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR7_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x2D4++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR7_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x2D8++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR7_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" group.byte 0x300++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR8_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x304++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR8_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x308++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR8_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x30C++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR8_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x310++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR8_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x314++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR8_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x318++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR8_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" group.byte 0x340++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR9_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x344++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR9_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x348++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR9_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x34C++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR9_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x350++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR9_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x354++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR9_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x358++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR9_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" group.byte 0x380++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR10_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x384++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR10_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x388++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR10_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x38C++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR10_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x390++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR10_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x394++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR10_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x398++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR10_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" group.byte 0x3C0++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR11_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x3C4++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR11_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x3C8++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR11_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x3CC++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR11_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x3D0++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR11_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x3D4++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR11_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x3D8++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR11_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" group.byte 0x400++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR12_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x404++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR12_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x408++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR12_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x40C++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR12_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x410++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR12_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x414++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR12_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x418++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR12_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" group.byte 0x440++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR13_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x444++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR13_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x448++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR13_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x44C++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR13_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x450++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR13_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x454++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR13_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x458++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR13_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" group.byte 0x480++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR14_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x484++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR14_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x488++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR14_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x48C++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR14_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x490++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR14_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x494++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR14_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x498++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR14_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" group.byte 0x4C0++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR15_GSEL" bitfld.byte 0x0 0.--2. "GSEL,Select input source:0: G0 selected..5: G5 selected" "0: G0 selected,?,?,?,?,5: G5 selected,?,?" group.byte 0x4C4++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR15_G0" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCA to corresponding xbar1: PWMx.SOCA is selected0: PWMx.SOCA is de-selected" group.byte 0x4C8++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR15_G1" hexmask.byte 0x0 0.--4. 1. "SEL,ETPWM SOCB to corresponding xbar1: PWMx.SOCB is selected0: PWMx.SOCB is de-selected" group.byte 0x4CC++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR15_G2" hexmask.byte 0x0 0.--4. 1. "SEL,ADC DMA requests to corresponding xbar0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.byte 0x4D0++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR15_G3" hexmask.byte 0x0 0.--3. 1. "SEL,FSI DMA requests to corresponding xbar0: FSIRX0.RX_DMA_EVT1; FSIRX0_DMATRIG12: FSIRX0_DMATRIG23: FSIRX1.RX_DMA_EVT4; FSIRX1_DMATRIG15: FSIRX1_DMATRIG26: FSIRX2.RX_DMA_EVT7; FSIRX2_DMATRIG18: FSIRX2_DMATRIG29: FSIRX3.RX_DMA_EVT10; FSIRX3_DMATRIG111:.." group.byte 0x4D4++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR15_G4" bitfld.byte 0x0 0.--2. "SEL,SDFM DMA requests to corresponding xbar0: SD0.FILT1.DRINT1: SD0.FILT2.DRINT2: SD0.FILT3.DRINT3: SD0.FILT4.DRINT4: SD1.FILT1.DRINT5: SD1.FILT2.DRINT6: SD1.FILT3.DRINT7: SD1.FILT4.DRINT" "0,1,2,3,4,5,6,7" group.byte 0x4D8++0x0 line.byte 0x0 "CONTROLSS_DMAXBAR_DMAXBAR15_G5" hexmask.byte 0x0 0.--3. 1. "SEL,ECAP DMA requests to corresponding xbar0: ECAP0.DMA_INT1: ECAP1.DMA_INT2: ECAP2.DMA_INT3: ECAP3.DMA_INT4: ECAP4.DMA_INT5: ECAP5.DMA_INT6: ECAP6.DMA_INT7: ECAP7.DMA_INT8: ECAP8.DMA_INT9: ECAP9.DMA_INT" tree.end base ad:0x0 tree "ECAP" tree "ECAP0" base ad:0x50240000 group.long 0x0++0x17 line.long 0x0 "CONTROLSS_ECAP0_TSCTR" hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1) This register reads HRCOUNTER value and is not writable 2) can be reset using CTRFILTRESET 3) Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "CONTROLSS_ECAP0_CTRPHS" hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "CONTROLSS_ECAP0_CAP1" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by: - Time-Stamp counter value (TSCTR) during a capture event - Software - may be useful for test purposes or initialization - ARPD shadow register (CAP3) when used in APWM mode" line.long 0xC "CONTROLSS_ECAP0_CAP2" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by: - Time-Stamp ( counter value) during a capture event - Software - may be useful for test purposes - ACMP shadow register (CAP4) when used in APWM mode" line.long 0x10 "CONTROLSS_ECAP0_CAP3" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register. In APWM mode this is the period shadow (APRD) register. You can update the PWM period value through this register. CAP3 (APRD) shadows CAP1 in this mode." line.long 0x14 "CONTROLSS_ECAP0_CAP4" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register. In APWM mode this is the compare shadow (ACMP) register. You can update the PWM compare value via this register. CAP4 (ACMP) shadows CAP2 in this mode." group.long 0x24++0x3 line.long 0x0 "CONTROLSS_ECAP0_ECCTL0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b (R/W) = SOC trigger source is CEVT1 01b (R/W) = SOC trigger source is CEVT2 10b (R/W) = SOC trigger source is CEVT3 11b (R/W) = SOC trigger source is CEVT4 APWM Mode: 00b (R/W) = SOC trigger interrupt.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "CONTROLSS_ECAP0_ECCTL1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0x0 | ECAP_STOP_EMUTSCTR counter stops immediately on emulation suspend 0x1 | ECAP_RUNS_UNTILTSCTR counter runs until = 0 0x2 | ECAP_UNAF_EMU_SUSTSCTR counter is unaffected by emulation suspend (Run.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0x00 | ECAP_DIV1Divide by 1 (i.e . no prescale by-pass the prescaler) 0x01 | ECAP_DIV2Divide by 2 0x02 | ECAP_DIV4Divide by 4 0x03 | ECAP_DIV6Divide by 6 0x04 |.." newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 | ECAP_DISABLEDisable CAP1-4 register loads at capture event time. 1 | ECAP_ENABLEEnable CAP1-4.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 | ECAP_DO_NOT_RESET_EVENT4Do not reset counter on Capture Event 4 (absolute time stamp operation) 1 | ECAP_RESET_EVENT4Reset counter after Capture Event 4 time-stamp has been captured (used in.." "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 | ECAP_CAP_EVENT4_RISECapture Event 4 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT4_FALLCapture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 | ECAP_DO_NOT_RESET_EVENT3Do not reset counter on Capture Event 3 (absolute time stamp) 1 | ECAP_RESET_EVENT3Reset counter after Event 3 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 | ECAP_CAP_EVENT3_RISECapture Event 3 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT3_FALLCapture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 | ECAP_DO_NOT_RESET_EVENT2Do not reset counter on Capture Event 2 (absolute time stamp) 1 | ECAP_RESET_EVENT2Reset counter after Event 2 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 | ECAP_CAP_EVENT2_RISECapture Event 2 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT2_FALLCapture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 | ECAP_DO_NOT_RESET_EVENT1Do not reset counter on Capture Event 1 (absolute time stamp) 1 | ECAP_RESET_EVENT1Reset counter after Event 1 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 | ECAP_CAP_EVENT1_RISECapture Event 1 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT1_FALLCapture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "CONTROLSS_ECAP0_ECCTL2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b (R) = CAP1 register gets loaded on next capture event. 01b (R) = CAP2 register gets loaded on next capture event. 10b (R) = CAP3 register gets loaded on next capture event. 11b (R) =.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b (R/W) = DMA interrupt source is CEVT1 01b (R/W) = DMA interrupt source is CEVT2 10b (R/W) = DMA interrupt source is CEVT3 11b (R/W) = DMA interrupt source is CEVT4 APWM Mode: 00b (R/W) = DMA interrupt source.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h (R) = No effect 1h (W) = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 | ECAP_OUTPUT_ACTIVE_HIGHOutput is active high (Compare value defines high time) 1 | ECAP_OUTPUT_ACTIVE_LOWOutput is active low (Compare value defines.." "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 | ECAP_MODULEECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers - Permits user.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter (TSCTR) Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 |.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0x0 | SWSYNCsync out signal is SWSYNC 0x1 | ECAP_CTR_PRD_TO_SYNCOUTSelect CTR = PRD event to be the sync-out signal 0x2 | ECAP_DISABLE_SYNC_OUTDisable sync out signal 0x3 |.." "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter (TSCTR) Sync-In select mode 0 | ECAP_DISABLE_SYNC_INDisable sync-in option 1 | ECAP_ENABLE_COUNTER_REGISTEREnable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp (TSCTR) Counter Stop (freeze) Control 0 | ECAP_TSCTR_STOPPEDTSCTR stopped 1 | ECAP_TSCTR_FREE_RUNNINGTSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 | ECAP_NO_EFFECT_RETURNS_0Has no effect (reading always returns a 0) 1 | ECAP_ARMS_ONESHOTArms the one-shot sequence as follows: 1) Resets the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur before the CAP(1-4) registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1-4) of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control (applicable only in capture mode) 0 | ECAP_OPP_CONTOperate in continuous mode 1 | ECAP_OPP_ONEOperate in one-Shot mode" "0,1" line.word 0x4 "CONTROLSS_ECAP0_ECEINT" bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 | ECAP_DISAB_HRERROR_INTERRUPTDisable High Resolution Error as an Interrupt source 1 | ECAP_ENAB_HRERROR_INTERRUPTEnable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 | ECAP_DISAB_CE_INTERRUPTDisable Compare Equal as an Interrupt source 1 | ECAP_ENAB_CE_INTERRUPTEnable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 | ECAP_DISAB_PE_INTERRUPTDisable Period Equal as an Interrupt source 1 | ECAP_ENAB_PE_INTERRUPTEnable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 | ECAP_DISAB_CO_INTERRUPTDisabled counter Overflow as an Interrupt source 1 | ECAP_ENAB_CO_INTERRUPTEnable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 | ECAP_DISAB_CAP4_INTERRUPTDisable Capture Event 4 as an Interrupt source 1 | ECAP_ENAB_CAP4_INTERRUPTCapture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 | ECAP_DISAB_CAP3_INTERRUPTDisable Capture Event 3 as an Interrupt source 1 | ECAP_ENAB_CAP3_INTERRUPTEnable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 | ECAP_DISAB_CAP2_INTERRUPTDisable Capture Event 2 as an Interrupt source 1 | ECAP_ENAB_CAP2_INTERRUPTEnable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 | ECAP_DISAB_CAP1_INTERRUPTDisable Capture Event 1 as an Interrupt source 1 | ECAP_ENAB_CAP1_INTERRUPTEnable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "CONTROLSS_ECAP0_ECFLG" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_HIGH_RESOLUTION_ERRORIndicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_COMPARE_REGIndicates the counter (TSCTR) reached the compare.." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_PERIOD_VALUE_RESETIndicates the counter (TSCTR) reached the period register.." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_TRANSIndicates the counter (TSCTR) has made the transition from.." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_4TH_EVENT_ECAPXIndicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_3RD_EVENT_ECAPXIndicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_2ND_EVENT_ECAPXIndicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_1ST_EVENT_ECAPXIndicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_INTERRUPTIndicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_ECAP0_ECCLR" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_HRERRORWriting a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_CMPWriting a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTROVFWriting a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT4Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT3Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT2Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT1Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_INTWriting a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are.." "0,1" line.word 0x2 "CONTROLSS_ECAP0_ECFRC" bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTROVFWriting a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT4Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT3Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT2Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT1Sets the CEVT1 flag." "0,1" group.long 0x3C++0x7 line.long 0x0 "CONTROLSS_ECAP0_ECAPSYNCINSEL" hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determines the source of SYNCIN signal. 0x0 : Disabled using SOC tieoff. 0x7F : Refer to SOC spec for details." line.long 0x4 "CONTROLSS_ECAP0_HRCTL" bitfld.long 0x4 5. "CALIBCONT,Continuous mode Calibration Select Bit: 0 Continuous mode disabled. 1 Continuous mode enabled. Calibration automatically restarts at end of current calibration cycle." "0,1" newline rbitfld.long 0x4 4. "CALIBSTS,Calibration status Bit: 0 No active calibration cycle 1 Calibration cycle in progress" "0,1" newline bitfld.long 0x4 3. "CALIBSTART,Calibration start Bit: 0 No effect 1 Starts the calibration cycle" "0,1" newline bitfld.long 0x4 2. "PRDSEL,Calibration Period Match Select Bit: 0 Use SYSCLK Counter For Period Match (default at reset) 1 Reserved" "0,1" newline bitfld.long 0x4 1. "HRCLKE,High Resolution Clock Enable Bit: 0 High resolution clock disabled (default at reset) 1 High resolution clock enabled. The clock should be enabled before enabling the high res function via the HRE bit." "0,1" newline bitfld.long 0x4 0. "HRE,High Resolution Enable Bit: 0 High resolution mode disabled (default at reset) 1 High resolution mode enabled. Enabling this mode will connect the capture registers and edge event modes of the ECAP to be accessed by the High Res function. Note: The.." "0,1" group.long 0x48++0x3 line.long 0x0 "CONTROLSS_ECAP0_HRINTEN" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration Period Check status Interrupt Enable: 0 Disable Calibration Period Check interrupt status 1 Enable Calibration Period Check interrupt status" "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration done Interrupt Enable: 0 Disable Calibration done Interrupt 1 Enable Calibration done Interrupt" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CONTROLSS_ECAP0_HRFLG" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration period check status Flag Bit: 1 Indicates that calibration ended before PRDCHK due to overflow on one of the counters. 0 Indicates no event occurred. Note: This bit remains latched until cleared by the user using the HRCLR.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration Done Interrupt Flag Bit: 1 Indicates calibration cycle is completed 0 Indicates calibration cycle has not completed. Note: This bit remains latched until cleared by the user using the HRCLR [CALIBDONE] bit." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Global calibration Interrupt Status Flag: 1 Indicates that an interrupt was generated from CALIBDONE or CALPRDCHKSTS. 0 Indicates no interrupt generated." "0,1" group.long 0x50++0xB line.long 0x0 "CONTROLSS_ECAP0_HRCLR" bitfld.long 0x0 2. "CALPRDCHKSTS,Clear Calibration period check status Flag Bit: 1 Clears the CALPRDCHKSTS flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Clear Calibration Done Interrupt Flag Bit: 1 Clears the CALIBDONE interrupt flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Clear Global calibration Interrupt Flag 1 Clears the Global interrupt flag and enables further interrupts to be generated if any of the event flags are set. 0 No effect." "0,1" line.long 0x4 "CONTROLSS_ECAP0_HRFRC" bitfld.long 0x4 2. "CALPRDCHKSTS,Force CALPRDCHKSTS flag: 0 No effect 1 Sets the CALPRDCHKSTS flag." "0,1" newline bitfld.long 0x4 1. "CALIBDONE,Force CALIBDONE flag: 0 No effect 1 Sets the CALIBDONE flag." "0,1" line.long 0x8 "CONTROLSS_ECAP0_HRCALPRD" hexmask.long 0x8 0.--31. 1. "PRD,Register to program calibration period. The period value is matched against HRSYSCLKCTR. On a match an interrupt is generated and the counter registers values are captured." rgroup.long 0x5C++0xF line.long 0x0 "CONTROLSS_ECAP0_HRSYSCLKCTR" hexmask.long 0x0 0.--31. 1. "HRSYSCLKCTR,Current SYSCLK counter value" line.long 0x4 "CONTROLSS_ECAP0_HRSYSCLKCAP" hexmask.long 0x4 0.--31. 1. "HRSYSCLKCAP,HRSYSCLKCTR is captures into this register at end of calibration cycle." line.long 0x8 "CONTROLSS_ECAP0_HRCLKCTR" hexmask.long 0x8 0.--31. 1. "HRCLKCTR,Current HRCLK counter value Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" line.long 0xC "CONTROLSS_ECAP0_HRCLKCAP" hexmask.long 0xC 0.--31. 1. "HRCLKCAP,HRCLKCTR is captures into this register at end of calibration cycle. Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" group.long 0x74++0x3 line.long 0x0 "CONTROLSS_ECAP0_HRDEBUGCTL" hexmask.long.byte 0x0 8.--11. 1. "OBSERVE_SRC_SEL,Select bits for selecting source for OBSERVE1 and OBSERVE2 registers 1000 HROUTH and HROUTL will read HR1OUT 1001 HROUTH and HROUTL will read HR2OUT 1010 HROUTH and HROUTL will read Capture Delayline 1 OBS1 1011 HROUTH and HROUTL will.." newline bitfld.long 0x0 4.--5. "CALIB_INPUT_SEL,Select bit for calibration input can be used to get fault coverage using these inputs 00 CAPIN is one of 128 inputs selected by INPUTSEL 01 CAPIN is connected to CAPIN_MEMMAP_SOURCE 10 CAPIN is internally generated signal waveform with.." "0,1,2,3" newline bitfld.long 0x0 2. "CAPIN_MMAP_SOURCE,Memory mapped CAPIN source Note : select CALIN source first it may happen that you may see interrupt if MMAP source is different from current value of CAPIN. This is debug feature hence no additional HW is necessary to prevent this." "0,1" newline bitfld.long 0x0 1. "DELAYRESETDLINE,Controls the reset delayline timing 0 reset is forced on next falling edge of HRCLK (1/2 cycle after capture) 1 reset is applied a cycle later (1 1/2 cycles after capture)" "0,1" newline bitfld.long 0x0 0. "DISABLEINVSEL,Disable INVSEL Logic: 0 State machine controls inversion on input signal 1 CAPIN signal propagated into delay line without inversion this means only rising edges can be measured" "0,1" rgroup.long 0x78++0x7 line.long 0x0 "CONTROLSS_ECAP0_HRDEBUGOBSERVE1" hexmask.long 0x0 0.--31. 1. "HROUTH,Reads raw output of HROUT capture delay line 1" line.long 0x4 "CONTROLSS_ECAP0_HRDEBUGOBSERVE2" hexmask.long 0x4 0.--31. 1. "HROUTL,Reads raw output of HROUT capture delay line 2" group.long 0x80++0x3 line.long 0x0 "CONTROLSS_ECAP0_MUNIT_COMMON_CTL" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Disabled with SOC level tieoff. 0x1 to 0x7F : Global load strobe from SOC level including ETPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not affect signal monitoring achieved with SOC level tieoff. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and.." group.long 0xC0++0x7 line.long 0x0 "CONTROLSS_ECAP0_MUNIT_1_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "CONTROLSS_ECAP0_MUNIT_1_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "CONTROLSS_ECAP0_MUNIT_1_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP0_MUNIT_1_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP0_MUNIT_1_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP0_MUNIT_1_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "CONTROLSS_ECAP0_MUNIT_1_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP0_MUNIT_1_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "CONTROLSS_ECAP0_MUNIT_2_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "CONTROLSS_ECAP0_MUNIT_2_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "CONTROLSS_ECAP0_MUNIT_2_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP0_MUNIT_2_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP0_MUNIT_2_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP0_MUNIT_2_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "CONTROLSS_ECAP0_MUNIT_2_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP0_MUNIT_2_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP1" base ad:0x50241000 group.long 0x0++0x17 line.long 0x0 "CONTROLSS_ECAP1_TSCTR" hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1) This register reads HRCOUNTER value and is not writable 2) can be reset using CTRFILTRESET 3) Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "CONTROLSS_ECAP1_CTRPHS" hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "CONTROLSS_ECAP1_CAP1" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by: - Time-Stamp counter value (TSCTR) during a capture event - Software - may be useful for test purposes or initialization - ARPD shadow register (CAP3) when used in APWM mode" line.long 0xC "CONTROLSS_ECAP1_CAP2" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by: - Time-Stamp ( counter value) during a capture event - Software - may be useful for test purposes - ACMP shadow register (CAP4) when used in APWM mode" line.long 0x10 "CONTROLSS_ECAP1_CAP3" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register. In APWM mode this is the period shadow (APRD) register. You can update the PWM period value through this register. CAP3 (APRD) shadows CAP1 in this mode." line.long 0x14 "CONTROLSS_ECAP1_CAP4" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register. In APWM mode this is the compare shadow (ACMP) register. You can update the PWM compare value via this register. CAP4 (ACMP) shadows CAP2 in this mode." group.long 0x24++0x3 line.long 0x0 "CONTROLSS_ECAP1_ECCTL0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b (R/W) = SOC trigger source is CEVT1 01b (R/W) = SOC trigger source is CEVT2 10b (R/W) = SOC trigger source is CEVT3 11b (R/W) = SOC trigger source is CEVT4 APWM Mode: 00b (R/W) = SOC trigger interrupt.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "CONTROLSS_ECAP1_ECCTL1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0x0 | ECAP_STOP_EMUTSCTR counter stops immediately on emulation suspend 0x1 | ECAP_RUNS_UNTILTSCTR counter runs until = 0 0x2 | ECAP_UNAF_EMU_SUSTSCTR counter is unaffected by emulation suspend (Run.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0x00 | ECAP_DIV1Divide by 1 (i.e . no prescale by-pass the prescaler) 0x01 | ECAP_DIV2Divide by 2 0x02 | ECAP_DIV4Divide by 4 0x03 | ECAP_DIV6Divide by 6 0x04 |.." newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 | ECAP_DISABLEDisable CAP1-4 register loads at capture event time. 1 | ECAP_ENABLEEnable CAP1-4.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 | ECAP_DO_NOT_RESET_EVENT4Do not reset counter on Capture Event 4 (absolute time stamp operation) 1 | ECAP_RESET_EVENT4Reset counter after Capture Event 4 time-stamp has been captured (used in.." "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 | ECAP_CAP_EVENT4_RISECapture Event 4 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT4_FALLCapture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 | ECAP_DO_NOT_RESET_EVENT3Do not reset counter on Capture Event 3 (absolute time stamp) 1 | ECAP_RESET_EVENT3Reset counter after Event 3 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 | ECAP_CAP_EVENT3_RISECapture Event 3 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT3_FALLCapture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 | ECAP_DO_NOT_RESET_EVENT2Do not reset counter on Capture Event 2 (absolute time stamp) 1 | ECAP_RESET_EVENT2Reset counter after Event 2 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 | ECAP_CAP_EVENT2_RISECapture Event 2 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT2_FALLCapture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 | ECAP_DO_NOT_RESET_EVENT1Do not reset counter on Capture Event 1 (absolute time stamp) 1 | ECAP_RESET_EVENT1Reset counter after Event 1 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 | ECAP_CAP_EVENT1_RISECapture Event 1 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT1_FALLCapture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "CONTROLSS_ECAP1_ECCTL2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b (R) = CAP1 register gets loaded on next capture event. 01b (R) = CAP2 register gets loaded on next capture event. 10b (R) = CAP3 register gets loaded on next capture event. 11b (R) =.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b (R/W) = DMA interrupt source is CEVT1 01b (R/W) = DMA interrupt source is CEVT2 10b (R/W) = DMA interrupt source is CEVT3 11b (R/W) = DMA interrupt source is CEVT4 APWM Mode: 00b (R/W) = DMA interrupt source.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h (R) = No effect 1h (W) = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 | ECAP_OUTPUT_ACTIVE_HIGHOutput is active high (Compare value defines high time) 1 | ECAP_OUTPUT_ACTIVE_LOWOutput is active low (Compare value defines.." "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 | ECAP_MODULEECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers - Permits user.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter (TSCTR) Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 |.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0x0 | SWSYNCsync out signal is SWSYNC 0x1 | ECAP_CTR_PRD_TO_SYNCOUTSelect CTR = PRD event to be the sync-out signal 0x2 | ECAP_DISABLE_SYNC_OUTDisable sync out signal 0x3 |.." "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter (TSCTR) Sync-In select mode 0 | ECAP_DISABLE_SYNC_INDisable sync-in option 1 | ECAP_ENABLE_COUNTER_REGISTEREnable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp (TSCTR) Counter Stop (freeze) Control 0 | ECAP_TSCTR_STOPPEDTSCTR stopped 1 | ECAP_TSCTR_FREE_RUNNINGTSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 | ECAP_NO_EFFECT_RETURNS_0Has no effect (reading always returns a 0) 1 | ECAP_ARMS_ONESHOTArms the one-shot sequence as follows: 1) Resets the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur before the CAP(1-4) registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1-4) of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control (applicable only in capture mode) 0 | ECAP_OPP_CONTOperate in continuous mode 1 | ECAP_OPP_ONEOperate in one-Shot mode" "0,1" line.word 0x4 "CONTROLSS_ECAP1_ECEINT" bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 | ECAP_DISAB_HRERROR_INTERRUPTDisable High Resolution Error as an Interrupt source 1 | ECAP_ENAB_HRERROR_INTERRUPTEnable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 | ECAP_DISAB_CE_INTERRUPTDisable Compare Equal as an Interrupt source 1 | ECAP_ENAB_CE_INTERRUPTEnable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 | ECAP_DISAB_PE_INTERRUPTDisable Period Equal as an Interrupt source 1 | ECAP_ENAB_PE_INTERRUPTEnable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 | ECAP_DISAB_CO_INTERRUPTDisabled counter Overflow as an Interrupt source 1 | ECAP_ENAB_CO_INTERRUPTEnable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 | ECAP_DISAB_CAP4_INTERRUPTDisable Capture Event 4 as an Interrupt source 1 | ECAP_ENAB_CAP4_INTERRUPTCapture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 | ECAP_DISAB_CAP3_INTERRUPTDisable Capture Event 3 as an Interrupt source 1 | ECAP_ENAB_CAP3_INTERRUPTEnable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 | ECAP_DISAB_CAP2_INTERRUPTDisable Capture Event 2 as an Interrupt source 1 | ECAP_ENAB_CAP2_INTERRUPTEnable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 | ECAP_DISAB_CAP1_INTERRUPTDisable Capture Event 1 as an Interrupt source 1 | ECAP_ENAB_CAP1_INTERRUPTEnable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "CONTROLSS_ECAP1_ECFLG" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_HIGH_RESOLUTION_ERRORIndicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_COMPARE_REGIndicates the counter (TSCTR) reached the compare.." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_PERIOD_VALUE_RESETIndicates the counter (TSCTR) reached the period register.." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_TRANSIndicates the counter (TSCTR) has made the transition from.." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_4TH_EVENT_ECAPXIndicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_3RD_EVENT_ECAPXIndicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_2ND_EVENT_ECAPXIndicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_1ST_EVENT_ECAPXIndicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_INTERRUPTIndicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_ECAP1_ECCLR" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_HRERRORWriting a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_CMPWriting a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTROVFWriting a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT4Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT3Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT2Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT1Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_INTWriting a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are.." "0,1" line.word 0x2 "CONTROLSS_ECAP1_ECFRC" bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTROVFWriting a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT4Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT3Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT2Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT1Sets the CEVT1 flag." "0,1" group.long 0x3C++0x7 line.long 0x0 "CONTROLSS_ECAP1_ECAPSYNCINSEL" hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determines the source of SYNCIN signal. 0x0 : Disabled using SOC tieoff. 0x7F : Refer to SOC spec for details." line.long 0x4 "CONTROLSS_ECAP1_HRCTL" bitfld.long 0x4 5. "CALIBCONT,Continuous mode Calibration Select Bit: 0 Continuous mode disabled. 1 Continuous mode enabled. Calibration automatically restarts at end of current calibration cycle." "0,1" newline rbitfld.long 0x4 4. "CALIBSTS,Calibration status Bit: 0 No active calibration cycle 1 Calibration cycle in progress" "0,1" newline bitfld.long 0x4 3. "CALIBSTART,Calibration start Bit: 0 No effect 1 Starts the calibration cycle" "0,1" newline bitfld.long 0x4 2. "PRDSEL,Calibration Period Match Select Bit: 0 Use SYSCLK Counter For Period Match (default at reset) 1 Reserved" "0,1" newline bitfld.long 0x4 1. "HRCLKE,High Resolution Clock Enable Bit: 0 High resolution clock disabled (default at reset) 1 High resolution clock enabled. The clock should be enabled before enabling the high res function via the HRE bit." "0,1" newline bitfld.long 0x4 0. "HRE,High Resolution Enable Bit: 0 High resolution mode disabled (default at reset) 1 High resolution mode enabled. Enabling this mode will connect the capture registers and edge event modes of the ECAP to be accessed by the High Res function. Note: The.." "0,1" group.long 0x48++0x3 line.long 0x0 "CONTROLSS_ECAP1_HRINTEN" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration Period Check status Interrupt Enable: 0 Disable Calibration Period Check interrupt status 1 Enable Calibration Period Check interrupt status" "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration done Interrupt Enable: 0 Disable Calibration done Interrupt 1 Enable Calibration done Interrupt" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CONTROLSS_ECAP1_HRFLG" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration period check status Flag Bit: 1 Indicates that calibration ended before PRDCHK due to overflow on one of the counters. 0 Indicates no event occurred. Note: This bit remains latched until cleared by the user using the HRCLR.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration Done Interrupt Flag Bit: 1 Indicates calibration cycle is completed 0 Indicates calibration cycle has not completed. Note: This bit remains latched until cleared by the user using the HRCLR [CALIBDONE] bit." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Global calibration Interrupt Status Flag: 1 Indicates that an interrupt was generated from CALIBDONE or CALPRDCHKSTS. 0 Indicates no interrupt generated." "0,1" group.long 0x50++0xB line.long 0x0 "CONTROLSS_ECAP1_HRCLR" bitfld.long 0x0 2. "CALPRDCHKSTS,Clear Calibration period check status Flag Bit: 1 Clears the CALPRDCHKSTS flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Clear Calibration Done Interrupt Flag Bit: 1 Clears the CALIBDONE interrupt flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Clear Global calibration Interrupt Flag 1 Clears the Global interrupt flag and enables further interrupts to be generated if any of the event flags are set. 0 No effect." "0,1" line.long 0x4 "CONTROLSS_ECAP1_HRFRC" bitfld.long 0x4 2. "CALPRDCHKSTS,Force CALPRDCHKSTS flag: 0 No effect 1 Sets the CALPRDCHKSTS flag." "0,1" newline bitfld.long 0x4 1. "CALIBDONE,Force CALIBDONE flag: 0 No effect 1 Sets the CALIBDONE flag." "0,1" line.long 0x8 "CONTROLSS_ECAP1_HRCALPRD" hexmask.long 0x8 0.--31. 1. "PRD,Register to program calibration period. The period value is matched against HRSYSCLKCTR. On a match an interrupt is generated and the counter registers values are captured." rgroup.long 0x5C++0xF line.long 0x0 "CONTROLSS_ECAP1_HRSYSCLKCTR" hexmask.long 0x0 0.--31. 1. "HRSYSCLKCTR,Current SYSCLK counter value" line.long 0x4 "CONTROLSS_ECAP1_HRSYSCLKCAP" hexmask.long 0x4 0.--31. 1. "HRSYSCLKCAP,HRSYSCLKCTR is captures into this register at end of calibration cycle." line.long 0x8 "CONTROLSS_ECAP1_HRCLKCTR" hexmask.long 0x8 0.--31. 1. "HRCLKCTR,Current HRCLK counter value Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" line.long 0xC "CONTROLSS_ECAP1_HRCLKCAP" hexmask.long 0xC 0.--31. 1. "HRCLKCAP,HRCLKCTR is captures into this register at end of calibration cycle. Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" group.long 0x74++0x3 line.long 0x0 "CONTROLSS_ECAP1_HRDEBUGCTL" hexmask.long.byte 0x0 8.--11. 1. "OBSERVE_SRC_SEL,Select bits for selecting source for OBSERVE1 and OBSERVE2 registers 1000 HROUTH and HROUTL will read HR1OUT 1001 HROUTH and HROUTL will read HR2OUT 1010 HROUTH and HROUTL will read Capture Delayline 1 OBS1 1011 HROUTH and HROUTL will.." newline bitfld.long 0x0 4.--5. "CALIB_INPUT_SEL,Select bit for calibration input can be used to get fault coverage using these inputs 00 CAPIN is one of 128 inputs selected by INPUTSEL 01 CAPIN is connected to CAPIN_MEMMAP_SOURCE 10 CAPIN is internally generated signal waveform with.." "0,1,2,3" newline bitfld.long 0x0 2. "CAPIN_MMAP_SOURCE,Memory mapped CAPIN source Note : select CALIN source first it may happen that you may see interrupt if MMAP source is different from current value of CAPIN. This is debug feature hence no additional HW is necessary to prevent this." "0,1" newline bitfld.long 0x0 1. "DELAYRESETDLINE,Controls the reset delayline timing 0 reset is forced on next falling edge of HRCLK (1/2 cycle after capture) 1 reset is applied a cycle later (1 1/2 cycles after capture)" "0,1" newline bitfld.long 0x0 0. "DISABLEINVSEL,Disable INVSEL Logic: 0 State machine controls inversion on input signal 1 CAPIN signal propagated into delay line without inversion this means only rising edges can be measured" "0,1" rgroup.long 0x78++0x7 line.long 0x0 "CONTROLSS_ECAP1_HRDEBUGOBSERVE1" hexmask.long 0x0 0.--31. 1. "HROUTH,Reads raw output of HROUT capture delay line 1" line.long 0x4 "CONTROLSS_ECAP1_HRDEBUGOBSERVE2" hexmask.long 0x4 0.--31. 1. "HROUTL,Reads raw output of HROUT capture delay line 2" group.long 0x80++0x3 line.long 0x0 "CONTROLSS_ECAP1_MUNIT_COMMON_CTL" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Disabled with SOC level tieoff. 0x1 to 0x7F : Global load strobe from SOC level including ETPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not affect signal monitoring achieved with SOC level tieoff. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and.." group.long 0xC0++0x7 line.long 0x0 "CONTROLSS_ECAP1_MUNIT_1_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "CONTROLSS_ECAP1_MUNIT_1_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "CONTROLSS_ECAP1_MUNIT_1_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP1_MUNIT_1_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP1_MUNIT_1_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP1_MUNIT_1_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "CONTROLSS_ECAP1_MUNIT_1_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP1_MUNIT_1_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "CONTROLSS_ECAP1_MUNIT_2_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "CONTROLSS_ECAP1_MUNIT_2_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "CONTROLSS_ECAP1_MUNIT_2_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP1_MUNIT_2_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP1_MUNIT_2_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP1_MUNIT_2_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "CONTROLSS_ECAP1_MUNIT_2_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP1_MUNIT_2_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP2" base ad:0x50242000 group.long 0x0++0x17 line.long 0x0 "CONTROLSS_ECAP2_TSCTR" hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1) This register reads HRCOUNTER value and is not writable 2) can be reset using CTRFILTRESET 3) Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "CONTROLSS_ECAP2_CTRPHS" hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "CONTROLSS_ECAP2_CAP1" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by: - Time-Stamp counter value (TSCTR) during a capture event - Software - may be useful for test purposes or initialization - ARPD shadow register (CAP3) when used in APWM mode" line.long 0xC "CONTROLSS_ECAP2_CAP2" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by: - Time-Stamp ( counter value) during a capture event - Software - may be useful for test purposes - ACMP shadow register (CAP4) when used in APWM mode" line.long 0x10 "CONTROLSS_ECAP2_CAP3" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register. In APWM mode this is the period shadow (APRD) register. You can update the PWM period value through this register. CAP3 (APRD) shadows CAP1 in this mode." line.long 0x14 "CONTROLSS_ECAP2_CAP4" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register. In APWM mode this is the compare shadow (ACMP) register. You can update the PWM compare value via this register. CAP4 (ACMP) shadows CAP2 in this mode." group.long 0x24++0x3 line.long 0x0 "CONTROLSS_ECAP2_ECCTL0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b (R/W) = SOC trigger source is CEVT1 01b (R/W) = SOC trigger source is CEVT2 10b (R/W) = SOC trigger source is CEVT3 11b (R/W) = SOC trigger source is CEVT4 APWM Mode: 00b (R/W) = SOC trigger interrupt.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "CONTROLSS_ECAP2_ECCTL1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0x0 | ECAP_STOP_EMUTSCTR counter stops immediately on emulation suspend 0x1 | ECAP_RUNS_UNTILTSCTR counter runs until = 0 0x2 | ECAP_UNAF_EMU_SUSTSCTR counter is unaffected by emulation suspend (Run.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0x00 | ECAP_DIV1Divide by 1 (i.e . no prescale by-pass the prescaler) 0x01 | ECAP_DIV2Divide by 2 0x02 | ECAP_DIV4Divide by 4 0x03 | ECAP_DIV6Divide by 6 0x04 |.." newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 | ECAP_DISABLEDisable CAP1-4 register loads at capture event time. 1 | ECAP_ENABLEEnable CAP1-4.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 | ECAP_DO_NOT_RESET_EVENT4Do not reset counter on Capture Event 4 (absolute time stamp operation) 1 | ECAP_RESET_EVENT4Reset counter after Capture Event 4 time-stamp has been captured (used in.." "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 | ECAP_CAP_EVENT4_RISECapture Event 4 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT4_FALLCapture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 | ECAP_DO_NOT_RESET_EVENT3Do not reset counter on Capture Event 3 (absolute time stamp) 1 | ECAP_RESET_EVENT3Reset counter after Event 3 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 | ECAP_CAP_EVENT3_RISECapture Event 3 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT3_FALLCapture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 | ECAP_DO_NOT_RESET_EVENT2Do not reset counter on Capture Event 2 (absolute time stamp) 1 | ECAP_RESET_EVENT2Reset counter after Event 2 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 | ECAP_CAP_EVENT2_RISECapture Event 2 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT2_FALLCapture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 | ECAP_DO_NOT_RESET_EVENT1Do not reset counter on Capture Event 1 (absolute time stamp) 1 | ECAP_RESET_EVENT1Reset counter after Event 1 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 | ECAP_CAP_EVENT1_RISECapture Event 1 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT1_FALLCapture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "CONTROLSS_ECAP2_ECCTL2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b (R) = CAP1 register gets loaded on next capture event. 01b (R) = CAP2 register gets loaded on next capture event. 10b (R) = CAP3 register gets loaded on next capture event. 11b (R) =.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b (R/W) = DMA interrupt source is CEVT1 01b (R/W) = DMA interrupt source is CEVT2 10b (R/W) = DMA interrupt source is CEVT3 11b (R/W) = DMA interrupt source is CEVT4 APWM Mode: 00b (R/W) = DMA interrupt source.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h (R) = No effect 1h (W) = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 | ECAP_OUTPUT_ACTIVE_HIGHOutput is active high (Compare value defines high time) 1 | ECAP_OUTPUT_ACTIVE_LOWOutput is active low (Compare value defines.." "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 | ECAP_MODULEECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers - Permits user.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter (TSCTR) Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 |.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0x0 | SWSYNCsync out signal is SWSYNC 0x1 | ECAP_CTR_PRD_TO_SYNCOUTSelect CTR = PRD event to be the sync-out signal 0x2 | ECAP_DISABLE_SYNC_OUTDisable sync out signal 0x3 |.." "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter (TSCTR) Sync-In select mode 0 | ECAP_DISABLE_SYNC_INDisable sync-in option 1 | ECAP_ENABLE_COUNTER_REGISTEREnable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp (TSCTR) Counter Stop (freeze) Control 0 | ECAP_TSCTR_STOPPEDTSCTR stopped 1 | ECAP_TSCTR_FREE_RUNNINGTSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 | ECAP_NO_EFFECT_RETURNS_0Has no effect (reading always returns a 0) 1 | ECAP_ARMS_ONESHOTArms the one-shot sequence as follows: 1) Resets the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur before the CAP(1-4) registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1-4) of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control (applicable only in capture mode) 0 | ECAP_OPP_CONTOperate in continuous mode 1 | ECAP_OPP_ONEOperate in one-Shot mode" "0,1" line.word 0x4 "CONTROLSS_ECAP2_ECEINT" bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 | ECAP_DISAB_HRERROR_INTERRUPTDisable High Resolution Error as an Interrupt source 1 | ECAP_ENAB_HRERROR_INTERRUPTEnable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 | ECAP_DISAB_CE_INTERRUPTDisable Compare Equal as an Interrupt source 1 | ECAP_ENAB_CE_INTERRUPTEnable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 | ECAP_DISAB_PE_INTERRUPTDisable Period Equal as an Interrupt source 1 | ECAP_ENAB_PE_INTERRUPTEnable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 | ECAP_DISAB_CO_INTERRUPTDisabled counter Overflow as an Interrupt source 1 | ECAP_ENAB_CO_INTERRUPTEnable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 | ECAP_DISAB_CAP4_INTERRUPTDisable Capture Event 4 as an Interrupt source 1 | ECAP_ENAB_CAP4_INTERRUPTCapture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 | ECAP_DISAB_CAP3_INTERRUPTDisable Capture Event 3 as an Interrupt source 1 | ECAP_ENAB_CAP3_INTERRUPTEnable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 | ECAP_DISAB_CAP2_INTERRUPTDisable Capture Event 2 as an Interrupt source 1 | ECAP_ENAB_CAP2_INTERRUPTEnable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 | ECAP_DISAB_CAP1_INTERRUPTDisable Capture Event 1 as an Interrupt source 1 | ECAP_ENAB_CAP1_INTERRUPTEnable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "CONTROLSS_ECAP2_ECFLG" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_HIGH_RESOLUTION_ERRORIndicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_COMPARE_REGIndicates the counter (TSCTR) reached the compare.." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_PERIOD_VALUE_RESETIndicates the counter (TSCTR) reached the period register.." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_TRANSIndicates the counter (TSCTR) has made the transition from.." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_4TH_EVENT_ECAPXIndicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_3RD_EVENT_ECAPXIndicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_2ND_EVENT_ECAPXIndicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_1ST_EVENT_ECAPXIndicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_INTERRUPTIndicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_ECAP2_ECCLR" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_HRERRORWriting a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_CMPWriting a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTROVFWriting a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT4Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT3Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT2Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT1Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_INTWriting a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are.." "0,1" line.word 0x2 "CONTROLSS_ECAP2_ECFRC" bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTROVFWriting a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT4Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT3Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT2Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT1Sets the CEVT1 flag." "0,1" group.long 0x3C++0x7 line.long 0x0 "CONTROLSS_ECAP2_ECAPSYNCINSEL" hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determines the source of SYNCIN signal. 0x0 : Disabled using SOC tieoff. 0x7F : Refer to SOC spec for details." line.long 0x4 "CONTROLSS_ECAP2_HRCTL" bitfld.long 0x4 5. "CALIBCONT,Continuous mode Calibration Select Bit: 0 Continuous mode disabled. 1 Continuous mode enabled. Calibration automatically restarts at end of current calibration cycle." "0,1" newline rbitfld.long 0x4 4. "CALIBSTS,Calibration status Bit: 0 No active calibration cycle 1 Calibration cycle in progress" "0,1" newline bitfld.long 0x4 3. "CALIBSTART,Calibration start Bit: 0 No effect 1 Starts the calibration cycle" "0,1" newline bitfld.long 0x4 2. "PRDSEL,Calibration Period Match Select Bit: 0 Use SYSCLK Counter For Period Match (default at reset) 1 Reserved" "0,1" newline bitfld.long 0x4 1. "HRCLKE,High Resolution Clock Enable Bit: 0 High resolution clock disabled (default at reset) 1 High resolution clock enabled. The clock should be enabled before enabling the high res function via the HRE bit." "0,1" newline bitfld.long 0x4 0. "HRE,High Resolution Enable Bit: 0 High resolution mode disabled (default at reset) 1 High resolution mode enabled. Enabling this mode will connect the capture registers and edge event modes of the ECAP to be accessed by the High Res function. Note: The.." "0,1" group.long 0x48++0x3 line.long 0x0 "CONTROLSS_ECAP2_HRINTEN" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration Period Check status Interrupt Enable: 0 Disable Calibration Period Check interrupt status 1 Enable Calibration Period Check interrupt status" "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration done Interrupt Enable: 0 Disable Calibration done Interrupt 1 Enable Calibration done Interrupt" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CONTROLSS_ECAP2_HRFLG" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration period check status Flag Bit: 1 Indicates that calibration ended before PRDCHK due to overflow on one of the counters. 0 Indicates no event occurred. Note: This bit remains latched until cleared by the user using the HRCLR.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration Done Interrupt Flag Bit: 1 Indicates calibration cycle is completed 0 Indicates calibration cycle has not completed. Note: This bit remains latched until cleared by the user using the HRCLR [CALIBDONE] bit." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Global calibration Interrupt Status Flag: 1 Indicates that an interrupt was generated from CALIBDONE or CALPRDCHKSTS. 0 Indicates no interrupt generated." "0,1" group.long 0x50++0xB line.long 0x0 "CONTROLSS_ECAP2_HRCLR" bitfld.long 0x0 2. "CALPRDCHKSTS,Clear Calibration period check status Flag Bit: 1 Clears the CALPRDCHKSTS flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Clear Calibration Done Interrupt Flag Bit: 1 Clears the CALIBDONE interrupt flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Clear Global calibration Interrupt Flag 1 Clears the Global interrupt flag and enables further interrupts to be generated if any of the event flags are set. 0 No effect." "0,1" line.long 0x4 "CONTROLSS_ECAP2_HRFRC" bitfld.long 0x4 2. "CALPRDCHKSTS,Force CALPRDCHKSTS flag: 0 No effect 1 Sets the CALPRDCHKSTS flag." "0,1" newline bitfld.long 0x4 1. "CALIBDONE,Force CALIBDONE flag: 0 No effect 1 Sets the CALIBDONE flag." "0,1" line.long 0x8 "CONTROLSS_ECAP2_HRCALPRD" hexmask.long 0x8 0.--31. 1. "PRD,Register to program calibration period. The period value is matched against HRSYSCLKCTR. On a match an interrupt is generated and the counter registers values are captured." rgroup.long 0x5C++0xF line.long 0x0 "CONTROLSS_ECAP2_HRSYSCLKCTR" hexmask.long 0x0 0.--31. 1. "HRSYSCLKCTR,Current SYSCLK counter value" line.long 0x4 "CONTROLSS_ECAP2_HRSYSCLKCAP" hexmask.long 0x4 0.--31. 1. "HRSYSCLKCAP,HRSYSCLKCTR is captures into this register at end of calibration cycle." line.long 0x8 "CONTROLSS_ECAP2_HRCLKCTR" hexmask.long 0x8 0.--31. 1. "HRCLKCTR,Current HRCLK counter value Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" line.long 0xC "CONTROLSS_ECAP2_HRCLKCAP" hexmask.long 0xC 0.--31. 1. "HRCLKCAP,HRCLKCTR is captures into this register at end of calibration cycle. Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" group.long 0x74++0x3 line.long 0x0 "CONTROLSS_ECAP2_HRDEBUGCTL" hexmask.long.byte 0x0 8.--11. 1. "OBSERVE_SRC_SEL,Select bits for selecting source for OBSERVE1 and OBSERVE2 registers 1000 HROUTH and HROUTL will read HR1OUT 1001 HROUTH and HROUTL will read HR2OUT 1010 HROUTH and HROUTL will read Capture Delayline 1 OBS1 1011 HROUTH and HROUTL will.." newline bitfld.long 0x0 4.--5. "CALIB_INPUT_SEL,Select bit for calibration input can be used to get fault coverage using these inputs 00 CAPIN is one of 128 inputs selected by INPUTSEL 01 CAPIN is connected to CAPIN_MEMMAP_SOURCE 10 CAPIN is internally generated signal waveform with.." "0,1,2,3" newline bitfld.long 0x0 2. "CAPIN_MMAP_SOURCE,Memory mapped CAPIN source Note : select CALIN source first it may happen that you may see interrupt if MMAP source is different from current value of CAPIN. This is debug feature hence no additional HW is necessary to prevent this." "0,1" newline bitfld.long 0x0 1. "DELAYRESETDLINE,Controls the reset delayline timing 0 reset is forced on next falling edge of HRCLK (1/2 cycle after capture) 1 reset is applied a cycle later (1 1/2 cycles after capture)" "0,1" newline bitfld.long 0x0 0. "DISABLEINVSEL,Disable INVSEL Logic: 0 State machine controls inversion on input signal 1 CAPIN signal propagated into delay line without inversion this means only rising edges can be measured" "0,1" rgroup.long 0x78++0x7 line.long 0x0 "CONTROLSS_ECAP2_HRDEBUGOBSERVE1" hexmask.long 0x0 0.--31. 1. "HROUTH,Reads raw output of HROUT capture delay line 1" line.long 0x4 "CONTROLSS_ECAP2_HRDEBUGOBSERVE2" hexmask.long 0x4 0.--31. 1. "HROUTL,Reads raw output of HROUT capture delay line 2" group.long 0x80++0x3 line.long 0x0 "CONTROLSS_ECAP2_MUNIT_COMMON_CTL" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Disabled with SOC level tieoff. 0x1 to 0x7F : Global load strobe from SOC level including ETPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not affect signal monitoring achieved with SOC level tieoff. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and.." group.long 0xC0++0x7 line.long 0x0 "CONTROLSS_ECAP2_MUNIT_1_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "CONTROLSS_ECAP2_MUNIT_1_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "CONTROLSS_ECAP2_MUNIT_1_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP2_MUNIT_1_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP2_MUNIT_1_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP2_MUNIT_1_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "CONTROLSS_ECAP2_MUNIT_1_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP2_MUNIT_1_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "CONTROLSS_ECAP2_MUNIT_2_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "CONTROLSS_ECAP2_MUNIT_2_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "CONTROLSS_ECAP2_MUNIT_2_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP2_MUNIT_2_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP2_MUNIT_2_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP2_MUNIT_2_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "CONTROLSS_ECAP2_MUNIT_2_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP2_MUNIT_2_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP3" base ad:0x50243000 group.long 0x0++0x17 line.long 0x0 "CONTROLSS_ECAP3_TSCTR" hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1) This register reads HRCOUNTER value and is not writable 2) can be reset using CTRFILTRESET 3) Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "CONTROLSS_ECAP3_CTRPHS" hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "CONTROLSS_ECAP3_CAP1" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by: - Time-Stamp counter value (TSCTR) during a capture event - Software - may be useful for test purposes or initialization - ARPD shadow register (CAP3) when used in APWM mode" line.long 0xC "CONTROLSS_ECAP3_CAP2" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by: - Time-Stamp ( counter value) during a capture event - Software - may be useful for test purposes - ACMP shadow register (CAP4) when used in APWM mode" line.long 0x10 "CONTROLSS_ECAP3_CAP3" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register. In APWM mode this is the period shadow (APRD) register. You can update the PWM period value through this register. CAP3 (APRD) shadows CAP1 in this mode." line.long 0x14 "CONTROLSS_ECAP3_CAP4" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register. In APWM mode this is the compare shadow (ACMP) register. You can update the PWM compare value via this register. CAP4 (ACMP) shadows CAP2 in this mode." group.long 0x24++0x3 line.long 0x0 "CONTROLSS_ECAP3_ECCTL0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b (R/W) = SOC trigger source is CEVT1 01b (R/W) = SOC trigger source is CEVT2 10b (R/W) = SOC trigger source is CEVT3 11b (R/W) = SOC trigger source is CEVT4 APWM Mode: 00b (R/W) = SOC trigger interrupt.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "CONTROLSS_ECAP3_ECCTL1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0x0 | ECAP_STOP_EMUTSCTR counter stops immediately on emulation suspend 0x1 | ECAP_RUNS_UNTILTSCTR counter runs until = 0 0x2 | ECAP_UNAF_EMU_SUSTSCTR counter is unaffected by emulation suspend (Run.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0x00 | ECAP_DIV1Divide by 1 (i.e . no prescale by-pass the prescaler) 0x01 | ECAP_DIV2Divide by 2 0x02 | ECAP_DIV4Divide by 4 0x03 | ECAP_DIV6Divide by 6 0x04 |.." newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 | ECAP_DISABLEDisable CAP1-4 register loads at capture event time. 1 | ECAP_ENABLEEnable CAP1-4.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 | ECAP_DO_NOT_RESET_EVENT4Do not reset counter on Capture Event 4 (absolute time stamp operation) 1 | ECAP_RESET_EVENT4Reset counter after Capture Event 4 time-stamp has been captured (used in.." "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 | ECAP_CAP_EVENT4_RISECapture Event 4 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT4_FALLCapture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 | ECAP_DO_NOT_RESET_EVENT3Do not reset counter on Capture Event 3 (absolute time stamp) 1 | ECAP_RESET_EVENT3Reset counter after Event 3 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 | ECAP_CAP_EVENT3_RISECapture Event 3 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT3_FALLCapture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 | ECAP_DO_NOT_RESET_EVENT2Do not reset counter on Capture Event 2 (absolute time stamp) 1 | ECAP_RESET_EVENT2Reset counter after Event 2 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 | ECAP_CAP_EVENT2_RISECapture Event 2 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT2_FALLCapture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 | ECAP_DO_NOT_RESET_EVENT1Do not reset counter on Capture Event 1 (absolute time stamp) 1 | ECAP_RESET_EVENT1Reset counter after Event 1 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 | ECAP_CAP_EVENT1_RISECapture Event 1 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT1_FALLCapture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "CONTROLSS_ECAP3_ECCTL2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b (R) = CAP1 register gets loaded on next capture event. 01b (R) = CAP2 register gets loaded on next capture event. 10b (R) = CAP3 register gets loaded on next capture event. 11b (R) =.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b (R/W) = DMA interrupt source is CEVT1 01b (R/W) = DMA interrupt source is CEVT2 10b (R/W) = DMA interrupt source is CEVT3 11b (R/W) = DMA interrupt source is CEVT4 APWM Mode: 00b (R/W) = DMA interrupt source.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h (R) = No effect 1h (W) = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 | ECAP_OUTPUT_ACTIVE_HIGHOutput is active high (Compare value defines high time) 1 | ECAP_OUTPUT_ACTIVE_LOWOutput is active low (Compare value defines.." "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 | ECAP_MODULEECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers - Permits user.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter (TSCTR) Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 |.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0x0 | SWSYNCsync out signal is SWSYNC 0x1 | ECAP_CTR_PRD_TO_SYNCOUTSelect CTR = PRD event to be the sync-out signal 0x2 | ECAP_DISABLE_SYNC_OUTDisable sync out signal 0x3 |.." "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter (TSCTR) Sync-In select mode 0 | ECAP_DISABLE_SYNC_INDisable sync-in option 1 | ECAP_ENABLE_COUNTER_REGISTEREnable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp (TSCTR) Counter Stop (freeze) Control 0 | ECAP_TSCTR_STOPPEDTSCTR stopped 1 | ECAP_TSCTR_FREE_RUNNINGTSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 | ECAP_NO_EFFECT_RETURNS_0Has no effect (reading always returns a 0) 1 | ECAP_ARMS_ONESHOTArms the one-shot sequence as follows: 1) Resets the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur before the CAP(1-4) registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1-4) of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control (applicable only in capture mode) 0 | ECAP_OPP_CONTOperate in continuous mode 1 | ECAP_OPP_ONEOperate in one-Shot mode" "0,1" line.word 0x4 "CONTROLSS_ECAP3_ECEINT" bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 | ECAP_DISAB_HRERROR_INTERRUPTDisable High Resolution Error as an Interrupt source 1 | ECAP_ENAB_HRERROR_INTERRUPTEnable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 | ECAP_DISAB_CE_INTERRUPTDisable Compare Equal as an Interrupt source 1 | ECAP_ENAB_CE_INTERRUPTEnable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 | ECAP_DISAB_PE_INTERRUPTDisable Period Equal as an Interrupt source 1 | ECAP_ENAB_PE_INTERRUPTEnable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 | ECAP_DISAB_CO_INTERRUPTDisabled counter Overflow as an Interrupt source 1 | ECAP_ENAB_CO_INTERRUPTEnable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 | ECAP_DISAB_CAP4_INTERRUPTDisable Capture Event 4 as an Interrupt source 1 | ECAP_ENAB_CAP4_INTERRUPTCapture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 | ECAP_DISAB_CAP3_INTERRUPTDisable Capture Event 3 as an Interrupt source 1 | ECAP_ENAB_CAP3_INTERRUPTEnable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 | ECAP_DISAB_CAP2_INTERRUPTDisable Capture Event 2 as an Interrupt source 1 | ECAP_ENAB_CAP2_INTERRUPTEnable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 | ECAP_DISAB_CAP1_INTERRUPTDisable Capture Event 1 as an Interrupt source 1 | ECAP_ENAB_CAP1_INTERRUPTEnable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "CONTROLSS_ECAP3_ECFLG" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_HIGH_RESOLUTION_ERRORIndicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_COMPARE_REGIndicates the counter (TSCTR) reached the compare.." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_PERIOD_VALUE_RESETIndicates the counter (TSCTR) reached the period register.." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_TRANSIndicates the counter (TSCTR) has made the transition from.." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_4TH_EVENT_ECAPXIndicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_3RD_EVENT_ECAPXIndicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_2ND_EVENT_ECAPXIndicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_1ST_EVENT_ECAPXIndicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_INTERRUPTIndicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_ECAP3_ECCLR" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_HRERRORWriting a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_CMPWriting a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTROVFWriting a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT4Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT3Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT2Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT1Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_INTWriting a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are.." "0,1" line.word 0x2 "CONTROLSS_ECAP3_ECFRC" bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTROVFWriting a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT4Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT3Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT2Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT1Sets the CEVT1 flag." "0,1" group.long 0x3C++0x7 line.long 0x0 "CONTROLSS_ECAP3_ECAPSYNCINSEL" hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determines the source of SYNCIN signal. 0x0 : Disabled using SOC tieoff. 0x7F : Refer to SOC spec for details." line.long 0x4 "CONTROLSS_ECAP3_HRCTL" bitfld.long 0x4 5. "CALIBCONT,Continuous mode Calibration Select Bit: 0 Continuous mode disabled. 1 Continuous mode enabled. Calibration automatically restarts at end of current calibration cycle." "0,1" newline rbitfld.long 0x4 4. "CALIBSTS,Calibration status Bit: 0 No active calibration cycle 1 Calibration cycle in progress" "0,1" newline bitfld.long 0x4 3. "CALIBSTART,Calibration start Bit: 0 No effect 1 Starts the calibration cycle" "0,1" newline bitfld.long 0x4 2. "PRDSEL,Calibration Period Match Select Bit: 0 Use SYSCLK Counter For Period Match (default at reset) 1 Reserved" "0,1" newline bitfld.long 0x4 1. "HRCLKE,High Resolution Clock Enable Bit: 0 High resolution clock disabled (default at reset) 1 High resolution clock enabled. The clock should be enabled before enabling the high res function via the HRE bit." "0,1" newline bitfld.long 0x4 0. "HRE,High Resolution Enable Bit: 0 High resolution mode disabled (default at reset) 1 High resolution mode enabled. Enabling this mode will connect the capture registers and edge event modes of the ECAP to be accessed by the High Res function. Note: The.." "0,1" group.long 0x48++0x3 line.long 0x0 "CONTROLSS_ECAP3_HRINTEN" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration Period Check status Interrupt Enable: 0 Disable Calibration Period Check interrupt status 1 Enable Calibration Period Check interrupt status" "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration done Interrupt Enable: 0 Disable Calibration done Interrupt 1 Enable Calibration done Interrupt" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CONTROLSS_ECAP3_HRFLG" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration period check status Flag Bit: 1 Indicates that calibration ended before PRDCHK due to overflow on one of the counters. 0 Indicates no event occurred. Note: This bit remains latched until cleared by the user using the HRCLR.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration Done Interrupt Flag Bit: 1 Indicates calibration cycle is completed 0 Indicates calibration cycle has not completed. Note: This bit remains latched until cleared by the user using the HRCLR [CALIBDONE] bit." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Global calibration Interrupt Status Flag: 1 Indicates that an interrupt was generated from CALIBDONE or CALPRDCHKSTS. 0 Indicates no interrupt generated." "0,1" group.long 0x50++0xB line.long 0x0 "CONTROLSS_ECAP3_HRCLR" bitfld.long 0x0 2. "CALPRDCHKSTS,Clear Calibration period check status Flag Bit: 1 Clears the CALPRDCHKSTS flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Clear Calibration Done Interrupt Flag Bit: 1 Clears the CALIBDONE interrupt flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Clear Global calibration Interrupt Flag 1 Clears the Global interrupt flag and enables further interrupts to be generated if any of the event flags are set. 0 No effect." "0,1" line.long 0x4 "CONTROLSS_ECAP3_HRFRC" bitfld.long 0x4 2. "CALPRDCHKSTS,Force CALPRDCHKSTS flag: 0 No effect 1 Sets the CALPRDCHKSTS flag." "0,1" newline bitfld.long 0x4 1. "CALIBDONE,Force CALIBDONE flag: 0 No effect 1 Sets the CALIBDONE flag." "0,1" line.long 0x8 "CONTROLSS_ECAP3_HRCALPRD" hexmask.long 0x8 0.--31. 1. "PRD,Register to program calibration period. The period value is matched against HRSYSCLKCTR. On a match an interrupt is generated and the counter registers values are captured." rgroup.long 0x5C++0xF line.long 0x0 "CONTROLSS_ECAP3_HRSYSCLKCTR" hexmask.long 0x0 0.--31. 1. "HRSYSCLKCTR,Current SYSCLK counter value" line.long 0x4 "CONTROLSS_ECAP3_HRSYSCLKCAP" hexmask.long 0x4 0.--31. 1. "HRSYSCLKCAP,HRSYSCLKCTR is captures into this register at end of calibration cycle." line.long 0x8 "CONTROLSS_ECAP3_HRCLKCTR" hexmask.long 0x8 0.--31. 1. "HRCLKCTR,Current HRCLK counter value Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" line.long 0xC "CONTROLSS_ECAP3_HRCLKCAP" hexmask.long 0xC 0.--31. 1. "HRCLKCAP,HRCLKCTR is captures into this register at end of calibration cycle. Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" group.long 0x74++0x3 line.long 0x0 "CONTROLSS_ECAP3_HRDEBUGCTL" hexmask.long.byte 0x0 8.--11. 1. "OBSERVE_SRC_SEL,Select bits for selecting source for OBSERVE1 and OBSERVE2 registers 1000 HROUTH and HROUTL will read HR1OUT 1001 HROUTH and HROUTL will read HR2OUT 1010 HROUTH and HROUTL will read Capture Delayline 1 OBS1 1011 HROUTH and HROUTL will.." newline bitfld.long 0x0 4.--5. "CALIB_INPUT_SEL,Select bit for calibration input can be used to get fault coverage using these inputs 00 CAPIN is one of 128 inputs selected by INPUTSEL 01 CAPIN is connected to CAPIN_MEMMAP_SOURCE 10 CAPIN is internally generated signal waveform with.." "0,1,2,3" newline bitfld.long 0x0 2. "CAPIN_MMAP_SOURCE,Memory mapped CAPIN source Note : select CALIN source first it may happen that you may see interrupt if MMAP source is different from current value of CAPIN. This is debug feature hence no additional HW is necessary to prevent this." "0,1" newline bitfld.long 0x0 1. "DELAYRESETDLINE,Controls the reset delayline timing 0 reset is forced on next falling edge of HRCLK (1/2 cycle after capture) 1 reset is applied a cycle later (1 1/2 cycles after capture)" "0,1" newline bitfld.long 0x0 0. "DISABLEINVSEL,Disable INVSEL Logic: 0 State machine controls inversion on input signal 1 CAPIN signal propagated into delay line without inversion this means only rising edges can be measured" "0,1" rgroup.long 0x78++0x7 line.long 0x0 "CONTROLSS_ECAP3_HRDEBUGOBSERVE1" hexmask.long 0x0 0.--31. 1. "HROUTH,Reads raw output of HROUT capture delay line 1" line.long 0x4 "CONTROLSS_ECAP3_HRDEBUGOBSERVE2" hexmask.long 0x4 0.--31. 1. "HROUTL,Reads raw output of HROUT capture delay line 2" group.long 0x80++0x3 line.long 0x0 "CONTROLSS_ECAP3_MUNIT_COMMON_CTL" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Disabled with SOC level tieoff. 0x1 to 0x7F : Global load strobe from SOC level including ETPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not affect signal monitoring achieved with SOC level tieoff. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and.." group.long 0xC0++0x7 line.long 0x0 "CONTROLSS_ECAP3_MUNIT_1_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "CONTROLSS_ECAP3_MUNIT_1_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "CONTROLSS_ECAP3_MUNIT_1_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP3_MUNIT_1_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP3_MUNIT_1_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP3_MUNIT_1_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "CONTROLSS_ECAP3_MUNIT_1_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP3_MUNIT_1_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "CONTROLSS_ECAP3_MUNIT_2_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "CONTROLSS_ECAP3_MUNIT_2_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "CONTROLSS_ECAP3_MUNIT_2_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP3_MUNIT_2_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP3_MUNIT_2_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP3_MUNIT_2_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "CONTROLSS_ECAP3_MUNIT_2_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP3_MUNIT_2_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP4" base ad:0x50244000 group.long 0x0++0x17 line.long 0x0 "CONTROLSS_ECAP4_TSCTR" hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1) This register reads HRCOUNTER value and is not writable 2) can be reset using CTRFILTRESET 3) Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "CONTROLSS_ECAP4_CTRPHS" hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "CONTROLSS_ECAP4_CAP1" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by: - Time-Stamp counter value (TSCTR) during a capture event - Software - may be useful for test purposes or initialization - ARPD shadow register (CAP3) when used in APWM mode" line.long 0xC "CONTROLSS_ECAP4_CAP2" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by: - Time-Stamp ( counter value) during a capture event - Software - may be useful for test purposes - ACMP shadow register (CAP4) when used in APWM mode" line.long 0x10 "CONTROLSS_ECAP4_CAP3" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register. In APWM mode this is the period shadow (APRD) register. You can update the PWM period value through this register. CAP3 (APRD) shadows CAP1 in this mode." line.long 0x14 "CONTROLSS_ECAP4_CAP4" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register. In APWM mode this is the compare shadow (ACMP) register. You can update the PWM compare value via this register. CAP4 (ACMP) shadows CAP2 in this mode." group.long 0x24++0x3 line.long 0x0 "CONTROLSS_ECAP4_ECCTL0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b (R/W) = SOC trigger source is CEVT1 01b (R/W) = SOC trigger source is CEVT2 10b (R/W) = SOC trigger source is CEVT3 11b (R/W) = SOC trigger source is CEVT4 APWM Mode: 00b (R/W) = SOC trigger interrupt.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "CONTROLSS_ECAP4_ECCTL1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0x0 | ECAP_STOP_EMUTSCTR counter stops immediately on emulation suspend 0x1 | ECAP_RUNS_UNTILTSCTR counter runs until = 0 0x2 | ECAP_UNAF_EMU_SUSTSCTR counter is unaffected by emulation suspend (Run.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0x00 | ECAP_DIV1Divide by 1 (i.e . no prescale by-pass the prescaler) 0x01 | ECAP_DIV2Divide by 2 0x02 | ECAP_DIV4Divide by 4 0x03 | ECAP_DIV6Divide by 6 0x04 |.." newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 | ECAP_DISABLEDisable CAP1-4 register loads at capture event time. 1 | ECAP_ENABLEEnable CAP1-4.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 | ECAP_DO_NOT_RESET_EVENT4Do not reset counter on Capture Event 4 (absolute time stamp operation) 1 | ECAP_RESET_EVENT4Reset counter after Capture Event 4 time-stamp has been captured (used in.." "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 | ECAP_CAP_EVENT4_RISECapture Event 4 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT4_FALLCapture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 | ECAP_DO_NOT_RESET_EVENT3Do not reset counter on Capture Event 3 (absolute time stamp) 1 | ECAP_RESET_EVENT3Reset counter after Event 3 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 | ECAP_CAP_EVENT3_RISECapture Event 3 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT3_FALLCapture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 | ECAP_DO_NOT_RESET_EVENT2Do not reset counter on Capture Event 2 (absolute time stamp) 1 | ECAP_RESET_EVENT2Reset counter after Event 2 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 | ECAP_CAP_EVENT2_RISECapture Event 2 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT2_FALLCapture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 | ECAP_DO_NOT_RESET_EVENT1Do not reset counter on Capture Event 1 (absolute time stamp) 1 | ECAP_RESET_EVENT1Reset counter after Event 1 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 | ECAP_CAP_EVENT1_RISECapture Event 1 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT1_FALLCapture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "CONTROLSS_ECAP4_ECCTL2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b (R) = CAP1 register gets loaded on next capture event. 01b (R) = CAP2 register gets loaded on next capture event. 10b (R) = CAP3 register gets loaded on next capture event. 11b (R) =.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b (R/W) = DMA interrupt source is CEVT1 01b (R/W) = DMA interrupt source is CEVT2 10b (R/W) = DMA interrupt source is CEVT3 11b (R/W) = DMA interrupt source is CEVT4 APWM Mode: 00b (R/W) = DMA interrupt source.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h (R) = No effect 1h (W) = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 | ECAP_OUTPUT_ACTIVE_HIGHOutput is active high (Compare value defines high time) 1 | ECAP_OUTPUT_ACTIVE_LOWOutput is active low (Compare value defines.." "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 | ECAP_MODULEECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers - Permits user.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter (TSCTR) Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 |.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0x0 | SWSYNCsync out signal is SWSYNC 0x1 | ECAP_CTR_PRD_TO_SYNCOUTSelect CTR = PRD event to be the sync-out signal 0x2 | ECAP_DISABLE_SYNC_OUTDisable sync out signal 0x3 |.." "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter (TSCTR) Sync-In select mode 0 | ECAP_DISABLE_SYNC_INDisable sync-in option 1 | ECAP_ENABLE_COUNTER_REGISTEREnable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp (TSCTR) Counter Stop (freeze) Control 0 | ECAP_TSCTR_STOPPEDTSCTR stopped 1 | ECAP_TSCTR_FREE_RUNNINGTSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 | ECAP_NO_EFFECT_RETURNS_0Has no effect (reading always returns a 0) 1 | ECAP_ARMS_ONESHOTArms the one-shot sequence as follows: 1) Resets the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur before the CAP(1-4) registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1-4) of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control (applicable only in capture mode) 0 | ECAP_OPP_CONTOperate in continuous mode 1 | ECAP_OPP_ONEOperate in one-Shot mode" "0,1" line.word 0x4 "CONTROLSS_ECAP4_ECEINT" bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 | ECAP_DISAB_HRERROR_INTERRUPTDisable High Resolution Error as an Interrupt source 1 | ECAP_ENAB_HRERROR_INTERRUPTEnable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 | ECAP_DISAB_CE_INTERRUPTDisable Compare Equal as an Interrupt source 1 | ECAP_ENAB_CE_INTERRUPTEnable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 | ECAP_DISAB_PE_INTERRUPTDisable Period Equal as an Interrupt source 1 | ECAP_ENAB_PE_INTERRUPTEnable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 | ECAP_DISAB_CO_INTERRUPTDisabled counter Overflow as an Interrupt source 1 | ECAP_ENAB_CO_INTERRUPTEnable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 | ECAP_DISAB_CAP4_INTERRUPTDisable Capture Event 4 as an Interrupt source 1 | ECAP_ENAB_CAP4_INTERRUPTCapture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 | ECAP_DISAB_CAP3_INTERRUPTDisable Capture Event 3 as an Interrupt source 1 | ECAP_ENAB_CAP3_INTERRUPTEnable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 | ECAP_DISAB_CAP2_INTERRUPTDisable Capture Event 2 as an Interrupt source 1 | ECAP_ENAB_CAP2_INTERRUPTEnable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 | ECAP_DISAB_CAP1_INTERRUPTDisable Capture Event 1 as an Interrupt source 1 | ECAP_ENAB_CAP1_INTERRUPTEnable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "CONTROLSS_ECAP4_ECFLG" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_HIGH_RESOLUTION_ERRORIndicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_COMPARE_REGIndicates the counter (TSCTR) reached the compare.." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_PERIOD_VALUE_RESETIndicates the counter (TSCTR) reached the period register.." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_TRANSIndicates the counter (TSCTR) has made the transition from.." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_4TH_EVENT_ECAPXIndicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_3RD_EVENT_ECAPXIndicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_2ND_EVENT_ECAPXIndicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_1ST_EVENT_ECAPXIndicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_INTERRUPTIndicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_ECAP4_ECCLR" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_HRERRORWriting a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_CMPWriting a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTROVFWriting a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT4Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT3Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT2Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT1Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_INTWriting a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are.." "0,1" line.word 0x2 "CONTROLSS_ECAP4_ECFRC" bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTROVFWriting a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT4Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT3Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT2Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT1Sets the CEVT1 flag." "0,1" group.long 0x3C++0x7 line.long 0x0 "CONTROLSS_ECAP4_ECAPSYNCINSEL" hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determines the source of SYNCIN signal. 0x0 : Disabled using SOC tieoff. 0x7F : Refer to SOC spec for details." line.long 0x4 "CONTROLSS_ECAP4_HRCTL" bitfld.long 0x4 5. "CALIBCONT,Continuous mode Calibration Select Bit: 0 Continuous mode disabled. 1 Continuous mode enabled. Calibration automatically restarts at end of current calibration cycle." "0,1" newline rbitfld.long 0x4 4. "CALIBSTS,Calibration status Bit: 0 No active calibration cycle 1 Calibration cycle in progress" "0,1" newline bitfld.long 0x4 3. "CALIBSTART,Calibration start Bit: 0 No effect 1 Starts the calibration cycle" "0,1" newline bitfld.long 0x4 2. "PRDSEL,Calibration Period Match Select Bit: 0 Use SYSCLK Counter For Period Match (default at reset) 1 Reserved" "0,1" newline bitfld.long 0x4 1. "HRCLKE,High Resolution Clock Enable Bit: 0 High resolution clock disabled (default at reset) 1 High resolution clock enabled. The clock should be enabled before enabling the high res function via the HRE bit." "0,1" newline bitfld.long 0x4 0. "HRE,High Resolution Enable Bit: 0 High resolution mode disabled (default at reset) 1 High resolution mode enabled. Enabling this mode will connect the capture registers and edge event modes of the ECAP to be accessed by the High Res function. Note: The.." "0,1" group.long 0x48++0x3 line.long 0x0 "CONTROLSS_ECAP4_HRINTEN" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration Period Check status Interrupt Enable: 0 Disable Calibration Period Check interrupt status 1 Enable Calibration Period Check interrupt status" "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration done Interrupt Enable: 0 Disable Calibration done Interrupt 1 Enable Calibration done Interrupt" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CONTROLSS_ECAP4_HRFLG" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration period check status Flag Bit: 1 Indicates that calibration ended before PRDCHK due to overflow on one of the counters. 0 Indicates no event occurred. Note: This bit remains latched until cleared by the user using the HRCLR.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration Done Interrupt Flag Bit: 1 Indicates calibration cycle is completed 0 Indicates calibration cycle has not completed. Note: This bit remains latched until cleared by the user using the HRCLR [CALIBDONE] bit." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Global calibration Interrupt Status Flag: 1 Indicates that an interrupt was generated from CALIBDONE or CALPRDCHKSTS. 0 Indicates no interrupt generated." "0,1" group.long 0x50++0xB line.long 0x0 "CONTROLSS_ECAP4_HRCLR" bitfld.long 0x0 2. "CALPRDCHKSTS,Clear Calibration period check status Flag Bit: 1 Clears the CALPRDCHKSTS flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Clear Calibration Done Interrupt Flag Bit: 1 Clears the CALIBDONE interrupt flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Clear Global calibration Interrupt Flag 1 Clears the Global interrupt flag and enables further interrupts to be generated if any of the event flags are set. 0 No effect." "0,1" line.long 0x4 "CONTROLSS_ECAP4_HRFRC" bitfld.long 0x4 2. "CALPRDCHKSTS,Force CALPRDCHKSTS flag: 0 No effect 1 Sets the CALPRDCHKSTS flag." "0,1" newline bitfld.long 0x4 1. "CALIBDONE,Force CALIBDONE flag: 0 No effect 1 Sets the CALIBDONE flag." "0,1" line.long 0x8 "CONTROLSS_ECAP4_HRCALPRD" hexmask.long 0x8 0.--31. 1. "PRD,Register to program calibration period. The period value is matched against HRSYSCLKCTR. On a match an interrupt is generated and the counter registers values are captured." rgroup.long 0x5C++0xF line.long 0x0 "CONTROLSS_ECAP4_HRSYSCLKCTR" hexmask.long 0x0 0.--31. 1. "HRSYSCLKCTR,Current SYSCLK counter value" line.long 0x4 "CONTROLSS_ECAP4_HRSYSCLKCAP" hexmask.long 0x4 0.--31. 1. "HRSYSCLKCAP,HRSYSCLKCTR is captures into this register at end of calibration cycle." line.long 0x8 "CONTROLSS_ECAP4_HRCLKCTR" hexmask.long 0x8 0.--31. 1. "HRCLKCTR,Current HRCLK counter value Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" line.long 0xC "CONTROLSS_ECAP4_HRCLKCAP" hexmask.long 0xC 0.--31. 1. "HRCLKCAP,HRCLKCTR is captures into this register at end of calibration cycle. Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" group.long 0x74++0x3 line.long 0x0 "CONTROLSS_ECAP4_HRDEBUGCTL" hexmask.long.byte 0x0 8.--11. 1. "OBSERVE_SRC_SEL,Select bits for selecting source for OBSERVE1 and OBSERVE2 registers 1000 HROUTH and HROUTL will read HR1OUT 1001 HROUTH and HROUTL will read HR2OUT 1010 HROUTH and HROUTL will read Capture Delayline 1 OBS1 1011 HROUTH and HROUTL will.." newline bitfld.long 0x0 4.--5. "CALIB_INPUT_SEL,Select bit for calibration input can be used to get fault coverage using these inputs 00 CAPIN is one of 128 inputs selected by INPUTSEL 01 CAPIN is connected to CAPIN_MEMMAP_SOURCE 10 CAPIN is internally generated signal waveform with.." "0,1,2,3" newline bitfld.long 0x0 2. "CAPIN_MMAP_SOURCE,Memory mapped CAPIN source Note : select CALIN source first it may happen that you may see interrupt if MMAP source is different from current value of CAPIN. This is debug feature hence no additional HW is necessary to prevent this." "0,1" newline bitfld.long 0x0 1. "DELAYRESETDLINE,Controls the reset delayline timing 0 reset is forced on next falling edge of HRCLK (1/2 cycle after capture) 1 reset is applied a cycle later (1 1/2 cycles after capture)" "0,1" newline bitfld.long 0x0 0. "DISABLEINVSEL,Disable INVSEL Logic: 0 State machine controls inversion on input signal 1 CAPIN signal propagated into delay line without inversion this means only rising edges can be measured" "0,1" rgroup.long 0x78++0x7 line.long 0x0 "CONTROLSS_ECAP4_HRDEBUGOBSERVE1" hexmask.long 0x0 0.--31. 1. "HROUTH,Reads raw output of HROUT capture delay line 1" line.long 0x4 "CONTROLSS_ECAP4_HRDEBUGOBSERVE2" hexmask.long 0x4 0.--31. 1. "HROUTL,Reads raw output of HROUT capture delay line 2" group.long 0x80++0x3 line.long 0x0 "CONTROLSS_ECAP4_MUNIT_COMMON_CTL" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Disabled with SOC level tieoff. 0x1 to 0x7F : Global load strobe from SOC level including ETPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not affect signal monitoring achieved with SOC level tieoff. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and.." group.long 0xC0++0x7 line.long 0x0 "CONTROLSS_ECAP4_MUNIT_1_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "CONTROLSS_ECAP4_MUNIT_1_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "CONTROLSS_ECAP4_MUNIT_1_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP4_MUNIT_1_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP4_MUNIT_1_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP4_MUNIT_1_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "CONTROLSS_ECAP4_MUNIT_1_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP4_MUNIT_1_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "CONTROLSS_ECAP4_MUNIT_2_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "CONTROLSS_ECAP4_MUNIT_2_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "CONTROLSS_ECAP4_MUNIT_2_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP4_MUNIT_2_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP4_MUNIT_2_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP4_MUNIT_2_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "CONTROLSS_ECAP4_MUNIT_2_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP4_MUNIT_2_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP5" base ad:0x50245000 group.long 0x0++0x17 line.long 0x0 "CONTROLSS_ECAP5_TSCTR" hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1) This register reads HRCOUNTER value and is not writable 2) can be reset using CTRFILTRESET 3) Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "CONTROLSS_ECAP5_CTRPHS" hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "CONTROLSS_ECAP5_CAP1" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by: - Time-Stamp counter value (TSCTR) during a capture event - Software - may be useful for test purposes or initialization - ARPD shadow register (CAP3) when used in APWM mode" line.long 0xC "CONTROLSS_ECAP5_CAP2" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by: - Time-Stamp ( counter value) during a capture event - Software - may be useful for test purposes - ACMP shadow register (CAP4) when used in APWM mode" line.long 0x10 "CONTROLSS_ECAP5_CAP3" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register. In APWM mode this is the period shadow (APRD) register. You can update the PWM period value through this register. CAP3 (APRD) shadows CAP1 in this mode." line.long 0x14 "CONTROLSS_ECAP5_CAP4" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register. In APWM mode this is the compare shadow (ACMP) register. You can update the PWM compare value via this register. CAP4 (ACMP) shadows CAP2 in this mode." group.long 0x24++0x3 line.long 0x0 "CONTROLSS_ECAP5_ECCTL0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b (R/W) = SOC trigger source is CEVT1 01b (R/W) = SOC trigger source is CEVT2 10b (R/W) = SOC trigger source is CEVT3 11b (R/W) = SOC trigger source is CEVT4 APWM Mode: 00b (R/W) = SOC trigger interrupt.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "CONTROLSS_ECAP5_ECCTL1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0x0 | ECAP_STOP_EMUTSCTR counter stops immediately on emulation suspend 0x1 | ECAP_RUNS_UNTILTSCTR counter runs until = 0 0x2 | ECAP_UNAF_EMU_SUSTSCTR counter is unaffected by emulation suspend (Run.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0x00 | ECAP_DIV1Divide by 1 (i.e . no prescale by-pass the prescaler) 0x01 | ECAP_DIV2Divide by 2 0x02 | ECAP_DIV4Divide by 4 0x03 | ECAP_DIV6Divide by 6 0x04 |.." newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 | ECAP_DISABLEDisable CAP1-4 register loads at capture event time. 1 | ECAP_ENABLEEnable CAP1-4.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 | ECAP_DO_NOT_RESET_EVENT4Do not reset counter on Capture Event 4 (absolute time stamp operation) 1 | ECAP_RESET_EVENT4Reset counter after Capture Event 4 time-stamp has been captured (used in.." "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 | ECAP_CAP_EVENT4_RISECapture Event 4 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT4_FALLCapture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 | ECAP_DO_NOT_RESET_EVENT3Do not reset counter on Capture Event 3 (absolute time stamp) 1 | ECAP_RESET_EVENT3Reset counter after Event 3 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 | ECAP_CAP_EVENT3_RISECapture Event 3 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT3_FALLCapture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 | ECAP_DO_NOT_RESET_EVENT2Do not reset counter on Capture Event 2 (absolute time stamp) 1 | ECAP_RESET_EVENT2Reset counter after Event 2 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 | ECAP_CAP_EVENT2_RISECapture Event 2 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT2_FALLCapture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 | ECAP_DO_NOT_RESET_EVENT1Do not reset counter on Capture Event 1 (absolute time stamp) 1 | ECAP_RESET_EVENT1Reset counter after Event 1 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 | ECAP_CAP_EVENT1_RISECapture Event 1 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT1_FALLCapture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "CONTROLSS_ECAP5_ECCTL2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b (R) = CAP1 register gets loaded on next capture event. 01b (R) = CAP2 register gets loaded on next capture event. 10b (R) = CAP3 register gets loaded on next capture event. 11b (R) =.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b (R/W) = DMA interrupt source is CEVT1 01b (R/W) = DMA interrupt source is CEVT2 10b (R/W) = DMA interrupt source is CEVT3 11b (R/W) = DMA interrupt source is CEVT4 APWM Mode: 00b (R/W) = DMA interrupt source.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h (R) = No effect 1h (W) = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 | ECAP_OUTPUT_ACTIVE_HIGHOutput is active high (Compare value defines high time) 1 | ECAP_OUTPUT_ACTIVE_LOWOutput is active low (Compare value defines.." "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 | ECAP_MODULEECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers - Permits user.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter (TSCTR) Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 |.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0x0 | SWSYNCsync out signal is SWSYNC 0x1 | ECAP_CTR_PRD_TO_SYNCOUTSelect CTR = PRD event to be the sync-out signal 0x2 | ECAP_DISABLE_SYNC_OUTDisable sync out signal 0x3 |.." "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter (TSCTR) Sync-In select mode 0 | ECAP_DISABLE_SYNC_INDisable sync-in option 1 | ECAP_ENABLE_COUNTER_REGISTEREnable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp (TSCTR) Counter Stop (freeze) Control 0 | ECAP_TSCTR_STOPPEDTSCTR stopped 1 | ECAP_TSCTR_FREE_RUNNINGTSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 | ECAP_NO_EFFECT_RETURNS_0Has no effect (reading always returns a 0) 1 | ECAP_ARMS_ONESHOTArms the one-shot sequence as follows: 1) Resets the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur before the CAP(1-4) registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1-4) of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control (applicable only in capture mode) 0 | ECAP_OPP_CONTOperate in continuous mode 1 | ECAP_OPP_ONEOperate in one-Shot mode" "0,1" line.word 0x4 "CONTROLSS_ECAP5_ECEINT" bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 | ECAP_DISAB_HRERROR_INTERRUPTDisable High Resolution Error as an Interrupt source 1 | ECAP_ENAB_HRERROR_INTERRUPTEnable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 | ECAP_DISAB_CE_INTERRUPTDisable Compare Equal as an Interrupt source 1 | ECAP_ENAB_CE_INTERRUPTEnable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 | ECAP_DISAB_PE_INTERRUPTDisable Period Equal as an Interrupt source 1 | ECAP_ENAB_PE_INTERRUPTEnable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 | ECAP_DISAB_CO_INTERRUPTDisabled counter Overflow as an Interrupt source 1 | ECAP_ENAB_CO_INTERRUPTEnable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 | ECAP_DISAB_CAP4_INTERRUPTDisable Capture Event 4 as an Interrupt source 1 | ECAP_ENAB_CAP4_INTERRUPTCapture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 | ECAP_DISAB_CAP3_INTERRUPTDisable Capture Event 3 as an Interrupt source 1 | ECAP_ENAB_CAP3_INTERRUPTEnable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 | ECAP_DISAB_CAP2_INTERRUPTDisable Capture Event 2 as an Interrupt source 1 | ECAP_ENAB_CAP2_INTERRUPTEnable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 | ECAP_DISAB_CAP1_INTERRUPTDisable Capture Event 1 as an Interrupt source 1 | ECAP_ENAB_CAP1_INTERRUPTEnable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "CONTROLSS_ECAP5_ECFLG" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_HIGH_RESOLUTION_ERRORIndicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_COMPARE_REGIndicates the counter (TSCTR) reached the compare.." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_PERIOD_VALUE_RESETIndicates the counter (TSCTR) reached the period register.." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_TRANSIndicates the counter (TSCTR) has made the transition from.." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_4TH_EVENT_ECAPXIndicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_3RD_EVENT_ECAPXIndicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_2ND_EVENT_ECAPXIndicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_1ST_EVENT_ECAPXIndicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_INTERRUPTIndicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_ECAP5_ECCLR" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_HRERRORWriting a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_CMPWriting a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTROVFWriting a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT4Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT3Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT2Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT1Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_INTWriting a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are.." "0,1" line.word 0x2 "CONTROLSS_ECAP5_ECFRC" bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTROVFWriting a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT4Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT3Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT2Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT1Sets the CEVT1 flag." "0,1" group.long 0x3C++0x7 line.long 0x0 "CONTROLSS_ECAP5_ECAPSYNCINSEL" hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determines the source of SYNCIN signal. 0x0 : Disabled using SOC tieoff. 0x7F : Refer to SOC spec for details." line.long 0x4 "CONTROLSS_ECAP5_HRCTL" bitfld.long 0x4 5. "CALIBCONT,Continuous mode Calibration Select Bit: 0 Continuous mode disabled. 1 Continuous mode enabled. Calibration automatically restarts at end of current calibration cycle." "0,1" newline rbitfld.long 0x4 4. "CALIBSTS,Calibration status Bit: 0 No active calibration cycle 1 Calibration cycle in progress" "0,1" newline bitfld.long 0x4 3. "CALIBSTART,Calibration start Bit: 0 No effect 1 Starts the calibration cycle" "0,1" newline bitfld.long 0x4 2. "PRDSEL,Calibration Period Match Select Bit: 0 Use SYSCLK Counter For Period Match (default at reset) 1 Reserved" "0,1" newline bitfld.long 0x4 1. "HRCLKE,High Resolution Clock Enable Bit: 0 High resolution clock disabled (default at reset) 1 High resolution clock enabled. The clock should be enabled before enabling the high res function via the HRE bit." "0,1" newline bitfld.long 0x4 0. "HRE,High Resolution Enable Bit: 0 High resolution mode disabled (default at reset) 1 High resolution mode enabled. Enabling this mode will connect the capture registers and edge event modes of the ECAP to be accessed by the High Res function. Note: The.." "0,1" group.long 0x48++0x3 line.long 0x0 "CONTROLSS_ECAP5_HRINTEN" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration Period Check status Interrupt Enable: 0 Disable Calibration Period Check interrupt status 1 Enable Calibration Period Check interrupt status" "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration done Interrupt Enable: 0 Disable Calibration done Interrupt 1 Enable Calibration done Interrupt" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CONTROLSS_ECAP5_HRFLG" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration period check status Flag Bit: 1 Indicates that calibration ended before PRDCHK due to overflow on one of the counters. 0 Indicates no event occurred. Note: This bit remains latched until cleared by the user using the HRCLR.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration Done Interrupt Flag Bit: 1 Indicates calibration cycle is completed 0 Indicates calibration cycle has not completed. Note: This bit remains latched until cleared by the user using the HRCLR [CALIBDONE] bit." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Global calibration Interrupt Status Flag: 1 Indicates that an interrupt was generated from CALIBDONE or CALPRDCHKSTS. 0 Indicates no interrupt generated." "0,1" group.long 0x50++0xB line.long 0x0 "CONTROLSS_ECAP5_HRCLR" bitfld.long 0x0 2. "CALPRDCHKSTS,Clear Calibration period check status Flag Bit: 1 Clears the CALPRDCHKSTS flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Clear Calibration Done Interrupt Flag Bit: 1 Clears the CALIBDONE interrupt flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Clear Global calibration Interrupt Flag 1 Clears the Global interrupt flag and enables further interrupts to be generated if any of the event flags are set. 0 No effect." "0,1" line.long 0x4 "CONTROLSS_ECAP5_HRFRC" bitfld.long 0x4 2. "CALPRDCHKSTS,Force CALPRDCHKSTS flag: 0 No effect 1 Sets the CALPRDCHKSTS flag." "0,1" newline bitfld.long 0x4 1. "CALIBDONE,Force CALIBDONE flag: 0 No effect 1 Sets the CALIBDONE flag." "0,1" line.long 0x8 "CONTROLSS_ECAP5_HRCALPRD" hexmask.long 0x8 0.--31. 1. "PRD,Register to program calibration period. The period value is matched against HRSYSCLKCTR. On a match an interrupt is generated and the counter registers values are captured." rgroup.long 0x5C++0xF line.long 0x0 "CONTROLSS_ECAP5_HRSYSCLKCTR" hexmask.long 0x0 0.--31. 1. "HRSYSCLKCTR,Current SYSCLK counter value" line.long 0x4 "CONTROLSS_ECAP5_HRSYSCLKCAP" hexmask.long 0x4 0.--31. 1. "HRSYSCLKCAP,HRSYSCLKCTR is captures into this register at end of calibration cycle." line.long 0x8 "CONTROLSS_ECAP5_HRCLKCTR" hexmask.long 0x8 0.--31. 1. "HRCLKCTR,Current HRCLK counter value Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" line.long 0xC "CONTROLSS_ECAP5_HRCLKCAP" hexmask.long 0xC 0.--31. 1. "HRCLKCAP,HRCLKCTR is captures into this register at end of calibration cycle. Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" group.long 0x74++0x3 line.long 0x0 "CONTROLSS_ECAP5_HRDEBUGCTL" hexmask.long.byte 0x0 8.--11. 1. "OBSERVE_SRC_SEL,Select bits for selecting source for OBSERVE1 and OBSERVE2 registers 1000 HROUTH and HROUTL will read HR1OUT 1001 HROUTH and HROUTL will read HR2OUT 1010 HROUTH and HROUTL will read Capture Delayline 1 OBS1 1011 HROUTH and HROUTL will.." newline bitfld.long 0x0 4.--5. "CALIB_INPUT_SEL,Select bit for calibration input can be used to get fault coverage using these inputs 00 CAPIN is one of 128 inputs selected by INPUTSEL 01 CAPIN is connected to CAPIN_MEMMAP_SOURCE 10 CAPIN is internally generated signal waveform with.." "0,1,2,3" newline bitfld.long 0x0 2. "CAPIN_MMAP_SOURCE,Memory mapped CAPIN source Note : select CALIN source first it may happen that you may see interrupt if MMAP source is different from current value of CAPIN. This is debug feature hence no additional HW is necessary to prevent this." "0,1" newline bitfld.long 0x0 1. "DELAYRESETDLINE,Controls the reset delayline timing 0 reset is forced on next falling edge of HRCLK (1/2 cycle after capture) 1 reset is applied a cycle later (1 1/2 cycles after capture)" "0,1" newline bitfld.long 0x0 0. "DISABLEINVSEL,Disable INVSEL Logic: 0 State machine controls inversion on input signal 1 CAPIN signal propagated into delay line without inversion this means only rising edges can be measured" "0,1" rgroup.long 0x78++0x7 line.long 0x0 "CONTROLSS_ECAP5_HRDEBUGOBSERVE1" hexmask.long 0x0 0.--31. 1. "HROUTH,Reads raw output of HROUT capture delay line 1" line.long 0x4 "CONTROLSS_ECAP5_HRDEBUGOBSERVE2" hexmask.long 0x4 0.--31. 1. "HROUTL,Reads raw output of HROUT capture delay line 2" group.long 0x80++0x3 line.long 0x0 "CONTROLSS_ECAP5_MUNIT_COMMON_CTL" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Disabled with SOC level tieoff. 0x1 to 0x7F : Global load strobe from SOC level including ETPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not affect signal monitoring achieved with SOC level tieoff. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and.." group.long 0xC0++0x7 line.long 0x0 "CONTROLSS_ECAP5_MUNIT_1_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "CONTROLSS_ECAP5_MUNIT_1_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "CONTROLSS_ECAP5_MUNIT_1_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP5_MUNIT_1_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP5_MUNIT_1_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP5_MUNIT_1_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "CONTROLSS_ECAP5_MUNIT_1_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP5_MUNIT_1_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "CONTROLSS_ECAP5_MUNIT_2_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "CONTROLSS_ECAP5_MUNIT_2_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "CONTROLSS_ECAP5_MUNIT_2_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP5_MUNIT_2_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP5_MUNIT_2_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP5_MUNIT_2_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "CONTROLSS_ECAP5_MUNIT_2_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP5_MUNIT_2_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP6" base ad:0x50246000 group.long 0x0++0x17 line.long 0x0 "CONTROLSS_ECAP6_TSCTR" hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1) This register reads HRCOUNTER value and is not writable 2) can be reset using CTRFILTRESET 3) Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "CONTROLSS_ECAP6_CTRPHS" hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "CONTROLSS_ECAP6_CAP1" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by: - Time-Stamp counter value (TSCTR) during a capture event - Software - may be useful for test purposes or initialization - ARPD shadow register (CAP3) when used in APWM mode" line.long 0xC "CONTROLSS_ECAP6_CAP2" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by: - Time-Stamp ( counter value) during a capture event - Software - may be useful for test purposes - ACMP shadow register (CAP4) when used in APWM mode" line.long 0x10 "CONTROLSS_ECAP6_CAP3" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register. In APWM mode this is the period shadow (APRD) register. You can update the PWM period value through this register. CAP3 (APRD) shadows CAP1 in this mode." line.long 0x14 "CONTROLSS_ECAP6_CAP4" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register. In APWM mode this is the compare shadow (ACMP) register. You can update the PWM compare value via this register. CAP4 (ACMP) shadows CAP2 in this mode." group.long 0x24++0x3 line.long 0x0 "CONTROLSS_ECAP6_ECCTL0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b (R/W) = SOC trigger source is CEVT1 01b (R/W) = SOC trigger source is CEVT2 10b (R/W) = SOC trigger source is CEVT3 11b (R/W) = SOC trigger source is CEVT4 APWM Mode: 00b (R/W) = SOC trigger interrupt.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "CONTROLSS_ECAP6_ECCTL1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0x0 | ECAP_STOP_EMUTSCTR counter stops immediately on emulation suspend 0x1 | ECAP_RUNS_UNTILTSCTR counter runs until = 0 0x2 | ECAP_UNAF_EMU_SUSTSCTR counter is unaffected by emulation suspend (Run.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0x00 | ECAP_DIV1Divide by 1 (i.e . no prescale by-pass the prescaler) 0x01 | ECAP_DIV2Divide by 2 0x02 | ECAP_DIV4Divide by 4 0x03 | ECAP_DIV6Divide by 6 0x04 |.." newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 | ECAP_DISABLEDisable CAP1-4 register loads at capture event time. 1 | ECAP_ENABLEEnable CAP1-4.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 | ECAP_DO_NOT_RESET_EVENT4Do not reset counter on Capture Event 4 (absolute time stamp operation) 1 | ECAP_RESET_EVENT4Reset counter after Capture Event 4 time-stamp has been captured (used in.." "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 | ECAP_CAP_EVENT4_RISECapture Event 4 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT4_FALLCapture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 | ECAP_DO_NOT_RESET_EVENT3Do not reset counter on Capture Event 3 (absolute time stamp) 1 | ECAP_RESET_EVENT3Reset counter after Event 3 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 | ECAP_CAP_EVENT3_RISECapture Event 3 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT3_FALLCapture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 | ECAP_DO_NOT_RESET_EVENT2Do not reset counter on Capture Event 2 (absolute time stamp) 1 | ECAP_RESET_EVENT2Reset counter after Event 2 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 | ECAP_CAP_EVENT2_RISECapture Event 2 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT2_FALLCapture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 | ECAP_DO_NOT_RESET_EVENT1Do not reset counter on Capture Event 1 (absolute time stamp) 1 | ECAP_RESET_EVENT1Reset counter after Event 1 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 | ECAP_CAP_EVENT1_RISECapture Event 1 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT1_FALLCapture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "CONTROLSS_ECAP6_ECCTL2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b (R) = CAP1 register gets loaded on next capture event. 01b (R) = CAP2 register gets loaded on next capture event. 10b (R) = CAP3 register gets loaded on next capture event. 11b (R) =.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b (R/W) = DMA interrupt source is CEVT1 01b (R/W) = DMA interrupt source is CEVT2 10b (R/W) = DMA interrupt source is CEVT3 11b (R/W) = DMA interrupt source is CEVT4 APWM Mode: 00b (R/W) = DMA interrupt source.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h (R) = No effect 1h (W) = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 | ECAP_OUTPUT_ACTIVE_HIGHOutput is active high (Compare value defines high time) 1 | ECAP_OUTPUT_ACTIVE_LOWOutput is active low (Compare value defines.." "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 | ECAP_MODULEECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers - Permits user.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter (TSCTR) Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 |.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0x0 | SWSYNCsync out signal is SWSYNC 0x1 | ECAP_CTR_PRD_TO_SYNCOUTSelect CTR = PRD event to be the sync-out signal 0x2 | ECAP_DISABLE_SYNC_OUTDisable sync out signal 0x3 |.." "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter (TSCTR) Sync-In select mode 0 | ECAP_DISABLE_SYNC_INDisable sync-in option 1 | ECAP_ENABLE_COUNTER_REGISTEREnable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp (TSCTR) Counter Stop (freeze) Control 0 | ECAP_TSCTR_STOPPEDTSCTR stopped 1 | ECAP_TSCTR_FREE_RUNNINGTSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 | ECAP_NO_EFFECT_RETURNS_0Has no effect (reading always returns a 0) 1 | ECAP_ARMS_ONESHOTArms the one-shot sequence as follows: 1) Resets the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur before the CAP(1-4) registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1-4) of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control (applicable only in capture mode) 0 | ECAP_OPP_CONTOperate in continuous mode 1 | ECAP_OPP_ONEOperate in one-Shot mode" "0,1" line.word 0x4 "CONTROLSS_ECAP6_ECEINT" bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 | ECAP_DISAB_HRERROR_INTERRUPTDisable High Resolution Error as an Interrupt source 1 | ECAP_ENAB_HRERROR_INTERRUPTEnable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 | ECAP_DISAB_CE_INTERRUPTDisable Compare Equal as an Interrupt source 1 | ECAP_ENAB_CE_INTERRUPTEnable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 | ECAP_DISAB_PE_INTERRUPTDisable Period Equal as an Interrupt source 1 | ECAP_ENAB_PE_INTERRUPTEnable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 | ECAP_DISAB_CO_INTERRUPTDisabled counter Overflow as an Interrupt source 1 | ECAP_ENAB_CO_INTERRUPTEnable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 | ECAP_DISAB_CAP4_INTERRUPTDisable Capture Event 4 as an Interrupt source 1 | ECAP_ENAB_CAP4_INTERRUPTCapture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 | ECAP_DISAB_CAP3_INTERRUPTDisable Capture Event 3 as an Interrupt source 1 | ECAP_ENAB_CAP3_INTERRUPTEnable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 | ECAP_DISAB_CAP2_INTERRUPTDisable Capture Event 2 as an Interrupt source 1 | ECAP_ENAB_CAP2_INTERRUPTEnable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 | ECAP_DISAB_CAP1_INTERRUPTDisable Capture Event 1 as an Interrupt source 1 | ECAP_ENAB_CAP1_INTERRUPTEnable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "CONTROLSS_ECAP6_ECFLG" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_HIGH_RESOLUTION_ERRORIndicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_COMPARE_REGIndicates the counter (TSCTR) reached the compare.." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_PERIOD_VALUE_RESETIndicates the counter (TSCTR) reached the period register.." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_TRANSIndicates the counter (TSCTR) has made the transition from.." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_4TH_EVENT_ECAPXIndicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_3RD_EVENT_ECAPXIndicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_2ND_EVENT_ECAPXIndicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_1ST_EVENT_ECAPXIndicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_INTERRUPTIndicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_ECAP6_ECCLR" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_HRERRORWriting a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_CMPWriting a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTROVFWriting a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT4Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT3Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT2Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT1Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_INTWriting a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are.." "0,1" line.word 0x2 "CONTROLSS_ECAP6_ECFRC" bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTROVFWriting a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT4Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT3Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT2Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT1Sets the CEVT1 flag." "0,1" group.long 0x3C++0x7 line.long 0x0 "CONTROLSS_ECAP6_ECAPSYNCINSEL" hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determines the source of SYNCIN signal. 0x0 : Disabled using SOC tieoff. 0x7F : Refer to SOC spec for details." line.long 0x4 "CONTROLSS_ECAP6_HRCTL" bitfld.long 0x4 5. "CALIBCONT,Continuous mode Calibration Select Bit: 0 Continuous mode disabled. 1 Continuous mode enabled. Calibration automatically restarts at end of current calibration cycle." "0,1" newline rbitfld.long 0x4 4. "CALIBSTS,Calibration status Bit: 0 No active calibration cycle 1 Calibration cycle in progress" "0,1" newline bitfld.long 0x4 3. "CALIBSTART,Calibration start Bit: 0 No effect 1 Starts the calibration cycle" "0,1" newline bitfld.long 0x4 2. "PRDSEL,Calibration Period Match Select Bit: 0 Use SYSCLK Counter For Period Match (default at reset) 1 Reserved" "0,1" newline bitfld.long 0x4 1. "HRCLKE,High Resolution Clock Enable Bit: 0 High resolution clock disabled (default at reset) 1 High resolution clock enabled. The clock should be enabled before enabling the high res function via the HRE bit." "0,1" newline bitfld.long 0x4 0. "HRE,High Resolution Enable Bit: 0 High resolution mode disabled (default at reset) 1 High resolution mode enabled. Enabling this mode will connect the capture registers and edge event modes of the ECAP to be accessed by the High Res function. Note: The.." "0,1" group.long 0x48++0x3 line.long 0x0 "CONTROLSS_ECAP6_HRINTEN" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration Period Check status Interrupt Enable: 0 Disable Calibration Period Check interrupt status 1 Enable Calibration Period Check interrupt status" "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration done Interrupt Enable: 0 Disable Calibration done Interrupt 1 Enable Calibration done Interrupt" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CONTROLSS_ECAP6_HRFLG" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration period check status Flag Bit: 1 Indicates that calibration ended before PRDCHK due to overflow on one of the counters. 0 Indicates no event occurred. Note: This bit remains latched until cleared by the user using the HRCLR.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration Done Interrupt Flag Bit: 1 Indicates calibration cycle is completed 0 Indicates calibration cycle has not completed. Note: This bit remains latched until cleared by the user using the HRCLR [CALIBDONE] bit." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Global calibration Interrupt Status Flag: 1 Indicates that an interrupt was generated from CALIBDONE or CALPRDCHKSTS. 0 Indicates no interrupt generated." "0,1" group.long 0x50++0xB line.long 0x0 "CONTROLSS_ECAP6_HRCLR" bitfld.long 0x0 2. "CALPRDCHKSTS,Clear Calibration period check status Flag Bit: 1 Clears the CALPRDCHKSTS flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Clear Calibration Done Interrupt Flag Bit: 1 Clears the CALIBDONE interrupt flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Clear Global calibration Interrupt Flag 1 Clears the Global interrupt flag and enables further interrupts to be generated if any of the event flags are set. 0 No effect." "0,1" line.long 0x4 "CONTROLSS_ECAP6_HRFRC" bitfld.long 0x4 2. "CALPRDCHKSTS,Force CALPRDCHKSTS flag: 0 No effect 1 Sets the CALPRDCHKSTS flag." "0,1" newline bitfld.long 0x4 1. "CALIBDONE,Force CALIBDONE flag: 0 No effect 1 Sets the CALIBDONE flag." "0,1" line.long 0x8 "CONTROLSS_ECAP6_HRCALPRD" hexmask.long 0x8 0.--31. 1. "PRD,Register to program calibration period. The period value is matched against HRSYSCLKCTR. On a match an interrupt is generated and the counter registers values are captured." rgroup.long 0x5C++0xF line.long 0x0 "CONTROLSS_ECAP6_HRSYSCLKCTR" hexmask.long 0x0 0.--31. 1. "HRSYSCLKCTR,Current SYSCLK counter value" line.long 0x4 "CONTROLSS_ECAP6_HRSYSCLKCAP" hexmask.long 0x4 0.--31. 1. "HRSYSCLKCAP,HRSYSCLKCTR is captures into this register at end of calibration cycle." line.long 0x8 "CONTROLSS_ECAP6_HRCLKCTR" hexmask.long 0x8 0.--31. 1. "HRCLKCTR,Current HRCLK counter value Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" line.long 0xC "CONTROLSS_ECAP6_HRCLKCAP" hexmask.long 0xC 0.--31. 1. "HRCLKCAP,HRCLKCTR is captures into this register at end of calibration cycle. Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" group.long 0x74++0x3 line.long 0x0 "CONTROLSS_ECAP6_HRDEBUGCTL" hexmask.long.byte 0x0 8.--11. 1. "OBSERVE_SRC_SEL,Select bits for selecting source for OBSERVE1 and OBSERVE2 registers 1000 HROUTH and HROUTL will read HR1OUT 1001 HROUTH and HROUTL will read HR2OUT 1010 HROUTH and HROUTL will read Capture Delayline 1 OBS1 1011 HROUTH and HROUTL will.." newline bitfld.long 0x0 4.--5. "CALIB_INPUT_SEL,Select bit for calibration input can be used to get fault coverage using these inputs 00 CAPIN is one of 128 inputs selected by INPUTSEL 01 CAPIN is connected to CAPIN_MEMMAP_SOURCE 10 CAPIN is internally generated signal waveform with.." "0,1,2,3" newline bitfld.long 0x0 2. "CAPIN_MMAP_SOURCE,Memory mapped CAPIN source Note : select CALIN source first it may happen that you may see interrupt if MMAP source is different from current value of CAPIN. This is debug feature hence no additional HW is necessary to prevent this." "0,1" newline bitfld.long 0x0 1. "DELAYRESETDLINE,Controls the reset delayline timing 0 reset is forced on next falling edge of HRCLK (1/2 cycle after capture) 1 reset is applied a cycle later (1 1/2 cycles after capture)" "0,1" newline bitfld.long 0x0 0. "DISABLEINVSEL,Disable INVSEL Logic: 0 State machine controls inversion on input signal 1 CAPIN signal propagated into delay line without inversion this means only rising edges can be measured" "0,1" rgroup.long 0x78++0x7 line.long 0x0 "CONTROLSS_ECAP6_HRDEBUGOBSERVE1" hexmask.long 0x0 0.--31. 1. "HROUTH,Reads raw output of HROUT capture delay line 1" line.long 0x4 "CONTROLSS_ECAP6_HRDEBUGOBSERVE2" hexmask.long 0x4 0.--31. 1. "HROUTL,Reads raw output of HROUT capture delay line 2" group.long 0x80++0x3 line.long 0x0 "CONTROLSS_ECAP6_MUNIT_COMMON_CTL" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Disabled with SOC level tieoff. 0x1 to 0x7F : Global load strobe from SOC level including ETPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not affect signal monitoring achieved with SOC level tieoff. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and.." group.long 0xC0++0x7 line.long 0x0 "CONTROLSS_ECAP6_MUNIT_1_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "CONTROLSS_ECAP6_MUNIT_1_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "CONTROLSS_ECAP6_MUNIT_1_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP6_MUNIT_1_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP6_MUNIT_1_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP6_MUNIT_1_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "CONTROLSS_ECAP6_MUNIT_1_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP6_MUNIT_1_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "CONTROLSS_ECAP6_MUNIT_2_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "CONTROLSS_ECAP6_MUNIT_2_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "CONTROLSS_ECAP6_MUNIT_2_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP6_MUNIT_2_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP6_MUNIT_2_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP6_MUNIT_2_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "CONTROLSS_ECAP6_MUNIT_2_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP6_MUNIT_2_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP7" base ad:0x50247000 group.long 0x0++0x17 line.long 0x0 "CONTROLSS_ECAP7_TSCTR" hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1) This register reads HRCOUNTER value and is not writable 2) can be reset using CTRFILTRESET 3) Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "CONTROLSS_ECAP7_CTRPHS" hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "CONTROLSS_ECAP7_CAP1" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by: - Time-Stamp counter value (TSCTR) during a capture event - Software - may be useful for test purposes or initialization - ARPD shadow register (CAP3) when used in APWM mode" line.long 0xC "CONTROLSS_ECAP7_CAP2" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by: - Time-Stamp ( counter value) during a capture event - Software - may be useful for test purposes - ACMP shadow register (CAP4) when used in APWM mode" line.long 0x10 "CONTROLSS_ECAP7_CAP3" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register. In APWM mode this is the period shadow (APRD) register. You can update the PWM period value through this register. CAP3 (APRD) shadows CAP1 in this mode." line.long 0x14 "CONTROLSS_ECAP7_CAP4" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register. In APWM mode this is the compare shadow (ACMP) register. You can update the PWM compare value via this register. CAP4 (ACMP) shadows CAP2 in this mode." group.long 0x24++0x3 line.long 0x0 "CONTROLSS_ECAP7_ECCTL0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b (R/W) = SOC trigger source is CEVT1 01b (R/W) = SOC trigger source is CEVT2 10b (R/W) = SOC trigger source is CEVT3 11b (R/W) = SOC trigger source is CEVT4 APWM Mode: 00b (R/W) = SOC trigger interrupt.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "CONTROLSS_ECAP7_ECCTL1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0x0 | ECAP_STOP_EMUTSCTR counter stops immediately on emulation suspend 0x1 | ECAP_RUNS_UNTILTSCTR counter runs until = 0 0x2 | ECAP_UNAF_EMU_SUSTSCTR counter is unaffected by emulation suspend (Run.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0x00 | ECAP_DIV1Divide by 1 (i.e . no prescale by-pass the prescaler) 0x01 | ECAP_DIV2Divide by 2 0x02 | ECAP_DIV4Divide by 4 0x03 | ECAP_DIV6Divide by 6 0x04 |.." newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 | ECAP_DISABLEDisable CAP1-4 register loads at capture event time. 1 | ECAP_ENABLEEnable CAP1-4.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 | ECAP_DO_NOT_RESET_EVENT4Do not reset counter on Capture Event 4 (absolute time stamp operation) 1 | ECAP_RESET_EVENT4Reset counter after Capture Event 4 time-stamp has been captured (used in.." "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 | ECAP_CAP_EVENT4_RISECapture Event 4 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT4_FALLCapture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 | ECAP_DO_NOT_RESET_EVENT3Do not reset counter on Capture Event 3 (absolute time stamp) 1 | ECAP_RESET_EVENT3Reset counter after Event 3 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 | ECAP_CAP_EVENT3_RISECapture Event 3 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT3_FALLCapture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 | ECAP_DO_NOT_RESET_EVENT2Do not reset counter on Capture Event 2 (absolute time stamp) 1 | ECAP_RESET_EVENT2Reset counter after Event 2 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 | ECAP_CAP_EVENT2_RISECapture Event 2 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT2_FALLCapture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 | ECAP_DO_NOT_RESET_EVENT1Do not reset counter on Capture Event 1 (absolute time stamp) 1 | ECAP_RESET_EVENT1Reset counter after Event 1 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 | ECAP_CAP_EVENT1_RISECapture Event 1 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT1_FALLCapture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "CONTROLSS_ECAP7_ECCTL2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b (R) = CAP1 register gets loaded on next capture event. 01b (R) = CAP2 register gets loaded on next capture event. 10b (R) = CAP3 register gets loaded on next capture event. 11b (R) =.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b (R/W) = DMA interrupt source is CEVT1 01b (R/W) = DMA interrupt source is CEVT2 10b (R/W) = DMA interrupt source is CEVT3 11b (R/W) = DMA interrupt source is CEVT4 APWM Mode: 00b (R/W) = DMA interrupt source.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h (R) = No effect 1h (W) = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 | ECAP_OUTPUT_ACTIVE_HIGHOutput is active high (Compare value defines high time) 1 | ECAP_OUTPUT_ACTIVE_LOWOutput is active low (Compare value defines.." "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 | ECAP_MODULEECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers - Permits user.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter (TSCTR) Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 |.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0x0 | SWSYNCsync out signal is SWSYNC 0x1 | ECAP_CTR_PRD_TO_SYNCOUTSelect CTR = PRD event to be the sync-out signal 0x2 | ECAP_DISABLE_SYNC_OUTDisable sync out signal 0x3 |.." "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter (TSCTR) Sync-In select mode 0 | ECAP_DISABLE_SYNC_INDisable sync-in option 1 | ECAP_ENABLE_COUNTER_REGISTEREnable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp (TSCTR) Counter Stop (freeze) Control 0 | ECAP_TSCTR_STOPPEDTSCTR stopped 1 | ECAP_TSCTR_FREE_RUNNINGTSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 | ECAP_NO_EFFECT_RETURNS_0Has no effect (reading always returns a 0) 1 | ECAP_ARMS_ONESHOTArms the one-shot sequence as follows: 1) Resets the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur before the CAP(1-4) registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1-4) of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control (applicable only in capture mode) 0 | ECAP_OPP_CONTOperate in continuous mode 1 | ECAP_OPP_ONEOperate in one-Shot mode" "0,1" line.word 0x4 "CONTROLSS_ECAP7_ECEINT" bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 | ECAP_DISAB_HRERROR_INTERRUPTDisable High Resolution Error as an Interrupt source 1 | ECAP_ENAB_HRERROR_INTERRUPTEnable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 | ECAP_DISAB_CE_INTERRUPTDisable Compare Equal as an Interrupt source 1 | ECAP_ENAB_CE_INTERRUPTEnable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 | ECAP_DISAB_PE_INTERRUPTDisable Period Equal as an Interrupt source 1 | ECAP_ENAB_PE_INTERRUPTEnable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 | ECAP_DISAB_CO_INTERRUPTDisabled counter Overflow as an Interrupt source 1 | ECAP_ENAB_CO_INTERRUPTEnable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 | ECAP_DISAB_CAP4_INTERRUPTDisable Capture Event 4 as an Interrupt source 1 | ECAP_ENAB_CAP4_INTERRUPTCapture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 | ECAP_DISAB_CAP3_INTERRUPTDisable Capture Event 3 as an Interrupt source 1 | ECAP_ENAB_CAP3_INTERRUPTEnable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 | ECAP_DISAB_CAP2_INTERRUPTDisable Capture Event 2 as an Interrupt source 1 | ECAP_ENAB_CAP2_INTERRUPTEnable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 | ECAP_DISAB_CAP1_INTERRUPTDisable Capture Event 1 as an Interrupt source 1 | ECAP_ENAB_CAP1_INTERRUPTEnable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "CONTROLSS_ECAP7_ECFLG" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_HIGH_RESOLUTION_ERRORIndicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_COMPARE_REGIndicates the counter (TSCTR) reached the compare.." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_PERIOD_VALUE_RESETIndicates the counter (TSCTR) reached the period register.." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_TRANSIndicates the counter (TSCTR) has made the transition from.." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_4TH_EVENT_ECAPXIndicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_3RD_EVENT_ECAPXIndicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_2ND_EVENT_ECAPXIndicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_1ST_EVENT_ECAPXIndicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_INTERRUPTIndicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_ECAP7_ECCLR" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_HRERRORWriting a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_CMPWriting a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTROVFWriting a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT4Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT3Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT2Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT1Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_INTWriting a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are.." "0,1" line.word 0x2 "CONTROLSS_ECAP7_ECFRC" bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTROVFWriting a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT4Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT3Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT2Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT1Sets the CEVT1 flag." "0,1" group.long 0x3C++0x7 line.long 0x0 "CONTROLSS_ECAP7_ECAPSYNCINSEL" hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determines the source of SYNCIN signal. 0x0 : Disabled using SOC tieoff. 0x7F : Refer to SOC spec for details." line.long 0x4 "CONTROLSS_ECAP7_HRCTL" bitfld.long 0x4 5. "CALIBCONT,Continuous mode Calibration Select Bit: 0 Continuous mode disabled. 1 Continuous mode enabled. Calibration automatically restarts at end of current calibration cycle." "0,1" newline rbitfld.long 0x4 4. "CALIBSTS,Calibration status Bit: 0 No active calibration cycle 1 Calibration cycle in progress" "0,1" newline bitfld.long 0x4 3. "CALIBSTART,Calibration start Bit: 0 No effect 1 Starts the calibration cycle" "0,1" newline bitfld.long 0x4 2. "PRDSEL,Calibration Period Match Select Bit: 0 Use SYSCLK Counter For Period Match (default at reset) 1 Reserved" "0,1" newline bitfld.long 0x4 1. "HRCLKE,High Resolution Clock Enable Bit: 0 High resolution clock disabled (default at reset) 1 High resolution clock enabled. The clock should be enabled before enabling the high res function via the HRE bit." "0,1" newline bitfld.long 0x4 0. "HRE,High Resolution Enable Bit: 0 High resolution mode disabled (default at reset) 1 High resolution mode enabled. Enabling this mode will connect the capture registers and edge event modes of the ECAP to be accessed by the High Res function. Note: The.." "0,1" group.long 0x48++0x3 line.long 0x0 "CONTROLSS_ECAP7_HRINTEN" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration Period Check status Interrupt Enable: 0 Disable Calibration Period Check interrupt status 1 Enable Calibration Period Check interrupt status" "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration done Interrupt Enable: 0 Disable Calibration done Interrupt 1 Enable Calibration done Interrupt" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CONTROLSS_ECAP7_HRFLG" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration period check status Flag Bit: 1 Indicates that calibration ended before PRDCHK due to overflow on one of the counters. 0 Indicates no event occurred. Note: This bit remains latched until cleared by the user using the HRCLR.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration Done Interrupt Flag Bit: 1 Indicates calibration cycle is completed 0 Indicates calibration cycle has not completed. Note: This bit remains latched until cleared by the user using the HRCLR [CALIBDONE] bit." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Global calibration Interrupt Status Flag: 1 Indicates that an interrupt was generated from CALIBDONE or CALPRDCHKSTS. 0 Indicates no interrupt generated." "0,1" group.long 0x50++0xB line.long 0x0 "CONTROLSS_ECAP7_HRCLR" bitfld.long 0x0 2. "CALPRDCHKSTS,Clear Calibration period check status Flag Bit: 1 Clears the CALPRDCHKSTS flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Clear Calibration Done Interrupt Flag Bit: 1 Clears the CALIBDONE interrupt flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Clear Global calibration Interrupt Flag 1 Clears the Global interrupt flag and enables further interrupts to be generated if any of the event flags are set. 0 No effect." "0,1" line.long 0x4 "CONTROLSS_ECAP7_HRFRC" bitfld.long 0x4 2. "CALPRDCHKSTS,Force CALPRDCHKSTS flag: 0 No effect 1 Sets the CALPRDCHKSTS flag." "0,1" newline bitfld.long 0x4 1. "CALIBDONE,Force CALIBDONE flag: 0 No effect 1 Sets the CALIBDONE flag." "0,1" line.long 0x8 "CONTROLSS_ECAP7_HRCALPRD" hexmask.long 0x8 0.--31. 1. "PRD,Register to program calibration period. The period value is matched against HRSYSCLKCTR. On a match an interrupt is generated and the counter registers values are captured." rgroup.long 0x5C++0xF line.long 0x0 "CONTROLSS_ECAP7_HRSYSCLKCTR" hexmask.long 0x0 0.--31. 1. "HRSYSCLKCTR,Current SYSCLK counter value" line.long 0x4 "CONTROLSS_ECAP7_HRSYSCLKCAP" hexmask.long 0x4 0.--31. 1. "HRSYSCLKCAP,HRSYSCLKCTR is captures into this register at end of calibration cycle." line.long 0x8 "CONTROLSS_ECAP7_HRCLKCTR" hexmask.long 0x8 0.--31. 1. "HRCLKCTR,Current HRCLK counter value Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" line.long 0xC "CONTROLSS_ECAP7_HRCLKCAP" hexmask.long 0xC 0.--31. 1. "HRCLKCAP,HRCLKCTR is captures into this register at end of calibration cycle. Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" group.long 0x74++0x3 line.long 0x0 "CONTROLSS_ECAP7_HRDEBUGCTL" hexmask.long.byte 0x0 8.--11. 1. "OBSERVE_SRC_SEL,Select bits for selecting source for OBSERVE1 and OBSERVE2 registers 1000 HROUTH and HROUTL will read HR1OUT 1001 HROUTH and HROUTL will read HR2OUT 1010 HROUTH and HROUTL will read Capture Delayline 1 OBS1 1011 HROUTH and HROUTL will.." newline bitfld.long 0x0 4.--5. "CALIB_INPUT_SEL,Select bit for calibration input can be used to get fault coverage using these inputs 00 CAPIN is one of 128 inputs selected by INPUTSEL 01 CAPIN is connected to CAPIN_MEMMAP_SOURCE 10 CAPIN is internally generated signal waveform with.." "0,1,2,3" newline bitfld.long 0x0 2. "CAPIN_MMAP_SOURCE,Memory mapped CAPIN source Note : select CALIN source first it may happen that you may see interrupt if MMAP source is different from current value of CAPIN. This is debug feature hence no additional HW is necessary to prevent this." "0,1" newline bitfld.long 0x0 1. "DELAYRESETDLINE,Controls the reset delayline timing 0 reset is forced on next falling edge of HRCLK (1/2 cycle after capture) 1 reset is applied a cycle later (1 1/2 cycles after capture)" "0,1" newline bitfld.long 0x0 0. "DISABLEINVSEL,Disable INVSEL Logic: 0 State machine controls inversion on input signal 1 CAPIN signal propagated into delay line without inversion this means only rising edges can be measured" "0,1" rgroup.long 0x78++0x7 line.long 0x0 "CONTROLSS_ECAP7_HRDEBUGOBSERVE1" hexmask.long 0x0 0.--31. 1. "HROUTH,Reads raw output of HROUT capture delay line 1" line.long 0x4 "CONTROLSS_ECAP7_HRDEBUGOBSERVE2" hexmask.long 0x4 0.--31. 1. "HROUTL,Reads raw output of HROUT capture delay line 2" group.long 0x80++0x3 line.long 0x0 "CONTROLSS_ECAP7_MUNIT_COMMON_CTL" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Disabled with SOC level tieoff. 0x1 to 0x7F : Global load strobe from SOC level including ETPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not affect signal monitoring achieved with SOC level tieoff. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and.." group.long 0xC0++0x7 line.long 0x0 "CONTROLSS_ECAP7_MUNIT_1_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "CONTROLSS_ECAP7_MUNIT_1_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "CONTROLSS_ECAP7_MUNIT_1_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP7_MUNIT_1_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP7_MUNIT_1_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP7_MUNIT_1_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "CONTROLSS_ECAP7_MUNIT_1_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP7_MUNIT_1_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "CONTROLSS_ECAP7_MUNIT_2_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "CONTROLSS_ECAP7_MUNIT_2_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "CONTROLSS_ECAP7_MUNIT_2_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP7_MUNIT_2_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP7_MUNIT_2_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP7_MUNIT_2_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "CONTROLSS_ECAP7_MUNIT_2_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP7_MUNIT_2_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP8" base ad:0x50248000 group.long 0x0++0x17 line.long 0x0 "CONTROLSS_ECAP8_TSCTR" hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1) This register reads HRCOUNTER value and is not writable 2) can be reset using CTRFILTRESET 3) Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "CONTROLSS_ECAP8_CTRPHS" hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "CONTROLSS_ECAP8_CAP1" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by: - Time-Stamp counter value (TSCTR) during a capture event - Software - may be useful for test purposes or initialization - ARPD shadow register (CAP3) when used in APWM mode" line.long 0xC "CONTROLSS_ECAP8_CAP2" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by: - Time-Stamp ( counter value) during a capture event - Software - may be useful for test purposes - ACMP shadow register (CAP4) when used in APWM mode" line.long 0x10 "CONTROLSS_ECAP8_CAP3" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register. In APWM mode this is the period shadow (APRD) register. You can update the PWM period value through this register. CAP3 (APRD) shadows CAP1 in this mode." line.long 0x14 "CONTROLSS_ECAP8_CAP4" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register. In APWM mode this is the compare shadow (ACMP) register. You can update the PWM compare value via this register. CAP4 (ACMP) shadows CAP2 in this mode." group.long 0x24++0x3 line.long 0x0 "CONTROLSS_ECAP8_ECCTL0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b (R/W) = SOC trigger source is CEVT1 01b (R/W) = SOC trigger source is CEVT2 10b (R/W) = SOC trigger source is CEVT3 11b (R/W) = SOC trigger source is CEVT4 APWM Mode: 00b (R/W) = SOC trigger interrupt.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "CONTROLSS_ECAP8_ECCTL1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0x0 | ECAP_STOP_EMUTSCTR counter stops immediately on emulation suspend 0x1 | ECAP_RUNS_UNTILTSCTR counter runs until = 0 0x2 | ECAP_UNAF_EMU_SUSTSCTR counter is unaffected by emulation suspend (Run.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0x00 | ECAP_DIV1Divide by 1 (i.e . no prescale by-pass the prescaler) 0x01 | ECAP_DIV2Divide by 2 0x02 | ECAP_DIV4Divide by 4 0x03 | ECAP_DIV6Divide by 6 0x04 |.." newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 | ECAP_DISABLEDisable CAP1-4 register loads at capture event time. 1 | ECAP_ENABLEEnable CAP1-4.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 | ECAP_DO_NOT_RESET_EVENT4Do not reset counter on Capture Event 4 (absolute time stamp operation) 1 | ECAP_RESET_EVENT4Reset counter after Capture Event 4 time-stamp has been captured (used in.." "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 | ECAP_CAP_EVENT4_RISECapture Event 4 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT4_FALLCapture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 | ECAP_DO_NOT_RESET_EVENT3Do not reset counter on Capture Event 3 (absolute time stamp) 1 | ECAP_RESET_EVENT3Reset counter after Event 3 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 | ECAP_CAP_EVENT3_RISECapture Event 3 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT3_FALLCapture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 | ECAP_DO_NOT_RESET_EVENT2Do not reset counter on Capture Event 2 (absolute time stamp) 1 | ECAP_RESET_EVENT2Reset counter after Event 2 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 | ECAP_CAP_EVENT2_RISECapture Event 2 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT2_FALLCapture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 | ECAP_DO_NOT_RESET_EVENT1Do not reset counter on Capture Event 1 (absolute time stamp) 1 | ECAP_RESET_EVENT1Reset counter after Event 1 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 | ECAP_CAP_EVENT1_RISECapture Event 1 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT1_FALLCapture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "CONTROLSS_ECAP8_ECCTL2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b (R) = CAP1 register gets loaded on next capture event. 01b (R) = CAP2 register gets loaded on next capture event. 10b (R) = CAP3 register gets loaded on next capture event. 11b (R) =.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b (R/W) = DMA interrupt source is CEVT1 01b (R/W) = DMA interrupt source is CEVT2 10b (R/W) = DMA interrupt source is CEVT3 11b (R/W) = DMA interrupt source is CEVT4 APWM Mode: 00b (R/W) = DMA interrupt source.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h (R) = No effect 1h (W) = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 | ECAP_OUTPUT_ACTIVE_HIGHOutput is active high (Compare value defines high time) 1 | ECAP_OUTPUT_ACTIVE_LOWOutput is active low (Compare value defines.." "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 | ECAP_MODULEECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers - Permits user.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter (TSCTR) Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 |.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0x0 | SWSYNCsync out signal is SWSYNC 0x1 | ECAP_CTR_PRD_TO_SYNCOUTSelect CTR = PRD event to be the sync-out signal 0x2 | ECAP_DISABLE_SYNC_OUTDisable sync out signal 0x3 |.." "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter (TSCTR) Sync-In select mode 0 | ECAP_DISABLE_SYNC_INDisable sync-in option 1 | ECAP_ENABLE_COUNTER_REGISTEREnable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp (TSCTR) Counter Stop (freeze) Control 0 | ECAP_TSCTR_STOPPEDTSCTR stopped 1 | ECAP_TSCTR_FREE_RUNNINGTSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 | ECAP_NO_EFFECT_RETURNS_0Has no effect (reading always returns a 0) 1 | ECAP_ARMS_ONESHOTArms the one-shot sequence as follows: 1) Resets the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur before the CAP(1-4) registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1-4) of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control (applicable only in capture mode) 0 | ECAP_OPP_CONTOperate in continuous mode 1 | ECAP_OPP_ONEOperate in one-Shot mode" "0,1" line.word 0x4 "CONTROLSS_ECAP8_ECEINT" bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 | ECAP_DISAB_HRERROR_INTERRUPTDisable High Resolution Error as an Interrupt source 1 | ECAP_ENAB_HRERROR_INTERRUPTEnable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 | ECAP_DISAB_CE_INTERRUPTDisable Compare Equal as an Interrupt source 1 | ECAP_ENAB_CE_INTERRUPTEnable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 | ECAP_DISAB_PE_INTERRUPTDisable Period Equal as an Interrupt source 1 | ECAP_ENAB_PE_INTERRUPTEnable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 | ECAP_DISAB_CO_INTERRUPTDisabled counter Overflow as an Interrupt source 1 | ECAP_ENAB_CO_INTERRUPTEnable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 | ECAP_DISAB_CAP4_INTERRUPTDisable Capture Event 4 as an Interrupt source 1 | ECAP_ENAB_CAP4_INTERRUPTCapture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 | ECAP_DISAB_CAP3_INTERRUPTDisable Capture Event 3 as an Interrupt source 1 | ECAP_ENAB_CAP3_INTERRUPTEnable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 | ECAP_DISAB_CAP2_INTERRUPTDisable Capture Event 2 as an Interrupt source 1 | ECAP_ENAB_CAP2_INTERRUPTEnable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 | ECAP_DISAB_CAP1_INTERRUPTDisable Capture Event 1 as an Interrupt source 1 | ECAP_ENAB_CAP1_INTERRUPTEnable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "CONTROLSS_ECAP8_ECFLG" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_HIGH_RESOLUTION_ERRORIndicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_COMPARE_REGIndicates the counter (TSCTR) reached the compare.." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_PERIOD_VALUE_RESETIndicates the counter (TSCTR) reached the period register.." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_TRANSIndicates the counter (TSCTR) has made the transition from.." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_4TH_EVENT_ECAPXIndicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_3RD_EVENT_ECAPXIndicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_2ND_EVENT_ECAPXIndicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_1ST_EVENT_ECAPXIndicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_INTERRUPTIndicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_ECAP8_ECCLR" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_HRERRORWriting a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_CMPWriting a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTROVFWriting a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT4Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT3Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT2Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT1Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_INTWriting a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are.." "0,1" line.word 0x2 "CONTROLSS_ECAP8_ECFRC" bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTROVFWriting a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT4Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT3Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT2Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT1Sets the CEVT1 flag." "0,1" group.long 0x3C++0x7 line.long 0x0 "CONTROLSS_ECAP8_ECAPSYNCINSEL" hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determines the source of SYNCIN signal. 0x0 : Disabled using SOC tieoff. 0x7F : Refer to SOC spec for details." line.long 0x4 "CONTROLSS_ECAP8_HRCTL" bitfld.long 0x4 5. "CALIBCONT,Continuous mode Calibration Select Bit: 0 Continuous mode disabled. 1 Continuous mode enabled. Calibration automatically restarts at end of current calibration cycle." "0,1" newline rbitfld.long 0x4 4. "CALIBSTS,Calibration status Bit: 0 No active calibration cycle 1 Calibration cycle in progress" "0,1" newline bitfld.long 0x4 3. "CALIBSTART,Calibration start Bit: 0 No effect 1 Starts the calibration cycle" "0,1" newline bitfld.long 0x4 2. "PRDSEL,Calibration Period Match Select Bit: 0 Use SYSCLK Counter For Period Match (default at reset) 1 Reserved" "0,1" newline bitfld.long 0x4 1. "HRCLKE,High Resolution Clock Enable Bit: 0 High resolution clock disabled (default at reset) 1 High resolution clock enabled. The clock should be enabled before enabling the high res function via the HRE bit." "0,1" newline bitfld.long 0x4 0. "HRE,High Resolution Enable Bit: 0 High resolution mode disabled (default at reset) 1 High resolution mode enabled. Enabling this mode will connect the capture registers and edge event modes of the ECAP to be accessed by the High Res function. Note: The.." "0,1" group.long 0x48++0x3 line.long 0x0 "CONTROLSS_ECAP8_HRINTEN" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration Period Check status Interrupt Enable: 0 Disable Calibration Period Check interrupt status 1 Enable Calibration Period Check interrupt status" "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration done Interrupt Enable: 0 Disable Calibration done Interrupt 1 Enable Calibration done Interrupt" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CONTROLSS_ECAP8_HRFLG" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration period check status Flag Bit: 1 Indicates that calibration ended before PRDCHK due to overflow on one of the counters. 0 Indicates no event occurred. Note: This bit remains latched until cleared by the user using the HRCLR.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration Done Interrupt Flag Bit: 1 Indicates calibration cycle is completed 0 Indicates calibration cycle has not completed. Note: This bit remains latched until cleared by the user using the HRCLR [CALIBDONE] bit." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Global calibration Interrupt Status Flag: 1 Indicates that an interrupt was generated from CALIBDONE or CALPRDCHKSTS. 0 Indicates no interrupt generated." "0,1" group.long 0x50++0xB line.long 0x0 "CONTROLSS_ECAP8_HRCLR" bitfld.long 0x0 2. "CALPRDCHKSTS,Clear Calibration period check status Flag Bit: 1 Clears the CALPRDCHKSTS flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Clear Calibration Done Interrupt Flag Bit: 1 Clears the CALIBDONE interrupt flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Clear Global calibration Interrupt Flag 1 Clears the Global interrupt flag and enables further interrupts to be generated if any of the event flags are set. 0 No effect." "0,1" line.long 0x4 "CONTROLSS_ECAP8_HRFRC" bitfld.long 0x4 2. "CALPRDCHKSTS,Force CALPRDCHKSTS flag: 0 No effect 1 Sets the CALPRDCHKSTS flag." "0,1" newline bitfld.long 0x4 1. "CALIBDONE,Force CALIBDONE flag: 0 No effect 1 Sets the CALIBDONE flag." "0,1" line.long 0x8 "CONTROLSS_ECAP8_HRCALPRD" hexmask.long 0x8 0.--31. 1. "PRD,Register to program calibration period. The period value is matched against HRSYSCLKCTR. On a match an interrupt is generated and the counter registers values are captured." rgroup.long 0x5C++0xF line.long 0x0 "CONTROLSS_ECAP8_HRSYSCLKCTR" hexmask.long 0x0 0.--31. 1. "HRSYSCLKCTR,Current SYSCLK counter value" line.long 0x4 "CONTROLSS_ECAP8_HRSYSCLKCAP" hexmask.long 0x4 0.--31. 1. "HRSYSCLKCAP,HRSYSCLKCTR is captures into this register at end of calibration cycle." line.long 0x8 "CONTROLSS_ECAP8_HRCLKCTR" hexmask.long 0x8 0.--31. 1. "HRCLKCTR,Current HRCLK counter value Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" line.long 0xC "CONTROLSS_ECAP8_HRCLKCAP" hexmask.long 0xC 0.--31. 1. "HRCLKCAP,HRCLKCTR is captures into this register at end of calibration cycle. Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" group.long 0x74++0x3 line.long 0x0 "CONTROLSS_ECAP8_HRDEBUGCTL" hexmask.long.byte 0x0 8.--11. 1. "OBSERVE_SRC_SEL,Select bits for selecting source for OBSERVE1 and OBSERVE2 registers 1000 HROUTH and HROUTL will read HR1OUT 1001 HROUTH and HROUTL will read HR2OUT 1010 HROUTH and HROUTL will read Capture Delayline 1 OBS1 1011 HROUTH and HROUTL will.." newline bitfld.long 0x0 4.--5. "CALIB_INPUT_SEL,Select bit for calibration input can be used to get fault coverage using these inputs 00 CAPIN is one of 128 inputs selected by INPUTSEL 01 CAPIN is connected to CAPIN_MEMMAP_SOURCE 10 CAPIN is internally generated signal waveform with.." "0,1,2,3" newline bitfld.long 0x0 2. "CAPIN_MMAP_SOURCE,Memory mapped CAPIN source Note : select CALIN source first it may happen that you may see interrupt if MMAP source is different from current value of CAPIN. This is debug feature hence no additional HW is necessary to prevent this." "0,1" newline bitfld.long 0x0 1. "DELAYRESETDLINE,Controls the reset delayline timing 0 reset is forced on next falling edge of HRCLK (1/2 cycle after capture) 1 reset is applied a cycle later (1 1/2 cycles after capture)" "0,1" newline bitfld.long 0x0 0. "DISABLEINVSEL,Disable INVSEL Logic: 0 State machine controls inversion on input signal 1 CAPIN signal propagated into delay line without inversion this means only rising edges can be measured" "0,1" rgroup.long 0x78++0x7 line.long 0x0 "CONTROLSS_ECAP8_HRDEBUGOBSERVE1" hexmask.long 0x0 0.--31. 1. "HROUTH,Reads raw output of HROUT capture delay line 1" line.long 0x4 "CONTROLSS_ECAP8_HRDEBUGOBSERVE2" hexmask.long 0x4 0.--31. 1. "HROUTL,Reads raw output of HROUT capture delay line 2" group.long 0x80++0x3 line.long 0x0 "CONTROLSS_ECAP8_MUNIT_COMMON_CTL" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Disabled with SOC level tieoff. 0x1 to 0x7F : Global load strobe from SOC level including ETPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not affect signal monitoring achieved with SOC level tieoff. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and.." group.long 0xC0++0x7 line.long 0x0 "CONTROLSS_ECAP8_MUNIT_1_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "CONTROLSS_ECAP8_MUNIT_1_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "CONTROLSS_ECAP8_MUNIT_1_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP8_MUNIT_1_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP8_MUNIT_1_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP8_MUNIT_1_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "CONTROLSS_ECAP8_MUNIT_1_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP8_MUNIT_1_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "CONTROLSS_ECAP8_MUNIT_2_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "CONTROLSS_ECAP8_MUNIT_2_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "CONTROLSS_ECAP8_MUNIT_2_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP8_MUNIT_2_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP8_MUNIT_2_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP8_MUNIT_2_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "CONTROLSS_ECAP8_MUNIT_2_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP8_MUNIT_2_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree "ECAP9" base ad:0x50249000 group.long 0x0++0x17 line.long 0x0 "CONTROLSS_ECAP9_TSCTR" hexmask.long 0x0 0.--31. 1. "TSCTR,Active 32-bit counter register that is used as the capture time-base HR mode : 1) This register reads HRCOUNTER value and is not writable 2) can be reset using CTRFILTRESET 3) Its not synchronized to SYSCLK domain so reads may not be accurate" line.long 0x4 "CONTROLSS_ECAP9_CTRPHS" hexmask.long 0x4 0.--31. 1. "CTRPHS,Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP.." line.long 0x8 "CONTROLSS_ECAP9_CAP1" hexmask.long 0x8 0.--31. 1. "CAP1,This register can be loaded (written) by: - Time-Stamp counter value (TSCTR) during a capture event - Software - may be useful for test purposes or initialization - ARPD shadow register (CAP3) when used in APWM mode" line.long 0xC "CONTROLSS_ECAP9_CAP2" hexmask.long 0xC 0.--31. 1. "CAP2,This register can be loaded (written) by: - Time-Stamp ( counter value) during a capture event - Software - may be useful for test purposes - ACMP shadow register (CAP4) when used in APWM mode" line.long 0x10 "CONTROLSS_ECAP9_CAP3" hexmask.long 0x10 0.--31. 1. "CAP3,In CMP mode this is a time-stamp capture register. In APWM mode this is the period shadow (APRD) register. You can update the PWM period value through this register. CAP3 (APRD) shadows CAP1 in this mode." line.long 0x14 "CONTROLSS_ECAP9_CAP4" hexmask.long 0x14 0.--31. 1. "CAP4,In CMP mode this is a time-stamp capture register. In APWM mode this is the compare shadow (ACMP) register. You can update the PWM compare value via this register. CAP4 (ACMP) shadows CAP2 in this mode." group.long 0x24++0x3 line.long 0x0 "CONTROLSS_ECAP9_ECCTL0" bitfld.long 0x0 16.--17. "SOCEVTSEL,ADC SOC event select Capture Mode: 00b (R/W) = SOC trigger source is CEVT1 01b (R/W) = SOC trigger source is CEVT2 10b (R/W) = SOC trigger source is CEVT3 11b (R/W) = SOC trigger source is CEVT4 APWM Mode: 00b (R/W) = SOC trigger interrupt.." "0,1,2,3" newline hexmask.long.byte 0x0 12.--15. 1. "QUALPRD,Qual period to filter out noise on input signals being monitored Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of.." newline hexmask.long.byte 0x0 0.--7. 1. "INPUTSEL,Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]" group.word 0x28++0x5 line.word 0x0 "CONTROLSS_ECAP9_ECCTL1" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Control 0x0 | ECAP_STOP_EMUTSCTR counter stops immediately on emulation suspend 0x1 | ECAP_RUNS_UNTILTSCTR counter runs until = 0 0x2 | ECAP_UNAF_EMU_SUSTSCTR counter is unaffected by emulation suspend (Run.." "0,1,2,3" newline hexmask.word.byte 0x0 9.--13. 1. "PRESCALE,Event Filter prescale select 0x00 | ECAP_DIV1Divide by 1 (i.e . no prescale by-pass the prescaler) 0x01 | ECAP_DIV2Divide by 2 0x02 | ECAP_DIV4Divide by 4 0x03 | ECAP_DIV6Divide by 6 0x04 |.." newline bitfld.word 0x0 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event. Note that this bit does not disable CEVTn events from being generated. 0 | ECAP_DISABLEDisable CAP1-4 register loads at capture event time. 1 | ECAP_ENABLEEnable CAP1-4.." "0,1" newline bitfld.word 0x0 7. "CTRRST4,Counter Reset on Capture Event 4 0 | ECAP_DO_NOT_RESET_EVENT4Do not reset counter on Capture Event 4 (absolute time stamp operation) 1 | ECAP_RESET_EVENT4Reset counter after Capture Event 4 time-stamp has been captured (used in.." "0,1" newline bitfld.word 0x0 6. "CAP4POL,Capture Event 4 Polarity select 0 | ECAP_CAP_EVENT4_RISECapture Event 4 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT4_FALLCapture Event 4 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 5. "CTRRST3,Counter Reset on Capture Event 3 0 | ECAP_DO_NOT_RESET_EVENT3Do not reset counter on Capture Event 3 (absolute time stamp) 1 | ECAP_RESET_EVENT3Reset counter after Event 3 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 4. "CAP3POL,Capture Event 3 Polarity select 0 | ECAP_CAP_EVENT3_RISECapture Event 3 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT3_FALLCapture Event 3 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 3. "CTRRST2,Counter Reset on Capture Event 2 0 | ECAP_DO_NOT_RESET_EVENT2Do not reset counter on Capture Event 2 (absolute time stamp) 1 | ECAP_RESET_EVENT2Reset counter after Event 2 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 2. "CAP2POL,Capture Event 2 Polarity select 0 | ECAP_CAP_EVENT2_RISECapture Event 2 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT2_FALLCapture Event 2 triggered on a falling edge (FE)" "0,1" newline bitfld.word 0x0 1. "CTRRST1,Counter Reset on Capture Event 1 0 | ECAP_DO_NOT_RESET_EVENT1Do not reset counter on Capture Event 1 (absolute time stamp) 1 | ECAP_RESET_EVENT1Reset counter after Event 1 time-stamp has been captured (used in difference mode.." "0,1" newline bitfld.word 0x0 0. "CAP1POL,Capture Event 1 Polarity select 0 | ECAP_CAP_EVENT1_RISECapture Event 1 triggered on a rising edge (RE) 1 | ECAP_CAP_EVENT1_FALLCapture Event 1 triggered on a falling edge (FE)" "0,1" line.word 0x2 "CONTROLSS_ECAP9_ECCTL2" bitfld.word 0x2 14.--15. "MODCNTRSTS,This bit field reads current status on modulo counter 00b (R) = CAP1 register gets loaded on next capture event. 01b (R) = CAP2 register gets loaded on next capture event. 10b (R) = CAP3 register gets loaded on next capture event. 11b (R) =.." "0,1,2,3" newline bitfld.word 0x2 12.--13. "DMAEVTSEL,DMA event select Capture Mode: 00b (R/W) = DMA interrupt source is CEVT1 01b (R/W) = DMA interrupt source is CEVT2 10b (R/W) = DMA interrupt source is CEVT3 11b (R/W) = DMA interrupt source is CEVT4 APWM Mode: 00b (R/W) = DMA interrupt source.." "0,1,2,3" newline bitfld.word 0x2 11. "CTRFILTRESET,Reset Bit 0h (R) = No effect 1h (W) = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while.." "0,1" newline bitfld.word 0x2 10. "APWMPOL,APWM output polarity select. This is applicable only in APWM operating mode. 0 | ECAP_OUTPUT_ACTIVE_HIGHOutput is active high (Compare value defines high time) 1 | ECAP_OUTPUT_ACTIVE_LOWOutput is active low (Compare value defines.." "0,1" newline bitfld.word 0x2 9. "CAP_APWM,CAP/APWM operating mode select 0 | ECAP_MODULEECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers - Permits user.." "0,1" newline bitfld.word 0x2 8. "SWSYNC,Software-forced Counter (TSCTR) Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode the synchronization pulse can also be sourced from the CTR = PRD event. 0 |.." "0,1" newline bitfld.word 0x2 6.--7. "SYNCO_SEL,Sync-Out Select 0x0 | SWSYNCsync out signal is SWSYNC 0x1 | ECAP_CTR_PRD_TO_SYNCOUTSelect CTR = PRD event to be the sync-out signal 0x2 | ECAP_DISABLE_SYNC_OUTDisable sync out signal 0x3 |.." "0,1,2,3" newline bitfld.word 0x2 5. "SYNCI_EN,Counter (TSCTR) Sync-In select mode 0 | ECAP_DISABLE_SYNC_INDisable sync-in option 1 | ECAP_ENABLE_COUNTER_REGISTEREnable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event." "0,1" newline bitfld.word 0x2 4. "TSCTRSTOP,Time Stamp (TSCTR) Counter Stop (freeze) Control 0 | ECAP_TSCTR_STOPPEDTSCTR stopped 1 | ECAP_TSCTR_FREE_RUNNINGTSCTR free-running" "0,1" newline bitfld.word 0x2 3. "REARM,Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 0 | ECAP_NO_EFFECT_RETURNS_0Has no effect (reading always returns a 0) 1 | ECAP_ARMS_ONESHOTArms the one-shot sequence as follows: 1) Resets the.." "0,1" newline bitfld.word 0x2 1.--2. "STOP_WRAP,Stop value for one-shot mode. This is the number (between 1-4) of captures allowed to occur before the CAP(1-4) registers are frozen that is capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1-4) of the.." "0,1,2,3" newline bitfld.word 0x2 0. "CONT_ONESHT,Continuous or one-shot mode control (applicable only in capture mode) 0 | ECAP_OPP_CONTOperate in continuous mode 1 | ECAP_OPP_ONEOperate in one-Shot mode" "0,1" line.word 0x4 "CONTROLSS_ECAP9_ECEINT" bitfld.word 0x4 12. "MUNIT_2_ERROR_EVT2,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt" "0: Disable Monitoring unit 2 error event 2 interrupt,1: Enable Monitoring unit 2 error event 2 interrupt" newline bitfld.word 0x4 11. "MUNIT_2_ERROR_EVT1,Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt" "0: Disable Monitoring unit 2 error event 1 interrupt,1: Enable Monitoring unit 2 error event 1 interrupt" newline bitfld.word 0x4 10. "MUNIT_1_ERROR_EVT2,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt" "0: Disable Monitoring unit 1 error event 2 interrupt,1: Enable Monitoring unit 1 error event 2 interrupt" newline bitfld.word 0x4 9. "MUNIT_1_ERROR_EVT1,Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt" "0: Disable Monitoring unit 1 error event 1 interrupt,1: Enable Monitoring unit 1 error event 1 interrupt" newline bitfld.word 0x4 8. "HRERROR,High resolution error interrupt enable 0 | ECAP_DISAB_HRERROR_INTERRUPTDisable High Resolution Error as an Interrupt source 1 | ECAP_ENAB_HRERROR_INTERRUPTEnable High Resolution Error as an Interrupt source" "0,1" newline bitfld.word 0x4 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 | ECAP_DISAB_CE_INTERRUPTDisable Compare Equal as an Interrupt source 1 | ECAP_ENAB_CE_INTERRUPTEnable Compare Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 | ECAP_DISAB_PE_INTERRUPTDisable Period Equal as an Interrupt source 1 | ECAP_ENAB_PE_INTERRUPTEnable Period Equal as an Interrupt source" "0,1" newline bitfld.word 0x4 5. "CTROVF,Counter Overflow Interrupt Enable 0 | ECAP_DISAB_CO_INTERRUPTDisabled counter Overflow as an Interrupt source 1 | ECAP_ENAB_CO_INTERRUPTEnable counter Overflow as an Interrupt source" "0,1" newline bitfld.word 0x4 4. "CEVT4,Capture Event 4 Interrupt Enable 0 | ECAP_DISAB_CAP4_INTERRUPTDisable Capture Event 4 as an Interrupt source 1 | ECAP_ENAB_CAP4_INTERRUPTCapture Event 4 Interrupt Enable" "0,1" newline bitfld.word 0x4 3. "CEVT3,Capture Event 3 Interrupt Enable 0 | ECAP_DISAB_CAP3_INTERRUPTDisable Capture Event 3 as an Interrupt source 1 | ECAP_ENAB_CAP3_INTERRUPTEnable Capture Event 3 as an Interrupt source" "0,1" newline bitfld.word 0x4 2. "CEVT2,Capture Event 2 Interrupt Enable 0 | ECAP_DISAB_CAP2_INTERRUPTDisable Capture Event 2 as an Interrupt source 1 | ECAP_ENAB_CAP2_INTERRUPTEnable Capture Event 2 as an Interrupt source" "0,1" newline bitfld.word 0x4 1. "CEVT1,Capture Event 1 Interrupt Enable 0 | ECAP_DISAB_CAP1_INTERRUPTDisable Capture Event 1 as an Interrupt source 1 | ECAP_ENAB_CAP1_INTERRUPTEnable Capture Event 1 as an Interrupt source" "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "CONTROLSS_ECAP9_ECFLG" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 2" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Error event 2 Interrupt Flag from monitoring unit 1" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_HIGH_RESOLUTION_ERRORIndicates the High resolution Error occurred" "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Compare Equal Compare Status Flag. This flag is active only in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_COMPARE_REGIndicates the counter (TSCTR) reached the compare.." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Flag. This flag is only active in APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_PERIOD_VALUE_RESETIndicates the counter (TSCTR) reached the period register.." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_COUNTER_TRANSIndicates the counter (TSCTR) has made the transition from.." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Flag This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_4TH_EVENT_ECAPXIndicates the fourth event occurred at ECAPx pin" "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Flag. This flag is active only in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_3RD_EVENT_ECAPXIndicates the third event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_2ND_EVENT_ECAPXIndicates the second event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Flag. This flag is only active in CAP mode. Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_1ST_EVENT_ECAPXIndicates the first event occurred at ECAPx pin." "0,1" newline bitfld.word 0x0 0. "INT,Global Interrupt Status Flag Read0 | ECAP_INDICATE_NO_EVENTIndicates no event occurred Read1 | ECAP_INDICATE_INTERRUPTIndicates that an interrupt was generated." "0,1" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_ECAP9_ECCLR" bitfld.word 0x0 12. "MUNIT_2_ERROR_EVT2,Writing '1' clears MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 11. "MUNIT_2_ERROR_EVT1,Writing '1' clears MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 10. "MUNIT_1_ERROR_EVT2,Writing '1' clears MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x0 9. "MUNIT_1_ERROR_EVT1,Writing '1' clears MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x0 8. "HRERROR,High resolution error status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_HRERRORWriting a 1 clears the HRERROR flag." "0,1" newline bitfld.word 0x0 7. "CTR_CMP,Counter Equal Compare Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_CMPWriting a 1 clears the CTR=CMP flag." "0,1" newline bitfld.word 0x0 6. "CTR_PRD,Counter Equal Period Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 clears the CTR=PRD flag." "0,1" newline bitfld.word 0x0 5. "CTROVF,Counter Overflow Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CTROVFWriting a 1 clears the CTROVF flag." "0,1" newline bitfld.word 0x0 4. "CEVT4,Capture Event 4 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT4Writing a 1 clears the CEVT4 flag." "0,1" newline bitfld.word 0x0 3. "CEVT3,Capture Event 3 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT3Writing a 1 clears the CEVT3 flag." "0,1" newline bitfld.word 0x0 2. "CEVT2,Capture Event 2 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT2Writing a 1 clears the CEVT2 flag." "0,1" newline bitfld.word 0x0 1. "CEVT1,Capture Event 1 Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_CEVT1Writing a 1 clears the CEVT1 flag." "0,1" newline bitfld.word 0x0 0. "INT,ECAP Global Interrupt Status Clear 0 | ECAP_0_NO_EFFECTWriting a 0 has no effect. Always reads back a 0 1 | ECAP_1_CLEARS_INTWriting a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are.." "0,1" line.word 0x2 "CONTROLSS_ECAP9_ECFRC" bitfld.word 0x2 12. "MUNIT_2_ERROR_EVT2,Writing '1' sets MUNIT_2_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 11. "MUNIT_2_ERROR_EVT1,Writing '1' sets MUNIT_2_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 10. "MUNIT_1_ERROR_EVT2,Writing '1' sets MUNIT_1_ERROR_EVT2 interrupt flag" "0,1" newline bitfld.word 0x2 9. "MUNIT_1_ERROR_EVT1,Writing '1' sets MUNIT_1_ERROR_EVT1 interrupt flag" "0,1" newline bitfld.word 0x2 8. "HRERROR,High resolution error Force interrupt 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 7. "CTR_CMP,Force Counter Equal Compare Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTR_CMPWriting a 1 sets the CTR_CMP flag." "0,1" newline bitfld.word 0x2 6. "CTR_PRD,Force Counter Equal Period Interrupt. This event is only active in APWM mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_CLEARS_CTR_PRDWriting a 1 sets the CTR_PRD flag." "0,1" newline bitfld.word 0x2 5. "CTROVF,Force Counter Overflow 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CTROVFWriting a 1 to this bit sets the CTROVF flag." "0,1" newline bitfld.word 0x2 4. "CEVT4,Force Capture Event 4. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT4Writing a 1 sets the CEVT4 flag." "0,1" newline bitfld.word 0x2 3. "CEVT3,Force Capture Event 3. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT3Writing a 1 sets the CEVT3 flag." "0,1" newline bitfld.word 0x2 2. "CEVT2,Force Capture Event 2. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT2Writing a 1 sets the CEVT2 flag." "0,1" newline bitfld.word 0x2 1. "CEVT1,Force Capture Event 1. This event is only active in CAP mode. 0 | ECAP_NO_EFFECT_0No effect. Always reads back a 0. 1 | ECAP_1_SETS_CEVT1Sets the CEVT1 flag." "0,1" group.long 0x3C++0x7 line.long 0x0 "CONTROLSS_ECAP9_ECAPSYNCINSEL" hexmask.long.byte 0x0 0.--6. 1. "SEL,These bits determines the source of SYNCIN signal. 0x0 : Disabled using SOC tieoff. 0x7F : Refer to SOC spec for details." line.long 0x4 "CONTROLSS_ECAP9_HRCTL" bitfld.long 0x4 5. "CALIBCONT,Continuous mode Calibration Select Bit: 0 Continuous mode disabled. 1 Continuous mode enabled. Calibration automatically restarts at end of current calibration cycle." "0,1" newline rbitfld.long 0x4 4. "CALIBSTS,Calibration status Bit: 0 No active calibration cycle 1 Calibration cycle in progress" "0,1" newline bitfld.long 0x4 3. "CALIBSTART,Calibration start Bit: 0 No effect 1 Starts the calibration cycle" "0,1" newline bitfld.long 0x4 2. "PRDSEL,Calibration Period Match Select Bit: 0 Use SYSCLK Counter For Period Match (default at reset) 1 Reserved" "0,1" newline bitfld.long 0x4 1. "HRCLKE,High Resolution Clock Enable Bit: 0 High resolution clock disabled (default at reset) 1 High resolution clock enabled. The clock should be enabled before enabling the high res function via the HRE bit." "0,1" newline bitfld.long 0x4 0. "HRE,High Resolution Enable Bit: 0 High resolution mode disabled (default at reset) 1 High resolution mode enabled. Enabling this mode will connect the capture registers and edge event modes of the ECAP to be accessed by the High Res function. Note: The.." "0,1" group.long 0x48++0x3 line.long 0x0 "CONTROLSS_ECAP9_HRINTEN" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration Period Check status Interrupt Enable: 0 Disable Calibration Period Check interrupt status 1 Enable Calibration Period Check interrupt status" "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration done Interrupt Enable: 0 Disable Calibration done Interrupt 1 Enable Calibration done Interrupt" "0,1" rgroup.long 0x4C++0x3 line.long 0x0 "CONTROLSS_ECAP9_HRFLG" bitfld.long 0x0 2. "CALPRDCHKSTS,Calibration period check status Flag Bit: 1 Indicates that calibration ended before PRDCHK due to overflow on one of the counters. 0 Indicates no event occurred. Note: This bit remains latched until cleared by the user using the HRCLR.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Calibration Done Interrupt Flag Bit: 1 Indicates calibration cycle is completed 0 Indicates calibration cycle has not completed. Note: This bit remains latched until cleared by the user using the HRCLR [CALIBDONE] bit." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Global calibration Interrupt Status Flag: 1 Indicates that an interrupt was generated from CALIBDONE or CALPRDCHKSTS. 0 Indicates no interrupt generated." "0,1" group.long 0x50++0xB line.long 0x0 "CONTROLSS_ECAP9_HRCLR" bitfld.long 0x0 2. "CALPRDCHKSTS,Clear Calibration period check status Flag Bit: 1 Clears the CALPRDCHKSTS flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 1. "CALIBDONE,Clear Calibration Done Interrupt Flag Bit: 1 Clears the CALIBDONE interrupt flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set.." "0,1" newline bitfld.long 0x0 0. "CALIBINT,Clear Global calibration Interrupt Flag 1 Clears the Global interrupt flag and enables further interrupts to be generated if any of the event flags are set. 0 No effect." "0,1" line.long 0x4 "CONTROLSS_ECAP9_HRFRC" bitfld.long 0x4 2. "CALPRDCHKSTS,Force CALPRDCHKSTS flag: 0 No effect 1 Sets the CALPRDCHKSTS flag." "0,1" newline bitfld.long 0x4 1. "CALIBDONE,Force CALIBDONE flag: 0 No effect 1 Sets the CALIBDONE flag." "0,1" line.long 0x8 "CONTROLSS_ECAP9_HRCALPRD" hexmask.long 0x8 0.--31. 1. "PRD,Register to program calibration period. The period value is matched against HRSYSCLKCTR. On a match an interrupt is generated and the counter registers values are captured." rgroup.long 0x5C++0xF line.long 0x0 "CONTROLSS_ECAP9_HRSYSCLKCTR" hexmask.long 0x0 0.--31. 1. "HRSYSCLKCTR,Current SYSCLK counter value" line.long 0x4 "CONTROLSS_ECAP9_HRSYSCLKCAP" hexmask.long 0x4 0.--31. 1. "HRSYSCLKCAP,HRSYSCLKCTR is captures into this register at end of calibration cycle." line.long 0x8 "CONTROLSS_ECAP9_HRCLKCTR" hexmask.long 0x8 0.--31. 1. "HRCLKCTR,Current HRCLK counter value Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" line.long 0xC "CONTROLSS_ECAP9_HRCLKCAP" hexmask.long 0xC 0.--31. 1. "HRCLKCAP,HRCLKCTR is captures into this register at end of calibration cycle. Note: HRCLK is not synchronized to SYSCLK domain so reads may not be accurate" group.long 0x74++0x3 line.long 0x0 "CONTROLSS_ECAP9_HRDEBUGCTL" hexmask.long.byte 0x0 8.--11. 1. "OBSERVE_SRC_SEL,Select bits for selecting source for OBSERVE1 and OBSERVE2 registers 1000 HROUTH and HROUTL will read HR1OUT 1001 HROUTH and HROUTL will read HR2OUT 1010 HROUTH and HROUTL will read Capture Delayline 1 OBS1 1011 HROUTH and HROUTL will.." newline bitfld.long 0x0 4.--5. "CALIB_INPUT_SEL,Select bit for calibration input can be used to get fault coverage using these inputs 00 CAPIN is one of 128 inputs selected by INPUTSEL 01 CAPIN is connected to CAPIN_MEMMAP_SOURCE 10 CAPIN is internally generated signal waveform with.." "0,1,2,3" newline bitfld.long 0x0 2. "CAPIN_MMAP_SOURCE,Memory mapped CAPIN source Note : select CALIN source first it may happen that you may see interrupt if MMAP source is different from current value of CAPIN. This is debug feature hence no additional HW is necessary to prevent this." "0,1" newline bitfld.long 0x0 1. "DELAYRESETDLINE,Controls the reset delayline timing 0 reset is forced on next falling edge of HRCLK (1/2 cycle after capture) 1 reset is applied a cycle later (1 1/2 cycles after capture)" "0,1" newline bitfld.long 0x0 0. "DISABLEINVSEL,Disable INVSEL Logic: 0 State machine controls inversion on input signal 1 CAPIN signal propagated into delay line without inversion this means only rising edges can be measured" "0,1" rgroup.long 0x78++0x7 line.long 0x0 "CONTROLSS_ECAP9_HRDEBUGOBSERVE1" hexmask.long 0x0 0.--31. 1. "HROUTH,Reads raw output of HROUT capture delay line 1" line.long 0x4 "CONTROLSS_ECAP9_HRDEBUGOBSERVE2" hexmask.long 0x4 0.--31. 1. "HROUTL,Reads raw output of HROUT capture delay line 2" group.long 0x80++0x3 line.long 0x0 "CONTROLSS_ECAP9_MUNIT_COMMON_CTL" hexmask.long.byte 0x0 8.--14. 1. "GLDSTRBSEL,Global load strobe select to enable shadow to active loading 0x0 : Disabled with SOC level tieoff. 0x1 to 0x7F : Global load strobe from SOC level including ETPWM global load strobes." newline hexmask.long.byte 0x0 0.--6. 1. "TRIPSEL,Trip signal select to disable and enable signal monitoring automatically 0x0 : Disabled Trip signals does not affect signal monitoring achieved with SOC level tieoff. 0x1 to 0x7F : Signal monioring is disabled when selected signal is high and.." group.long 0xC0++0x7 line.long 0x0 "CONTROLSS_ECAP9_MUNIT_1_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 1 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_1_DEBUG_RANGE_MIN and MUNIT_1_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 1 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 1 is disabled 1 : Monitoring unit 1 is enabled" "0: Monitoring unit 1 is disabled,1: Monitoring unit 1 is enabled" line.long 0x4 "CONTROLSS_ECAP9_MUNIT_1_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_1_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0xD0++0xF line.long 0x0 "CONTROLSS_ECAP9_MUNIT_1_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP9_MUNIT_1_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP9_MUNIT_1_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP9_MUNIT_1_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0xE0++0x7 line.long 0x0 "CONTROLSS_ECAP9_MUNIT_1_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP9_MUNIT_1_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 1. Is updated when MUNIT_1_CTL.DEBUG_RANGE_EN is set to '1'" group.long 0x100++0x7 line.long 0x0 "CONTROLSS_ECAP9_MUNIT_2_CTL" hexmask.long.byte 0x0 8.--11. 1. "MON_SEL,Type of monitoring 0 : High Pulse width 1 : Low Pulse width 2 : Period width from Rise to Rise 3 : Period width from fall to fall 4 : Monitor rise edge 5 : Monitor fall edge 6-15 : Reserved (High Pulse width)" newline bitfld.long 0x0 1. "DEBUG_RANGE_EN,Debug mode enable. 0 : Debug mode is disabled. 1 : Debug mode of monitoring unit 2 is enabled to obtain the variation seen in the system for debug purpose. Range is captured in MUNIT_2_DEBUG_RANGE_MIN and MUNIT_2_DEBUG_RANGE_MAX registers.." "0: Debug mode is disabled,1: Debug mode of monitoring unit 2 is enabled to.." newline bitfld.long 0x0 0. "EN,0 : Monitoring unit 2 is disabled 1 : Monitoring unit 2 is enabled" "0: Monitoring unit 2 is disabled,1: Monitoring unit 2 is enabled" line.long 0x4 "CONTROLSS_ECAP9_MUNIT_2_SHADOW_CTL" bitfld.long 0x4 2. "LOADMODE,Load mode 0 : Active registers are loaded with shadow on next sync event 1 : Active registers are loaded with shadow on EPWMx.GLDLCSTRB event" "0: Active registers are loaded with shadow on next..,1: Active registers are loaded with shadow on EPWMx" newline bitfld.long 0x4 1. "SWSYNC,Copies Min and Max values from shadow to active registers immediately if MUNIT_2_SHADOW_CTL.SYNCI_EN is set." "0,1" newline bitfld.long 0x4 0. "SYNCI_EN,Shadow Enable 0 : Disabled 1 : Enabled" "0: Disabled,1: Enabled" group.long 0x110++0xF line.long 0x0 "CONTROLSS_ECAP9_MUNIT_2_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Minimum value for monitoring" line.long 0x4 "CONTROLSS_ECAP9_MUNIT_2_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Maximum value for monitoring" line.long 0x8 "CONTROLSS_ECAP9_MUNIT_2_MIN_SHADOW" hexmask.long 0x8 0.--31. 1. "MIN_VALUE_SHADOW,Shadow minimum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." line.long 0xC "CONTROLSS_ECAP9_MUNIT_2_MAX_SHADOW" hexmask.long 0xC 0.--31. 1. "MAX_VALUE_SHADOW,Shadow maximum value for monitoring. Shadow value is loaded to active register on Sync event or global load strobe." rgroup.long 0x120++0x7 line.long 0x0 "CONTROLSS_ECAP9_MUNIT_2_DEBUG_RANGE_MIN" hexmask.long 0x0 0.--31. 1. "MIN_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" line.long 0x4 "CONTROLSS_ECAP9_MUNIT_2_DEBUG_RANGE_MAX" hexmask.long 0x4 0.--31. 1. "MAX_VALUE,Observed Min value of check being enabled on minotoring unit 2. Is updated when MUNIT_2_CTL.DEBUG_RANGE_EN is set to '1'" tree.end tree.end tree "EPWM" tree "EPWM_G0" tree "G0_EPWM0" base ad:0x50000000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM0_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM0_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM0_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM0_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM0_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM0_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM0_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM0_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM0_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM0_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM0_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM0_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM0_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM0_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM0_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM0_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM0_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM0_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM0_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM0_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM0_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM0_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM0_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM0_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM0_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM0_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM0_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM0_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM0_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM0_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM0_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM0_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM0_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM0_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM0_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM0_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM0_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM0_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM0_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM0_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM0_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM0_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM0_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM0_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM0_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM0_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM0_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM0_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM0_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM0_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM0_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM0_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM0_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM0_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM0_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM0_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM0_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM0_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM0_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM0_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM0_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM0_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM0_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM0_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM0_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM0_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM0_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM0_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM0_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM0_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM0_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM0_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM0_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM0_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM0_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM0_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM0_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM0_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM0_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM0_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM0_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM0_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM0_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM0_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM0_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM0_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM0_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM0_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM0_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM0_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM0_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM0_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM0_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM0_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM0_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM0_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM0_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM0_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM0_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM0_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM0_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM0_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM0_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM0_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM0_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM0_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM0_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM0_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM0_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM0_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM0_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM0_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM0_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM0_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM0_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM0_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM0_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM0_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM0_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM0_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM0_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM0_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM0_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM0_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM0_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM0_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM0_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM0_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM0_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM0_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM0_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM0_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM0_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM0_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM0_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM0_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM1" base ad:0x50001000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM1_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM1_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM1_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM1_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM1_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM1_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM1_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM1_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM1_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM1_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM1_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM1_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM1_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM1_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM1_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM1_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM1_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM1_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM1_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM1_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM1_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM1_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM1_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM1_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM1_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM1_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM1_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM1_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM1_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM1_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM1_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM1_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM1_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM1_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM1_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM1_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM1_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM1_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM1_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM1_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM1_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM1_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM1_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM1_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM1_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM1_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM1_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM1_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM1_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM1_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM1_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM1_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM1_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM1_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM1_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM1_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM1_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM1_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM1_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM1_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM1_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM1_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM1_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM1_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM1_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM1_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM1_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM1_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM1_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM1_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM1_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM1_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM1_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM1_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM1_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM1_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM1_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM1_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM1_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM1_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM1_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM1_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM1_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM1_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM1_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM1_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM1_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM1_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM1_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM1_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM1_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM1_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM1_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM1_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM1_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM1_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM1_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM1_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM1_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM1_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM1_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM1_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM1_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM1_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM1_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM1_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM1_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM1_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM1_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM1_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM1_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM1_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM1_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM1_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM1_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM1_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM1_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM1_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM1_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM1_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM1_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM1_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM1_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM1_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM1_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM1_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM1_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM1_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM1_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM1_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM1_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM1_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM1_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM1_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM1_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM1_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM2" base ad:0x50002000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM2_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM2_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM2_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM2_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM2_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM2_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM2_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM2_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM2_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM2_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM2_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM2_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM2_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM2_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM2_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM2_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM2_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM2_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM2_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM2_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM2_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM2_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM2_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM2_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM2_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM2_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM2_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM2_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM2_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM2_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM2_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM2_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM2_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM2_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM2_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM2_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM2_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM2_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM2_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM2_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM2_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM2_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM2_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM2_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM2_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM2_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM2_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM2_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM2_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM2_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM2_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM2_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM2_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM2_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM2_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM2_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM2_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM2_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM2_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM2_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM2_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM2_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM2_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM2_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM2_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM2_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM2_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM2_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM2_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM2_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM2_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM2_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM2_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM2_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM2_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM2_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM2_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM2_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM2_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM2_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM2_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM2_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM2_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM2_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM2_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM2_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM2_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM2_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM2_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM2_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM2_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM2_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM2_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM2_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM2_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM2_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM2_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM2_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM2_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM2_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM2_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM2_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM2_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM2_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM2_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM2_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM2_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM2_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM2_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM2_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM2_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM2_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM2_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM2_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM2_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM2_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM2_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM2_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM2_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM2_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM2_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM2_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM2_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM2_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM2_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM2_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM2_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM2_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM2_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM2_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM2_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM2_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM2_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM2_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM2_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM2_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM3" base ad:0x50003000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM3_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM3_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM3_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM3_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM3_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM3_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM3_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM3_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM3_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM3_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM3_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM3_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM3_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM3_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM3_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM3_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM3_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM3_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM3_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM3_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM3_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM3_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM3_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM3_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM3_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM3_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM3_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM3_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM3_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM3_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM3_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM3_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM3_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM3_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM3_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM3_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM3_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM3_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM3_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM3_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM3_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM3_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM3_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM3_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM3_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM3_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM3_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM3_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM3_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM3_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM3_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM3_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM3_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM3_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM3_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM3_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM3_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM3_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM3_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM3_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM3_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM3_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM3_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM3_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM3_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM3_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM3_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM3_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM3_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM3_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM3_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM3_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM3_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM3_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM3_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM3_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM3_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM3_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM3_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM3_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM3_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM3_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM3_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM3_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM3_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM3_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM3_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM3_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM3_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM3_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM3_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM3_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM3_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM3_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM3_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM3_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM3_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM3_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM3_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM3_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM3_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM3_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM3_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM3_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM3_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM3_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM3_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM3_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM3_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM3_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM3_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM3_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM3_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM3_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM3_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM3_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM3_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM3_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM3_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM3_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM3_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM3_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM3_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM3_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM3_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM3_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM3_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM3_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM3_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM3_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM3_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM3_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM3_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM3_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM3_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM3_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM4" base ad:0x50004000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM4_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM4_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM4_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM4_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM4_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM4_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM4_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM4_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM4_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM4_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM4_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM4_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM4_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM4_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM4_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM4_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM4_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM4_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM4_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM4_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM4_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM4_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM4_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM4_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM4_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM4_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM4_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM4_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM4_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM4_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM4_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM4_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM4_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM4_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM4_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM4_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM4_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM4_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM4_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM4_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM4_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM4_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM4_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM4_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM4_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM4_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM4_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM4_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM4_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM4_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM4_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM4_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM4_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM4_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM4_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM4_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM4_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM4_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM4_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM4_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM4_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM4_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM4_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM4_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM4_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM4_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM4_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM4_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM4_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM4_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM4_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM4_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM4_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM4_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM4_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM4_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM4_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM4_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM4_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM4_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM4_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM4_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM4_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM4_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM4_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM4_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM4_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM4_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM4_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM4_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM4_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM4_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM4_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM4_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM4_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM4_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM4_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM4_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM4_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM4_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM4_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM4_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM4_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM4_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM4_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM4_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM4_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM4_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM4_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM4_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM4_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM4_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM4_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM4_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM4_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM4_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM4_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM4_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM4_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM4_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM4_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM4_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM4_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM4_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM4_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM4_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM4_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM4_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM4_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM4_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM4_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM4_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM4_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM4_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM4_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM4_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM5" base ad:0x50005000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM5_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM5_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM5_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM5_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM5_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM5_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM5_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM5_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM5_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM5_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM5_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM5_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM5_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM5_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM5_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM5_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM5_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM5_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM5_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM5_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM5_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM5_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM5_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM5_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM5_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM5_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM5_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM5_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM5_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM5_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM5_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM5_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM5_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM5_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM5_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM5_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM5_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM5_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM5_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM5_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM5_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM5_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM5_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM5_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM5_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM5_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM5_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM5_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM5_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM5_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM5_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM5_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM5_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM5_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM5_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM5_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM5_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM5_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM5_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM5_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM5_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM5_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM5_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM5_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM5_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM5_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM5_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM5_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM5_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM5_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM5_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM5_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM5_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM5_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM5_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM5_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM5_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM5_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM5_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM5_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM5_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM5_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM5_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM5_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM5_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM5_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM5_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM5_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM5_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM5_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM5_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM5_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM5_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM5_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM5_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM5_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM5_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM5_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM5_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM5_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM5_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM5_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM5_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM5_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM5_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM5_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM5_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM5_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM5_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM5_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM5_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM5_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM5_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM5_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM5_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM5_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM5_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM5_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM5_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM5_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM5_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM5_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM5_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM5_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM5_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM5_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM5_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM5_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM5_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM5_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM5_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM5_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM5_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM5_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM5_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM5_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM6" base ad:0x50006000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM6_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM6_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM6_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM6_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM6_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM6_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM6_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM6_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM6_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM6_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM6_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM6_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM6_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM6_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM6_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM6_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM6_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM6_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM6_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM6_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM6_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM6_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM6_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM6_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM6_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM6_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM6_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM6_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM6_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM6_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM6_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM6_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM6_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM6_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM6_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM6_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM6_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM6_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM6_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM6_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM6_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM6_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM6_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM6_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM6_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM6_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM6_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM6_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM6_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM6_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM6_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM6_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM6_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM6_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM6_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM6_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM6_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM6_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM6_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM6_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM6_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM6_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM6_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM6_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM6_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM6_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM6_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM6_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM6_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM6_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM6_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM6_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM6_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM6_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM6_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM6_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM6_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM6_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM6_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM6_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM6_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM6_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM6_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM6_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM6_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM6_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM6_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM6_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM6_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM6_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM6_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM6_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM6_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM6_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM6_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM6_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM6_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM6_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM6_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM6_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM6_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM6_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM6_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM6_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM6_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM6_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM6_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM6_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM6_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM6_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM6_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM6_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM6_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM6_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM6_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM6_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM6_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM6_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM6_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM6_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM6_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM6_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM6_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM6_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM6_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM6_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM6_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM6_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM6_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM6_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM6_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM6_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM6_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM6_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM6_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM6_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM7" base ad:0x50007000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM7_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM7_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM7_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM7_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM7_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM7_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM7_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM7_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM7_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM7_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM7_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM7_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM7_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM7_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM7_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM7_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM7_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM7_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM7_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM7_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM7_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM7_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM7_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM7_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM7_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM7_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM7_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM7_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM7_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM7_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM7_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM7_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM7_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM7_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM7_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM7_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM7_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM7_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM7_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM7_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM7_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM7_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM7_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM7_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM7_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM7_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM7_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM7_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM7_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM7_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM7_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM7_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM7_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM7_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM7_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM7_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM7_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM7_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM7_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM7_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM7_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM7_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM7_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM7_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM7_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM7_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM7_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM7_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM7_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM7_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM7_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM7_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM7_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM7_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM7_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM7_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM7_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM7_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM7_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM7_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM7_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM7_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM7_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM7_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM7_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM7_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM7_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM7_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM7_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM7_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM7_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM7_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM7_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM7_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM7_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM7_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM7_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM7_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM7_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM7_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM7_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM7_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM7_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM7_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM7_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM7_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM7_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM7_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM7_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM7_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM7_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM7_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM7_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM7_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM7_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM7_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM7_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM7_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM7_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM7_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM7_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM7_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM7_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM7_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM7_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM7_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM7_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM7_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM7_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM7_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM7_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM7_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM7_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM7_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM7_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM7_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM8" base ad:0x50008000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM8_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM8_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM8_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM8_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM8_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM8_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM8_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM8_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM8_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM8_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM8_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM8_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM8_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM8_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM8_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM8_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM8_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM8_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM8_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM8_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM8_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM8_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM8_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM8_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM8_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM8_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM8_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM8_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM8_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM8_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM8_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM8_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM8_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM8_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM8_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM8_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM8_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM8_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM8_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM8_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM8_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM8_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM8_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM8_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM8_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM8_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM8_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM8_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM8_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM8_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM8_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM8_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM8_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM8_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM8_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM8_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM8_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM8_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM8_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM8_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM8_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM8_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM8_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM8_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM8_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM8_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM8_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM8_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM8_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM8_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM8_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM8_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM8_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM8_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM8_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM8_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM8_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM8_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM8_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM8_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM8_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM8_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM8_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM8_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM8_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM8_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM8_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM8_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM8_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM8_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM8_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM8_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM8_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM8_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM8_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM8_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM8_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM8_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM8_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM8_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM8_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM8_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM8_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM8_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM8_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM8_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM8_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM8_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM8_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM8_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM8_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM8_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM8_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM8_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM8_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM8_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM8_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM8_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM8_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM8_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM8_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM8_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM8_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM8_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM8_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM8_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM8_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM8_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM8_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM8_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM8_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM8_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM8_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM8_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM8_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM8_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM9" base ad:0x50009000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM9_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM9_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM9_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM9_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM9_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM9_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM9_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM9_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM9_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM9_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM9_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM9_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM9_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM9_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM9_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM9_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM9_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM9_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM9_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM9_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM9_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM9_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM9_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM9_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM9_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM9_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM9_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM9_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM9_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM9_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM9_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM9_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM9_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM9_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM9_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM9_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM9_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM9_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM9_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM9_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM9_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM9_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM9_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM9_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM9_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM9_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM9_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM9_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM9_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM9_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM9_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM9_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM9_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM9_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM9_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM9_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM9_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM9_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM9_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM9_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM9_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM9_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM9_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM9_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM9_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM9_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM9_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM9_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM9_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM9_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM9_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM9_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM9_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM9_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM9_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM9_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM9_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM9_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM9_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM9_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM9_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM9_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM9_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM9_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM9_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM9_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM9_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM9_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM9_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM9_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM9_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM9_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM9_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM9_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM9_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM9_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM9_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM9_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM9_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM9_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM9_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM9_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM9_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM9_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM9_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM9_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM9_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM9_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM9_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM9_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM9_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM9_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM9_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM9_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM9_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM9_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM9_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM9_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM9_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM9_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM9_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM9_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM9_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM9_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM9_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM9_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM9_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM9_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM9_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM9_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM9_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM9_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM9_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM9_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM9_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM9_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM10" base ad:0x5000A000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM10_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM10_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM10_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM10_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM10_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM10_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM10_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM10_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM10_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM10_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM10_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM10_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM10_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM10_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM10_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM10_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM10_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM10_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM10_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM10_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM10_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM10_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM10_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM10_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM10_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM10_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM10_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM10_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM10_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM10_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM10_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM10_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM10_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM10_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM10_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM10_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM10_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM10_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM10_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM10_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM10_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM10_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM10_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM10_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM10_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM10_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM10_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM10_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM10_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM10_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM10_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM10_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM10_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM10_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM10_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM10_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM10_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM10_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM10_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM10_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM10_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM10_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM10_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM10_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM10_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM10_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM10_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM10_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM10_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM10_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM10_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM10_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM10_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM10_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM10_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM10_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM10_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM10_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM10_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM10_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM10_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM10_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM10_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM10_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM10_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM10_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM10_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM10_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM10_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM10_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM10_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM10_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM10_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM10_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM10_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM10_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM10_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM10_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM10_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM10_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM10_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM10_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM10_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM10_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM10_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM10_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM10_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM10_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM10_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM10_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM10_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM10_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM10_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM10_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM10_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM10_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM10_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM10_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM10_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM10_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM10_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM10_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM10_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM10_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM10_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM10_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM10_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM10_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM10_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM10_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM10_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM10_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM10_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM10_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM10_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM10_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM11" base ad:0x5000B000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM11_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM11_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM11_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM11_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM11_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM11_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM11_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM11_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM11_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM11_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM11_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM11_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM11_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM11_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM11_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM11_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM11_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM11_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM11_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM11_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM11_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM11_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM11_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM11_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM11_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM11_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM11_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM11_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM11_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM11_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM11_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM11_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM11_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM11_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM11_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM11_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM11_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM11_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM11_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM11_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM11_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM11_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM11_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM11_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM11_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM11_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM11_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM11_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM11_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM11_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM11_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM11_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM11_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM11_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM11_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM11_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM11_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM11_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM11_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM11_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM11_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM11_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM11_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM11_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM11_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM11_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM11_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM11_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM11_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM11_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM11_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM11_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM11_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM11_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM11_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM11_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM11_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM11_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM11_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM11_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM11_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM11_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM11_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM11_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM11_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM11_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM11_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM11_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM11_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM11_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM11_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM11_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM11_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM11_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM11_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM11_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM11_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM11_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM11_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM11_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM11_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM11_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM11_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM11_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM11_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM11_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM11_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM11_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM11_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM11_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM11_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM11_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM11_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM11_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM11_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM11_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM11_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM11_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM11_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM11_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM11_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM11_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM11_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM11_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM11_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM11_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM11_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM11_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM11_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM11_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM11_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM11_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM11_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM11_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM11_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM11_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM12" base ad:0x5000C000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM12_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM12_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM12_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM12_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM12_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM12_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM12_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM12_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM12_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM12_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM12_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM12_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM12_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM12_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM12_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM12_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM12_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM12_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM12_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM12_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM12_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM12_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM12_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM12_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM12_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM12_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM12_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM12_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM12_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM12_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM12_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM12_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM12_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM12_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM12_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM12_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM12_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM12_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM12_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM12_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM12_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM12_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM12_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM12_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM12_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM12_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM12_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM12_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM12_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM12_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM12_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM12_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM12_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM12_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM12_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM12_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM12_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM12_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM12_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM12_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM12_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM12_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM12_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM12_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM12_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM12_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM12_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM12_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM12_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM12_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM12_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM12_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM12_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM12_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM12_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM12_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM12_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM12_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM12_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM12_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM12_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM12_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM12_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM12_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM12_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM12_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM12_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM12_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM12_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM12_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM12_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM12_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM12_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM12_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM12_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM12_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM12_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM12_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM12_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM12_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM12_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM12_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM12_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM12_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM12_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM12_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM12_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM12_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM12_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM12_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM12_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM12_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM12_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM12_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM12_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM12_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM12_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM12_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM12_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM12_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM12_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM12_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM12_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM12_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM12_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM12_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM12_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM12_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM12_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM12_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM12_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM12_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM12_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM12_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM12_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM12_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM13" base ad:0x5000D000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM13_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM13_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM13_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM13_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM13_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM13_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM13_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM13_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM13_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM13_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM13_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM13_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM13_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM13_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM13_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM13_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM13_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM13_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM13_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM13_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM13_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM13_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM13_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM13_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM13_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM13_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM13_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM13_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM13_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM13_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM13_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM13_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM13_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM13_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM13_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM13_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM13_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM13_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM13_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM13_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM13_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM13_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM13_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM13_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM13_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM13_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM13_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM13_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM13_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM13_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM13_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM13_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM13_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM13_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM13_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM13_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM13_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM13_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM13_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM13_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM13_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM13_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM13_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM13_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM13_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM13_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM13_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM13_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM13_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM13_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM13_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM13_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM13_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM13_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM13_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM13_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM13_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM13_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM13_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM13_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM13_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM13_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM13_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM13_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM13_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM13_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM13_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM13_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM13_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM13_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM13_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM13_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM13_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM13_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM13_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM13_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM13_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM13_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM13_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM13_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM13_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM13_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM13_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM13_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM13_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM13_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM13_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM13_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM13_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM13_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM13_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM13_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM13_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM13_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM13_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM13_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM13_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM13_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM13_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM13_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM13_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM13_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM13_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM13_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM13_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM13_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM13_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM13_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM13_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM13_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM13_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM13_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM13_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM13_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM13_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM13_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM14" base ad:0x5000E000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM14_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM14_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM14_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM14_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM14_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM14_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM14_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM14_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM14_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM14_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM14_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM14_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM14_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM14_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM14_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM14_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM14_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM14_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM14_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM14_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM14_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM14_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM14_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM14_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM14_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM14_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM14_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM14_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM14_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM14_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM14_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM14_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM14_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM14_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM14_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM14_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM14_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM14_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM14_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM14_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM14_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM14_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM14_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM14_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM14_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM14_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM14_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM14_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM14_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM14_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM14_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM14_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM14_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM14_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM14_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM14_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM14_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM14_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM14_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM14_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM14_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM14_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM14_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM14_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM14_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM14_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM14_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM14_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM14_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM14_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM14_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM14_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM14_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM14_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM14_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM14_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM14_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM14_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM14_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM14_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM14_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM14_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM14_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM14_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM14_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM14_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM14_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM14_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM14_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM14_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM14_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM14_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM14_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM14_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM14_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM14_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM14_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM14_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM14_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM14_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM14_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM14_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM14_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM14_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM14_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM14_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM14_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM14_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM14_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM14_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM14_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM14_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM14_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM14_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM14_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM14_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM14_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM14_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM14_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM14_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM14_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM14_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM14_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM14_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM14_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM14_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM14_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM14_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM14_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM14_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM14_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM14_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM14_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM14_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM14_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM14_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM15" base ad:0x5000F000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM15_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM15_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM15_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM15_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM15_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM15_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM15_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM15_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM15_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM15_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM15_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM15_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM15_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM15_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM15_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM15_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM15_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM15_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM15_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM15_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM15_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM15_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM15_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM15_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM15_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM15_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM15_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM15_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM15_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM15_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM15_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM15_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM15_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM15_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM15_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM15_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM15_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM15_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM15_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM15_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM15_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM15_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM15_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM15_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM15_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM15_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM15_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM15_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM15_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM15_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM15_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM15_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM15_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM15_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM15_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM15_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM15_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM15_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM15_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM15_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM15_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM15_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM15_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM15_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM15_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM15_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM15_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM15_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM15_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM15_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM15_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM15_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM15_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM15_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM15_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM15_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM15_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM15_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM15_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM15_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM15_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM15_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM15_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM15_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM15_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM15_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM15_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM15_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM15_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM15_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM15_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM15_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM15_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM15_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM15_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM15_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM15_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM15_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM15_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM15_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM15_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM15_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM15_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM15_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM15_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM15_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM15_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM15_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM15_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM15_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM15_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM15_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM15_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM15_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM15_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM15_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM15_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM15_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM15_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM15_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM15_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM15_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM15_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM15_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM15_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM15_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM15_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM15_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM15_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM15_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM15_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM15_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM15_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM15_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM15_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM15_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM16" base ad:0x50010000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM16_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM16_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM16_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM16_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM16_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM16_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM16_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM16_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM16_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM16_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM16_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM16_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM16_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM16_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM16_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM16_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM16_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM16_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM16_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM16_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM16_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM16_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM16_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM16_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM16_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM16_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM16_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM16_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM16_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM16_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM16_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM16_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM16_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM16_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM16_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM16_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM16_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM16_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM16_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM16_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM16_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM16_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM16_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM16_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM16_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM16_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM16_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM16_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM16_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM16_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM16_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM16_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM16_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM16_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM16_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM16_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM16_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM16_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM16_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM16_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM16_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM16_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM16_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM16_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM16_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM16_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM16_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM16_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM16_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM16_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM16_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM16_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM16_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM16_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM16_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM16_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM16_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM16_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM16_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM16_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM16_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM16_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM16_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM16_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM16_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM16_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM16_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM16_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM16_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM16_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM16_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM16_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM16_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM16_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM16_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM16_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM16_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM16_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM16_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM16_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM16_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM16_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM16_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM16_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM16_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM16_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM16_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM16_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM16_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM16_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM16_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM16_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM16_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM16_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM16_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM16_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM16_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM16_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM16_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM16_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM16_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM16_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM16_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM16_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM16_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM16_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM16_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM16_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM16_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM16_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM16_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM16_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM16_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM16_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM16_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM16_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM17" base ad:0x50011000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM17_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM17_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM17_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM17_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM17_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM17_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM17_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM17_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM17_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM17_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM17_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM17_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM17_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM17_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM17_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM17_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM17_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM17_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM17_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM17_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM17_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM17_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM17_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM17_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM17_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM17_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM17_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM17_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM17_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM17_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM17_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM17_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM17_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM17_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM17_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM17_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM17_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM17_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM17_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM17_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM17_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM17_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM17_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM17_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM17_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM17_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM17_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM17_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM17_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM17_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM17_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM17_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM17_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM17_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM17_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM17_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM17_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM17_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM17_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM17_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM17_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM17_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM17_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM17_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM17_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM17_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM17_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM17_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM17_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM17_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM17_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM17_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM17_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM17_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM17_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM17_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM17_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM17_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM17_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM17_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM17_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM17_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM17_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM17_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM17_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM17_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM17_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM17_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM17_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM17_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM17_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM17_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM17_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM17_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM17_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM17_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM17_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM17_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM17_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM17_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM17_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM17_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM17_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM17_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM17_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM17_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM17_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM17_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM17_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM17_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM17_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM17_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM17_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM17_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM17_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM17_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM17_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM17_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM17_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM17_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM17_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM17_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM17_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM17_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM17_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM17_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM17_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM17_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM17_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM17_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM17_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM17_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM17_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM17_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM17_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM17_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM18" base ad:0x50012000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM18_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM18_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM18_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM18_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM18_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM18_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM18_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM18_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM18_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM18_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM18_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM18_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM18_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM18_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM18_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM18_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM18_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM18_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM18_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM18_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM18_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM18_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM18_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM18_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM18_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM18_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM18_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM18_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM18_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM18_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM18_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM18_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM18_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM18_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM18_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM18_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM18_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM18_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM18_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM18_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM18_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM18_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM18_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM18_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM18_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM18_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM18_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM18_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM18_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM18_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM18_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM18_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM18_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM18_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM18_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM18_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM18_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM18_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM18_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM18_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM18_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM18_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM18_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM18_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM18_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM18_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM18_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM18_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM18_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM18_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM18_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM18_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM18_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM18_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM18_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM18_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM18_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM18_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM18_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM18_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM18_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM18_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM18_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM18_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM18_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM18_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM18_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM18_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM18_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM18_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM18_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM18_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM18_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM18_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM18_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM18_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM18_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM18_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM18_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM18_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM18_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM18_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM18_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM18_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM18_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM18_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM18_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM18_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM18_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM18_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM18_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM18_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM18_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM18_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM18_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM18_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM18_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM18_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM18_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM18_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM18_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM18_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM18_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM18_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM18_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM18_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM18_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM18_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM18_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM18_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM18_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM18_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM18_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM18_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM18_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM18_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM19" base ad:0x50013000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM19_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM19_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM19_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM19_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM19_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM19_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM19_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM19_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM19_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM19_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM19_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM19_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM19_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM19_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM19_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM19_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM19_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM19_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM19_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM19_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM19_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM19_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM19_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM19_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM19_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM19_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM19_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM19_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM19_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM19_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM19_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM19_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM19_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM19_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM19_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM19_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM19_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM19_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM19_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM19_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM19_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM19_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM19_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM19_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM19_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM19_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM19_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM19_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM19_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM19_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM19_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM19_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM19_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM19_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM19_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM19_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM19_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM19_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM19_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM19_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM19_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM19_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM19_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM19_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM19_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM19_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM19_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM19_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM19_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM19_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM19_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM19_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM19_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM19_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM19_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM19_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM19_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM19_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM19_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM19_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM19_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM19_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM19_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM19_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM19_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM19_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM19_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM19_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM19_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM19_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM19_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM19_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM19_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM19_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM19_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM19_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM19_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM19_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM19_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM19_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM19_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM19_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM19_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM19_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM19_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM19_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM19_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM19_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM19_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM19_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM19_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM19_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM19_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM19_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM19_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM19_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM19_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM19_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM19_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM19_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM19_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM19_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM19_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM19_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM19_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM19_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM19_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM19_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM19_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM19_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM19_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM19_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM19_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM19_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM19_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM19_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM20" base ad:0x50014000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM20_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM20_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM20_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM20_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM20_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM20_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM20_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM20_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM20_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM20_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM20_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM20_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM20_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM20_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM20_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM20_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM20_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM20_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM20_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM20_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM20_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM20_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM20_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM20_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM20_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM20_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM20_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM20_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM20_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM20_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM20_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM20_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM20_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM20_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM20_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM20_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM20_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM20_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM20_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM20_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM20_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM20_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM20_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM20_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM20_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM20_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM20_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM20_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM20_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM20_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM20_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM20_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM20_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM20_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM20_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM20_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM20_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM20_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM20_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM20_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM20_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM20_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM20_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM20_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM20_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM20_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM20_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM20_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM20_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM20_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM20_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM20_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM20_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM20_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM20_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM20_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM20_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM20_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM20_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM20_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM20_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM20_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM20_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM20_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM20_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM20_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM20_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM20_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM20_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM20_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM20_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM20_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM20_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM20_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM20_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM20_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM20_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM20_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM20_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM20_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM20_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM20_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM20_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM20_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM20_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM20_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM20_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM20_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM20_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM20_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM20_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM20_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM20_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM20_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM20_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM20_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM20_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM20_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM20_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM20_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM20_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM20_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM20_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM20_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM20_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM20_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM20_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM20_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM20_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM20_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM20_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM20_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM20_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM20_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM20_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM20_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM21" base ad:0x50015000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM21_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM21_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM21_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM21_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM21_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM21_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM21_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM21_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM21_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM21_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM21_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM21_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM21_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM21_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM21_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM21_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM21_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM21_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM21_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM21_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM21_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM21_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM21_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM21_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM21_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM21_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM21_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM21_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM21_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM21_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM21_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM21_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM21_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM21_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM21_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM21_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM21_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM21_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM21_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM21_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM21_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM21_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM21_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM21_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM21_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM21_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM21_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM21_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM21_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM21_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM21_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM21_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM21_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM21_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM21_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM21_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM21_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM21_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM21_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM21_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM21_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM21_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM21_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM21_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM21_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM21_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM21_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM21_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM21_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM21_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM21_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM21_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM21_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM21_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM21_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM21_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM21_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM21_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM21_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM21_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM21_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM21_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM21_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM21_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM21_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM21_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM21_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM21_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM21_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM21_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM21_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM21_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM21_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM21_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM21_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM21_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM21_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM21_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM21_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM21_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM21_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM21_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM21_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM21_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM21_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM21_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM21_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM21_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM21_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM21_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM21_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM21_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM21_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM21_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM21_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM21_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM21_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM21_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM21_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM21_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM21_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM21_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM21_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM21_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM21_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM21_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM21_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM21_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM21_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM21_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM21_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM21_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM21_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM21_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM21_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM21_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM22" base ad:0x50016000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM22_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM22_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM22_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM22_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM22_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM22_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM22_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM22_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM22_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM22_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM22_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM22_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM22_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM22_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM22_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM22_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM22_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM22_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM22_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM22_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM22_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM22_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM22_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM22_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM22_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM22_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM22_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM22_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM22_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM22_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM22_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM22_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM22_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM22_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM22_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM22_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM22_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM22_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM22_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM22_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM22_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM22_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM22_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM22_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM22_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM22_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM22_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM22_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM22_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM22_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM22_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM22_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM22_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM22_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM22_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM22_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM22_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM22_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM22_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM22_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM22_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM22_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM22_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM22_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM22_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM22_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM22_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM22_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM22_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM22_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM22_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM22_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM22_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM22_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM22_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM22_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM22_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM22_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM22_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM22_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM22_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM22_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM22_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM22_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM22_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM22_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM22_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM22_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM22_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM22_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM22_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM22_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM22_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM22_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM22_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM22_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM22_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM22_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM22_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM22_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM22_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM22_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM22_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM22_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM22_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM22_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM22_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM22_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM22_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM22_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM22_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM22_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM22_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM22_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM22_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM22_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM22_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM22_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM22_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM22_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM22_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM22_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM22_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM22_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM22_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM22_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM22_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM22_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM22_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM22_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM22_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM22_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM22_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM22_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM22_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM22_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM23" base ad:0x50017000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM23_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM23_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM23_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM23_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM23_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM23_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM23_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM23_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM23_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM23_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM23_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM23_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM23_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM23_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM23_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM23_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM23_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM23_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM23_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM23_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM23_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM23_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM23_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM23_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM23_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM23_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM23_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM23_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM23_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM23_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM23_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM23_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM23_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM23_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM23_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM23_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM23_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM23_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM23_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM23_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM23_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM23_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM23_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM23_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM23_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM23_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM23_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM23_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM23_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM23_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM23_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM23_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM23_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM23_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM23_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM23_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM23_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM23_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM23_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM23_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM23_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM23_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM23_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM23_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM23_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM23_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM23_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM23_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM23_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM23_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM23_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM23_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM23_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM23_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM23_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM23_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM23_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM23_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM23_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM23_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM23_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM23_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM23_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM23_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM23_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM23_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM23_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM23_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM23_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM23_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM23_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM23_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM23_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM23_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM23_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM23_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM23_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM23_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM23_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM23_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM23_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM23_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM23_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM23_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM23_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM23_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM23_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM23_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM23_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM23_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM23_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM23_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM23_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM23_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM23_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM23_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM23_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM23_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM23_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM23_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM23_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM23_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM23_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM23_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM23_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM23_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM23_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM23_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM23_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM23_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM23_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM23_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM23_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM23_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM23_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM23_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM24" base ad:0x50018000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM24_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM24_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM24_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM24_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM24_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM24_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM24_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM24_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM24_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM24_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM24_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM24_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM24_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM24_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM24_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM24_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM24_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM24_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM24_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM24_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM24_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM24_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM24_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM24_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM24_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM24_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM24_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM24_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM24_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM24_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM24_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM24_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM24_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM24_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM24_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM24_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM24_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM24_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM24_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM24_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM24_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM24_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM24_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM24_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM24_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM24_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM24_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM24_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM24_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM24_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM24_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM24_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM24_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM24_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM24_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM24_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM24_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM24_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM24_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM24_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM24_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM24_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM24_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM24_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM24_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM24_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM24_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM24_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM24_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM24_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM24_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM24_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM24_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM24_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM24_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM24_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM24_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM24_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM24_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM24_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM24_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM24_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM24_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM24_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM24_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM24_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM24_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM24_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM24_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM24_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM24_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM24_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM24_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM24_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM24_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM24_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM24_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM24_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM24_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM24_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM24_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM24_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM24_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM24_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM24_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM24_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM24_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM24_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM24_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM24_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM24_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM24_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM24_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM24_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM24_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM24_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM24_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM24_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM24_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM24_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM24_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM24_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM24_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM24_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM24_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM24_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM24_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM24_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM24_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM24_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM24_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM24_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM24_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM24_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM24_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM24_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM25" base ad:0x50019000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM25_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM25_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM25_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM25_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM25_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM25_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM25_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM25_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM25_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM25_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM25_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM25_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM25_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM25_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM25_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM25_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM25_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM25_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM25_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM25_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM25_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM25_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM25_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM25_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM25_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM25_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM25_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM25_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM25_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM25_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM25_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM25_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM25_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM25_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM25_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM25_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM25_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM25_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM25_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM25_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM25_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM25_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM25_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM25_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM25_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM25_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM25_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM25_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM25_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM25_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM25_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM25_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM25_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM25_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM25_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM25_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM25_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM25_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM25_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM25_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM25_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM25_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM25_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM25_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM25_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM25_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM25_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM25_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM25_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM25_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM25_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM25_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM25_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM25_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM25_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM25_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM25_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM25_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM25_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM25_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM25_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM25_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM25_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM25_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM25_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM25_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM25_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM25_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM25_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM25_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM25_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM25_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM25_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM25_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM25_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM25_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM25_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM25_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM25_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM25_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM25_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM25_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM25_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM25_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM25_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM25_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM25_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM25_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM25_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM25_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM25_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM25_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM25_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM25_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM25_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM25_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM25_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM25_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM25_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM25_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM25_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM25_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM25_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM25_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM25_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM25_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM25_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM25_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM25_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM25_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM25_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM25_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM25_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM25_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM25_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM25_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM26" base ad:0x5001A000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM26_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM26_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM26_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM26_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM26_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM26_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM26_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM26_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM26_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM26_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM26_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM26_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM26_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM26_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM26_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM26_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM26_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM26_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM26_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM26_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM26_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM26_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM26_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM26_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM26_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM26_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM26_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM26_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM26_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM26_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM26_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM26_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM26_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM26_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM26_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM26_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM26_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM26_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM26_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM26_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM26_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM26_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM26_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM26_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM26_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM26_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM26_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM26_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM26_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM26_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM26_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM26_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM26_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM26_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM26_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM26_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM26_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM26_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM26_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM26_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM26_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM26_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM26_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM26_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM26_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM26_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM26_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM26_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM26_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM26_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM26_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM26_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM26_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM26_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM26_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM26_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM26_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM26_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM26_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM26_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM26_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM26_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM26_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM26_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM26_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM26_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM26_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM26_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM26_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM26_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM26_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM26_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM26_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM26_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM26_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM26_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM26_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM26_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM26_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM26_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM26_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM26_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM26_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM26_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM26_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM26_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM26_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM26_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM26_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM26_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM26_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM26_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM26_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM26_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM26_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM26_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM26_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM26_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM26_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM26_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM26_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM26_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM26_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM26_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM26_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM26_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM26_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM26_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM26_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM26_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM26_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM26_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM26_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM26_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM26_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM26_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM27" base ad:0x5001B000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM27_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM27_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM27_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM27_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM27_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM27_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM27_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM27_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM27_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM27_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM27_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM27_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM27_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM27_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM27_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM27_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM27_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM27_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM27_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM27_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM27_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM27_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM27_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM27_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM27_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM27_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM27_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM27_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM27_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM27_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM27_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM27_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM27_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM27_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM27_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM27_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM27_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM27_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM27_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM27_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM27_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM27_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM27_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM27_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM27_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM27_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM27_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM27_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM27_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM27_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM27_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM27_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM27_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM27_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM27_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM27_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM27_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM27_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM27_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM27_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM27_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM27_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM27_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM27_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM27_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM27_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM27_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM27_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM27_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM27_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM27_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM27_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM27_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM27_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM27_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM27_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM27_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM27_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM27_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM27_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM27_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM27_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM27_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM27_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM27_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM27_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM27_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM27_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM27_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM27_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM27_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM27_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM27_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM27_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM27_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM27_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM27_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM27_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM27_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM27_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM27_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM27_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM27_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM27_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM27_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM27_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM27_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM27_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM27_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM27_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM27_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM27_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM27_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM27_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM27_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM27_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM27_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM27_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM27_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM27_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM27_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM27_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM27_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM27_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM27_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM27_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM27_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM27_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM27_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM27_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM27_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM27_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM27_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM27_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM27_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM27_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM28" base ad:0x5001C000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM28_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM28_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM28_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM28_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM28_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM28_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM28_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM28_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM28_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM28_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM28_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM28_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM28_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM28_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM28_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM28_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM28_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM28_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM28_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM28_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM28_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM28_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM28_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM28_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM28_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM28_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM28_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM28_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM28_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM28_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM28_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM28_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM28_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM28_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM28_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM28_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM28_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM28_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM28_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM28_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM28_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM28_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM28_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM28_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM28_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM28_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM28_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM28_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM28_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM28_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM28_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM28_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM28_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM28_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM28_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM28_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM28_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM28_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM28_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM28_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM28_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM28_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM28_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM28_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM28_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM28_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM28_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM28_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM28_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM28_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM28_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM28_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM28_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM28_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM28_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM28_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM28_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM28_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM28_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM28_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM28_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM28_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM28_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM28_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM28_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM28_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM28_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM28_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM28_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM28_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM28_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM28_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM28_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM28_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM28_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM28_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM28_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM28_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM28_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM28_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM28_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM28_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM28_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM28_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM28_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM28_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM28_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM28_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM28_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM28_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM28_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM28_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM28_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM28_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM28_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM28_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM28_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM28_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM28_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM28_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM28_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM28_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM28_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM28_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM28_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM28_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM28_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM28_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM28_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM28_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM28_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM28_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM28_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM28_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM28_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM28_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM29" base ad:0x5001D000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM29_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM29_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM29_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM29_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM29_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM29_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM29_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM29_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM29_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM29_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM29_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM29_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM29_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM29_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM29_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM29_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM29_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM29_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM29_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM29_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM29_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM29_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM29_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM29_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM29_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM29_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM29_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM29_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM29_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM29_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM29_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM29_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM29_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM29_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM29_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM29_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM29_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM29_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM29_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM29_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM29_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM29_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM29_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM29_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM29_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM29_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM29_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM29_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM29_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM29_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM29_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM29_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM29_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM29_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM29_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM29_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM29_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM29_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM29_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM29_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM29_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM29_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM29_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM29_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM29_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM29_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM29_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM29_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM29_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM29_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM29_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM29_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM29_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM29_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM29_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM29_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM29_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM29_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM29_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM29_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM29_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM29_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM29_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM29_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM29_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM29_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM29_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM29_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM29_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM29_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM29_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM29_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM29_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM29_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM29_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM29_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM29_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM29_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM29_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM29_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM29_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM29_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM29_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM29_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM29_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM29_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM29_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM29_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM29_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM29_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM29_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM29_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM29_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM29_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM29_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM29_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM29_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM29_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM29_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM29_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM29_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM29_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM29_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM29_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM29_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM29_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM29_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM29_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM29_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM29_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM29_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM29_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM29_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM29_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM29_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM29_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM30" base ad:0x5001E000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM30_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM30_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM30_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM30_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM30_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM30_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM30_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM30_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM30_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM30_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM30_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM30_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM30_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM30_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM30_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM30_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM30_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM30_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM30_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM30_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM30_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM30_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM30_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM30_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM30_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM30_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM30_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM30_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM30_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM30_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM30_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM30_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM30_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM30_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM30_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM30_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM30_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM30_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM30_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM30_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM30_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM30_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM30_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM30_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM30_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM30_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM30_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM30_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM30_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM30_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM30_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM30_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM30_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM30_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM30_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM30_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM30_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM30_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM30_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM30_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM30_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM30_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM30_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM30_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM30_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM30_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM30_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM30_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM30_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM30_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM30_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM30_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM30_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM30_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM30_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM30_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM30_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM30_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM30_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM30_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM30_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM30_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM30_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM30_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM30_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM30_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM30_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM30_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM30_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM30_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM30_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM30_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM30_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM30_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM30_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM30_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM30_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM30_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM30_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM30_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM30_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM30_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM30_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM30_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM30_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM30_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM30_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM30_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM30_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM30_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM30_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM30_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM30_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM30_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM30_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM30_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM30_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM30_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM30_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM30_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM30_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM30_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM30_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM30_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM30_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM30_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM30_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM30_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM30_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM30_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM30_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM30_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM30_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM30_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM30_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM30_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G0_EPWM31" base ad:0x5001F000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM31_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G0_EPWM31_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G0_EPWM31_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G0_EPWM31_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G0_EPWM31_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G0_EPWM31_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G0_EPWM31_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G0_EPWM31_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G0_EPWM31_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G0_EPWM31_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM31_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G0_EPWM31_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G0_EPWM31_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G0_EPWM31_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G0_EPWM31_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM31_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G0_EPWM31_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G0_EPWM31_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G0_EPWM31_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G0_EPWM31_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G0_EPWM31_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G0_EPWM31_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G0_EPWM31_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G0_EPWM31_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G0_EPWM31_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G0_EPWM31_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G0_EPWM31_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G0_EPWM31_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G0_EPWM31_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G0_EPWM31_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G0_EPWM31_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G0_EPWM31_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G0_EPWM31_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G0_EPWM31_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G0_EPWM31_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G0_EPWM31_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G0_EPWM31_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G0_EPWM31_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM31_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G0_EPWM31_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G0_EPWM31_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G0_EPWM31_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G0_EPWM31_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G0_EPWM31_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G0_EPWM31_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G0_EPWM31_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G0_EPWM31_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM31_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G0_EPWM31_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G0_EPWM31_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G0_EPWM31_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G0_EPWM31_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G0_EPWM31_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G0_EPWM31_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G0_EPWM31_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G0_EPWM31_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G0_EPWM31_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G0_EPWM31_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G0_EPWM31_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G0_EPWM31_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G0_EPWM31_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G0_EPWM31_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G0_EPWM31_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G0_EPWM31_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G0_EPWM31_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM31_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G0_EPWM31_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G0_EPWM31_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G0_EPWM31_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G0_EPWM31_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G0_EPWM31_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G0_EPWM31_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G0_EPWM31_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G0_EPWM31_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G0_EPWM31_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G0_EPWM31_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM31_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM31_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM31_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM31_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM31_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM31_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM31_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM31_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G0_EPWM31_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G0_EPWM31_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM31_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM31_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM31_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM31_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM31_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM31_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM31_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM31_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM31_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM31_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM31_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G0_EPWM31_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM31_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM31_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM31_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM31_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM31_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM31_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM31_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM31_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G0_EPWM31_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM31_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G0_EPWM31_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G0_EPWM31_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G0_EPWM31_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G0_EPWM31_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G0_EPWM31_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G0_EPWM31_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G0_EPWM31_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G0_EPWM31_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G0_EPWM31_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G0_EPWM31_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G0_EPWM31_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G0_EPWM31_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G0_EPWM31_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G0_EPWM31_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G0_EPWM31_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G0_EPWM31_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G0_EPWM31_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G0_EPWM31_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G0_EPWM31_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G0_EPWM31_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G0_EPWM31_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G0_EPWM31_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G0_EPWM31_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G0_EPWM31_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G0_EPWM31_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G0_EPWM31_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G0_EPWM31_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G0_EPWM31_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM_G1" tree "G1_EPWM0" base ad:0x50040000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM0_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM0_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM0_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM0_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM0_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM0_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM0_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM0_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM0_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM0_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM0_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM0_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM0_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM0_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM0_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM0_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM0_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM0_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM0_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM0_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM0_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM0_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM0_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM0_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM0_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM0_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM0_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM0_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM0_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM0_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM0_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM0_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM0_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM0_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM0_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM0_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM0_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM0_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM0_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM0_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM0_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM0_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM0_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM0_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM0_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM0_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM0_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM0_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM0_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM0_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM0_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM0_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM0_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM0_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM0_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM0_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM0_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM0_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM0_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM0_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM0_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM0_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM0_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM0_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM0_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM0_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM0_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM0_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM0_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM0_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM0_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM0_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM0_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM0_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM0_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM0_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM0_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM0_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM0_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM0_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM0_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM0_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM0_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM0_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM0_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM0_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM0_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM0_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM0_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM0_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM0_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM0_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM0_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM0_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM0_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM0_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM0_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM0_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM0_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM0_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM0_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM0_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM0_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM0_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM0_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM0_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM0_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM0_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM0_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM0_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM0_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM0_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM0_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM0_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM0_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM0_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM0_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM0_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM0_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM0_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM0_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM0_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM0_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM0_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM0_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM0_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM0_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM0_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM0_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM0_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM0_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM0_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM0_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM0_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM0_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM0_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM1" base ad:0x50041000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM1_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM1_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM1_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM1_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM1_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM1_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM1_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM1_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM1_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM1_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM1_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM1_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM1_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM1_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM1_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM1_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM1_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM1_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM1_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM1_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM1_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM1_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM1_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM1_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM1_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM1_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM1_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM1_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM1_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM1_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM1_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM1_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM1_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM1_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM1_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM1_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM1_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM1_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM1_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM1_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM1_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM1_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM1_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM1_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM1_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM1_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM1_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM1_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM1_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM1_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM1_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM1_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM1_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM1_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM1_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM1_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM1_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM1_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM1_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM1_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM1_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM1_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM1_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM1_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM1_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM1_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM1_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM1_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM1_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM1_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM1_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM1_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM1_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM1_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM1_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM1_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM1_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM1_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM1_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM1_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM1_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM1_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM1_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM1_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM1_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM1_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM1_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM1_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM1_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM1_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM1_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM1_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM1_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM1_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM1_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM1_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM1_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM1_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM1_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM1_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM1_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM1_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM1_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM1_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM1_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM1_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM1_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM1_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM1_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM1_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM1_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM1_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM1_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM1_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM1_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM1_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM1_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM1_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM1_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM1_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM1_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM1_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM1_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM1_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM1_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM1_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM1_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM1_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM1_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM1_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM1_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM1_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM1_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM1_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM1_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM1_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM2" base ad:0x50042000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM2_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM2_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM2_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM2_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM2_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM2_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM2_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM2_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM2_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM2_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM2_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM2_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM2_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM2_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM2_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM2_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM2_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM2_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM2_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM2_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM2_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM2_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM2_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM2_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM2_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM2_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM2_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM2_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM2_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM2_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM2_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM2_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM2_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM2_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM2_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM2_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM2_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM2_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM2_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM2_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM2_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM2_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM2_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM2_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM2_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM2_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM2_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM2_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM2_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM2_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM2_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM2_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM2_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM2_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM2_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM2_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM2_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM2_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM2_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM2_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM2_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM2_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM2_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM2_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM2_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM2_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM2_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM2_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM2_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM2_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM2_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM2_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM2_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM2_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM2_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM2_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM2_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM2_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM2_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM2_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM2_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM2_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM2_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM2_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM2_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM2_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM2_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM2_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM2_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM2_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM2_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM2_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM2_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM2_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM2_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM2_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM2_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM2_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM2_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM2_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM2_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM2_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM2_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM2_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM2_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM2_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM2_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM2_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM2_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM2_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM2_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM2_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM2_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM2_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM2_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM2_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM2_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM2_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM2_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM2_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM2_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM2_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM2_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM2_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM2_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM2_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM2_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM2_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM2_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM2_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM2_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM2_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM2_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM2_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM2_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM2_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM3" base ad:0x50043000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM3_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM3_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM3_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM3_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM3_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM3_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM3_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM3_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM3_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM3_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM3_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM3_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM3_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM3_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM3_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM3_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM3_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM3_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM3_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM3_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM3_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM3_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM3_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM3_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM3_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM3_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM3_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM3_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM3_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM3_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM3_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM3_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM3_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM3_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM3_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM3_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM3_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM3_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM3_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM3_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM3_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM3_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM3_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM3_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM3_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM3_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM3_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM3_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM3_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM3_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM3_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM3_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM3_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM3_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM3_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM3_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM3_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM3_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM3_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM3_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM3_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM3_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM3_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM3_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM3_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM3_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM3_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM3_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM3_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM3_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM3_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM3_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM3_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM3_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM3_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM3_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM3_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM3_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM3_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM3_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM3_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM3_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM3_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM3_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM3_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM3_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM3_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM3_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM3_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM3_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM3_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM3_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM3_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM3_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM3_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM3_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM3_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM3_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM3_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM3_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM3_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM3_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM3_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM3_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM3_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM3_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM3_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM3_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM3_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM3_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM3_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM3_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM3_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM3_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM3_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM3_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM3_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM3_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM3_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM3_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM3_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM3_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM3_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM3_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM3_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM3_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM3_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM3_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM3_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM3_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM3_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM3_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM3_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM3_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM3_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM3_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM4" base ad:0x50044000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM4_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM4_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM4_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM4_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM4_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM4_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM4_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM4_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM4_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM4_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM4_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM4_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM4_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM4_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM4_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM4_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM4_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM4_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM4_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM4_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM4_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM4_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM4_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM4_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM4_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM4_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM4_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM4_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM4_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM4_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM4_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM4_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM4_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM4_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM4_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM4_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM4_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM4_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM4_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM4_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM4_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM4_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM4_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM4_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM4_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM4_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM4_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM4_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM4_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM4_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM4_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM4_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM4_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM4_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM4_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM4_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM4_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM4_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM4_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM4_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM4_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM4_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM4_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM4_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM4_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM4_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM4_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM4_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM4_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM4_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM4_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM4_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM4_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM4_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM4_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM4_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM4_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM4_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM4_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM4_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM4_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM4_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM4_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM4_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM4_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM4_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM4_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM4_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM4_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM4_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM4_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM4_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM4_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM4_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM4_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM4_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM4_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM4_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM4_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM4_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM4_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM4_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM4_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM4_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM4_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM4_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM4_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM4_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM4_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM4_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM4_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM4_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM4_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM4_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM4_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM4_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM4_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM4_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM4_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM4_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM4_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM4_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM4_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM4_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM4_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM4_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM4_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM4_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM4_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM4_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM4_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM4_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM4_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM4_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM4_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM4_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM5" base ad:0x50045000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM5_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM5_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM5_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM5_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM5_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM5_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM5_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM5_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM5_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM5_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM5_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM5_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM5_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM5_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM5_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM5_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM5_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM5_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM5_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM5_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM5_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM5_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM5_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM5_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM5_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM5_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM5_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM5_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM5_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM5_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM5_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM5_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM5_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM5_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM5_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM5_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM5_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM5_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM5_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM5_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM5_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM5_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM5_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM5_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM5_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM5_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM5_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM5_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM5_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM5_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM5_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM5_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM5_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM5_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM5_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM5_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM5_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM5_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM5_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM5_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM5_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM5_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM5_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM5_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM5_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM5_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM5_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM5_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM5_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM5_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM5_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM5_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM5_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM5_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM5_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM5_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM5_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM5_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM5_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM5_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM5_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM5_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM5_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM5_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM5_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM5_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM5_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM5_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM5_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM5_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM5_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM5_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM5_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM5_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM5_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM5_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM5_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM5_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM5_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM5_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM5_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM5_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM5_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM5_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM5_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM5_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM5_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM5_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM5_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM5_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM5_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM5_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM5_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM5_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM5_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM5_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM5_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM5_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM5_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM5_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM5_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM5_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM5_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM5_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM5_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM5_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM5_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM5_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM5_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM5_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM5_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM5_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM5_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM5_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM5_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM5_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM6" base ad:0x50046000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM6_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM6_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM6_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM6_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM6_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM6_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM6_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM6_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM6_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM6_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM6_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM6_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM6_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM6_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM6_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM6_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM6_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM6_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM6_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM6_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM6_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM6_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM6_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM6_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM6_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM6_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM6_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM6_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM6_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM6_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM6_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM6_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM6_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM6_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM6_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM6_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM6_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM6_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM6_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM6_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM6_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM6_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM6_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM6_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM6_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM6_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM6_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM6_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM6_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM6_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM6_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM6_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM6_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM6_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM6_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM6_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM6_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM6_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM6_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM6_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM6_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM6_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM6_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM6_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM6_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM6_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM6_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM6_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM6_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM6_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM6_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM6_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM6_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM6_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM6_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM6_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM6_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM6_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM6_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM6_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM6_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM6_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM6_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM6_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM6_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM6_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM6_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM6_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM6_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM6_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM6_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM6_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM6_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM6_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM6_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM6_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM6_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM6_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM6_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM6_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM6_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM6_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM6_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM6_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM6_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM6_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM6_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM6_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM6_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM6_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM6_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM6_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM6_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM6_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM6_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM6_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM6_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM6_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM6_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM6_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM6_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM6_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM6_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM6_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM6_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM6_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM6_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM6_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM6_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM6_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM6_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM6_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM6_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM6_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM6_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM6_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM7" base ad:0x50047000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM7_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM7_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM7_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM7_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM7_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM7_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM7_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM7_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM7_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM7_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM7_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM7_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM7_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM7_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM7_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM7_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM7_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM7_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM7_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM7_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM7_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM7_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM7_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM7_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM7_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM7_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM7_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM7_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM7_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM7_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM7_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM7_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM7_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM7_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM7_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM7_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM7_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM7_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM7_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM7_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM7_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM7_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM7_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM7_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM7_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM7_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM7_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM7_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM7_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM7_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM7_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM7_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM7_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM7_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM7_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM7_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM7_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM7_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM7_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM7_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM7_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM7_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM7_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM7_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM7_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM7_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM7_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM7_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM7_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM7_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM7_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM7_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM7_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM7_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM7_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM7_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM7_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM7_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM7_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM7_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM7_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM7_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM7_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM7_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM7_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM7_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM7_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM7_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM7_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM7_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM7_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM7_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM7_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM7_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM7_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM7_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM7_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM7_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM7_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM7_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM7_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM7_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM7_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM7_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM7_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM7_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM7_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM7_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM7_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM7_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM7_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM7_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM7_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM7_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM7_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM7_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM7_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM7_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM7_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM7_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM7_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM7_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM7_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM7_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM7_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM7_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM7_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM7_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM7_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM7_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM7_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM7_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM7_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM7_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM7_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM7_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM8" base ad:0x50048000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM8_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM8_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM8_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM8_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM8_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM8_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM8_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM8_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM8_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM8_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM8_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM8_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM8_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM8_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM8_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM8_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM8_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM8_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM8_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM8_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM8_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM8_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM8_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM8_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM8_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM8_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM8_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM8_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM8_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM8_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM8_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM8_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM8_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM8_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM8_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM8_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM8_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM8_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM8_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM8_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM8_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM8_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM8_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM8_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM8_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM8_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM8_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM8_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM8_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM8_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM8_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM8_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM8_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM8_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM8_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM8_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM8_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM8_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM8_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM8_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM8_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM8_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM8_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM8_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM8_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM8_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM8_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM8_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM8_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM8_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM8_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM8_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM8_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM8_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM8_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM8_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM8_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM8_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM8_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM8_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM8_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM8_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM8_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM8_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM8_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM8_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM8_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM8_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM8_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM8_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM8_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM8_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM8_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM8_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM8_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM8_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM8_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM8_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM8_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM8_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM8_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM8_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM8_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM8_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM8_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM8_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM8_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM8_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM8_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM8_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM8_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM8_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM8_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM8_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM8_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM8_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM8_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM8_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM8_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM8_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM8_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM8_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM8_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM8_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM8_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM8_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM8_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM8_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM8_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM8_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM8_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM8_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM8_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM8_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM8_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM8_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM9" base ad:0x50049000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM9_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM9_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM9_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM9_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM9_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM9_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM9_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM9_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM9_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM9_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM9_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM9_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM9_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM9_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM9_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM9_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM9_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM9_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM9_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM9_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM9_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM9_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM9_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM9_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM9_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM9_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM9_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM9_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM9_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM9_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM9_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM9_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM9_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM9_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM9_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM9_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM9_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM9_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM9_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM9_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM9_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM9_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM9_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM9_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM9_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM9_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM9_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM9_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM9_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM9_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM9_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM9_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM9_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM9_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM9_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM9_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM9_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM9_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM9_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM9_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM9_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM9_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM9_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM9_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM9_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM9_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM9_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM9_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM9_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM9_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM9_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM9_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM9_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM9_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM9_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM9_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM9_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM9_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM9_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM9_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM9_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM9_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM9_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM9_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM9_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM9_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM9_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM9_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM9_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM9_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM9_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM9_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM9_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM9_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM9_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM9_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM9_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM9_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM9_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM9_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM9_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM9_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM9_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM9_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM9_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM9_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM9_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM9_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM9_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM9_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM9_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM9_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM9_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM9_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM9_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM9_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM9_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM9_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM9_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM9_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM9_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM9_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM9_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM9_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM9_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM9_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM9_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM9_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM9_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM9_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM9_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM9_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM9_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM9_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM9_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM9_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM10" base ad:0x5004A000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM10_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM10_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM10_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM10_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM10_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM10_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM10_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM10_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM10_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM10_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM10_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM10_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM10_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM10_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM10_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM10_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM10_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM10_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM10_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM10_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM10_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM10_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM10_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM10_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM10_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM10_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM10_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM10_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM10_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM10_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM10_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM10_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM10_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM10_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM10_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM10_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM10_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM10_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM10_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM10_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM10_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM10_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM10_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM10_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM10_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM10_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM10_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM10_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM10_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM10_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM10_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM10_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM10_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM10_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM10_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM10_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM10_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM10_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM10_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM10_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM10_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM10_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM10_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM10_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM10_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM10_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM10_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM10_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM10_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM10_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM10_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM10_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM10_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM10_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM10_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM10_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM10_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM10_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM10_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM10_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM10_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM10_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM10_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM10_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM10_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM10_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM10_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM10_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM10_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM10_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM10_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM10_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM10_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM10_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM10_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM10_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM10_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM10_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM10_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM10_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM10_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM10_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM10_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM10_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM10_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM10_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM10_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM10_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM10_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM10_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM10_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM10_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM10_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM10_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM10_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM10_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM10_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM10_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM10_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM10_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM10_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM10_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM10_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM10_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM10_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM10_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM10_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM10_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM10_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM10_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM10_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM10_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM10_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM10_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM10_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM10_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM11" base ad:0x5004B000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM11_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM11_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM11_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM11_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM11_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM11_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM11_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM11_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM11_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM11_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM11_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM11_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM11_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM11_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM11_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM11_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM11_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM11_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM11_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM11_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM11_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM11_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM11_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM11_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM11_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM11_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM11_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM11_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM11_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM11_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM11_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM11_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM11_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM11_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM11_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM11_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM11_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM11_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM11_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM11_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM11_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM11_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM11_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM11_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM11_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM11_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM11_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM11_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM11_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM11_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM11_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM11_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM11_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM11_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM11_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM11_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM11_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM11_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM11_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM11_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM11_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM11_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM11_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM11_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM11_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM11_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM11_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM11_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM11_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM11_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM11_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM11_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM11_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM11_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM11_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM11_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM11_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM11_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM11_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM11_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM11_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM11_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM11_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM11_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM11_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM11_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM11_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM11_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM11_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM11_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM11_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM11_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM11_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM11_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM11_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM11_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM11_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM11_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM11_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM11_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM11_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM11_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM11_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM11_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM11_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM11_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM11_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM11_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM11_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM11_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM11_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM11_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM11_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM11_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM11_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM11_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM11_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM11_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM11_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM11_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM11_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM11_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM11_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM11_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM11_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM11_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM11_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM11_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM11_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM11_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM11_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM11_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM11_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM11_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM11_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM11_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM12" base ad:0x5004C000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM12_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM12_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM12_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM12_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM12_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM12_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM12_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM12_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM12_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM12_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM12_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM12_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM12_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM12_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM12_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM12_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM12_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM12_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM12_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM12_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM12_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM12_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM12_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM12_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM12_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM12_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM12_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM12_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM12_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM12_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM12_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM12_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM12_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM12_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM12_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM12_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM12_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM12_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM12_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM12_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM12_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM12_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM12_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM12_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM12_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM12_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM12_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM12_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM12_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM12_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM12_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM12_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM12_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM12_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM12_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM12_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM12_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM12_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM12_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM12_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM12_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM12_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM12_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM12_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM12_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM12_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM12_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM12_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM12_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM12_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM12_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM12_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM12_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM12_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM12_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM12_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM12_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM12_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM12_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM12_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM12_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM12_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM12_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM12_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM12_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM12_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM12_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM12_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM12_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM12_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM12_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM12_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM12_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM12_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM12_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM12_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM12_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM12_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM12_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM12_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM12_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM12_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM12_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM12_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM12_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM12_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM12_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM12_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM12_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM12_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM12_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM12_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM12_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM12_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM12_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM12_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM12_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM12_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM12_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM12_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM12_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM12_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM12_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM12_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM12_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM12_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM12_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM12_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM12_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM12_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM12_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM12_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM12_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM12_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM12_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM12_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM13" base ad:0x5004D000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM13_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM13_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM13_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM13_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM13_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM13_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM13_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM13_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM13_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM13_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM13_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM13_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM13_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM13_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM13_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM13_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM13_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM13_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM13_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM13_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM13_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM13_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM13_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM13_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM13_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM13_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM13_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM13_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM13_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM13_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM13_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM13_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM13_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM13_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM13_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM13_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM13_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM13_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM13_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM13_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM13_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM13_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM13_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM13_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM13_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM13_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM13_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM13_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM13_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM13_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM13_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM13_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM13_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM13_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM13_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM13_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM13_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM13_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM13_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM13_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM13_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM13_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM13_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM13_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM13_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM13_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM13_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM13_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM13_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM13_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM13_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM13_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM13_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM13_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM13_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM13_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM13_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM13_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM13_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM13_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM13_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM13_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM13_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM13_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM13_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM13_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM13_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM13_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM13_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM13_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM13_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM13_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM13_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM13_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM13_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM13_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM13_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM13_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM13_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM13_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM13_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM13_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM13_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM13_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM13_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM13_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM13_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM13_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM13_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM13_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM13_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM13_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM13_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM13_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM13_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM13_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM13_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM13_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM13_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM13_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM13_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM13_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM13_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM13_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM13_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM13_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM13_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM13_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM13_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM13_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM13_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM13_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM13_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM13_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM13_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM13_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM14" base ad:0x5004E000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM14_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM14_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM14_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM14_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM14_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM14_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM14_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM14_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM14_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM14_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM14_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM14_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM14_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM14_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM14_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM14_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM14_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM14_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM14_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM14_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM14_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM14_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM14_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM14_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM14_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM14_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM14_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM14_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM14_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM14_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM14_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM14_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM14_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM14_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM14_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM14_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM14_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM14_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM14_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM14_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM14_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM14_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM14_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM14_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM14_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM14_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM14_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM14_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM14_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM14_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM14_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM14_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM14_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM14_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM14_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM14_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM14_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM14_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM14_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM14_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM14_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM14_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM14_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM14_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM14_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM14_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM14_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM14_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM14_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM14_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM14_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM14_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM14_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM14_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM14_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM14_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM14_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM14_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM14_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM14_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM14_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM14_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM14_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM14_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM14_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM14_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM14_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM14_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM14_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM14_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM14_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM14_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM14_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM14_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM14_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM14_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM14_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM14_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM14_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM14_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM14_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM14_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM14_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM14_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM14_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM14_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM14_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM14_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM14_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM14_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM14_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM14_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM14_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM14_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM14_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM14_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM14_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM14_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM14_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM14_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM14_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM14_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM14_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM14_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM14_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM14_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM14_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM14_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM14_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM14_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM14_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM14_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM14_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM14_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM14_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM14_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM15" base ad:0x5004F000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM15_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM15_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM15_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM15_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM15_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM15_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM15_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM15_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM15_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM15_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM15_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM15_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM15_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM15_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM15_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM15_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM15_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM15_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM15_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM15_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM15_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM15_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM15_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM15_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM15_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM15_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM15_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM15_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM15_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM15_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM15_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM15_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM15_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM15_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM15_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM15_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM15_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM15_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM15_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM15_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM15_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM15_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM15_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM15_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM15_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM15_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM15_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM15_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM15_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM15_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM15_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM15_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM15_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM15_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM15_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM15_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM15_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM15_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM15_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM15_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM15_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM15_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM15_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM15_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM15_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM15_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM15_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM15_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM15_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM15_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM15_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM15_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM15_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM15_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM15_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM15_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM15_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM15_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM15_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM15_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM15_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM15_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM15_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM15_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM15_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM15_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM15_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM15_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM15_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM15_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM15_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM15_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM15_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM15_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM15_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM15_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM15_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM15_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM15_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM15_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM15_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM15_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM15_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM15_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM15_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM15_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM15_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM15_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM15_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM15_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM15_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM15_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM15_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM15_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM15_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM15_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM15_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM15_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM15_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM15_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM15_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM15_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM15_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM15_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM15_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM15_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM15_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM15_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM15_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM15_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM15_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM15_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM15_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM15_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM15_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM15_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM16" base ad:0x50050000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM16_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM16_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM16_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM16_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM16_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM16_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM16_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM16_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM16_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM16_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM16_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM16_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM16_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM16_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM16_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM16_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM16_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM16_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM16_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM16_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM16_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM16_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM16_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM16_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM16_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM16_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM16_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM16_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM16_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM16_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM16_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM16_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM16_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM16_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM16_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM16_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM16_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM16_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM16_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM16_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM16_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM16_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM16_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM16_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM16_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM16_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM16_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM16_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM16_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM16_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM16_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM16_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM16_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM16_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM16_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM16_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM16_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM16_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM16_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM16_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM16_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM16_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM16_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM16_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM16_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM16_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM16_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM16_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM16_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM16_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM16_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM16_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM16_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM16_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM16_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM16_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM16_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM16_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM16_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM16_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM16_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM16_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM16_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM16_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM16_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM16_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM16_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM16_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM16_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM16_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM16_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM16_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM16_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM16_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM16_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM16_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM16_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM16_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM16_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM16_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM16_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM16_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM16_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM16_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM16_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM16_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM16_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM16_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM16_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM16_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM16_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM16_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM16_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM16_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM16_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM16_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM16_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM16_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM16_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM16_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM16_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM16_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM16_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM16_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM16_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM16_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM16_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM16_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM16_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM16_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM16_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM16_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM16_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM16_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM16_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM16_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM17" base ad:0x50051000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM17_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM17_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM17_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM17_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM17_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM17_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM17_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM17_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM17_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM17_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM17_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM17_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM17_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM17_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM17_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM17_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM17_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM17_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM17_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM17_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM17_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM17_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM17_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM17_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM17_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM17_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM17_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM17_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM17_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM17_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM17_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM17_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM17_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM17_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM17_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM17_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM17_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM17_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM17_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM17_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM17_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM17_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM17_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM17_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM17_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM17_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM17_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM17_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM17_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM17_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM17_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM17_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM17_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM17_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM17_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM17_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM17_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM17_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM17_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM17_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM17_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM17_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM17_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM17_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM17_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM17_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM17_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM17_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM17_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM17_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM17_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM17_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM17_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM17_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM17_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM17_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM17_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM17_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM17_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM17_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM17_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM17_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM17_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM17_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM17_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM17_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM17_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM17_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM17_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM17_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM17_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM17_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM17_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM17_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM17_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM17_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM17_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM17_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM17_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM17_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM17_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM17_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM17_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM17_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM17_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM17_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM17_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM17_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM17_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM17_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM17_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM17_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM17_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM17_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM17_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM17_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM17_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM17_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM17_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM17_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM17_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM17_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM17_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM17_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM17_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM17_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM17_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM17_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM17_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM17_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM17_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM17_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM17_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM17_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM17_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM17_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM18" base ad:0x50052000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM18_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM18_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM18_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM18_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM18_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM18_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM18_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM18_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM18_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM18_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM18_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM18_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM18_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM18_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM18_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM18_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM18_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM18_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM18_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM18_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM18_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM18_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM18_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM18_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM18_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM18_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM18_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM18_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM18_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM18_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM18_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM18_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM18_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM18_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM18_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM18_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM18_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM18_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM18_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM18_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM18_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM18_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM18_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM18_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM18_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM18_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM18_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM18_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM18_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM18_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM18_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM18_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM18_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM18_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM18_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM18_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM18_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM18_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM18_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM18_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM18_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM18_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM18_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM18_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM18_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM18_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM18_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM18_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM18_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM18_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM18_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM18_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM18_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM18_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM18_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM18_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM18_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM18_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM18_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM18_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM18_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM18_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM18_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM18_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM18_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM18_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM18_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM18_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM18_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM18_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM18_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM18_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM18_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM18_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM18_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM18_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM18_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM18_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM18_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM18_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM18_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM18_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM18_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM18_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM18_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM18_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM18_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM18_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM18_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM18_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM18_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM18_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM18_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM18_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM18_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM18_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM18_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM18_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM18_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM18_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM18_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM18_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM18_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM18_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM18_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM18_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM18_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM18_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM18_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM18_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM18_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM18_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM18_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM18_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM18_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM18_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM19" base ad:0x50053000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM19_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM19_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM19_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM19_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM19_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM19_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM19_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM19_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM19_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM19_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM19_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM19_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM19_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM19_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM19_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM19_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM19_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM19_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM19_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM19_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM19_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM19_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM19_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM19_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM19_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM19_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM19_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM19_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM19_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM19_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM19_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM19_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM19_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM19_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM19_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM19_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM19_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM19_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM19_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM19_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM19_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM19_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM19_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM19_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM19_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM19_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM19_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM19_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM19_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM19_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM19_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM19_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM19_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM19_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM19_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM19_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM19_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM19_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM19_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM19_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM19_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM19_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM19_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM19_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM19_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM19_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM19_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM19_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM19_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM19_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM19_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM19_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM19_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM19_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM19_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM19_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM19_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM19_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM19_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM19_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM19_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM19_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM19_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM19_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM19_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM19_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM19_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM19_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM19_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM19_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM19_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM19_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM19_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM19_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM19_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM19_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM19_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM19_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM19_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM19_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM19_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM19_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM19_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM19_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM19_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM19_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM19_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM19_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM19_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM19_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM19_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM19_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM19_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM19_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM19_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM19_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM19_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM19_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM19_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM19_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM19_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM19_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM19_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM19_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM19_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM19_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM19_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM19_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM19_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM19_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM19_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM19_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM19_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM19_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM19_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM19_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM20" base ad:0x50054000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM20_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM20_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM20_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM20_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM20_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM20_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM20_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM20_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM20_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM20_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM20_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM20_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM20_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM20_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM20_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM20_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM20_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM20_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM20_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM20_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM20_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM20_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM20_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM20_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM20_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM20_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM20_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM20_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM20_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM20_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM20_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM20_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM20_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM20_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM20_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM20_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM20_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM20_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM20_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM20_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM20_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM20_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM20_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM20_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM20_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM20_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM20_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM20_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM20_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM20_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM20_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM20_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM20_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM20_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM20_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM20_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM20_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM20_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM20_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM20_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM20_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM20_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM20_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM20_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM20_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM20_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM20_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM20_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM20_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM20_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM20_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM20_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM20_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM20_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM20_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM20_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM20_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM20_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM20_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM20_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM20_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM20_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM20_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM20_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM20_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM20_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM20_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM20_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM20_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM20_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM20_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM20_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM20_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM20_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM20_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM20_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM20_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM20_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM20_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM20_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM20_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM20_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM20_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM20_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM20_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM20_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM20_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM20_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM20_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM20_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM20_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM20_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM20_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM20_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM20_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM20_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM20_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM20_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM20_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM20_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM20_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM20_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM20_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM20_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM20_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM20_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM20_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM20_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM20_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM20_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM20_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM20_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM20_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM20_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM20_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM20_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM21" base ad:0x50055000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM21_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM21_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM21_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM21_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM21_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM21_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM21_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM21_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM21_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM21_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM21_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM21_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM21_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM21_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM21_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM21_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM21_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM21_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM21_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM21_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM21_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM21_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM21_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM21_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM21_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM21_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM21_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM21_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM21_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM21_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM21_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM21_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM21_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM21_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM21_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM21_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM21_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM21_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM21_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM21_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM21_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM21_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM21_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM21_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM21_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM21_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM21_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM21_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM21_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM21_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM21_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM21_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM21_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM21_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM21_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM21_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM21_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM21_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM21_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM21_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM21_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM21_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM21_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM21_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM21_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM21_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM21_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM21_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM21_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM21_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM21_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM21_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM21_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM21_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM21_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM21_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM21_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM21_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM21_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM21_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM21_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM21_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM21_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM21_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM21_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM21_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM21_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM21_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM21_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM21_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM21_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM21_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM21_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM21_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM21_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM21_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM21_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM21_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM21_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM21_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM21_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM21_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM21_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM21_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM21_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM21_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM21_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM21_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM21_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM21_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM21_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM21_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM21_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM21_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM21_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM21_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM21_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM21_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM21_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM21_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM21_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM21_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM21_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM21_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM21_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM21_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM21_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM21_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM21_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM21_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM21_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM21_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM21_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM21_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM21_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM21_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM22" base ad:0x50056000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM22_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM22_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM22_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM22_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM22_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM22_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM22_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM22_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM22_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM22_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM22_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM22_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM22_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM22_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM22_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM22_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM22_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM22_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM22_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM22_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM22_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM22_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM22_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM22_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM22_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM22_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM22_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM22_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM22_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM22_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM22_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM22_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM22_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM22_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM22_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM22_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM22_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM22_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM22_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM22_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM22_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM22_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM22_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM22_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM22_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM22_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM22_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM22_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM22_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM22_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM22_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM22_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM22_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM22_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM22_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM22_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM22_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM22_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM22_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM22_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM22_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM22_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM22_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM22_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM22_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM22_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM22_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM22_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM22_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM22_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM22_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM22_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM22_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM22_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM22_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM22_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM22_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM22_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM22_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM22_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM22_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM22_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM22_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM22_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM22_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM22_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM22_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM22_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM22_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM22_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM22_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM22_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM22_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM22_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM22_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM22_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM22_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM22_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM22_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM22_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM22_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM22_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM22_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM22_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM22_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM22_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM22_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM22_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM22_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM22_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM22_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM22_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM22_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM22_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM22_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM22_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM22_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM22_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM22_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM22_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM22_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM22_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM22_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM22_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM22_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM22_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM22_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM22_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM22_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM22_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM22_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM22_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM22_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM22_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM22_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM22_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM23" base ad:0x50057000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM23_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM23_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM23_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM23_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM23_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM23_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM23_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM23_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM23_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM23_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM23_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM23_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM23_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM23_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM23_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM23_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM23_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM23_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM23_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM23_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM23_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM23_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM23_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM23_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM23_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM23_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM23_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM23_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM23_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM23_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM23_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM23_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM23_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM23_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM23_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM23_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM23_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM23_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM23_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM23_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM23_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM23_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM23_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM23_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM23_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM23_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM23_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM23_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM23_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM23_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM23_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM23_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM23_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM23_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM23_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM23_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM23_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM23_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM23_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM23_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM23_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM23_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM23_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM23_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM23_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM23_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM23_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM23_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM23_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM23_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM23_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM23_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM23_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM23_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM23_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM23_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM23_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM23_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM23_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM23_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM23_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM23_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM23_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM23_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM23_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM23_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM23_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM23_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM23_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM23_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM23_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM23_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM23_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM23_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM23_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM23_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM23_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM23_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM23_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM23_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM23_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM23_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM23_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM23_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM23_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM23_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM23_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM23_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM23_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM23_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM23_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM23_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM23_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM23_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM23_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM23_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM23_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM23_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM23_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM23_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM23_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM23_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM23_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM23_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM23_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM23_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM23_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM23_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM23_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM23_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM23_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM23_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM23_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM23_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM23_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM23_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM24" base ad:0x50058000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM24_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM24_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM24_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM24_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM24_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM24_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM24_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM24_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM24_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM24_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM24_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM24_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM24_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM24_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM24_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM24_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM24_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM24_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM24_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM24_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM24_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM24_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM24_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM24_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM24_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM24_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM24_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM24_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM24_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM24_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM24_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM24_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM24_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM24_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM24_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM24_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM24_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM24_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM24_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM24_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM24_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM24_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM24_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM24_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM24_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM24_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM24_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM24_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM24_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM24_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM24_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM24_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM24_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM24_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM24_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM24_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM24_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM24_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM24_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM24_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM24_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM24_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM24_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM24_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM24_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM24_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM24_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM24_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM24_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM24_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM24_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM24_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM24_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM24_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM24_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM24_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM24_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM24_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM24_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM24_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM24_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM24_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM24_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM24_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM24_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM24_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM24_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM24_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM24_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM24_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM24_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM24_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM24_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM24_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM24_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM24_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM24_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM24_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM24_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM24_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM24_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM24_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM24_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM24_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM24_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM24_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM24_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM24_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM24_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM24_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM24_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM24_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM24_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM24_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM24_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM24_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM24_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM24_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM24_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM24_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM24_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM24_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM24_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM24_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM24_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM24_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM24_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM24_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM24_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM24_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM24_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM24_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM24_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM24_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM24_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM24_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM25" base ad:0x50059000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM25_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM25_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM25_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM25_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM25_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM25_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM25_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM25_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM25_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM25_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM25_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM25_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM25_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM25_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM25_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM25_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM25_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM25_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM25_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM25_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM25_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM25_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM25_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM25_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM25_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM25_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM25_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM25_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM25_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM25_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM25_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM25_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM25_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM25_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM25_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM25_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM25_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM25_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM25_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM25_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM25_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM25_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM25_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM25_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM25_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM25_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM25_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM25_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM25_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM25_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM25_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM25_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM25_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM25_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM25_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM25_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM25_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM25_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM25_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM25_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM25_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM25_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM25_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM25_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM25_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM25_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM25_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM25_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM25_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM25_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM25_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM25_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM25_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM25_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM25_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM25_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM25_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM25_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM25_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM25_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM25_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM25_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM25_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM25_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM25_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM25_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM25_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM25_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM25_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM25_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM25_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM25_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM25_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM25_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM25_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM25_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM25_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM25_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM25_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM25_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM25_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM25_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM25_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM25_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM25_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM25_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM25_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM25_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM25_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM25_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM25_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM25_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM25_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM25_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM25_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM25_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM25_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM25_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM25_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM25_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM25_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM25_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM25_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM25_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM25_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM25_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM25_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM25_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM25_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM25_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM25_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM25_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM25_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM25_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM25_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM25_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM26" base ad:0x5005A000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM26_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM26_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM26_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM26_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM26_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM26_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM26_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM26_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM26_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM26_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM26_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM26_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM26_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM26_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM26_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM26_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM26_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM26_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM26_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM26_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM26_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM26_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM26_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM26_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM26_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM26_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM26_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM26_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM26_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM26_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM26_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM26_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM26_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM26_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM26_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM26_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM26_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM26_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM26_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM26_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM26_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM26_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM26_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM26_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM26_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM26_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM26_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM26_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM26_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM26_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM26_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM26_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM26_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM26_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM26_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM26_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM26_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM26_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM26_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM26_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM26_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM26_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM26_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM26_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM26_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM26_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM26_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM26_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM26_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM26_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM26_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM26_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM26_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM26_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM26_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM26_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM26_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM26_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM26_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM26_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM26_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM26_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM26_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM26_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM26_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM26_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM26_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM26_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM26_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM26_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM26_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM26_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM26_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM26_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM26_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM26_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM26_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM26_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM26_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM26_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM26_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM26_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM26_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM26_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM26_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM26_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM26_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM26_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM26_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM26_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM26_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM26_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM26_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM26_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM26_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM26_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM26_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM26_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM26_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM26_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM26_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM26_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM26_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM26_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM26_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM26_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM26_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM26_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM26_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM26_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM26_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM26_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM26_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM26_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM26_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM26_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM27" base ad:0x5005B000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM27_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM27_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM27_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM27_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM27_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM27_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM27_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM27_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM27_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM27_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM27_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM27_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM27_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM27_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM27_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM27_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM27_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM27_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM27_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM27_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM27_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM27_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM27_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM27_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM27_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM27_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM27_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM27_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM27_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM27_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM27_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM27_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM27_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM27_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM27_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM27_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM27_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM27_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM27_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM27_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM27_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM27_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM27_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM27_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM27_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM27_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM27_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM27_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM27_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM27_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM27_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM27_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM27_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM27_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM27_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM27_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM27_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM27_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM27_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM27_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM27_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM27_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM27_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM27_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM27_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM27_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM27_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM27_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM27_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM27_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM27_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM27_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM27_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM27_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM27_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM27_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM27_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM27_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM27_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM27_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM27_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM27_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM27_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM27_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM27_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM27_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM27_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM27_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM27_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM27_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM27_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM27_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM27_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM27_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM27_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM27_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM27_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM27_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM27_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM27_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM27_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM27_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM27_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM27_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM27_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM27_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM27_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM27_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM27_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM27_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM27_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM27_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM27_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM27_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM27_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM27_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM27_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM27_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM27_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM27_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM27_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM27_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM27_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM27_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM27_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM27_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM27_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM27_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM27_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM27_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM27_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM27_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM27_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM27_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM27_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM27_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM28" base ad:0x5005C000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM28_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM28_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM28_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM28_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM28_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM28_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM28_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM28_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM28_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM28_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM28_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM28_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM28_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM28_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM28_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM28_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM28_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM28_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM28_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM28_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM28_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM28_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM28_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM28_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM28_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM28_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM28_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM28_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM28_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM28_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM28_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM28_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM28_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM28_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM28_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM28_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM28_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM28_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM28_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM28_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM28_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM28_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM28_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM28_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM28_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM28_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM28_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM28_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM28_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM28_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM28_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM28_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM28_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM28_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM28_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM28_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM28_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM28_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM28_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM28_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM28_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM28_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM28_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM28_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM28_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM28_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM28_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM28_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM28_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM28_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM28_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM28_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM28_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM28_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM28_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM28_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM28_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM28_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM28_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM28_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM28_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM28_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM28_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM28_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM28_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM28_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM28_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM28_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM28_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM28_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM28_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM28_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM28_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM28_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM28_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM28_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM28_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM28_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM28_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM28_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM28_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM28_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM28_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM28_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM28_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM28_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM28_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM28_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM28_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM28_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM28_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM28_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM28_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM28_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM28_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM28_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM28_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM28_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM28_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM28_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM28_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM28_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM28_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM28_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM28_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM28_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM28_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM28_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM28_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM28_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM28_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM28_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM28_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM28_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM28_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM28_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM29" base ad:0x5005D000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM29_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM29_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM29_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM29_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM29_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM29_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM29_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM29_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM29_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM29_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM29_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM29_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM29_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM29_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM29_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM29_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM29_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM29_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM29_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM29_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM29_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM29_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM29_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM29_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM29_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM29_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM29_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM29_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM29_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM29_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM29_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM29_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM29_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM29_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM29_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM29_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM29_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM29_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM29_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM29_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM29_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM29_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM29_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM29_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM29_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM29_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM29_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM29_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM29_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM29_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM29_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM29_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM29_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM29_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM29_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM29_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM29_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM29_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM29_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM29_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM29_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM29_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM29_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM29_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM29_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM29_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM29_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM29_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM29_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM29_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM29_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM29_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM29_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM29_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM29_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM29_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM29_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM29_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM29_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM29_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM29_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM29_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM29_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM29_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM29_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM29_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM29_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM29_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM29_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM29_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM29_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM29_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM29_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM29_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM29_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM29_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM29_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM29_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM29_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM29_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM29_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM29_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM29_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM29_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM29_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM29_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM29_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM29_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM29_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM29_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM29_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM29_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM29_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM29_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM29_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM29_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM29_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM29_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM29_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM29_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM29_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM29_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM29_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM29_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM29_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM29_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM29_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM29_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM29_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM29_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM29_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM29_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM29_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM29_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM29_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM29_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM30" base ad:0x5005E000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM30_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM30_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM30_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM30_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM30_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM30_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM30_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM30_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM30_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM30_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM30_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM30_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM30_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM30_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM30_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM30_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM30_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM30_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM30_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM30_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM30_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM30_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM30_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM30_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM30_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM30_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM30_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM30_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM30_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM30_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM30_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM30_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM30_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM30_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM30_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM30_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM30_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM30_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM30_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM30_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM30_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM30_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM30_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM30_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM30_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM30_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM30_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM30_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM30_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM30_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM30_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM30_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM30_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM30_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM30_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM30_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM30_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM30_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM30_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM30_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM30_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM30_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM30_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM30_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM30_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM30_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM30_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM30_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM30_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM30_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM30_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM30_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM30_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM30_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM30_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM30_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM30_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM30_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM30_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM30_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM30_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM30_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM30_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM30_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM30_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM30_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM30_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM30_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM30_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM30_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM30_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM30_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM30_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM30_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM30_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM30_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM30_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM30_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM30_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM30_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM30_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM30_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM30_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM30_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM30_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM30_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM30_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM30_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM30_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM30_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM30_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM30_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM30_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM30_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM30_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM30_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM30_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM30_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM30_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM30_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM30_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM30_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM30_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM30_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM30_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM30_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM30_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM30_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM30_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM30_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM30_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM30_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM30_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM30_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM30_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM30_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G1_EPWM31" base ad:0x5005F000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM31_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G1_EPWM31_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G1_EPWM31_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G1_EPWM31_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G1_EPWM31_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G1_EPWM31_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G1_EPWM31_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G1_EPWM31_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G1_EPWM31_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G1_EPWM31_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM31_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G1_EPWM31_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G1_EPWM31_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G1_EPWM31_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G1_EPWM31_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM31_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G1_EPWM31_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G1_EPWM31_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G1_EPWM31_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G1_EPWM31_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G1_EPWM31_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G1_EPWM31_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G1_EPWM31_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G1_EPWM31_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G1_EPWM31_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G1_EPWM31_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G1_EPWM31_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G1_EPWM31_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G1_EPWM31_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G1_EPWM31_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G1_EPWM31_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G1_EPWM31_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G1_EPWM31_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G1_EPWM31_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G1_EPWM31_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G1_EPWM31_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G1_EPWM31_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G1_EPWM31_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM31_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G1_EPWM31_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G1_EPWM31_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G1_EPWM31_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G1_EPWM31_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G1_EPWM31_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G1_EPWM31_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G1_EPWM31_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G1_EPWM31_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM31_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G1_EPWM31_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G1_EPWM31_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G1_EPWM31_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G1_EPWM31_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G1_EPWM31_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G1_EPWM31_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G1_EPWM31_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G1_EPWM31_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G1_EPWM31_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G1_EPWM31_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G1_EPWM31_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G1_EPWM31_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G1_EPWM31_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G1_EPWM31_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G1_EPWM31_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G1_EPWM31_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G1_EPWM31_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM31_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G1_EPWM31_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G1_EPWM31_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G1_EPWM31_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G1_EPWM31_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G1_EPWM31_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G1_EPWM31_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G1_EPWM31_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G1_EPWM31_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G1_EPWM31_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G1_EPWM31_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM31_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM31_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM31_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM31_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM31_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM31_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM31_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM31_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G1_EPWM31_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G1_EPWM31_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM31_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM31_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM31_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM31_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM31_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM31_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM31_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM31_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM31_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM31_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM31_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G1_EPWM31_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM31_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM31_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM31_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM31_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM31_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM31_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM31_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM31_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G1_EPWM31_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM31_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G1_EPWM31_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G1_EPWM31_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G1_EPWM31_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G1_EPWM31_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G1_EPWM31_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G1_EPWM31_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G1_EPWM31_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G1_EPWM31_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G1_EPWM31_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G1_EPWM31_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G1_EPWM31_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G1_EPWM31_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G1_EPWM31_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G1_EPWM31_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G1_EPWM31_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G1_EPWM31_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G1_EPWM31_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G1_EPWM31_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G1_EPWM31_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G1_EPWM31_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G1_EPWM31_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G1_EPWM31_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G1_EPWM31_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G1_EPWM31_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G1_EPWM31_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G1_EPWM31_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G1_EPWM31_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G1_EPWM31_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM_G2" tree "G2_EPWM0" base ad:0x50080000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM0_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM0_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM0_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM0_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM0_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM0_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM0_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM0_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM0_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM0_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM0_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM0_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM0_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM0_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM0_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM0_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM0_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM0_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM0_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM0_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM0_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM0_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM0_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM0_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM0_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM0_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM0_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM0_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM0_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM0_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM0_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM0_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM0_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM0_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM0_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM0_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM0_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM0_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM0_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM0_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM0_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM0_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM0_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM0_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM0_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM0_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM0_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM0_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM0_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM0_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM0_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM0_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM0_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM0_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM0_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM0_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM0_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM0_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM0_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM0_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM0_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM0_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM0_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM0_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM0_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM0_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM0_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM0_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM0_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM0_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM0_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM0_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM0_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM0_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM0_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM0_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM0_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM0_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM0_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM0_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM0_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM0_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM0_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM0_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM0_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM0_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM0_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM0_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM0_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM0_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM0_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM0_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM0_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM0_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM0_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM0_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM0_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM0_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM0_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM0_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM0_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM0_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM0_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM0_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM0_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM0_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM0_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM0_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM0_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM0_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM0_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM0_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM0_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM0_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM0_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM0_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM0_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM0_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM0_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM0_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM0_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM0_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM0_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM0_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM0_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM0_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM0_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM0_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM0_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM0_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM0_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM0_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM0_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM0_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM0_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM0_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM1" base ad:0x50081000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM1_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM1_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM1_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM1_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM1_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM1_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM1_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM1_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM1_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM1_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM1_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM1_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM1_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM1_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM1_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM1_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM1_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM1_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM1_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM1_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM1_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM1_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM1_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM1_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM1_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM1_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM1_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM1_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM1_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM1_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM1_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM1_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM1_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM1_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM1_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM1_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM1_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM1_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM1_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM1_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM1_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM1_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM1_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM1_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM1_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM1_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM1_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM1_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM1_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM1_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM1_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM1_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM1_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM1_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM1_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM1_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM1_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM1_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM1_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM1_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM1_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM1_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM1_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM1_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM1_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM1_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM1_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM1_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM1_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM1_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM1_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM1_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM1_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM1_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM1_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM1_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM1_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM1_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM1_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM1_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM1_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM1_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM1_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM1_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM1_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM1_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM1_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM1_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM1_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM1_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM1_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM1_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM1_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM1_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM1_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM1_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM1_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM1_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM1_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM1_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM1_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM1_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM1_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM1_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM1_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM1_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM1_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM1_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM1_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM1_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM1_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM1_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM1_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM1_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM1_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM1_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM1_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM1_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM1_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM1_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM1_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM1_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM1_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM1_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM1_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM1_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM1_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM1_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM1_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM1_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM1_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM1_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM1_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM1_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM1_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM1_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM2" base ad:0x50082000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM2_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM2_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM2_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM2_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM2_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM2_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM2_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM2_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM2_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM2_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM2_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM2_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM2_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM2_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM2_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM2_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM2_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM2_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM2_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM2_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM2_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM2_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM2_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM2_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM2_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM2_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM2_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM2_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM2_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM2_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM2_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM2_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM2_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM2_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM2_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM2_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM2_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM2_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM2_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM2_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM2_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM2_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM2_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM2_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM2_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM2_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM2_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM2_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM2_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM2_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM2_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM2_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM2_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM2_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM2_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM2_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM2_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM2_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM2_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM2_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM2_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM2_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM2_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM2_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM2_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM2_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM2_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM2_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM2_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM2_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM2_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM2_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM2_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM2_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM2_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM2_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM2_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM2_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM2_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM2_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM2_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM2_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM2_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM2_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM2_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM2_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM2_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM2_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM2_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM2_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM2_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM2_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM2_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM2_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM2_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM2_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM2_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM2_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM2_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM2_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM2_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM2_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM2_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM2_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM2_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM2_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM2_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM2_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM2_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM2_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM2_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM2_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM2_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM2_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM2_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM2_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM2_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM2_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM2_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM2_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM2_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM2_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM2_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM2_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM2_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM2_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM2_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM2_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM2_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM2_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM2_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM2_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM2_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM2_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM2_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM2_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM3" base ad:0x50083000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM3_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM3_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM3_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM3_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM3_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM3_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM3_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM3_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM3_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM3_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM3_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM3_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM3_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM3_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM3_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM3_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM3_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM3_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM3_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM3_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM3_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM3_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM3_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM3_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM3_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM3_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM3_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM3_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM3_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM3_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM3_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM3_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM3_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM3_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM3_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM3_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM3_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM3_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM3_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM3_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM3_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM3_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM3_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM3_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM3_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM3_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM3_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM3_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM3_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM3_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM3_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM3_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM3_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM3_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM3_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM3_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM3_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM3_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM3_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM3_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM3_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM3_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM3_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM3_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM3_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM3_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM3_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM3_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM3_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM3_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM3_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM3_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM3_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM3_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM3_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM3_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM3_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM3_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM3_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM3_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM3_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM3_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM3_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM3_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM3_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM3_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM3_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM3_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM3_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM3_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM3_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM3_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM3_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM3_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM3_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM3_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM3_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM3_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM3_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM3_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM3_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM3_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM3_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM3_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM3_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM3_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM3_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM3_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM3_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM3_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM3_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM3_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM3_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM3_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM3_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM3_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM3_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM3_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM3_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM3_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM3_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM3_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM3_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM3_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM3_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM3_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM3_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM3_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM3_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM3_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM3_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM3_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM3_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM3_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM3_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM3_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM4" base ad:0x50084000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM4_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM4_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM4_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM4_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM4_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM4_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM4_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM4_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM4_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM4_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM4_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM4_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM4_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM4_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM4_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM4_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM4_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM4_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM4_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM4_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM4_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM4_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM4_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM4_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM4_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM4_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM4_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM4_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM4_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM4_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM4_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM4_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM4_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM4_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM4_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM4_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM4_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM4_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM4_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM4_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM4_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM4_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM4_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM4_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM4_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM4_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM4_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM4_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM4_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM4_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM4_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM4_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM4_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM4_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM4_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM4_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM4_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM4_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM4_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM4_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM4_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM4_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM4_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM4_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM4_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM4_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM4_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM4_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM4_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM4_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM4_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM4_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM4_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM4_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM4_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM4_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM4_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM4_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM4_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM4_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM4_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM4_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM4_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM4_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM4_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM4_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM4_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM4_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM4_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM4_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM4_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM4_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM4_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM4_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM4_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM4_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM4_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM4_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM4_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM4_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM4_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM4_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM4_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM4_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM4_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM4_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM4_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM4_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM4_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM4_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM4_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM4_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM4_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM4_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM4_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM4_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM4_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM4_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM4_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM4_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM4_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM4_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM4_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM4_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM4_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM4_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM4_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM4_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM4_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM4_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM4_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM4_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM4_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM4_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM4_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM4_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM5" base ad:0x50085000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM5_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM5_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM5_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM5_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM5_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM5_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM5_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM5_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM5_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM5_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM5_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM5_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM5_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM5_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM5_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM5_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM5_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM5_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM5_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM5_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM5_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM5_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM5_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM5_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM5_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM5_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM5_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM5_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM5_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM5_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM5_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM5_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM5_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM5_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM5_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM5_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM5_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM5_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM5_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM5_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM5_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM5_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM5_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM5_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM5_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM5_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM5_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM5_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM5_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM5_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM5_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM5_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM5_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM5_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM5_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM5_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM5_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM5_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM5_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM5_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM5_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM5_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM5_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM5_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM5_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM5_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM5_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM5_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM5_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM5_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM5_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM5_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM5_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM5_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM5_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM5_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM5_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM5_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM5_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM5_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM5_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM5_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM5_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM5_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM5_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM5_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM5_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM5_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM5_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM5_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM5_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM5_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM5_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM5_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM5_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM5_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM5_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM5_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM5_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM5_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM5_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM5_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM5_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM5_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM5_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM5_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM5_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM5_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM5_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM5_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM5_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM5_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM5_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM5_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM5_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM5_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM5_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM5_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM5_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM5_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM5_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM5_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM5_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM5_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM5_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM5_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM5_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM5_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM5_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM5_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM5_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM5_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM5_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM5_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM5_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM5_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM6" base ad:0x50086000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM6_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM6_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM6_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM6_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM6_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM6_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM6_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM6_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM6_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM6_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM6_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM6_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM6_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM6_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM6_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM6_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM6_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM6_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM6_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM6_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM6_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM6_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM6_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM6_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM6_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM6_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM6_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM6_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM6_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM6_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM6_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM6_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM6_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM6_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM6_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM6_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM6_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM6_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM6_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM6_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM6_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM6_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM6_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM6_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM6_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM6_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM6_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM6_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM6_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM6_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM6_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM6_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM6_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM6_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM6_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM6_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM6_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM6_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM6_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM6_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM6_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM6_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM6_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM6_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM6_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM6_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM6_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM6_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM6_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM6_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM6_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM6_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM6_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM6_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM6_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM6_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM6_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM6_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM6_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM6_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM6_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM6_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM6_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM6_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM6_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM6_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM6_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM6_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM6_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM6_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM6_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM6_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM6_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM6_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM6_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM6_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM6_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM6_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM6_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM6_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM6_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM6_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM6_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM6_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM6_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM6_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM6_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM6_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM6_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM6_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM6_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM6_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM6_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM6_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM6_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM6_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM6_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM6_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM6_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM6_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM6_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM6_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM6_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM6_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM6_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM6_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM6_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM6_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM6_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM6_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM6_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM6_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM6_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM6_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM6_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM6_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM7" base ad:0x50087000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM7_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM7_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM7_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM7_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM7_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM7_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM7_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM7_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM7_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM7_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM7_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM7_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM7_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM7_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM7_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM7_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM7_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM7_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM7_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM7_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM7_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM7_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM7_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM7_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM7_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM7_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM7_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM7_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM7_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM7_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM7_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM7_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM7_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM7_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM7_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM7_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM7_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM7_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM7_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM7_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM7_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM7_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM7_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM7_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM7_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM7_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM7_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM7_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM7_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM7_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM7_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM7_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM7_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM7_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM7_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM7_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM7_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM7_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM7_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM7_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM7_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM7_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM7_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM7_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM7_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM7_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM7_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM7_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM7_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM7_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM7_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM7_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM7_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM7_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM7_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM7_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM7_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM7_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM7_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM7_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM7_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM7_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM7_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM7_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM7_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM7_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM7_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM7_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM7_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM7_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM7_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM7_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM7_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM7_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM7_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM7_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM7_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM7_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM7_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM7_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM7_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM7_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM7_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM7_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM7_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM7_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM7_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM7_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM7_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM7_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM7_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM7_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM7_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM7_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM7_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM7_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM7_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM7_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM7_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM7_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM7_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM7_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM7_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM7_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM7_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM7_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM7_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM7_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM7_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM7_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM7_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM7_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM7_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM7_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM7_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM7_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM8" base ad:0x50088000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM8_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM8_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM8_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM8_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM8_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM8_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM8_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM8_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM8_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM8_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM8_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM8_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM8_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM8_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM8_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM8_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM8_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM8_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM8_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM8_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM8_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM8_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM8_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM8_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM8_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM8_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM8_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM8_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM8_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM8_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM8_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM8_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM8_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM8_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM8_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM8_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM8_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM8_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM8_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM8_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM8_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM8_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM8_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM8_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM8_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM8_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM8_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM8_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM8_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM8_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM8_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM8_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM8_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM8_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM8_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM8_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM8_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM8_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM8_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM8_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM8_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM8_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM8_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM8_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM8_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM8_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM8_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM8_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM8_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM8_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM8_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM8_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM8_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM8_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM8_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM8_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM8_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM8_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM8_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM8_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM8_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM8_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM8_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM8_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM8_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM8_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM8_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM8_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM8_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM8_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM8_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM8_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM8_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM8_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM8_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM8_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM8_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM8_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM8_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM8_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM8_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM8_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM8_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM8_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM8_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM8_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM8_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM8_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM8_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM8_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM8_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM8_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM8_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM8_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM8_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM8_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM8_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM8_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM8_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM8_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM8_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM8_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM8_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM8_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM8_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM8_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM8_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM8_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM8_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM8_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM8_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM8_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM8_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM8_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM8_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM8_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM9" base ad:0x50089000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM9_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM9_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM9_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM9_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM9_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM9_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM9_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM9_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM9_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM9_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM9_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM9_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM9_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM9_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM9_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM9_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM9_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM9_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM9_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM9_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM9_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM9_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM9_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM9_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM9_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM9_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM9_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM9_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM9_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM9_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM9_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM9_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM9_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM9_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM9_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM9_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM9_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM9_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM9_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM9_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM9_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM9_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM9_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM9_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM9_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM9_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM9_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM9_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM9_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM9_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM9_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM9_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM9_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM9_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM9_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM9_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM9_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM9_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM9_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM9_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM9_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM9_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM9_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM9_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM9_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM9_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM9_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM9_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM9_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM9_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM9_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM9_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM9_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM9_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM9_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM9_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM9_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM9_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM9_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM9_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM9_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM9_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM9_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM9_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM9_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM9_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM9_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM9_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM9_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM9_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM9_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM9_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM9_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM9_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM9_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM9_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM9_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM9_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM9_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM9_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM9_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM9_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM9_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM9_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM9_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM9_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM9_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM9_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM9_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM9_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM9_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM9_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM9_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM9_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM9_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM9_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM9_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM9_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM9_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM9_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM9_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM9_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM9_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM9_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM9_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM9_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM9_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM9_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM9_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM9_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM9_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM9_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM9_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM9_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM9_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM9_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM10" base ad:0x5008A000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM10_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM10_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM10_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM10_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM10_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM10_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM10_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM10_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM10_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM10_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM10_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM10_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM10_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM10_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM10_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM10_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM10_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM10_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM10_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM10_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM10_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM10_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM10_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM10_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM10_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM10_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM10_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM10_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM10_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM10_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM10_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM10_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM10_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM10_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM10_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM10_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM10_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM10_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM10_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM10_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM10_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM10_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM10_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM10_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM10_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM10_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM10_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM10_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM10_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM10_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM10_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM10_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM10_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM10_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM10_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM10_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM10_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM10_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM10_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM10_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM10_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM10_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM10_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM10_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM10_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM10_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM10_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM10_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM10_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM10_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM10_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM10_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM10_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM10_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM10_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM10_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM10_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM10_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM10_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM10_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM10_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM10_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM10_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM10_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM10_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM10_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM10_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM10_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM10_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM10_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM10_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM10_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM10_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM10_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM10_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM10_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM10_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM10_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM10_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM10_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM10_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM10_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM10_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM10_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM10_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM10_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM10_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM10_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM10_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM10_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM10_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM10_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM10_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM10_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM10_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM10_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM10_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM10_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM10_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM10_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM10_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM10_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM10_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM10_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM10_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM10_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM10_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM10_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM10_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM10_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM10_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM10_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM10_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM10_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM10_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM10_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM11" base ad:0x5008B000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM11_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM11_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM11_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM11_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM11_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM11_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM11_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM11_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM11_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM11_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM11_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM11_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM11_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM11_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM11_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM11_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM11_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM11_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM11_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM11_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM11_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM11_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM11_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM11_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM11_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM11_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM11_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM11_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM11_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM11_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM11_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM11_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM11_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM11_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM11_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM11_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM11_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM11_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM11_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM11_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM11_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM11_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM11_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM11_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM11_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM11_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM11_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM11_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM11_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM11_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM11_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM11_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM11_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM11_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM11_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM11_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM11_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM11_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM11_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM11_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM11_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM11_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM11_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM11_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM11_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM11_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM11_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM11_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM11_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM11_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM11_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM11_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM11_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM11_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM11_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM11_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM11_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM11_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM11_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM11_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM11_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM11_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM11_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM11_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM11_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM11_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM11_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM11_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM11_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM11_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM11_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM11_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM11_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM11_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM11_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM11_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM11_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM11_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM11_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM11_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM11_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM11_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM11_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM11_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM11_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM11_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM11_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM11_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM11_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM11_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM11_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM11_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM11_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM11_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM11_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM11_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM11_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM11_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM11_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM11_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM11_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM11_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM11_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM11_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM11_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM11_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM11_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM11_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM11_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM11_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM11_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM11_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM11_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM11_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM11_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM11_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM12" base ad:0x5008C000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM12_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM12_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM12_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM12_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM12_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM12_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM12_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM12_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM12_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM12_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM12_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM12_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM12_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM12_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM12_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM12_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM12_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM12_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM12_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM12_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM12_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM12_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM12_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM12_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM12_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM12_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM12_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM12_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM12_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM12_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM12_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM12_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM12_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM12_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM12_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM12_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM12_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM12_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM12_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM12_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM12_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM12_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM12_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM12_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM12_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM12_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM12_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM12_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM12_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM12_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM12_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM12_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM12_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM12_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM12_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM12_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM12_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM12_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM12_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM12_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM12_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM12_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM12_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM12_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM12_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM12_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM12_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM12_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM12_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM12_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM12_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM12_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM12_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM12_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM12_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM12_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM12_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM12_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM12_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM12_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM12_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM12_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM12_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM12_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM12_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM12_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM12_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM12_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM12_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM12_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM12_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM12_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM12_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM12_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM12_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM12_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM12_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM12_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM12_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM12_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM12_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM12_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM12_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM12_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM12_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM12_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM12_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM12_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM12_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM12_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM12_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM12_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM12_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM12_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM12_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM12_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM12_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM12_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM12_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM12_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM12_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM12_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM12_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM12_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM12_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM12_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM12_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM12_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM12_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM12_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM12_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM12_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM12_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM12_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM12_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM12_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM13" base ad:0x5008D000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM13_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM13_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM13_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM13_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM13_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM13_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM13_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM13_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM13_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM13_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM13_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM13_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM13_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM13_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM13_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM13_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM13_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM13_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM13_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM13_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM13_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM13_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM13_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM13_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM13_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM13_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM13_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM13_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM13_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM13_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM13_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM13_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM13_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM13_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM13_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM13_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM13_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM13_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM13_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM13_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM13_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM13_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM13_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM13_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM13_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM13_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM13_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM13_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM13_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM13_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM13_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM13_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM13_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM13_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM13_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM13_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM13_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM13_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM13_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM13_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM13_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM13_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM13_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM13_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM13_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM13_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM13_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM13_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM13_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM13_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM13_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM13_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM13_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM13_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM13_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM13_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM13_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM13_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM13_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM13_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM13_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM13_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM13_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM13_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM13_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM13_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM13_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM13_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM13_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM13_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM13_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM13_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM13_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM13_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM13_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM13_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM13_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM13_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM13_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM13_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM13_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM13_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM13_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM13_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM13_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM13_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM13_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM13_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM13_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM13_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM13_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM13_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM13_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM13_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM13_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM13_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM13_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM13_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM13_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM13_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM13_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM13_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM13_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM13_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM13_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM13_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM13_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM13_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM13_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM13_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM13_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM13_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM13_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM13_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM13_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM13_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM14" base ad:0x5008E000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM14_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM14_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM14_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM14_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM14_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM14_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM14_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM14_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM14_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM14_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM14_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM14_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM14_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM14_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM14_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM14_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM14_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM14_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM14_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM14_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM14_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM14_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM14_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM14_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM14_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM14_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM14_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM14_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM14_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM14_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM14_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM14_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM14_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM14_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM14_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM14_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM14_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM14_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM14_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM14_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM14_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM14_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM14_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM14_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM14_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM14_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM14_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM14_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM14_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM14_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM14_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM14_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM14_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM14_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM14_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM14_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM14_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM14_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM14_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM14_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM14_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM14_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM14_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM14_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM14_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM14_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM14_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM14_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM14_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM14_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM14_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM14_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM14_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM14_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM14_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM14_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM14_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM14_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM14_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM14_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM14_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM14_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM14_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM14_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM14_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM14_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM14_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM14_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM14_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM14_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM14_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM14_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM14_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM14_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM14_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM14_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM14_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM14_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM14_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM14_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM14_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM14_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM14_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM14_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM14_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM14_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM14_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM14_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM14_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM14_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM14_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM14_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM14_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM14_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM14_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM14_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM14_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM14_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM14_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM14_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM14_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM14_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM14_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM14_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM14_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM14_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM14_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM14_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM14_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM14_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM14_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM14_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM14_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM14_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM14_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM14_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM15" base ad:0x5008F000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM15_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM15_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM15_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM15_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM15_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM15_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM15_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM15_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM15_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM15_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM15_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM15_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM15_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM15_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM15_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM15_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM15_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM15_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM15_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM15_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM15_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM15_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM15_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM15_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM15_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM15_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM15_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM15_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM15_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM15_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM15_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM15_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM15_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM15_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM15_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM15_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM15_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM15_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM15_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM15_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM15_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM15_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM15_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM15_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM15_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM15_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM15_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM15_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM15_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM15_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM15_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM15_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM15_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM15_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM15_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM15_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM15_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM15_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM15_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM15_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM15_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM15_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM15_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM15_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM15_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM15_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM15_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM15_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM15_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM15_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM15_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM15_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM15_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM15_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM15_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM15_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM15_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM15_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM15_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM15_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM15_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM15_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM15_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM15_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM15_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM15_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM15_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM15_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM15_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM15_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM15_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM15_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM15_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM15_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM15_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM15_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM15_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM15_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM15_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM15_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM15_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM15_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM15_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM15_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM15_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM15_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM15_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM15_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM15_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM15_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM15_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM15_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM15_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM15_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM15_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM15_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM15_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM15_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM15_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM15_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM15_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM15_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM15_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM15_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM15_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM15_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM15_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM15_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM15_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM15_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM15_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM15_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM15_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM15_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM15_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM15_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM16" base ad:0x50090000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM16_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM16_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM16_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM16_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM16_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM16_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM16_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM16_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM16_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM16_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM16_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM16_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM16_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM16_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM16_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM16_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM16_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM16_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM16_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM16_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM16_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM16_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM16_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM16_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM16_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM16_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM16_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM16_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM16_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM16_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM16_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM16_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM16_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM16_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM16_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM16_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM16_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM16_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM16_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM16_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM16_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM16_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM16_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM16_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM16_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM16_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM16_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM16_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM16_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM16_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM16_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM16_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM16_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM16_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM16_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM16_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM16_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM16_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM16_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM16_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM16_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM16_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM16_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM16_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM16_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM16_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM16_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM16_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM16_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM16_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM16_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM16_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM16_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM16_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM16_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM16_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM16_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM16_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM16_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM16_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM16_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM16_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM16_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM16_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM16_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM16_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM16_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM16_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM16_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM16_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM16_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM16_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM16_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM16_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM16_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM16_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM16_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM16_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM16_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM16_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM16_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM16_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM16_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM16_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM16_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM16_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM16_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM16_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM16_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM16_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM16_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM16_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM16_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM16_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM16_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM16_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM16_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM16_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM16_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM16_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM16_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM16_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM16_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM16_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM16_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM16_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM16_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM16_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM16_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM16_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM16_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM16_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM16_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM16_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM16_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM16_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM17" base ad:0x50091000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM17_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM17_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM17_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM17_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM17_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM17_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM17_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM17_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM17_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM17_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM17_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM17_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM17_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM17_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM17_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM17_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM17_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM17_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM17_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM17_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM17_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM17_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM17_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM17_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM17_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM17_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM17_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM17_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM17_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM17_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM17_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM17_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM17_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM17_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM17_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM17_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM17_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM17_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM17_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM17_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM17_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM17_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM17_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM17_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM17_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM17_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM17_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM17_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM17_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM17_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM17_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM17_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM17_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM17_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM17_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM17_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM17_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM17_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM17_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM17_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM17_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM17_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM17_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM17_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM17_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM17_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM17_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM17_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM17_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM17_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM17_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM17_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM17_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM17_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM17_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM17_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM17_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM17_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM17_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM17_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM17_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM17_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM17_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM17_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM17_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM17_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM17_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM17_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM17_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM17_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM17_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM17_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM17_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM17_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM17_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM17_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM17_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM17_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM17_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM17_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM17_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM17_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM17_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM17_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM17_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM17_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM17_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM17_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM17_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM17_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM17_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM17_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM17_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM17_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM17_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM17_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM17_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM17_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM17_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM17_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM17_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM17_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM17_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM17_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM17_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM17_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM17_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM17_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM17_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM17_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM17_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM17_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM17_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM17_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM17_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM17_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM18" base ad:0x50092000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM18_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM18_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM18_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM18_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM18_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM18_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM18_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM18_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM18_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM18_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM18_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM18_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM18_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM18_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM18_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM18_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM18_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM18_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM18_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM18_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM18_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM18_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM18_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM18_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM18_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM18_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM18_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM18_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM18_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM18_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM18_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM18_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM18_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM18_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM18_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM18_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM18_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM18_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM18_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM18_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM18_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM18_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM18_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM18_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM18_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM18_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM18_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM18_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM18_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM18_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM18_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM18_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM18_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM18_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM18_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM18_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM18_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM18_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM18_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM18_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM18_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM18_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM18_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM18_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM18_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM18_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM18_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM18_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM18_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM18_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM18_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM18_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM18_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM18_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM18_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM18_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM18_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM18_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM18_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM18_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM18_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM18_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM18_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM18_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM18_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM18_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM18_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM18_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM18_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM18_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM18_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM18_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM18_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM18_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM18_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM18_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM18_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM18_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM18_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM18_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM18_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM18_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM18_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM18_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM18_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM18_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM18_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM18_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM18_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM18_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM18_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM18_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM18_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM18_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM18_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM18_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM18_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM18_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM18_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM18_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM18_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM18_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM18_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM18_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM18_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM18_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM18_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM18_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM18_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM18_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM18_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM18_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM18_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM18_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM18_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM18_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM19" base ad:0x50093000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM19_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM19_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM19_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM19_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM19_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM19_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM19_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM19_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM19_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM19_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM19_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM19_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM19_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM19_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM19_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM19_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM19_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM19_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM19_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM19_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM19_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM19_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM19_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM19_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM19_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM19_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM19_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM19_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM19_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM19_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM19_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM19_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM19_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM19_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM19_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM19_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM19_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM19_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM19_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM19_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM19_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM19_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM19_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM19_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM19_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM19_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM19_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM19_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM19_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM19_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM19_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM19_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM19_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM19_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM19_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM19_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM19_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM19_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM19_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM19_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM19_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM19_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM19_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM19_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM19_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM19_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM19_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM19_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM19_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM19_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM19_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM19_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM19_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM19_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM19_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM19_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM19_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM19_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM19_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM19_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM19_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM19_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM19_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM19_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM19_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM19_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM19_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM19_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM19_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM19_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM19_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM19_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM19_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM19_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM19_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM19_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM19_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM19_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM19_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM19_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM19_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM19_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM19_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM19_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM19_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM19_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM19_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM19_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM19_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM19_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM19_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM19_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM19_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM19_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM19_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM19_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM19_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM19_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM19_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM19_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM19_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM19_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM19_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM19_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM19_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM19_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM19_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM19_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM19_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM19_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM19_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM19_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM19_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM19_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM19_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM19_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM20" base ad:0x50094000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM20_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM20_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM20_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM20_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM20_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM20_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM20_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM20_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM20_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM20_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM20_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM20_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM20_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM20_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM20_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM20_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM20_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM20_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM20_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM20_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM20_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM20_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM20_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM20_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM20_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM20_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM20_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM20_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM20_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM20_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM20_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM20_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM20_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM20_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM20_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM20_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM20_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM20_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM20_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM20_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM20_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM20_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM20_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM20_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM20_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM20_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM20_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM20_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM20_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM20_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM20_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM20_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM20_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM20_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM20_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM20_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM20_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM20_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM20_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM20_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM20_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM20_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM20_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM20_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM20_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM20_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM20_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM20_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM20_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM20_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM20_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM20_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM20_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM20_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM20_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM20_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM20_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM20_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM20_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM20_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM20_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM20_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM20_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM20_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM20_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM20_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM20_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM20_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM20_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM20_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM20_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM20_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM20_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM20_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM20_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM20_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM20_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM20_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM20_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM20_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM20_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM20_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM20_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM20_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM20_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM20_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM20_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM20_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM20_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM20_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM20_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM20_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM20_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM20_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM20_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM20_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM20_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM20_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM20_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM20_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM20_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM20_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM20_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM20_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM20_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM20_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM20_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM20_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM20_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM20_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM20_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM20_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM20_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM20_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM20_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM20_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM21" base ad:0x50095000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM21_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM21_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM21_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM21_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM21_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM21_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM21_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM21_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM21_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM21_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM21_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM21_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM21_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM21_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM21_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM21_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM21_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM21_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM21_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM21_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM21_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM21_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM21_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM21_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM21_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM21_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM21_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM21_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM21_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM21_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM21_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM21_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM21_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM21_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM21_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM21_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM21_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM21_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM21_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM21_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM21_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM21_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM21_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM21_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM21_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM21_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM21_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM21_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM21_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM21_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM21_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM21_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM21_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM21_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM21_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM21_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM21_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM21_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM21_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM21_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM21_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM21_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM21_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM21_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM21_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM21_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM21_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM21_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM21_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM21_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM21_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM21_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM21_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM21_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM21_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM21_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM21_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM21_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM21_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM21_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM21_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM21_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM21_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM21_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM21_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM21_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM21_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM21_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM21_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM21_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM21_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM21_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM21_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM21_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM21_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM21_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM21_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM21_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM21_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM21_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM21_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM21_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM21_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM21_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM21_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM21_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM21_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM21_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM21_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM21_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM21_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM21_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM21_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM21_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM21_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM21_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM21_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM21_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM21_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM21_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM21_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM21_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM21_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM21_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM21_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM21_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM21_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM21_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM21_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM21_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM21_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM21_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM21_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM21_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM21_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM21_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM22" base ad:0x50096000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM22_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM22_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM22_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM22_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM22_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM22_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM22_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM22_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM22_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM22_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM22_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM22_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM22_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM22_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM22_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM22_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM22_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM22_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM22_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM22_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM22_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM22_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM22_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM22_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM22_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM22_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM22_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM22_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM22_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM22_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM22_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM22_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM22_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM22_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM22_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM22_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM22_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM22_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM22_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM22_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM22_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM22_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM22_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM22_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM22_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM22_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM22_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM22_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM22_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM22_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM22_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM22_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM22_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM22_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM22_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM22_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM22_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM22_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM22_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM22_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM22_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM22_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM22_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM22_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM22_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM22_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM22_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM22_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM22_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM22_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM22_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM22_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM22_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM22_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM22_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM22_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM22_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM22_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM22_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM22_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM22_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM22_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM22_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM22_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM22_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM22_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM22_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM22_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM22_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM22_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM22_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM22_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM22_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM22_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM22_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM22_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM22_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM22_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM22_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM22_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM22_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM22_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM22_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM22_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM22_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM22_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM22_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM22_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM22_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM22_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM22_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM22_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM22_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM22_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM22_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM22_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM22_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM22_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM22_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM22_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM22_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM22_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM22_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM22_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM22_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM22_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM22_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM22_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM22_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM22_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM22_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM22_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM22_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM22_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM22_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM22_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM23" base ad:0x50097000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM23_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM23_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM23_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM23_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM23_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM23_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM23_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM23_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM23_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM23_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM23_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM23_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM23_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM23_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM23_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM23_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM23_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM23_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM23_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM23_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM23_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM23_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM23_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM23_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM23_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM23_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM23_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM23_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM23_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM23_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM23_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM23_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM23_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM23_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM23_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM23_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM23_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM23_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM23_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM23_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM23_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM23_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM23_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM23_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM23_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM23_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM23_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM23_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM23_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM23_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM23_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM23_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM23_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM23_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM23_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM23_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM23_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM23_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM23_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM23_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM23_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM23_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM23_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM23_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM23_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM23_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM23_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM23_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM23_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM23_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM23_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM23_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM23_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM23_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM23_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM23_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM23_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM23_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM23_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM23_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM23_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM23_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM23_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM23_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM23_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM23_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM23_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM23_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM23_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM23_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM23_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM23_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM23_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM23_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM23_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM23_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM23_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM23_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM23_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM23_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM23_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM23_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM23_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM23_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM23_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM23_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM23_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM23_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM23_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM23_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM23_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM23_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM23_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM23_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM23_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM23_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM23_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM23_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM23_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM23_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM23_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM23_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM23_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM23_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM23_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM23_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM23_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM23_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM23_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM23_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM23_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM23_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM23_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM23_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM23_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM23_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM24" base ad:0x50098000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM24_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM24_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM24_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM24_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM24_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM24_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM24_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM24_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM24_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM24_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM24_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM24_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM24_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM24_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM24_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM24_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM24_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM24_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM24_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM24_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM24_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM24_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM24_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM24_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM24_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM24_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM24_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM24_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM24_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM24_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM24_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM24_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM24_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM24_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM24_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM24_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM24_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM24_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM24_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM24_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM24_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM24_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM24_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM24_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM24_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM24_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM24_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM24_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM24_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM24_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM24_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM24_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM24_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM24_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM24_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM24_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM24_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM24_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM24_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM24_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM24_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM24_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM24_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM24_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM24_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM24_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM24_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM24_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM24_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM24_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM24_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM24_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM24_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM24_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM24_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM24_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM24_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM24_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM24_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM24_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM24_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM24_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM24_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM24_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM24_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM24_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM24_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM24_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM24_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM24_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM24_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM24_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM24_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM24_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM24_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM24_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM24_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM24_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM24_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM24_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM24_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM24_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM24_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM24_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM24_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM24_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM24_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM24_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM24_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM24_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM24_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM24_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM24_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM24_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM24_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM24_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM24_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM24_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM24_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM24_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM24_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM24_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM24_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM24_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM24_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM24_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM24_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM24_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM24_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM24_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM24_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM24_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM24_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM24_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM24_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM24_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM25" base ad:0x50099000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM25_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM25_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM25_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM25_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM25_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM25_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM25_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM25_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM25_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM25_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM25_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM25_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM25_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM25_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM25_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM25_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM25_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM25_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM25_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM25_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM25_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM25_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM25_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM25_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM25_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM25_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM25_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM25_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM25_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM25_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM25_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM25_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM25_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM25_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM25_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM25_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM25_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM25_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM25_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM25_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM25_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM25_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM25_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM25_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM25_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM25_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM25_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM25_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM25_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM25_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM25_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM25_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM25_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM25_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM25_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM25_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM25_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM25_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM25_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM25_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM25_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM25_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM25_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM25_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM25_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM25_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM25_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM25_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM25_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM25_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM25_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM25_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM25_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM25_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM25_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM25_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM25_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM25_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM25_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM25_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM25_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM25_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM25_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM25_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM25_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM25_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM25_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM25_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM25_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM25_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM25_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM25_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM25_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM25_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM25_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM25_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM25_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM25_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM25_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM25_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM25_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM25_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM25_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM25_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM25_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM25_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM25_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM25_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM25_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM25_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM25_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM25_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM25_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM25_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM25_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM25_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM25_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM25_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM25_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM25_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM25_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM25_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM25_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM25_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM25_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM25_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM25_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM25_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM25_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM25_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM25_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM25_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM25_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM25_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM25_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM25_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM26" base ad:0x5009A000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM26_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM26_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM26_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM26_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM26_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM26_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM26_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM26_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM26_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM26_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM26_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM26_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM26_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM26_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM26_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM26_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM26_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM26_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM26_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM26_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM26_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM26_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM26_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM26_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM26_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM26_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM26_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM26_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM26_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM26_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM26_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM26_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM26_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM26_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM26_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM26_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM26_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM26_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM26_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM26_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM26_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM26_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM26_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM26_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM26_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM26_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM26_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM26_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM26_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM26_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM26_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM26_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM26_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM26_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM26_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM26_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM26_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM26_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM26_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM26_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM26_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM26_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM26_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM26_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM26_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM26_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM26_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM26_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM26_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM26_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM26_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM26_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM26_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM26_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM26_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM26_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM26_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM26_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM26_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM26_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM26_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM26_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM26_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM26_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM26_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM26_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM26_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM26_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM26_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM26_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM26_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM26_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM26_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM26_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM26_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM26_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM26_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM26_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM26_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM26_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM26_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM26_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM26_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM26_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM26_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM26_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM26_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM26_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM26_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM26_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM26_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM26_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM26_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM26_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM26_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM26_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM26_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM26_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM26_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM26_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM26_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM26_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM26_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM26_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM26_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM26_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM26_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM26_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM26_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM26_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM26_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM26_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM26_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM26_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM26_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM26_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM27" base ad:0x5009B000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM27_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM27_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM27_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM27_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM27_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM27_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM27_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM27_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM27_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM27_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM27_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM27_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM27_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM27_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM27_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM27_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM27_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM27_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM27_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM27_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM27_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM27_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM27_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM27_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM27_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM27_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM27_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM27_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM27_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM27_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM27_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM27_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM27_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM27_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM27_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM27_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM27_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM27_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM27_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM27_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM27_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM27_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM27_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM27_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM27_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM27_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM27_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM27_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM27_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM27_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM27_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM27_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM27_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM27_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM27_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM27_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM27_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM27_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM27_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM27_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM27_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM27_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM27_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM27_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM27_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM27_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM27_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM27_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM27_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM27_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM27_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM27_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM27_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM27_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM27_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM27_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM27_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM27_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM27_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM27_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM27_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM27_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM27_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM27_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM27_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM27_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM27_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM27_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM27_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM27_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM27_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM27_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM27_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM27_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM27_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM27_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM27_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM27_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM27_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM27_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM27_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM27_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM27_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM27_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM27_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM27_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM27_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM27_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM27_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM27_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM27_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM27_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM27_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM27_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM27_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM27_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM27_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM27_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM27_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM27_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM27_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM27_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM27_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM27_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM27_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM27_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM27_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM27_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM27_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM27_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM27_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM27_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM27_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM27_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM27_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM27_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM28" base ad:0x5009C000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM28_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM28_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM28_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM28_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM28_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM28_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM28_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM28_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM28_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM28_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM28_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM28_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM28_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM28_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM28_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM28_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM28_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM28_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM28_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM28_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM28_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM28_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM28_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM28_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM28_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM28_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM28_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM28_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM28_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM28_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM28_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM28_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM28_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM28_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM28_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM28_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM28_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM28_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM28_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM28_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM28_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM28_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM28_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM28_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM28_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM28_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM28_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM28_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM28_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM28_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM28_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM28_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM28_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM28_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM28_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM28_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM28_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM28_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM28_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM28_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM28_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM28_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM28_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM28_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM28_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM28_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM28_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM28_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM28_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM28_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM28_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM28_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM28_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM28_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM28_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM28_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM28_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM28_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM28_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM28_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM28_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM28_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM28_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM28_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM28_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM28_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM28_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM28_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM28_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM28_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM28_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM28_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM28_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM28_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM28_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM28_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM28_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM28_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM28_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM28_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM28_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM28_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM28_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM28_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM28_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM28_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM28_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM28_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM28_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM28_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM28_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM28_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM28_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM28_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM28_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM28_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM28_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM28_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM28_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM28_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM28_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM28_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM28_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM28_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM28_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM28_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM28_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM28_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM28_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM28_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM28_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM28_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM28_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM28_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM28_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM28_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM29" base ad:0x5009D000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM29_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM29_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM29_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM29_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM29_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM29_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM29_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM29_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM29_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM29_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM29_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM29_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM29_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM29_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM29_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM29_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM29_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM29_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM29_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM29_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM29_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM29_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM29_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM29_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM29_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM29_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM29_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM29_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM29_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM29_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM29_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM29_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM29_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM29_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM29_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM29_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM29_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM29_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM29_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM29_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM29_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM29_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM29_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM29_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM29_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM29_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM29_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM29_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM29_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM29_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM29_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM29_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM29_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM29_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM29_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM29_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM29_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM29_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM29_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM29_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM29_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM29_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM29_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM29_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM29_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM29_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM29_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM29_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM29_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM29_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM29_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM29_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM29_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM29_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM29_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM29_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM29_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM29_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM29_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM29_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM29_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM29_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM29_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM29_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM29_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM29_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM29_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM29_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM29_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM29_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM29_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM29_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM29_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM29_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM29_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM29_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM29_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM29_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM29_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM29_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM29_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM29_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM29_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM29_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM29_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM29_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM29_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM29_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM29_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM29_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM29_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM29_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM29_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM29_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM29_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM29_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM29_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM29_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM29_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM29_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM29_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM29_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM29_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM29_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM29_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM29_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM29_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM29_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM29_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM29_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM29_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM29_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM29_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM29_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM29_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM29_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM30" base ad:0x5009E000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM30_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM30_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM30_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM30_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM30_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM30_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM30_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM30_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM30_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM30_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM30_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM30_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM30_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM30_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM30_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM30_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM30_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM30_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM30_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM30_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM30_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM30_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM30_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM30_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM30_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM30_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM30_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM30_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM30_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM30_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM30_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM30_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM30_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM30_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM30_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM30_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM30_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM30_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM30_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM30_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM30_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM30_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM30_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM30_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM30_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM30_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM30_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM30_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM30_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM30_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM30_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM30_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM30_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM30_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM30_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM30_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM30_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM30_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM30_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM30_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM30_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM30_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM30_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM30_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM30_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM30_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM30_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM30_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM30_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM30_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM30_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM30_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM30_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM30_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM30_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM30_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM30_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM30_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM30_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM30_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM30_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM30_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM30_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM30_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM30_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM30_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM30_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM30_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM30_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM30_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM30_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM30_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM30_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM30_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM30_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM30_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM30_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM30_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM30_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM30_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM30_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM30_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM30_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM30_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM30_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM30_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM30_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM30_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM30_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM30_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM30_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM30_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM30_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM30_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM30_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM30_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM30_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM30_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM30_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM30_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM30_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM30_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM30_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM30_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM30_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM30_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM30_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM30_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM30_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM30_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM30_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM30_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM30_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM30_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM30_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM30_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G2_EPWM31" base ad:0x5009F000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM31_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G2_EPWM31_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G2_EPWM31_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G2_EPWM31_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G2_EPWM31_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G2_EPWM31_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G2_EPWM31_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G2_EPWM31_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G2_EPWM31_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G2_EPWM31_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM31_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G2_EPWM31_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G2_EPWM31_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G2_EPWM31_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G2_EPWM31_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM31_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G2_EPWM31_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G2_EPWM31_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G2_EPWM31_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G2_EPWM31_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G2_EPWM31_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G2_EPWM31_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G2_EPWM31_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G2_EPWM31_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G2_EPWM31_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G2_EPWM31_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G2_EPWM31_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G2_EPWM31_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G2_EPWM31_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G2_EPWM31_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G2_EPWM31_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G2_EPWM31_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G2_EPWM31_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G2_EPWM31_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G2_EPWM31_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G2_EPWM31_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G2_EPWM31_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G2_EPWM31_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM31_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G2_EPWM31_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G2_EPWM31_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G2_EPWM31_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G2_EPWM31_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G2_EPWM31_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G2_EPWM31_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G2_EPWM31_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G2_EPWM31_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM31_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G2_EPWM31_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G2_EPWM31_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G2_EPWM31_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G2_EPWM31_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G2_EPWM31_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G2_EPWM31_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G2_EPWM31_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G2_EPWM31_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G2_EPWM31_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G2_EPWM31_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G2_EPWM31_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G2_EPWM31_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G2_EPWM31_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G2_EPWM31_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G2_EPWM31_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G2_EPWM31_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G2_EPWM31_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM31_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G2_EPWM31_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G2_EPWM31_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G2_EPWM31_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G2_EPWM31_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G2_EPWM31_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G2_EPWM31_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G2_EPWM31_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G2_EPWM31_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G2_EPWM31_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G2_EPWM31_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM31_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM31_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM31_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM31_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM31_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM31_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM31_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM31_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G2_EPWM31_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G2_EPWM31_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM31_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM31_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM31_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM31_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM31_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM31_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM31_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM31_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM31_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM31_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM31_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G2_EPWM31_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM31_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM31_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM31_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM31_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM31_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM31_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM31_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM31_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G2_EPWM31_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM31_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G2_EPWM31_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G2_EPWM31_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G2_EPWM31_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G2_EPWM31_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G2_EPWM31_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G2_EPWM31_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G2_EPWM31_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G2_EPWM31_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G2_EPWM31_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G2_EPWM31_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G2_EPWM31_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G2_EPWM31_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G2_EPWM31_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G2_EPWM31_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G2_EPWM31_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G2_EPWM31_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G2_EPWM31_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G2_EPWM31_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G2_EPWM31_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G2_EPWM31_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G2_EPWM31_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G2_EPWM31_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G2_EPWM31_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G2_EPWM31_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G2_EPWM31_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G2_EPWM31_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G2_EPWM31_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G2_EPWM31_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree "EPWM_G3" tree "G3_EPWM0" base ad:0x500C0000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM0_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM0_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM0_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM0_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM0_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM0_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM0_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM0_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM0_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM0_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM0_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM0_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM0_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM0_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM0_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM0_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM0_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM0_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM0_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM0_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM0_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM0_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM0_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM0_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM0_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM0_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM0_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM0_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM0_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM0_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM0_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM0_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM0_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM0_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM0_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM0_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM0_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM0_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM0_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM0_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM0_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM0_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM0_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM0_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM0_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM0_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM0_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM0_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM0_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM0_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM0_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM0_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM0_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM0_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM0_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM0_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM0_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM0_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM0_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM0_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM0_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM0_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM0_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM0_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM0_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM0_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM0_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM0_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM0_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM0_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM0_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM0_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM0_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM0_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM0_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM0_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM0_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM0_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM0_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM0_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM0_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM0_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM0_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM0_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM0_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM0_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM0_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM0_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM0_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM0_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM0_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM0_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM0_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM0_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM0_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM0_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM0_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM0_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM0_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM0_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM0_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM0_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM0_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM0_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM0_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM0_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM0_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM0_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM0_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM0_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM0_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM0_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM0_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM0_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM0_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM0_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM0_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM0_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM0_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM0_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM0_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM0_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM0_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM0_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM0_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM0_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM0_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM0_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM0_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM0_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM0_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM0_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM0_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM0_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM0_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM0_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM1" base ad:0x500C1000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM1_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM1_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM1_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM1_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM1_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM1_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM1_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM1_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM1_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM1_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM1_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM1_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM1_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM1_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM1_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM1_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM1_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM1_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM1_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM1_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM1_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM1_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM1_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM1_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM1_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM1_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM1_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM1_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM1_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM1_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM1_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM1_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM1_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM1_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM1_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM1_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM1_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM1_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM1_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM1_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM1_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM1_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM1_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM1_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM1_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM1_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM1_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM1_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM1_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM1_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM1_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM1_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM1_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM1_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM1_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM1_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM1_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM1_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM1_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM1_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM1_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM1_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM1_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM1_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM1_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM1_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM1_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM1_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM1_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM1_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM1_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM1_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM1_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM1_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM1_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM1_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM1_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM1_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM1_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM1_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM1_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM1_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM1_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM1_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM1_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM1_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM1_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM1_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM1_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM1_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM1_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM1_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM1_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM1_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM1_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM1_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM1_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM1_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM1_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM1_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM1_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM1_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM1_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM1_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM1_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM1_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM1_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM1_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM1_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM1_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM1_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM1_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM1_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM1_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM1_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM1_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM1_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM1_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM1_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM1_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM1_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM1_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM1_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM1_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM1_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM1_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM1_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM1_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM1_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM1_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM1_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM1_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM1_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM1_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM1_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM1_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM2" base ad:0x500C2000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM2_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM2_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM2_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM2_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM2_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM2_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM2_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM2_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM2_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM2_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM2_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM2_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM2_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM2_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM2_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM2_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM2_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM2_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM2_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM2_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM2_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM2_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM2_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM2_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM2_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM2_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM2_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM2_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM2_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM2_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM2_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM2_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM2_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM2_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM2_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM2_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM2_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM2_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM2_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM2_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM2_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM2_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM2_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM2_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM2_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM2_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM2_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM2_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM2_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM2_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM2_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM2_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM2_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM2_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM2_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM2_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM2_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM2_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM2_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM2_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM2_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM2_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM2_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM2_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM2_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM2_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM2_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM2_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM2_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM2_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM2_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM2_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM2_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM2_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM2_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM2_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM2_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM2_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM2_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM2_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM2_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM2_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM2_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM2_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM2_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM2_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM2_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM2_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM2_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM2_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM2_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM2_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM2_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM2_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM2_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM2_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM2_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM2_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM2_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM2_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM2_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM2_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM2_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM2_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM2_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM2_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM2_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM2_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM2_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM2_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM2_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM2_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM2_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM2_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM2_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM2_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM2_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM2_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM2_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM2_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM2_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM2_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM2_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM2_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM2_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM2_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM2_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM2_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM2_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM2_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM2_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM2_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM2_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM2_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM2_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM2_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM3" base ad:0x500C3000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM3_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM3_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM3_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM3_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM3_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM3_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM3_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM3_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM3_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM3_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM3_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM3_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM3_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM3_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM3_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM3_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM3_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM3_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM3_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM3_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM3_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM3_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM3_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM3_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM3_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM3_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM3_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM3_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM3_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM3_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM3_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM3_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM3_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM3_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM3_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM3_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM3_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM3_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM3_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM3_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM3_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM3_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM3_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM3_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM3_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM3_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM3_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM3_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM3_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM3_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM3_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM3_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM3_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM3_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM3_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM3_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM3_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM3_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM3_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM3_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM3_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM3_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM3_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM3_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM3_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM3_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM3_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM3_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM3_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM3_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM3_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM3_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM3_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM3_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM3_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM3_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM3_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM3_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM3_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM3_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM3_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM3_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM3_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM3_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM3_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM3_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM3_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM3_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM3_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM3_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM3_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM3_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM3_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM3_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM3_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM3_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM3_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM3_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM3_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM3_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM3_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM3_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM3_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM3_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM3_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM3_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM3_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM3_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM3_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM3_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM3_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM3_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM3_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM3_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM3_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM3_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM3_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM3_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM3_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM3_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM3_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM3_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM3_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM3_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM3_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM3_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM3_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM3_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM3_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM3_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM3_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM3_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM3_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM3_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM3_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM3_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM4" base ad:0x500C4000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM4_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM4_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM4_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM4_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM4_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM4_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM4_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM4_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM4_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM4_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM4_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM4_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM4_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM4_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM4_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM4_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM4_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM4_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM4_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM4_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM4_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM4_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM4_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM4_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM4_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM4_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM4_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM4_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM4_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM4_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM4_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM4_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM4_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM4_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM4_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM4_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM4_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM4_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM4_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM4_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM4_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM4_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM4_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM4_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM4_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM4_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM4_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM4_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM4_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM4_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM4_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM4_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM4_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM4_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM4_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM4_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM4_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM4_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM4_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM4_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM4_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM4_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM4_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM4_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM4_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM4_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM4_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM4_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM4_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM4_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM4_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM4_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM4_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM4_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM4_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM4_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM4_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM4_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM4_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM4_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM4_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM4_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM4_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM4_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM4_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM4_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM4_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM4_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM4_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM4_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM4_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM4_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM4_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM4_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM4_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM4_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM4_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM4_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM4_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM4_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM4_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM4_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM4_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM4_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM4_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM4_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM4_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM4_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM4_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM4_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM4_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM4_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM4_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM4_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM4_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM4_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM4_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM4_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM4_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM4_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM4_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM4_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM4_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM4_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM4_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM4_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM4_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM4_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM4_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM4_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM4_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM4_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM4_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM4_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM4_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM4_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM5" base ad:0x500C5000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM5_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM5_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM5_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM5_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM5_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM5_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM5_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM5_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM5_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM5_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM5_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM5_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM5_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM5_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM5_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM5_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM5_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM5_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM5_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM5_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM5_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM5_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM5_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM5_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM5_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM5_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM5_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM5_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM5_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM5_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM5_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM5_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM5_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM5_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM5_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM5_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM5_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM5_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM5_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM5_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM5_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM5_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM5_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM5_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM5_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM5_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM5_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM5_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM5_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM5_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM5_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM5_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM5_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM5_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM5_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM5_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM5_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM5_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM5_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM5_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM5_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM5_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM5_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM5_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM5_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM5_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM5_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM5_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM5_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM5_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM5_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM5_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM5_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM5_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM5_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM5_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM5_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM5_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM5_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM5_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM5_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM5_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM5_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM5_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM5_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM5_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM5_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM5_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM5_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM5_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM5_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM5_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM5_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM5_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM5_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM5_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM5_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM5_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM5_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM5_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM5_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM5_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM5_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM5_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM5_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM5_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM5_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM5_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM5_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM5_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM5_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM5_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM5_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM5_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM5_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM5_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM5_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM5_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM5_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM5_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM5_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM5_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM5_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM5_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM5_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM5_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM5_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM5_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM5_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM5_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM5_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM5_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM5_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM5_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM5_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM5_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM6" base ad:0x500C6000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM6_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM6_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM6_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM6_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM6_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM6_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM6_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM6_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM6_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM6_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM6_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM6_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM6_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM6_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM6_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM6_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM6_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM6_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM6_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM6_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM6_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM6_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM6_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM6_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM6_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM6_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM6_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM6_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM6_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM6_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM6_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM6_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM6_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM6_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM6_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM6_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM6_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM6_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM6_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM6_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM6_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM6_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM6_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM6_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM6_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM6_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM6_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM6_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM6_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM6_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM6_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM6_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM6_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM6_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM6_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM6_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM6_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM6_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM6_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM6_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM6_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM6_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM6_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM6_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM6_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM6_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM6_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM6_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM6_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM6_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM6_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM6_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM6_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM6_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM6_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM6_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM6_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM6_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM6_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM6_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM6_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM6_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM6_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM6_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM6_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM6_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM6_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM6_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM6_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM6_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM6_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM6_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM6_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM6_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM6_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM6_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM6_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM6_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM6_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM6_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM6_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM6_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM6_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM6_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM6_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM6_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM6_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM6_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM6_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM6_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM6_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM6_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM6_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM6_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM6_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM6_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM6_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM6_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM6_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM6_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM6_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM6_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM6_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM6_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM6_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM6_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM6_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM6_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM6_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM6_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM6_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM6_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM6_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM6_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM6_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM6_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM7" base ad:0x500C7000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM7_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM7_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM7_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM7_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM7_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM7_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM7_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM7_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM7_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM7_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM7_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM7_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM7_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM7_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM7_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM7_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM7_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM7_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM7_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM7_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM7_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM7_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM7_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM7_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM7_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM7_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM7_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM7_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM7_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM7_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM7_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM7_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM7_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM7_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM7_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM7_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM7_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM7_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM7_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM7_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM7_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM7_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM7_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM7_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM7_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM7_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM7_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM7_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM7_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM7_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM7_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM7_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM7_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM7_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM7_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM7_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM7_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM7_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM7_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM7_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM7_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM7_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM7_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM7_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM7_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM7_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM7_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM7_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM7_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM7_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM7_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM7_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM7_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM7_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM7_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM7_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM7_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM7_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM7_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM7_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM7_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM7_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM7_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM7_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM7_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM7_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM7_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM7_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM7_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM7_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM7_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM7_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM7_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM7_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM7_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM7_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM7_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM7_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM7_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM7_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM7_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM7_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM7_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM7_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM7_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM7_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM7_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM7_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM7_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM7_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM7_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM7_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM7_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM7_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM7_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM7_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM7_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM7_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM7_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM7_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM7_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM7_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM7_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM7_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM7_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM7_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM7_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM7_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM7_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM7_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM7_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM7_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM7_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM7_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM7_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM7_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM8" base ad:0x500C8000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM8_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM8_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM8_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM8_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM8_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM8_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM8_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM8_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM8_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM8_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM8_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM8_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM8_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM8_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM8_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM8_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM8_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM8_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM8_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM8_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM8_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM8_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM8_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM8_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM8_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM8_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM8_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM8_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM8_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM8_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM8_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM8_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM8_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM8_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM8_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM8_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM8_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM8_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM8_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM8_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM8_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM8_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM8_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM8_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM8_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM8_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM8_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM8_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM8_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM8_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM8_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM8_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM8_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM8_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM8_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM8_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM8_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM8_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM8_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM8_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM8_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM8_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM8_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM8_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM8_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM8_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM8_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM8_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM8_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM8_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM8_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM8_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM8_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM8_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM8_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM8_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM8_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM8_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM8_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM8_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM8_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM8_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM8_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM8_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM8_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM8_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM8_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM8_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM8_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM8_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM8_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM8_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM8_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM8_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM8_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM8_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM8_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM8_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM8_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM8_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM8_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM8_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM8_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM8_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM8_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM8_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM8_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM8_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM8_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM8_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM8_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM8_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM8_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM8_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM8_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM8_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM8_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM8_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM8_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM8_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM8_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM8_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM8_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM8_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM8_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM8_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM8_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM8_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM8_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM8_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM8_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM8_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM8_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM8_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM8_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM8_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM9" base ad:0x500C9000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM9_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM9_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM9_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM9_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM9_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM9_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM9_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM9_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM9_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM9_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM9_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM9_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM9_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM9_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM9_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM9_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM9_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM9_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM9_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM9_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM9_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM9_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM9_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM9_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM9_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM9_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM9_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM9_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM9_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM9_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM9_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM9_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM9_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM9_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM9_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM9_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM9_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM9_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM9_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM9_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM9_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM9_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM9_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM9_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM9_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM9_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM9_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM9_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM9_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM9_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM9_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM9_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM9_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM9_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM9_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM9_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM9_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM9_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM9_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM9_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM9_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM9_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM9_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM9_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM9_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM9_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM9_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM9_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM9_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM9_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM9_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM9_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM9_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM9_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM9_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM9_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM9_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM9_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM9_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM9_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM9_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM9_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM9_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM9_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM9_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM9_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM9_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM9_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM9_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM9_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM9_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM9_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM9_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM9_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM9_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM9_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM9_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM9_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM9_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM9_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM9_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM9_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM9_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM9_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM9_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM9_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM9_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM9_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM9_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM9_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM9_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM9_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM9_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM9_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM9_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM9_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM9_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM9_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM9_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM9_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM9_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM9_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM9_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM9_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM9_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM9_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM9_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM9_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM9_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM9_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM9_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM9_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM9_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM9_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM9_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM9_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM10" base ad:0x500CA000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM10_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM10_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM10_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM10_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM10_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM10_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM10_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM10_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM10_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM10_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM10_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM10_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM10_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM10_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM10_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM10_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM10_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM10_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM10_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM10_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM10_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM10_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM10_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM10_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM10_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM10_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM10_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM10_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM10_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM10_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM10_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM10_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM10_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM10_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM10_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM10_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM10_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM10_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM10_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM10_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM10_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM10_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM10_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM10_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM10_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM10_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM10_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM10_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM10_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM10_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM10_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM10_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM10_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM10_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM10_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM10_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM10_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM10_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM10_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM10_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM10_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM10_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM10_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM10_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM10_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM10_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM10_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM10_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM10_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM10_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM10_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM10_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM10_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM10_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM10_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM10_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM10_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM10_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM10_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM10_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM10_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM10_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM10_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM10_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM10_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM10_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM10_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM10_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM10_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM10_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM10_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM10_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM10_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM10_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM10_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM10_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM10_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM10_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM10_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM10_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM10_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM10_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM10_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM10_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM10_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM10_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM10_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM10_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM10_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM10_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM10_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM10_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM10_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM10_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM10_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM10_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM10_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM10_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM10_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM10_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM10_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM10_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM10_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM10_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM10_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM10_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM10_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM10_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM10_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM10_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM10_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM10_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM10_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM10_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM10_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM10_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM11" base ad:0x500CB000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM11_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM11_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM11_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM11_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM11_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM11_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM11_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM11_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM11_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM11_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM11_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM11_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM11_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM11_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM11_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM11_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM11_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM11_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM11_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM11_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM11_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM11_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM11_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM11_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM11_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM11_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM11_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM11_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM11_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM11_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM11_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM11_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM11_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM11_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM11_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM11_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM11_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM11_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM11_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM11_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM11_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM11_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM11_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM11_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM11_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM11_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM11_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM11_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM11_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM11_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM11_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM11_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM11_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM11_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM11_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM11_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM11_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM11_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM11_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM11_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM11_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM11_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM11_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM11_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM11_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM11_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM11_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM11_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM11_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM11_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM11_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM11_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM11_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM11_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM11_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM11_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM11_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM11_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM11_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM11_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM11_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM11_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM11_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM11_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM11_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM11_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM11_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM11_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM11_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM11_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM11_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM11_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM11_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM11_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM11_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM11_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM11_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM11_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM11_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM11_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM11_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM11_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM11_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM11_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM11_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM11_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM11_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM11_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM11_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM11_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM11_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM11_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM11_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM11_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM11_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM11_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM11_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM11_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM11_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM11_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM11_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM11_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM11_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM11_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM11_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM11_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM11_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM11_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM11_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM11_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM11_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM11_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM11_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM11_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM11_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM11_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM12" base ad:0x500CC000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM12_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM12_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM12_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM12_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM12_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM12_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM12_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM12_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM12_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM12_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM12_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM12_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM12_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM12_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM12_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM12_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM12_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM12_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM12_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM12_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM12_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM12_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM12_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM12_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM12_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM12_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM12_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM12_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM12_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM12_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM12_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM12_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM12_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM12_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM12_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM12_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM12_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM12_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM12_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM12_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM12_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM12_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM12_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM12_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM12_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM12_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM12_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM12_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM12_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM12_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM12_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM12_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM12_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM12_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM12_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM12_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM12_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM12_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM12_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM12_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM12_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM12_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM12_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM12_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM12_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM12_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM12_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM12_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM12_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM12_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM12_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM12_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM12_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM12_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM12_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM12_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM12_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM12_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM12_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM12_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM12_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM12_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM12_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM12_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM12_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM12_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM12_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM12_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM12_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM12_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM12_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM12_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM12_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM12_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM12_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM12_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM12_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM12_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM12_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM12_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM12_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM12_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM12_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM12_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM12_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM12_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM12_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM12_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM12_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM12_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM12_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM12_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM12_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM12_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM12_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM12_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM12_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM12_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM12_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM12_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM12_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM12_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM12_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM12_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM12_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM12_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM12_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM12_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM12_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM12_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM12_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM12_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM12_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM12_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM12_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM12_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM13" base ad:0x500CD000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM13_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM13_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM13_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM13_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM13_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM13_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM13_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM13_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM13_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM13_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM13_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM13_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM13_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM13_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM13_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM13_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM13_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM13_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM13_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM13_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM13_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM13_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM13_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM13_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM13_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM13_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM13_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM13_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM13_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM13_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM13_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM13_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM13_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM13_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM13_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM13_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM13_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM13_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM13_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM13_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM13_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM13_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM13_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM13_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM13_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM13_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM13_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM13_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM13_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM13_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM13_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM13_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM13_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM13_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM13_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM13_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM13_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM13_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM13_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM13_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM13_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM13_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM13_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM13_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM13_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM13_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM13_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM13_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM13_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM13_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM13_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM13_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM13_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM13_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM13_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM13_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM13_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM13_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM13_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM13_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM13_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM13_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM13_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM13_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM13_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM13_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM13_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM13_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM13_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM13_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM13_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM13_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM13_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM13_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM13_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM13_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM13_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM13_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM13_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM13_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM13_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM13_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM13_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM13_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM13_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM13_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM13_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM13_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM13_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM13_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM13_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM13_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM13_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM13_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM13_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM13_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM13_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM13_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM13_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM13_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM13_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM13_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM13_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM13_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM13_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM13_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM13_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM13_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM13_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM13_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM13_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM13_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM13_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM13_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM13_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM13_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM14" base ad:0x500CE000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM14_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM14_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM14_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM14_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM14_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM14_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM14_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM14_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM14_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM14_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM14_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM14_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM14_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM14_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM14_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM14_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM14_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM14_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM14_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM14_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM14_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM14_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM14_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM14_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM14_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM14_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM14_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM14_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM14_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM14_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM14_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM14_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM14_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM14_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM14_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM14_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM14_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM14_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM14_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM14_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM14_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM14_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM14_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM14_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM14_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM14_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM14_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM14_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM14_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM14_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM14_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM14_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM14_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM14_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM14_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM14_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM14_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM14_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM14_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM14_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM14_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM14_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM14_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM14_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM14_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM14_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM14_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM14_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM14_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM14_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM14_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM14_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM14_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM14_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM14_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM14_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM14_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM14_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM14_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM14_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM14_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM14_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM14_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM14_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM14_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM14_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM14_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM14_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM14_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM14_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM14_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM14_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM14_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM14_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM14_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM14_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM14_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM14_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM14_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM14_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM14_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM14_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM14_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM14_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM14_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM14_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM14_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM14_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM14_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM14_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM14_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM14_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM14_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM14_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM14_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM14_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM14_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM14_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM14_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM14_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM14_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM14_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM14_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM14_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM14_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM14_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM14_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM14_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM14_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM14_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM14_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM14_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM14_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM14_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM14_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM14_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM15" base ad:0x500CF000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM15_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM15_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM15_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM15_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM15_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM15_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM15_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM15_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM15_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM15_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM15_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM15_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM15_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM15_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM15_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM15_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM15_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM15_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM15_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM15_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM15_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM15_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM15_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM15_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM15_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM15_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM15_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM15_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM15_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM15_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM15_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM15_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM15_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM15_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM15_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM15_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM15_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM15_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM15_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM15_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM15_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM15_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM15_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM15_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM15_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM15_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM15_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM15_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM15_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM15_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM15_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM15_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM15_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM15_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM15_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM15_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM15_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM15_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM15_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM15_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM15_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM15_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM15_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM15_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM15_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM15_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM15_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM15_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM15_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM15_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM15_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM15_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM15_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM15_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM15_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM15_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM15_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM15_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM15_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM15_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM15_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM15_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM15_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM15_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM15_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM15_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM15_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM15_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM15_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM15_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM15_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM15_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM15_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM15_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM15_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM15_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM15_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM15_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM15_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM15_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM15_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM15_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM15_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM15_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM15_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM15_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM15_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM15_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM15_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM15_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM15_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM15_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM15_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM15_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM15_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM15_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM15_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM15_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM15_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM15_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM15_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM15_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM15_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM15_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM15_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM15_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM15_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM15_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM15_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM15_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM15_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM15_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM15_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM15_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM15_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM15_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM16" base ad:0x500D0000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM16_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM16_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM16_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM16_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM16_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM16_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM16_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM16_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM16_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM16_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM16_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM16_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM16_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM16_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM16_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM16_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM16_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM16_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM16_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM16_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM16_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM16_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM16_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM16_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM16_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM16_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM16_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM16_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM16_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM16_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM16_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM16_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM16_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM16_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM16_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM16_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM16_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM16_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM16_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM16_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM16_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM16_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM16_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM16_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM16_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM16_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM16_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM16_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM16_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM16_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM16_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM16_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM16_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM16_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM16_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM16_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM16_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM16_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM16_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM16_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM16_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM16_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM16_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM16_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM16_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM16_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM16_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM16_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM16_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM16_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM16_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM16_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM16_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM16_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM16_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM16_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM16_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM16_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM16_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM16_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM16_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM16_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM16_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM16_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM16_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM16_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM16_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM16_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM16_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM16_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM16_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM16_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM16_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM16_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM16_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM16_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM16_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM16_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM16_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM16_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM16_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM16_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM16_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM16_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM16_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM16_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM16_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM16_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM16_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM16_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM16_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM16_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM16_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM16_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM16_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM16_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM16_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM16_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM16_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM16_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM16_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM16_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM16_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM16_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM16_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM16_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM16_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM16_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM16_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM16_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM16_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM16_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM16_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM16_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM16_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM16_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM17" base ad:0x500D1000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM17_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM17_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM17_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM17_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM17_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM17_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM17_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM17_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM17_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM17_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM17_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM17_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM17_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM17_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM17_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM17_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM17_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM17_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM17_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM17_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM17_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM17_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM17_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM17_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM17_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM17_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM17_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM17_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM17_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM17_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM17_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM17_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM17_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM17_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM17_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM17_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM17_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM17_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM17_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM17_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM17_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM17_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM17_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM17_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM17_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM17_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM17_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM17_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM17_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM17_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM17_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM17_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM17_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM17_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM17_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM17_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM17_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM17_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM17_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM17_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM17_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM17_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM17_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM17_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM17_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM17_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM17_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM17_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM17_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM17_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM17_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM17_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM17_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM17_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM17_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM17_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM17_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM17_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM17_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM17_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM17_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM17_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM17_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM17_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM17_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM17_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM17_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM17_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM17_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM17_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM17_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM17_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM17_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM17_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM17_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM17_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM17_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM17_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM17_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM17_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM17_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM17_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM17_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM17_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM17_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM17_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM17_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM17_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM17_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM17_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM17_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM17_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM17_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM17_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM17_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM17_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM17_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM17_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM17_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM17_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM17_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM17_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM17_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM17_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM17_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM17_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM17_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM17_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM17_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM17_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM17_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM17_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM17_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM17_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM17_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM17_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM18" base ad:0x500D2000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM18_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM18_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM18_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM18_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM18_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM18_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM18_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM18_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM18_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM18_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM18_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM18_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM18_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM18_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM18_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM18_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM18_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM18_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM18_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM18_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM18_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM18_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM18_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM18_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM18_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM18_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM18_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM18_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM18_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM18_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM18_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM18_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM18_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM18_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM18_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM18_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM18_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM18_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM18_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM18_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM18_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM18_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM18_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM18_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM18_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM18_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM18_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM18_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM18_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM18_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM18_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM18_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM18_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM18_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM18_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM18_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM18_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM18_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM18_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM18_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM18_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM18_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM18_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM18_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM18_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM18_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM18_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM18_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM18_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM18_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM18_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM18_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM18_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM18_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM18_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM18_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM18_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM18_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM18_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM18_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM18_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM18_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM18_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM18_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM18_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM18_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM18_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM18_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM18_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM18_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM18_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM18_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM18_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM18_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM18_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM18_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM18_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM18_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM18_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM18_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM18_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM18_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM18_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM18_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM18_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM18_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM18_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM18_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM18_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM18_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM18_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM18_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM18_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM18_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM18_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM18_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM18_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM18_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM18_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM18_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM18_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM18_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM18_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM18_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM18_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM18_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM18_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM18_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM18_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM18_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM18_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM18_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM18_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM18_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM18_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM18_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM19" base ad:0x500D3000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM19_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM19_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM19_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM19_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM19_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM19_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM19_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM19_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM19_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM19_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM19_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM19_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM19_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM19_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM19_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM19_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM19_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM19_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM19_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM19_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM19_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM19_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM19_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM19_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM19_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM19_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM19_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM19_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM19_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM19_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM19_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM19_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM19_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM19_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM19_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM19_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM19_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM19_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM19_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM19_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM19_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM19_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM19_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM19_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM19_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM19_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM19_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM19_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM19_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM19_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM19_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM19_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM19_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM19_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM19_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM19_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM19_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM19_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM19_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM19_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM19_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM19_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM19_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM19_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM19_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM19_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM19_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM19_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM19_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM19_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM19_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM19_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM19_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM19_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM19_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM19_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM19_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM19_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM19_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM19_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM19_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM19_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM19_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM19_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM19_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM19_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM19_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM19_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM19_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM19_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM19_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM19_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM19_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM19_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM19_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM19_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM19_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM19_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM19_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM19_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM19_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM19_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM19_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM19_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM19_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM19_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM19_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM19_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM19_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM19_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM19_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM19_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM19_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM19_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM19_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM19_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM19_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM19_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM19_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM19_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM19_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM19_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM19_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM19_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM19_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM19_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM19_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM19_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM19_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM19_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM19_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM19_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM19_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM19_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM19_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM19_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM20" base ad:0x500D4000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM20_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM20_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM20_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM20_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM20_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM20_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM20_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM20_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM20_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM20_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM20_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM20_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM20_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM20_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM20_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM20_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM20_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM20_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM20_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM20_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM20_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM20_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM20_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM20_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM20_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM20_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM20_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM20_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM20_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM20_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM20_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM20_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM20_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM20_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM20_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM20_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM20_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM20_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM20_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM20_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM20_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM20_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM20_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM20_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM20_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM20_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM20_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM20_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM20_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM20_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM20_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM20_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM20_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM20_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM20_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM20_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM20_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM20_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM20_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM20_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM20_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM20_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM20_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM20_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM20_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM20_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM20_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM20_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM20_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM20_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM20_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM20_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM20_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM20_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM20_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM20_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM20_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM20_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM20_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM20_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM20_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM20_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM20_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM20_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM20_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM20_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM20_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM20_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM20_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM20_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM20_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM20_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM20_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM20_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM20_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM20_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM20_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM20_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM20_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM20_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM20_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM20_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM20_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM20_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM20_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM20_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM20_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM20_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM20_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM20_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM20_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM20_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM20_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM20_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM20_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM20_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM20_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM20_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM20_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM20_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM20_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM20_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM20_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM20_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM20_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM20_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM20_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM20_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM20_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM20_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM20_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM20_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM20_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM20_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM20_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM20_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM21" base ad:0x500D5000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM21_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM21_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM21_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM21_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM21_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM21_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM21_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM21_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM21_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM21_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM21_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM21_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM21_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM21_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM21_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM21_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM21_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM21_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM21_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM21_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM21_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM21_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM21_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM21_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM21_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM21_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM21_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM21_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM21_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM21_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM21_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM21_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM21_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM21_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM21_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM21_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM21_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM21_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM21_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM21_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM21_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM21_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM21_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM21_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM21_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM21_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM21_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM21_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM21_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM21_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM21_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM21_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM21_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM21_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM21_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM21_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM21_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM21_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM21_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM21_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM21_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM21_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM21_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM21_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM21_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM21_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM21_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM21_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM21_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM21_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM21_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM21_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM21_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM21_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM21_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM21_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM21_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM21_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM21_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM21_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM21_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM21_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM21_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM21_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM21_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM21_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM21_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM21_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM21_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM21_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM21_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM21_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM21_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM21_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM21_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM21_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM21_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM21_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM21_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM21_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM21_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM21_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM21_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM21_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM21_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM21_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM21_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM21_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM21_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM21_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM21_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM21_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM21_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM21_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM21_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM21_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM21_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM21_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM21_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM21_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM21_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM21_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM21_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM21_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM21_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM21_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM21_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM21_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM21_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM21_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM21_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM21_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM21_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM21_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM21_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM21_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM22" base ad:0x500D6000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM22_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM22_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM22_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM22_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM22_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM22_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM22_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM22_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM22_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM22_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM22_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM22_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM22_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM22_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM22_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM22_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM22_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM22_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM22_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM22_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM22_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM22_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM22_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM22_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM22_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM22_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM22_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM22_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM22_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM22_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM22_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM22_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM22_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM22_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM22_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM22_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM22_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM22_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM22_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM22_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM22_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM22_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM22_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM22_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM22_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM22_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM22_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM22_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM22_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM22_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM22_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM22_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM22_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM22_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM22_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM22_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM22_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM22_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM22_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM22_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM22_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM22_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM22_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM22_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM22_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM22_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM22_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM22_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM22_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM22_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM22_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM22_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM22_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM22_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM22_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM22_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM22_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM22_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM22_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM22_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM22_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM22_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM22_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM22_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM22_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM22_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM22_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM22_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM22_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM22_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM22_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM22_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM22_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM22_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM22_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM22_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM22_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM22_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM22_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM22_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM22_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM22_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM22_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM22_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM22_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM22_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM22_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM22_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM22_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM22_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM22_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM22_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM22_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM22_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM22_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM22_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM22_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM22_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM22_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM22_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM22_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM22_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM22_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM22_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM22_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM22_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM22_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM22_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM22_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM22_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM22_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM22_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM22_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM22_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM22_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM22_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM23" base ad:0x500D7000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM23_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM23_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM23_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM23_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM23_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM23_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM23_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM23_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM23_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM23_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM23_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM23_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM23_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM23_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM23_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM23_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM23_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM23_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM23_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM23_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM23_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM23_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM23_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM23_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM23_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM23_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM23_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM23_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM23_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM23_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM23_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM23_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM23_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM23_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM23_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM23_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM23_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM23_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM23_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM23_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM23_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM23_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM23_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM23_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM23_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM23_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM23_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM23_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM23_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM23_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM23_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM23_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM23_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM23_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM23_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM23_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM23_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM23_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM23_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM23_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM23_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM23_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM23_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM23_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM23_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM23_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM23_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM23_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM23_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM23_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM23_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM23_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM23_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM23_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM23_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM23_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM23_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM23_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM23_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM23_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM23_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM23_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM23_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM23_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM23_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM23_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM23_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM23_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM23_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM23_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM23_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM23_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM23_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM23_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM23_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM23_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM23_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM23_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM23_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM23_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM23_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM23_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM23_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM23_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM23_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM23_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM23_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM23_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM23_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM23_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM23_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM23_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM23_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM23_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM23_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM23_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM23_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM23_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM23_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM23_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM23_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM23_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM23_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM23_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM23_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM23_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM23_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM23_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM23_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM23_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM23_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM23_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM23_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM23_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM23_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM23_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM24" base ad:0x500D8000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM24_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM24_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM24_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM24_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM24_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM24_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM24_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM24_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM24_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM24_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM24_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM24_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM24_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM24_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM24_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM24_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM24_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM24_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM24_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM24_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM24_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM24_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM24_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM24_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM24_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM24_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM24_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM24_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM24_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM24_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM24_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM24_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM24_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM24_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM24_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM24_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM24_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM24_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM24_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM24_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM24_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM24_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM24_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM24_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM24_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM24_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM24_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM24_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM24_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM24_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM24_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM24_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM24_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM24_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM24_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM24_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM24_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM24_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM24_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM24_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM24_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM24_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM24_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM24_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM24_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM24_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM24_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM24_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM24_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM24_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM24_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM24_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM24_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM24_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM24_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM24_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM24_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM24_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM24_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM24_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM24_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM24_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM24_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM24_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM24_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM24_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM24_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM24_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM24_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM24_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM24_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM24_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM24_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM24_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM24_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM24_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM24_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM24_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM24_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM24_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM24_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM24_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM24_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM24_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM24_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM24_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM24_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM24_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM24_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM24_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM24_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM24_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM24_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM24_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM24_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM24_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM24_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM24_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM24_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM24_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM24_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM24_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM24_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM24_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM24_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM24_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM24_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM24_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM24_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM24_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM24_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM24_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM24_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM24_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM24_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM24_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM25" base ad:0x500D9000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM25_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM25_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM25_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM25_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM25_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM25_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM25_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM25_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM25_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM25_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM25_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM25_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM25_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM25_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM25_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM25_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM25_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM25_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM25_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM25_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM25_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM25_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM25_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM25_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM25_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM25_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM25_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM25_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM25_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM25_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM25_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM25_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM25_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM25_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM25_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM25_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM25_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM25_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM25_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM25_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM25_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM25_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM25_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM25_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM25_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM25_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM25_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM25_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM25_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM25_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM25_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM25_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM25_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM25_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM25_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM25_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM25_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM25_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM25_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM25_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM25_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM25_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM25_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM25_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM25_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM25_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM25_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM25_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM25_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM25_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM25_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM25_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM25_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM25_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM25_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM25_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM25_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM25_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM25_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM25_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM25_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM25_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM25_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM25_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM25_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM25_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM25_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM25_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM25_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM25_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM25_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM25_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM25_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM25_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM25_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM25_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM25_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM25_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM25_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM25_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM25_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM25_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM25_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM25_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM25_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM25_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM25_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM25_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM25_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM25_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM25_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM25_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM25_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM25_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM25_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM25_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM25_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM25_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM25_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM25_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM25_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM25_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM25_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM25_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM25_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM25_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM25_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM25_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM25_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM25_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM25_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM25_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM25_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM25_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM25_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM25_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM26" base ad:0x500DA000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM26_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM26_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM26_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM26_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM26_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM26_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM26_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM26_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM26_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM26_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM26_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM26_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM26_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM26_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM26_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM26_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM26_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM26_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM26_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM26_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM26_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM26_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM26_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM26_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM26_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM26_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM26_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM26_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM26_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM26_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM26_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM26_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM26_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM26_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM26_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM26_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM26_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM26_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM26_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM26_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM26_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM26_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM26_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM26_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM26_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM26_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM26_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM26_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM26_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM26_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM26_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM26_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM26_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM26_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM26_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM26_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM26_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM26_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM26_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM26_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM26_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM26_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM26_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM26_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM26_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM26_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM26_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM26_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM26_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM26_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM26_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM26_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM26_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM26_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM26_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM26_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM26_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM26_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM26_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM26_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM26_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM26_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM26_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM26_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM26_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM26_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM26_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM26_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM26_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM26_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM26_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM26_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM26_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM26_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM26_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM26_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM26_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM26_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM26_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM26_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM26_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM26_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM26_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM26_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM26_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM26_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM26_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM26_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM26_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM26_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM26_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM26_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM26_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM26_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM26_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM26_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM26_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM26_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM26_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM26_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM26_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM26_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM26_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM26_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM26_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM26_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM26_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM26_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM26_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM26_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM26_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM26_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM26_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM26_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM26_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM26_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM27" base ad:0x500DB000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM27_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM27_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM27_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM27_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM27_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM27_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM27_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM27_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM27_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM27_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM27_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM27_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM27_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM27_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM27_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM27_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM27_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM27_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM27_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM27_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM27_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM27_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM27_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM27_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM27_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM27_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM27_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM27_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM27_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM27_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM27_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM27_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM27_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM27_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM27_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM27_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM27_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM27_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM27_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM27_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM27_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM27_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM27_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM27_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM27_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM27_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM27_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM27_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM27_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM27_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM27_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM27_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM27_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM27_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM27_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM27_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM27_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM27_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM27_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM27_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM27_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM27_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM27_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM27_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM27_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM27_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM27_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM27_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM27_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM27_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM27_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM27_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM27_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM27_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM27_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM27_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM27_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM27_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM27_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM27_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM27_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM27_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM27_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM27_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM27_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM27_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM27_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM27_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM27_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM27_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM27_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM27_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM27_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM27_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM27_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM27_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM27_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM27_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM27_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM27_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM27_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM27_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM27_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM27_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM27_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM27_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM27_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM27_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM27_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM27_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM27_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM27_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM27_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM27_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM27_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM27_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM27_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM27_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM27_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM27_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM27_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM27_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM27_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM27_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM27_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM27_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM27_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM27_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM27_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM27_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM27_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM27_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM27_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM27_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM27_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM27_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM28" base ad:0x500DC000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM28_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM28_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM28_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM28_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM28_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM28_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM28_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM28_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM28_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM28_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM28_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM28_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM28_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM28_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM28_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM28_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM28_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM28_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM28_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM28_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM28_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM28_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM28_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM28_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM28_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM28_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM28_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM28_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM28_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM28_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM28_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM28_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM28_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM28_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM28_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM28_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM28_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM28_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM28_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM28_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM28_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM28_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM28_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM28_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM28_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM28_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM28_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM28_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM28_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM28_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM28_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM28_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM28_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM28_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM28_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM28_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM28_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM28_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM28_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM28_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM28_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM28_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM28_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM28_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM28_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM28_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM28_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM28_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM28_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM28_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM28_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM28_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM28_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM28_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM28_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM28_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM28_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM28_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM28_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM28_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM28_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM28_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM28_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM28_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM28_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM28_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM28_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM28_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM28_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM28_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM28_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM28_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM28_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM28_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM28_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM28_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM28_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM28_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM28_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM28_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM28_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM28_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM28_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM28_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM28_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM28_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM28_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM28_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM28_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM28_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM28_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM28_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM28_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM28_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM28_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM28_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM28_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM28_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM28_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM28_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM28_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM28_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM28_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM28_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM28_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM28_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM28_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM28_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM28_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM28_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM28_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM28_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM28_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM28_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM28_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM28_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM29" base ad:0x500DD000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM29_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM29_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM29_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM29_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM29_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM29_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM29_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM29_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM29_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM29_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM29_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM29_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM29_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM29_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM29_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM29_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM29_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM29_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM29_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM29_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM29_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM29_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM29_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM29_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM29_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM29_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM29_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM29_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM29_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM29_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM29_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM29_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM29_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM29_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM29_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM29_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM29_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM29_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM29_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM29_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM29_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM29_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM29_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM29_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM29_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM29_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM29_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM29_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM29_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM29_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM29_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM29_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM29_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM29_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM29_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM29_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM29_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM29_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM29_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM29_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM29_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM29_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM29_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM29_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM29_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM29_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM29_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM29_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM29_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM29_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM29_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM29_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM29_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM29_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM29_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM29_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM29_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM29_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM29_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM29_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM29_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM29_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM29_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM29_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM29_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM29_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM29_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM29_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM29_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM29_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM29_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM29_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM29_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM29_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM29_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM29_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM29_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM29_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM29_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM29_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM29_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM29_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM29_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM29_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM29_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM29_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM29_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM29_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM29_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM29_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM29_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM29_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM29_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM29_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM29_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM29_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM29_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM29_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM29_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM29_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM29_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM29_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM29_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM29_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM29_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM29_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM29_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM29_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM29_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM29_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM29_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM29_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM29_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM29_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM29_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM29_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM30" base ad:0x500DE000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM30_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM30_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM30_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM30_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM30_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM30_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM30_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM30_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM30_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM30_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM30_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM30_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM30_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM30_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM30_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM30_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM30_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM30_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM30_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM30_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM30_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM30_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM30_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM30_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM30_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM30_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM30_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM30_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM30_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM30_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM30_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM30_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM30_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM30_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM30_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM30_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM30_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM30_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM30_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM30_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM30_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM30_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM30_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM30_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM30_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM30_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM30_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM30_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM30_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM30_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM30_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM30_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM30_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM30_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM30_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM30_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM30_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM30_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM30_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM30_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM30_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM30_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM30_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM30_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM30_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM30_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM30_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM30_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM30_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM30_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM30_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM30_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM30_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM30_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM30_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM30_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM30_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM30_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM30_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM30_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM30_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM30_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM30_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM30_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM30_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM30_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM30_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM30_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM30_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM30_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM30_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM30_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM30_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM30_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM30_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM30_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM30_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM30_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM30_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM30_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM30_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM30_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM30_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM30_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM30_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM30_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM30_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM30_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM30_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM30_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM30_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM30_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM30_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM30_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM30_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM30_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM30_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM30_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM30_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM30_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM30_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM30_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM30_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM30_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM30_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM30_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM30_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM30_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM30_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM30_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM30_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM30_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM30_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM30_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM30_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM30_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree "G3_EPWM31" base ad:0x500DF000 group.word 0x0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM31_TBCTL,Time Base Control Register" bitfld.word 0x0 14.--15. "FREE_SOFT,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events 00: Stop after the next time-base counter increment or decrement 01: Stop when counter completes a whole cycle: - Up-count mode: stop.." "0: Stop after the next time-base counter increment..,1: Stop when counter completes a whole cycle:,?,?" newline bitfld.word 0x0 13. "PHSDIR,Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter [TBCTR] will count after a synchronization event occurs and a new phase.." "0: Count down after the synchronization event,1: Count up after the synchronization event" newline bitfld.word 0x0 10.--12. "CLKDIV,Time Base Clock Pre-Scale Bits These bits select the time base clock pre-scale value [TBCLK = EPWMCLK/[HSPCLKDIV * CLKDIV]: 000: /1 [default on reset] 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128" "0: /1 [default on reset],1: /2,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "HSPCLKDIV,High Speed Time Base Clock Pre-Scale Bits These bits determine part of the time-base clock prescale value. TBCLK = EPWMCLK / [HSPCLKDIV x CLKDIV]. This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV].." "0: /1,1: /2 [default on reset],?,?,?,?,?,?" newline bitfld.word 0x0 6. "SWFSYNC,Software Forced Sync Pulse 0: Writing a 0 has no effect and reads always return a 0. 1: Writing a 1 forces a one-time synchronization pulse to be generated. SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit." "0: Writing a 0 has no effect and reads always..,1: Writing a 1 forces a one-time synchronization.." newline bitfld.word 0x0 3. "PRDLD,Active Period Reg Load from Shadow Select 0: The period register [TBPRD] is loaded from its shadow register when the time-base counter TBCTR is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit. A write/read to the.." "0: The period register [TBPRD] is loaded from its..,1: Immediate Mode [Shadow register bypassed]: A.." newline bitfld.word 0x0 2. "PHSEN,Counter Reg Load from Phase Reg Enable 0: Do not load the time-base counter [TBCTR] from the time-base phase register [TBPHS]. 1: Allow Counter to be loaded from the Phase register [TBPHS] and shadow to active load events when an EPWMxSYNCI.." "0: Do not load the time-base counter [TBCTR] from..,1: Allow Counter to be loaded from the Phase.." newline bitfld.word 0x0 0.--1. "CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment.." "0: Up-count mode,1: Down-count mode,?,?" line.word 0x2 "CONTROLSS_G3_EPWM31_TBCTL2,Time Base Control Register 2" bitfld.word 0x2 14.--15. "PRDLDSYNC,Shadow to Active Period Register Load on SYNC event 00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of TBPRD occurs only when..,1: Shadow to Active Load of TBPRD occurs both when..,?,?" newline bitfld.word 0x2 7. "OSHTSYNC,Oneshot sync bit 0: Writing a '0' has no effect. 1: Allow one sync pulse to propogate." "0: Writing a '0' has no effect,1: Allow one sync pulse to propogate" newline bitfld.word 0x2 6. "OSHTSYNCMODE,Oneshot sync enable bit 0: Oneshot sync mode disabled 1: Oneshot sync mode enabled" "0: Oneshot sync mode disabled,1: Oneshot sync mode enabled" newline bitfld.word 0x2 5. "SELFCLRTRREM,Loop back sync pulse to enable self sync operation 0: Self clear function of TRREM disabled. 1: Self clear function of TRREM enabled" "0: Self clear function of TRREM disabled,1: Self clear function of TRREM enabled" group.word 0x6++0xD line.word 0x0 "CONTROLSS_G3_EPWM31_EPWMSYNCINSEL,EPWMxSYNCIN Source Select Register" hexmask.word.byte 0x0 0.--6. 1. "SEL,These bits determine the source of the EPWMxSYNCI signal 0x0: Disabled 0x01: EPWM0.SYNCOUT . 0x10: EPWM15.SYNCOUT 0x11:EPWM16.SYNCOUT . 0x20: EPWM31.SYNCOUT 0x21: Reserved . 0x40: ECAP0.SYNCOUT . 0x49: ECAP9.SYNCPUT 0x4A: Reserved . 0x4F: Reserved.." line.word 0x2 "CONTROLSS_G3_EPWM31_TBCTR,Time Base Counter Register" hexmask.word 0x2 0.--15. 1. "TBCTR,Time Base Counter Register" line.word 0x4 "CONTROLSS_G3_EPWM31_TBSTS,Time Base Status Register" bitfld.word 0x4 2. "CTRMAX,Time-Base Counter Max Latched Status Bit 0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 1: Reading a 1 on this bit indicates that the time-base counter reached the max value.." "0: Reading a 0 indicates the time-base counter..,1: Reading a 1 on this bit indicates that the.." newline bitfld.word 0x4 1. "SYNCI,Input Synchronization Latched Status Bit 0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 1: Reading a 1 on this bit indicates that an external synchronization event has occurred.." "0: Writing a 0 will have no effect,1: Reading a 1 on this bit indicates that an.." newline rbitfld.word 0x4 0. "CTRDIR,Time Base Counter Direction Status Bit 0: Time-Base Counter is currently counting down. 1: Time-Base Counter is currently counting up. Note: This bit is only valid when the counter is not frozen." "0: Time-Base Counter is currently counting down,1: Time-Base Counter is currently counting up" line.word 0x6 "CONTROLSS_G3_EPWM31_EPWMSYNCOUTEN,EPWMxSYNCOUT Source Enable Register" bitfld.word 0x6 6. "DCBEVT1EN,This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event" "0,1" newline bitfld.word 0x6 5. "DCAEVT1EN,This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event" "0,1" newline bitfld.word 0x6 4. "CMPDEN,This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD]" "0,1" newline bitfld.word 0x6 3. "CMPCEN,This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC]" "0,1" newline bitfld.word 0x6 2. "CMPBEN,This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB]" "0,1" newline bitfld.word 0x6 1. "ZEROEN,This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000" "0,1" newline bitfld.word 0x6 0. "SWEN,This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set" "0,1" line.word 0x8 "CONTROLSS_G3_EPWM31_TBCTL3,Time Base Control Register 3" bitfld.word 0x8 0. "OSSFRCEN,This bit determines which bit sets the EPWMxSYNCOUT One Shot Latch. 0 TBCTL2[OSHTSYNC] sets the One Shot Latch 1 GLDCTL2[OSHTLD] sets the One Shot Latch" "0,1" line.word 0xA "CONTROLSS_G3_EPWM31_CMPCTL,Counter Compare Control Register" bitfld.word 0xA 15. "LINKDUTYHR,CMPAHR CMPBHR Register Linking: 0 PWMA and PWMB outputs generated independently and CMPAHR CMPBHR are independent values as on Type-4 1 When this bit is set CMPBHR assumes the same value as CMPAHR. This is typically used in complimentary.." "0,1" newline bitfld.word 0xA 12.--13. "LOADBSYNC,Shadow to Active CMPB Register Load on SYNC event 00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when.." "0: Shadow to Active Load of CMPB:CMPBHR occurs..,1: Shadow to Active Load of CMPB:CMPBHR occurs both..,?,?" newline bitfld.word 0xA 10.--11. "LOADASYNC,Shadow to Active CMPA Register Load on SYNC event 00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE [bits 1 0] [same as legacy] 01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when.." "0: Shadow to Active Load of CMPA:CMPAHR occurs..,1: Shadow to Active Load of CMPA:CMPAHR occurs both..,?,?" newline rbitfld.word 0xA 9. "SHDWBFULL,Counter-compare B [CMPB] Shadow Register Full Status Flag This bit self clears once a loadstrobe occurs. 0: CMPB shadow FIFO not full yet 1: Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value" "0: CMPB shadow FIFO not full yet,1: Indicates the CMPB shadow FIFO is full a CPU.." newline rbitfld.word 0xA 8. "SHDWAFULL,Counter-compare A [CMPA] Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self.." "0: CMPA shadow FIFO not full yet,1: Indicates the CMPA shadow FIFO is full" newline bitfld.word 0xA 6. "SHDWBMODE,Counter-compare B [CMPB] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare B register is used. All writes and reads directly.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 4. "SHDWAMODE,Counter-compare A [CMPA] Register Operating Mode 0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register 1: Immediate mode. Only the active compare register is used. All writes and reads directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xA 2.--3. "LOADBMODE,Active Counter-Compare B [CMPB] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWBMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xA 0.--1. "LOADAMODE,Active Counter-Compare A [CMPA] Load From Shadow Select Mode This bit has no effect in immediate mode [CMPCTL[SHDWAMODE] = 1]. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0xC "CONTROLSS_G3_EPWM31_CMPCTL2,Counter Compare Control Register 2" bitfld.word 0xC 12.--13. "LOADDSYNC,Shadow to Active CMPD Register Load on SYNC event 00: Shadow to Active Load of CMPD occurs according to LOADDMODE 01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPD occurs according..,1: Shadow to Active Load of CMPD occurs both..,?,?" newline bitfld.word 0xC 10.--11. "LOADCSYNC,Shadow to Active CMPC Register Load on SYNC event 00: Shadow to Active Load of CMPC occurs according to LOADCMODE 01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs 10: Shadow to Active Load of.." "0: Shadow to Active Load of CMPC occurs according..,1: Shadow to Active Load of CMPC occurs both..,?,?" newline bitfld.word 0xC 6. "SHDWDMODE,Counter-Compare D Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 4. "SHDWCMODE,Counter-Compare C Register Operating Mode 0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access.." "0: Shadow mode,1: Immediate mode" newline bitfld.word 0xC 2.--3. "LOADDMODE,Active Counter-Compare D [CMPD] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0xC 0.--1. "LOADCMODE,Active Counter-Compare C [CMPC] Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" group.word 0x18++0x3 line.word 0x0 "CONTROLSS_G3_EPWM31_DBCTL,Dead-Band Generator Control Register" bitfld.word 0x0 15. "HALFCYCLE,Half Cycle Clocking Enable Bit 0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2." "0: Full cycle clocking enabled,1: Half cycle clocking enabled" newline bitfld.word 0x0 14. "DEDB_MODE,Dead Band Dual-Edge B Mode Control [S8 switch] 0: Rising edge delay applied to InA/InB as selected by S4 switch [IN-MODE bits] on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch [INMODE bits] on B signal.." "0: Rising edge delay applied to InA/InB as selected..,1: Rising edge delay and falling edge delay applied.." newline bitfld.word 0x0 12.--13. "OUTSWAP,Dead Band Output Swap Control Bit 13 controls the S6 switch and bit 12 controls the S7 switch. 00: OutA and OutB signals are as defined by OUT-MODE bits. 01: OutA = A-path as defined by OUT-MODE bits. OutB = A-path as defined by OUT-MODE.." "0: OutA and OutB signals are as defined by OUT-MODE..,1: OutA = A-path as defined by OUT-MODE bits,?,?" newline bitfld.word 0x0 11. "SHDWDBFEDMODE,FED Dead-Band Load Mode 0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate FED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 10. "SHDWDBREDMODE,RED Dead-Band Load Mode 0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate RED dead-band action. 1: Shadow mode. Operates as a double buffer. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 8.--9. "LOADFEDMODE,Active DBFED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 6.--7. "LOADREDMODE,Active DBRED Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode." "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" newline bitfld.word 0x0 4.--5. "IN_MODE,Dead-Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is.." "0: EPWMxA In [from the action-qualifier] is the..,1: EPWMxB In [from the action-qualifier] is the..,?,?" newline bitfld.word 0x0 2.--3. "POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to.." "0: Active high [AH] mode,1: Active low complementary [ALC] mode,?,?" newline bitfld.word 0x0 0.--1. "OUT_MODE,Dead-Band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch. 00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect. 01: Apath = InA [delay is by-passed for A signal.." "0: DBM is fully disabled or by-passed,1: Apath = InA [delay is by-passed for A signal..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM31_DBCTL2,Dead-Band Generator Control Register 2" bitfld.word 0x2 2. "SHDWDBCTLMODE,DBCTL Load Mode 0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register. 1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x2 0.--1. "LOADDBCTLMODE,Active DBCTL Load from Shadow Select Mode 00: Load on Counter = 0 [CNT_eq] 01: Load on Counter = Period [PRD_eq] 10: Load on either Counter = 0 or Counter = Period 11: Freeze [no loads possible] Note: has no effect in Immediate mode" "0: Load on Counter = 0 [CNT_eq],1: Load on Counter = Period [PRD_eq],?,?" group.word 0x20++0x3 line.word 0x0 "CONTROLSS_G3_EPWM31_AQCTL,Action Qualifier Control Register" bitfld.word 0x0 10.--11. "LDAQBSYNC,Shadow to Active AQCTLB Register Load on SYNC event 00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE 01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLB occurs according..,1: Shadow to Active Load of AQCTLB occurs both..,?,?" newline bitfld.word 0x0 8.--9. "LDAQASYNC,Shadow to Active AQCTLA Register Load on SYNC event 00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE 01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs. 10: Shadow to Active.." "0: Shadow to Active Load of AQCTLA occurs according..,1: Shadow to Active Load of AQCTLA occurs both..,?,?" newline bitfld.word 0x0 6. "SHDWAQBMODE,Action Qualifier B Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 4. "SHDWAQAMODE,Action Qualifier A Register operating mode 1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register. 0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU.." "0: Immediate mode,1: Shadow mode" newline bitfld.word 0x0 2.--3. "LDAQBMODE,Active Action Qualifier B Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 0.--1. "LDAQAMODE,Active Action Qualifier A Load from Shadow Select Mode 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10: Load on either CTR = Zero or CTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" line.word 0x2 "CONTROLSS_G3_EPWM31_AQTSRCSEL,Action Qualifier Trigger Event Source Select Register" hexmask.word.byte 0x2 4.--7. 1. "T2SEL,T2 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" newline hexmask.word.byte 0x2 0.--3. 1. "T1SEL,T1 Event Source Select Bits 0000: DCAEVT1 0001: DCAEVT2 0010: DCBEVT1 0011: DCBEVT2 0100: TZ1 0101: TZ2 0110: TZ3 0111: EPWMxSYNCI 1000: DCEVTFILT Others: Reserved" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_PCCTL,PWM Chopper Control Register" bitfld.word 0x0 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 000: Duty = 1/8 [12.5%] 001: Duty = 2/8 [25.0%] 010: Duty = 3/8 [37.5%] 011: Duty = 4/8 [50.0%] 100: Duty = 5/8 [62.5%] 101: Duty = 6/8 [75.0%] 110: Duty = 7/8 [87.5%] 111: Reserved" "0: Duty = 1/8 [12,1: Duty = 2/8 [25,?,?,?,?,?,?" newline bitfld.word 0x0 5.--7. "CHPFREQ,Chopping Clock Frequency 000: Divide by 1 [no prescale = 12.5 MHz at 100 MHz TBCLK] 001: Divide by 2 [6.25 MHz at 100 MHz TBCLK] 010: Divide by 3 [4.16 MHz at 100 MHz TBCLK] 011: Divide by 4 [3.12 MHz at 100 MHz TBCLK] 100: Divide by 5.." "0: Divide by 1 [no prescale,1: Divide by 2 [6,?,?,?,?,?,?" newline hexmask.word.byte 0x0 1.--4. 1. "OSHTWTH,One-Shot Pulse Width 0000: 1 x EPWMCLK / 8 wide [ = 80 ns at 100 MHz EPWMCLK] 0001: 2 x EPWMCLK / 8 wide [ = 160 ns at 100 MHz EPWMCLK] 0010: 3 x EPWMCLK / 8 wide [ = 240 ns at 100 MHz EPWMCLK] 0011: 4 x EPWMCLK / 8 wide [ = 320 ns at 100.." newline bitfld.word 0x0 0. "CHPEN,PWM-Chopping Enable 0: Disable [bypass] PWM chopping function 1: Enable chopping function" "0: Disable [bypass] PWM chopping function,1: Enable chopping function" group.word 0x30++0x3 line.word 0x0 "CONTROLSS_G3_EPWM31_VCAPCTL,Valley Capture Control Register" bitfld.word 0x0 10. "EDGEFILTDLYSEL,Valley Switching Mode Delay Selection 0: No delay applied to the edge filter output 1: HWDELAYVAL delay applied to the edge filter output" "0: No delay applied to the edge filter output,1: HWDELAYVAL delay applied to the edge filter output" newline bitfld.word 0x0 7.--9. "VDELAYDIV,Valley Delay Mode Divide Enable 000: HWVDELVAL = SWVDELVAL 001: HWVDELVAL = VCNTVAL+SWVDELVAL 010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL 011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL 100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL Note: Delay value between the.." "0: HWVDELVAL = SWVDELVAL,1: HWVDELVAL = VCNTVAL+SWVDELVAL,?,?,?,?,?,?" newline bitfld.word 0x0 2.--4. "TRIGSEL,Status of Numbered of Captured Events 000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART]. 001: Capture sequence is triggered by CNT_zero event. 010: Capture sequence is triggered by PRD_eq event. 011: Capture.." "0: Capture sequence is triggered by software via..,1: Capture sequence is triggered by CNT_zero event,?,?,?,?,?,?" newline bitfld.word 0x0 1. "VCAPSTART,Valley Capture Start 0: Writing a 0 has no effect 1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0 Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger.." "0: Writing a 0 has no effect,1: Trigger the capture sequence once if.." newline bitfld.word 0x0 0. "VCAPE,Valley Capture Enable/Disable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" line.word 0x2 "CONTROLSS_G3_EPWM31_VCNTCFG,Valley Counter Config Register" rbitfld.word 0x2 15. "STOPEDGESTS,Stop Edge Status Bit 0: Stop edge has not occurred 1: Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This.." "0: Stop edge has not occurred,1: Stop edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 8.--11. 1. "STOPEDGE,Counter Stop Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit.." newline rbitfld.word 0x2 7. "STARTEDGESTS,Start Edge Status Bit 0: Start edge has not occurred 1: Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs." "0: Start edge has not occurred,1: Start edge occurred Note: This bit is set only.." newline hexmask.word.byte 0x2 0.--3. 1. "STARTEDGE,Counter Start Edge Selection Once the counter operation is armed upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit.." group.word 0x40++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_HRCNFG,HRPWM Configuration Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 14.--15. "LINESEL,Delay Line Selection Bits: Selects which of the 4 delay lines for a particular ePWM/EPWM module to send to CALIN for calibration." "0,1,2,3" newline bitfld.word 0x0 11.--12. "HRLOADB,Shadow Mode Bit Selects the time event that loads the CMPBHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 10. "CTLMODEB,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPBHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPBHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 8.--9. "EDGMODEB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPBHR] 10: MEP control of falling edge [CMPBHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPBHR],?,?" newline bitfld.word 0x0 7. "SWAPAB,Swap ePWM A & B Output Signals This bit enables the swapping of the A & B signal outputs. The selection is as follows: 0: ePWMxA and ePWMxB outputs are unchanged. 1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA.." "0: ePWMxA and ePWMxB outputs are unchanged,1: ePWMxA signal appears on ePWMxB output and.." newline bitfld.word 0x0 6. "AUTOCONV,Auto Convert Delay Line Value Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in.." "0: Automatic HRMSTEP scaling is disabled,1: Automatic HRMSTEP scaling is enabled" newline bitfld.word 0x0 5. "SELOUTB,EPWMxB Output Select Bit This bit selects which signal is output on the ePWMxB channel output. The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion.." "0: ePWMxB output is normal,1: ePWMxB output is inverted version of ePWMxA signal" newline bitfld.word 0x0 3.--4. "HRLOAD,Shadow Mode Bit Selects the time event that loads the CMPAHR shadow value into the active register. 00: Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01: Load on CTR = PRD: Time-base counter equal to period [TBCTR =.." "0: Load on CTR = Zero: Time-base counter equal to..,1: Load on CTR = PRD: Time-base counter equal to..,?,?" newline bitfld.word 0x0 2. "CTLMODE,Control Mode Bits Selects the register [CMP/TBPRD or TBPHS] that controls the MEP: 0: CMPAHR[8] or TBPRDHR[8] Register controls the edge position [i.e. this is duty or period control mode]. [Default on Reset] 1: TBPHSHR[8] Register controls.." "0: CMPAHR[8] or TBPRDHR[8] Register controls the..,1: TBPHSHR[8] Register controls the edge position [i" newline bitfld.word 0x0 0.--1. "EDGMODE,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00: HRPWM capability is disabled [default on reset] 01: MEP control of rising edge [CMPAHR] 10: MEP control of falling edge [CMPAHR] 11:.." "0: HRPWM capability is disabled [default on reset],1: MEP control of rising edge [CMPAHR],?,?" group.word 0x4E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_HRCNFG2,HRPWM Configuration 2 Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect.." bitfld.word 0x0 15. "NOBYPASS,No Bypass Delay Line Update Bit: For internal test purposes this bit disables the 1 SYSCLK cycle bypass before delay line is updated." "0,1" newline bitfld.word 0x0 14. "DELLOADFRC,Delay Line Load Software Force: For internal test purposes software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]." "0,1" newline bitfld.word 0x0 4.--5. "CTLMODEDBFED,Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 2.--3. "CTLMODEDBRED,Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR =.." "0,1,2,3" newline bitfld.word 0x0 0.--1. "EDGMODEDB,Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11.." "0,1,2,3" group.word 0x5A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM31_HRPCTL,High Resolution Period Control Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." bitfld.word 0x0 4.--6. "PWMSYNCSELX,Extended selection bits for EPWMSYNCPER 000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition [compatible with previous EPWM versions] 001: Reserved 010: Reserved 011: Reserved 100: CTR = CMPC Count direction Up 101: CTR =.." "0: EPWMSYNCPER is defined by PWMSYNCSEL,1: Reserved,?,?,?,?,?,?" newline bitfld.word 0x0 3. "HRPSYNCE,SYNC Enable Bit [TRSYNCE]/High Resolution Period SYNC Enable Bit [HRPSYNCE]" "0,1" newline bitfld.word 0x0 2. "TBPHSHRLOADE,TBPHSHR Load Enable This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned.." "0: Disables synchronization of high-resolution..,1: Synchronize the high-resolution phase on a SYNCIN" newline bitfld.word 0x0 1. "PWMSYNCSEL,PWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC: 0 CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 1 CTR = zero: Time-base counter equal to zero [TBCTR =.." "0,1" newline bitfld.word 0x0 0. "HRPE,High Resolution Period Enable Bit 0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 0 ePWM. 1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and.." "0: High resolution period feature disabled,1: High resolution period enabled" line.word 0x2 "CONTROLSS_G3_EPWM31_TRREM,HRPWM High Resolution Remainder Register [[br]] [[br]]This register is only accessible on EPWM modules with HRPWM capabilities." hexmask.word 0x2 0.--10. 1. "TRREM,HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations. This value keeps track of the remainder portion of the HRPWM hardware calculations. Notes: 1. The lower 8-bits of the TRREM register.." group.word 0x68++0x3 line.word 0x0 "CONTROLSS_G3_EPWM31_GLDCTL,Global PWM Load Control Register" rbitfld.word 0x0 10.--12. "GLDCNT,Global Load Strobe Counter Register These bits indicate how many selected events have occurred: 000: No events 001: 1 event 010: 2 events 011: 3 events 100: 4 events 101: 5 events 110: 6 events 111: 7 events" "0: No events,1: 1 event,?,?,?,?,?,?" newline bitfld.word 0x0 7.--9. "GLDPRD,Global Load Strobe Period Select Register These bits select how many selected events need to occur before a load strobe is generated 000: Disable counter 001: Generate strobe on GLDCNT = 001 [1st event] 010: Generate strobe on GLDCNT = 010.." "0: Disable counter,1: Generate strobe on GLDCNT = 001 [1st event],?,?,?,?,?,?" newline bitfld.word 0x0 5. "OSHTMODE,One Shot Load Mode Control Bit 0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes. 1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with.." "0: One shot load mode is disabled and shadow to..,1: One shot mode is active" newline hexmask.word.byte 0x0 1.--4. 1. "GLDMODE,Global Load Pulse selection for Shadow to Active Mode Reloads 0000: Load on Counter = 0 [CNT_ZRO] 0001: Load on Counter = Period [PRD_EQ] 0010: Load on either Counter = 0 or Counter = Period 0011: Load on SYNCEVT - this is logical OR of.." newline bitfld.word 0x0 0. "GLD,Global Shadow to Active Load Event Control 0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified [Compatible with previous EPWM versions]. 1: When set all the shadow to active reload.." "0: Shadow to active reload for all shadowed..,1: When set" line.word 0x2 "CONTROLSS_G3_EPWM31_GLDCFG,Global PWM Load Config Register" bitfld.word 0x2 10. "AQCSFRC,Global load event configuration for AQCSFRC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 9. "AQCTLB_AQCTLB2,Global load event configuration for AQCTLB_AQCTLB2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 8. "AQCTLA_AQCTLA2,Global load event configuration for AQCTLA_AQCTLA2 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and.." "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 7. "DBCTL,Global load event configuration for DBCTL 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 6. "DBFED_DBFEDHR,Global load event configuration for DBFED_DBFEDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 5. "DBRED_DBREDHR,Global load event configuration for DBRED_DBREDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 4. "CMPD,Global load event configuration for CMPD 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 3. "CMPC,Global load event configuration for CMPC 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 2. "CMPB_CMPBHR,Global load event configuration for CMPB_CMPBHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 1. "CMPA_CMPAHR,Global load event configuration for CMPA_CMPAHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." newline bitfld.word 0x2 0. "TBPRD_TBPRDHR,Global load event configuration for TBPRD_TBPRDHR 0: Registers use local reload configuration even if GLDCTL[GLD]=1 [reload is compatible with previous EPWMs] 1: Registers use global load configuration if this bit is set and GLDCTL[GLD]=1" "0: Registers use local reload configuration even if..,1: Registers use global load configuration if this.." group.long 0x70++0x7 line.long 0x0 "CONTROLSS_G3_EPWM31_EPWMXLINK,EPWMx Link Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x0 26.--30. 1. "GLDCTL2LINK,GLDCTL2 Link Bits Writes to the GLDCTL2 registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's GLDCTL2 registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011:.." newline hexmask.long.byte 0x0 21.--25. 1. "CMPDLINK,CMPD Link Bits Writes to the CMPD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPD registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 16.--20. 1. "CMPCLINK,CMPC Link Bits Writes to the CMPC registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPC registers. 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." newline hexmask.long.byte 0x0 10.--14. 1. "CMPBLINK,CMPB_CMPBHR Link Bits Writes to the CMPB_CMPBHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPB_CMPBHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 5.--9. 1. "CMPALINK,CMPA_CMPAHR Link Bits Writes to the CMPA_CMPAHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's CMPA_CMPAHR registers. 00000: ePWM1 00001: ePWM2 00010:.." newline hexmask.long.byte 0x0 0.--4. 1. "TBPRDLINK,TBPRD_TBPRDHR Link Bits Writes to the TBPRD:TBPRDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's TBPRD_TBPRDHR registers. 00000: ePWM1 00001: ePWM2.." line.long 0x4 "CONTROLSS_G3_EPWM31_EPWMXLINK2,EPWMx Link 2 Register [[br]] [[br]]This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent.." hexmask.long.byte 0x4 5.--9. 1. "DBFEDLINK,DBFED_DBFEDHR Link Bits Writes to the DBFED:DBFEDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBFED_DBFEDHR registers. 00000: ePWM1 00001: ePWM2.." newline hexmask.long.byte 0x4 0.--4. 1. "DBREDLINK,DBRED_DBREDHR Link Bits Writes to the DBRED:DBREDHR registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's DBRED_DBREDHR registers. 00000: ePWM1 00001: ePWM2.." group.word 0x7A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_ETEST,EPWM Test Register" bitfld.word 0x0 0. "CMPFIX_OVERRIDE,0: Bug fix overriden 1: Bug fix takes effect" "0: Bug fix overriden,1: Bug fix takes effect" rgroup.word 0x7C++0x3 line.word 0x0 "CONTROLSS_G3_EPWM31_EPWMREV,EPWM Revision Register" hexmask.word.byte 0x0 8.--15. 1. "TYPE,EPWM Type Bits: These bits specify the EPWM type. These bits are changed if the functionality of the EPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x0 0.--7. 1. "REV,EPWM Silicon Revision Bits: These bits specify the EPWM revision. These bits are changed if any bug fixes are performed:" line.word 0x2 "CONTROLSS_G3_EPWM31_HRPWMREV,High Resolution Revision Register" hexmask.word.byte 0x2 8.--15. 1. "TYPE,HRPWM Type Bits: These bits specify the HRPWM type. These bits are changed if the functionality of the HRPWM is changed or any feature is added or removed:" newline hexmask.word.byte 0x2 0.--7. 1. "REV,HRPWM Silicon Revision Bits: These bits specify the HRPWM revision. These bits are changed if any bug fixes are performed:" group.word 0x80++0x7 line.word 0x0 "CONTROLSS_G3_EPWM31_AQCTLA,Action Qualifier Control Register For Output A" bitfld.word 0x0 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x0 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force EPWMxA output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x2 "CONTROLSS_G3_EPWM31_AQCTLA2,Additional Action Qualifier Control Register For Output A" bitfld.word 0x2 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" newline bitfld.word 0x2 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxA output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxA output low,?,?" line.word 0x4 "CONTROLSS_G3_EPWM31_AQCTLB,Action Qualifier Control Register For Output B" bitfld.word 0x4 10.--11. "CBD,Action When TBCTR = CMPB on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 8.--9. "CBU,Action When TBCTR = CMPB on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 6.--7. "CAD,Action When TBCTR = CMPA on Down Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 4.--5. "CAU,Action When TBCTR = CMPA on Up Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 2.--3. "PRD,Action When TBCTR = TBPRD Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x4 0.--1. "ZRO,Action When TBCTR = 0 Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force EPWMxB output high. 11:.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" line.word 0x6 "CONTROLSS_G3_EPWM31_AQCTLB2,Additional Action Qualifier Control Register For Output B" bitfld.word 0x6 6.--7. "T2D,Action when event occurs on T2 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 4.--5. "T2U,Action when event occurs on T2 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 2.--3. "T1D,Action when event occurs on T1 in DOWN-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" newline bitfld.word 0x6 0.--1. "T1U,Action when event occurs on T1 in UP-Count Note: By definition in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 00: Do nothing [action disabled] 01: Clear: force EPWMxB output low. 10: Set: force.." "0: Do nothing [action disabled],1: Clear: force EPWMxB output low,?,?" group.word 0x8E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_AQSFRC,Action Qualifier Software Force Register" bitfld.word 0x0 6.--7. "RLDCSF,AQCSFRC Active Register Reload From Shadow Options 00: Load on event counter equals zero 01: Load on event counter equals period 10: Load on event counter equals zero or counter equals period 11: Load immediately [the active register is.." "0: Load on event counter equals zero,1: Load on event counter equals period,?,?" newline bitfld.word 0x0 5. "OTSFB,One-Time Software Forced Event on Output B 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [i.e. a forced event is initiated.]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 3.--4. "ACTSFB,Action When One-Time Software Force B is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" newline bitfld.word 0x0 2. "OTSFA,One-Time Software Forced Event on Output A 0: Writing a 0 [zero] has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete [ i.e. a forced event is initiated]. This is a one-shot forced event. It.." "0: Writing a 0 [zero] has no effect,1: Initiates a single software forced event" newline bitfld.word 0x0 0.--1. "ACTSFA,Action When One-Time Software Force A Is Invoked 00: Does nothing [action disabled] 01: Clear [low] 10: Set [high] 11: Toggle [Low -> High High -> Low] Note: This action is not qualified by counter direction [CNT_dir]" "0: Does nothing [action disabled],1: Clear [low],?,?" group.word 0x92++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_AQCSFRC,Action Qualifier Continuous S/W Force Register" bitfld.word 0x0 2.--3. "CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output B,?,?" newline bitfld.word 0x0 0.--1. "CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge. In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 00: Software.." "0: Software forcing is disabled and has no effect,1: Forces a continuous low on output A,?,?" group.word 0xA0++0x7 line.word 0x0 "CONTROLSS_G3_EPWM31_DBREDHR,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word.byte 0x0 9.--15. 1. "DBREDHR,Dead Band Rising Edge Delay High Resolution Bits" newline hexmask.word.byte 0x0 1.--7. 1. "DBREDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x2 "CONTROLSS_G3_EPWM31_DBRED,Dead-Band Generator Rising Edge Delay High Resolution Mirror Register" hexmask.word 0x2 0.--13. 1. "DBRED,Rising edge delay value" line.word 0x4 "CONTROLSS_G3_EPWM31_DBFEDHR,Dead-Band Generator Falling Edge Delay High Resolution Register" hexmask.word.byte 0x4 9.--15. 1. "DBFEDHR,Dead Band Falling Edge Delay High Resolution Bits" newline hexmask.word.byte 0x4 1.--7. 1. "DBFEDHR_DELAY,These 7-bits contain the results of OTTO calculation [if auto-conversion is enabled]" line.word 0x6 "CONTROLSS_G3_EPWM31_DBFED,Dead-Band Generator Falling Edge Delay Count Register" hexmask.word 0x6 0.--13. 1. "DBFED,Falling Edge Delay Count 14-bit counter" group.long 0xC0++0x3 line.long 0x0 "CONTROLSS_G3_EPWM31_TBPHS,Time Base Phase High" hexmask.long.word 0x0 16.--31. 1. "TBPHS,Phase Offset Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. - If TBCTL[PHSEN] = 0 then the synchronization event is ignored and the time-base.." newline hexmask.long.word 0x0 0.--15. 1. "TBPHSHR,Phase Offset [High Resolution] Register. TBPHSHR must not be used. Instead TRREM [HRPWM remainder register] must be used to mimic the functionality of TBPHSHR. The lower 8 bits in this register are ignored - writes are ignored and reads return.." group.word 0xC4++0x5 line.word 0x0 "CONTROLSS_G3_EPWM31_TBPRDHR,Time Base Period High Resolution Register" hexmask.word 0x0 0.--15. 1. "TBPRDHR,Period High Resolution Bits The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are.." line.word 0x2 "CONTROLSS_G3_EPWM31_TBPRD,Time Base Period Register" hexmask.word 0x2 0.--15. 1. "TBPRD,Time Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. - If TBCTL[PRDLD] =.." line.word 0x4 "CONTROLSS_G3_EPWM31_TBPRDHRB,Calculation Result for EPWMxB" hexmask.word.byte 0x4 8.--15. 1. "TBPRDHRB,TBPRD High Resolution Calculation [2] Results for EPWMxB HRPWM Equations" newline hexmask.word.byte 0x4 0.--7. 1. "TBPRDHRB_DELAY,TBPRDHRB Delay" group.long 0xD4++0x7 line.long 0x0 "CONTROLSS_G3_EPWM31_CMPA,Counter Compare A Register" hexmask.long.word 0x0 16.--31. 1. "CMPA,Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare A event. This event is.." newline hexmask.long.word 0x0 0.--15. 1. "CMPAHR,Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the.." line.long 0x4 "CONTROLSS_G3_EPWM31_CMPB,Compare B Register" hexmask.long.word 0x4 16.--31. 1. "CMPB,Compare B Register The value in the active CMPB register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare B event. This event is.." newline hexmask.long.word 0x4 0.--15. 1. "CMPBHR,Compare B High Resolution Bits The lower 8 bits in this register are ignored" group.word 0xDE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_CMPC,Counter Compare C Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPC,Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare C event. Shadowing of.." group.word 0xE2++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_CMPD,Counter Compare D Register [[br]] [[br]]LINK feature access should always be 16-bit" hexmask.word 0x0 0.--15. 1. "CMPD,Compare D Register The value in the active CMPD register is continuously compared to the time-base counter [TBCTR]. When the values are equal the counter-compare module generates a time-base counter equal to counter compare D event. Shadowing of.." group.word 0xE8++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_GLDCTL2,Global PWM Load Control Register 2" bitfld.word 0x0 1. "GFRCLD,Force Load Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or.." "0: Writing of 0 will be ignored,1: Force one load event at the input of the event.." newline bitfld.word 0x0 0. "OSHTLD,Enable Reload Event in One Shot Mode 0: Writing of 0 will be ignored. Always reads back a 0. 1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared." "0: Writing of 0 will be ignored,1: Turns the one shot latch condition ON" group.word 0xEE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_SWVDELVAL,Software Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "SWVDELVAL,Software Valley Delay Value Register This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits." group.word 0x100++0x5 line.word 0x0 "CONTROLSS_G3_EPWM31_TZSEL,Trip Zone Select Register" bitfld.word 0x0 15. "DCBEVT1,Digital Compare Output B Event 1 Select 0: Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCBEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCBEVT1 as one-shot-trip source for this..,1: Enable DCBEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 14. "DCAEVT1,Digital Compare Output A Event 1 Select 0: Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1: Enable DCAEVT1 as one-shot-trip source for this ePWM module." "0: Disable DCAEVT1 as one-shot-trip source for this..,1: Enable DCAEVT1 as one-shot-trip source for this.." newline bitfld.word 0x0 13. "OSHT6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a one-shot trip source for this ePWM module 1: Enable TZ6 as a one-shot trip source for this ePWM module" "0: Disable TZ6 as a one-shot trip source for this..,1: Enable TZ6 as a one-shot trip source for this.." newline bitfld.word 0x0 12. "OSHT5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a one-shot trip source for this ePWM module 1: Enable TZ5 as a one-shot trip source for this ePWM module" "0: Disable TZ5 as a one-shot trip source for this..,1: Enable TZ5 as a one-shot trip source for this.." newline bitfld.word 0x0 11. "OSHT4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a one-shot trip source for this ePWM module 1: Enable TZ4 as a one-shot trip source for this ePWM module" "0: Disable TZ4 as a one-shot trip source for this..,1: Enable TZ4 as a one-shot trip source for this.." newline bitfld.word 0x0 10. "OSHT3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a one-shot trip source for this ePWM module 1: Enable TZ3 as a one-shot trip source for this ePWM module" "0: Disable TZ3 as a one-shot trip source for this..,1: Enable TZ3 as a one-shot trip source for this.." newline bitfld.word 0x0 9. "OSHT2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a one-shot trip source for this ePWM module 1: Enable TZ2 as a one-shot trip source for this ePWM module" "0: Disable TZ2 as a one-shot trip source for this..,1: Enable TZ2 as a one-shot trip source for this.." newline bitfld.word 0x0 8. "OSHT1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a one-shot trip source for this ePWM module 1: Enable TZ1 as a one-shot trip source for this ePWM module" "0: Disable TZ1 as a one-shot trip source for this..,1: Enable TZ1 as a one-shot trip source for this.." newline bitfld.word 0x0 7. "DCBEVT2,Digital Compare Output B Event 2 Select 0: Disable DCBEVT2 as a CBC trip source for this ePWM module 1: Enable DCBEVT2 as a CBC trip source for this ePWM module" "0: Disable DCBEVT2 as a CBC trip source for this..,1: Enable DCBEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 6. "DCAEVT2,Digital Compare Output A Event 2 Select 0: Disable DCAEVT2 as a CBC trip source for this ePWM module 1: Enable DCAEVT2 as a CBC trip source for this ePWM module" "0: Disable DCAEVT2 as a CBC trip source for this..,1: Enable DCAEVT2 as a CBC trip source for this.." newline bitfld.word 0x0 5. "CBC6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a CBC trip source for this ePWM module 1: Enable TZ6 as a CBC trip source for this ePWM module" "0: Disable TZ6 as a CBC trip source for this ePWM..,1: Enable TZ6 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 4. "CBC5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a CBC trip source for this ePWM module 1: Enable TZ5 as a CBC trip source for this ePWM module" "0: Disable TZ5 as a CBC trip source for this ePWM..,1: Enable TZ5 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 3. "CBC4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a CBC trip source for this ePWM module 1: Enable TZ4 as a CBC trip source for this ePWM module" "0: Disable TZ4 as a CBC trip source for this ePWM..,1: Enable TZ4 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 2. "CBC3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a CBC trip source for this ePWM module 1: Enable TZ3 as a CBC trip source for this ePWM module" "0: Disable TZ3 as a CBC trip source for this ePWM..,1: Enable TZ3 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 1. "CBC2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a CBC trip source for this ePWM module 1: Enable TZ2 as a CBC trip source for this ePWM module" "0: Disable TZ2 as a CBC trip source for this ePWM..,1: Enable TZ2 as a CBC trip source for this ePWM.." newline bitfld.word 0x0 0. "CBC1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a CBC trip source for this ePWM module 1: Enable TZ1 as a CBC trip source for this ePWM module" "0: Disable TZ1 as a CBC trip source for this ePWM..,1: Enable TZ1 as a CBC trip source for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM31_TZSEL2,Trip Zone Select Register 2" bitfld.word 0x2 8. "CAPEVTOST,CAPEVT OST Select 0: Disable CAPEVT as a one-shot trip source for this ePWM module 1: Enable CAPEVT as a one-shot trip source for this ePWM module" "0: Disable CAPEVT as a one-shot trip source for..,1: Enable CAPEVT as a one-shot trip source for this.." newline bitfld.word 0x2 0. "CAPEVTCBC,CAPEVT CBC mode Select 0: Disable CAPEVT as a CBC trip source for this ePWM module 1: Enable CAPEVT as a CBC trip source for this ePWM module" "0: Disable CAPEVT as a CBC trip source for this..,1: Enable CAPEVT as a CBC trip source for this ePWM.." line.word 0x4 "CONTROLSS_G3_EPWM31_TZDCSEL,Trip Zone Digital Comparator Select Register" bitfld.word 0x4 9.--11. "DCBEVT2,Digital Compare Output B Event 2 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCBEVT1,Digital Compare Output B Event 1 Selection 000: Event disabled 001: DCBH = low DCBL = don't care 010: DCBH = high DCBL = don't care 011: DCBL = low DCBH = don't care 100: DCBL = high DCBH = don't care 101: DCBL = high DCBH = low 110:.." "0: Event disabled,1: DCBH = low,?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT2,Digital Compare Output A Event 2 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1,Digital Compare Output A Event 1 Selection 000: Event disabled 001: DCAH = low DCAL = don't care 010: DCAH = high DCAL = don't care 011: DCAL = low DCAH = don't care 100: DCAL = high DCAH = don't care 101: DCAL = high DCAH = low 110:.." "0: Event disabled,1: DCAH = low,?,?,?,?,?,?" group.word 0x108++0x7 line.word 0x0 "CONTROLSS_G3_EPWM31_TZCTL,Trip Zone Control Register" bitfld.word 0x0 10.--11. "DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 8.--9. "DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB 00: High-impedance [EPWMxB = High-impedance state] 01: Force EPWMxB to a high state. 10: Force EPWMxB to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 6.--7. "DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 4.--5. "DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA 00: High-impedance [EPWMxA = High-impedance state] 01: Force EPWMxA to a high state. 10: Force EPWMxA to a low state. 11: Do Nothing trip action is disabled" "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" newline bitfld.word 0x0 2.--3. "TZB,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2Trip Action On EPWMxB When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxB = High-impedance.." "0: High-impedance [EPWMxB = High-impedance state],1: Force EPWMxB to a high state,?,?" newline bitfld.word 0x0 0.--1. "TZA,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 00: High-impedance [EPWMxA = High-impedance.." "0: High-impedance [EPWMxA = High-impedance state],1: Force EPWMxA to a high state,?,?" line.word 0x2 "CONTROLSS_G3_EPWM31_TZCTL2,Additional Trip Zone Control Register" bitfld.word 0x2 15. "ETZE,TZCTL2 Enable 0: Use trip action from TZCTL [legacy EPWM compatibility] 1: Use trip action defined in TZCTL2 TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored" "0: Use trip action from TZCTL [legacy EPWM..,1: Use trip action defined in TZCTL2" newline bitfld.word 0x2 9.--11. "TZBD,TZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101: Reserved 110:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 6.--8. "TZBU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x2 3.--5. "TZAD,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x2 0.--2. "TZAU,TZ1 to TZ6 DCAEVT1/2 DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x4 "CONTROLSS_G3_EPWM31_TZCTLDCA,Trip Zone Control Register Digital Compare A" bitfld.word 0x4 9.--11. "DCAEVT2D,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 6.--8. "DCAEVT2U,Digital Compare Output A Event 2 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 3.--5. "DCAEVT1D,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" newline bitfld.word 0x4 0.--2. "DCAEVT1U,Digital Compare Output A Event 1 Action On EPWMxA while Count direction is UP 000: HiZ [EPWMxA = HiZ state] 001: Forced Hi [EPWMxA = High state] 010: Forced Lo [EPWMxA = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxA = HiZ state],1: Forced Hi [EPWMxA = High state],?,?,?,?,?,?" line.word 0x6 "CONTROLSS_G3_EPWM31_TZCTLDCB,Trip Zone Control Register Digital Compare B" bitfld.word 0x6 9.--11. "DCBEVT2D,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 6.--8. "DCBEVT2U,Digital Compare Output B Event 2 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 3.--5. "DCBEVT1D,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" newline bitfld.word 0x6 0.--2. "DCBEVT1U,Digital Compare Output B Event 1 Action On EPWMxB while Count direction is UP 000: HiZ [EPWMxB = HiZ state] 001: Forced Hi [EPWMxB = High state] 010: Forced Lo [EPWMxB = Lo state] 011: Toggle [Low -> High High -> Low] 100: Reserved 101:.." "0: HiZ [EPWMxB = HiZ state],1: Forced Hi [EPWMxB = High state],?,?,?,?,?,?" group.word 0x11A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_TZEINT,Trip Zone Enable Interrupt Register" bitfld.word 0x0 7. "CAPEVT,Capture Event Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "DCBEVT2,Digital Compare Output B Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 5. "DCBEVT1,Digital Compare Output B Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 4. "DCAEVT2,Digital Compare Output A Event 2 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 3. "DCAEVT1,Digital Compare Output A Event 1 Interrupt Enable 0: Disabled 1: Enabled" "0: Disabled,1: Enabled" newline bitfld.word 0x0 2. "OST,Trip-zone One-Shot Interrupt Enable 0: Disable one-shot interrupt generation 1: Enable Interrupt generation a one-shot trip event will cause a EPWMx_TZINT PIE interrupt." "0: Disable one-shot interrupt generation,1: Enable Interrupt generation a one-shot trip.." newline bitfld.word 0x0 1. "CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0: Disable cycle-by-cycle interrupt generation. 1: Enable interrupt generation a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt." "0: Disable cycle-by-cycle interrupt generation,1: Enable interrupt generation a cycle-by-cycle.." rgroup.word 0x126++0x5 line.word 0x0 "CONTROLSS_G3_EPWM31_TZFLG,Trip Zone Flag Register" bitfld.word 0x0 7. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 6. "DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0: Indicates no trip event has occurred on DCBEVT2 1: Indicates a trip event has occurred for the event defined for DCBEVT2" "0: Indicates no trip event has occurred on DCBEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 5. "DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0: Indicates no trip event has occurred on DCBEVT1 1: Indicates a trip event has occurred for the event defined for DCBEVT1" "0: Indicates no trip event has occurred on DCBEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 4. "DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0: Indicates no trip event has occurred on DCAEVT2 1: Indicates a trip event has occurred for the event defined for DCAEVT2" "0: Indicates no trip event has occurred on DCAEVT2,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 3. "DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0: Indicates no trip event has occurred on DCAEVT1 1: Indicates a trip event has occurred for the event defined for DCAEVT1" "0: Indicates no trip event has occurred on DCAEVT1,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x0 2. "OST,Latched Status Flag for A One-Shot Trip Event 0: No one-shot trip event has occurred. 1: Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register." "0: No one-shot trip event has occurred,1: Indicates a trip event has occurred on a pin.." newline bitfld.word 0x0 1. "CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0: No cycle-by-cycle trip event has occurred. 1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually.." "0: No cycle-by-cycle trip event has occurred,1: Indicates a trip event has occurred on a signal.." newline bitfld.word 0x0 0. "INT,Latched Trip Interrupt Status Flag 0: Indicates no interrupt has been generated. 1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition. No further EPWMx_TZINT PIE interrupts will be generated until this flag is.." "0: Indicates no interrupt has been generated,1: Indicates an EPWMx_TZINT PIE interrupt was.." line.word 0x2 "CONTROLSS_G3_EPWM31_TZCBCFLG,Trip Zone CBC Flag Register" bitfld.word 0x2 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x2 7. "DCBEVT2,Latched Status Flag for Digital Compare B Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT2. 1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 6. "DCAEVT2,Latched Status Flag for Digital Compare A Output Event 2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT2. 1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 5. "CBC6,Latched Status Flag for CBC6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC6. 1: Reading a 1 indicates a trip has occured on the CBC6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 4. "CBC5,Latched Status Flag for CBC5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC5. 1: Reading a 1 indicates a trip has occured on the CBC5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 3. "CBC4,Latched Status Flag for CBC4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC4. 1: Reading a 1 indicates a trip has occured on the CBC4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 2. "CBC3,Latched Status Flag for CBC3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC3. 1: Reading a 1 indicates a trip has occured on the CBC3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 1. "CBC2,Latched Status Flag for CBC2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC2. 1: Reading a 1 indicates a trip has occured on the CBC2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x2 0. "CBC1,Latched Status Flag for CBC1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on CBC1. 1: Reading a 1 indicates a trip has occured on the CBC1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." line.word 0x4 "CONTROLSS_G3_EPWM31_TZOSTFLG,Trip Zone OST Flag Register" bitfld.word 0x4 8. "CAPEVT,Latched Status Flag for Capture Event 0: Indicates no trip event has occurred on CAPEVT 1: Indicates a trip event has occurred for the event defined for CAPEVT" "0: Indicates no trip event has occurred on CAPEVT,1: Indicates a trip event has occurred for the.." newline bitfld.word 0x4 7. "DCBEVT1,Latched Status Flag for Digital Compare B Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCBEVT1. 1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 6. "DCAEVT1,Latched Status Flag for Digital Compare A Output Event 1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on DCAEVT1. 1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 5. "OST6,Latched Status Flag for OST6 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST6. 1: Reading a 1 indicates a trip has occured on the OST6 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 4. "OST5,Latched Status Flag for OST5 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST5. 1: Reading a 1 indicates a trip has occured on the OST5 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 3. "OST4,Latched Status Flag for OST4 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST4. 1: Reading a 1 indicates a trip has occured on the OST4 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 2. "OST3,Latched Status Flag for OST3 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST3. 1: Reading a 1 indicates a trip has occured on the OST3 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 1. "OST2,Latched Status Flag for OST2 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST2. 1: Reading a 1 indicates a trip has occured on the OST2 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." newline bitfld.word 0x4 0. "OST1,Latched Status Flag for OST1 Trip Latch 0: Reading a 0 indicates that no trip has occurred on OST1. 1: Reading a 1 indicates a trip has occured on the OST1 selected event." "0: Reading a 0 indicates that no trip has occurred..,1: Reading a 1 indicates a trip has occured on the.." group.word 0x12E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM31_TZCLR,Trip Zone Clear Register" bitfld.word 0x0 14.--15. "CBCPULSE,Clear Pulse for Cycle-By-Cycle [CBC] Trip Latch This bit field determines which pulse clears the CBC trip latch. 00: CTR = zero pulse clears CBC trip latch. [Same as legacy designs.] 01: CTR = PRD pulse clears CBC trip latch. 10: CTR = zero.." "0: CTR = zero pulse clears CBC trip latch,1: CTR = PRD pulse clears CBC trip latch,?,?" newline bitfld.word 0x0 7. "CAPEVT,Clear Flag for Capture Event 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the CAPEVT event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the CAPEVT event trip condition" newline bitfld.word 0x0 6. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT2 event trip condition" newline bitfld.word 0x0 5. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCBEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCBEVT1 event trip condition" newline bitfld.word 0x0 4. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT2 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT2 event trip condition" newline bitfld.word 0x0 3. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 clears the DCAEVT1 event trip condition." "0: Writing 0 has no effect,1: Writing 1 clears the DCAEVT1 event trip condition" newline bitfld.word 0x0 2. "OST,Clear Flag for One-Shot Trip [OST] Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 1. "CBC,Clear Flag for Cycle-By-Cycle [CBC] Trip Latch 0: Has no effect. Always reads back a 0. 1: Clears this Trip [set] condition." "0: Has no effect,1: Clears this Trip [set] condition" newline bitfld.word 0x0 0. "INT,Global Interrupt Clear Flag 0: Has no effect. Always reads back a 0. 1: Clears the trip-interrupt flag for this ePWM module [TZFLG[INT]]. NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT].." "0: Has no effect,1: Clears the trip-interrupt flag for this ePWM.." line.word 0x2 "CONTROLSS_G3_EPWM31_TZCBCCLR,Trip Zone CBC Clear Register" bitfld.word 0x2 8. "CAPEVT,Clear Flag for CAPEVT selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CAPEVT] bit" newline bitfld.word 0x2 7. "DCBEVT2,Clear Flag for Digital Compare Output B Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit" newline bitfld.word 0x2 6. "DCAEVT2,Clear Flag for Digital Compare Output A Event 2 selected for CBC 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit" newline bitfld.word 0x2 5. "CBC6,Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC6] bit" newline bitfld.word 0x2 4. "CBC5,Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC5] bit" newline bitfld.word 0x2 3. "CBC4,Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC4] bit" newline bitfld.word 0x2 2. "CBC3,Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC3] bit" newline bitfld.word 0x2 1. "CBC2,Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC2] bit" newline bitfld.word 0x2 0. "CBC1,Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZCBCFLG[CBC1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZCBCFLG[CBC1] bit" line.word 0x4 "CONTROLSS_G3_EPWM31_TZOSTCLR,Trip Zone OST Clear Register" bitfld.word 0x4 8. "CAPEVT,Clear Flag for CAPEVT selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[CAPEVT] bit" newline bitfld.word 0x4 7. "DCBEVT1,Clear Flag for Digital Compare Output B Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit" newline bitfld.word 0x4 6. "DCAEVT1,Clear Flag for Digital Compare Output A Event 1 selected for OST 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit" newline bitfld.word 0x4 5. "OST6,Clear Flag for Oneshot [OST6] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST6] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST6] bit" newline bitfld.word 0x4 4. "OST5,Clear Flag for Oneshot [OST5] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST5] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST5] bit" newline bitfld.word 0x4 3. "OST4,Clear Flag for Oneshot [OST4] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST4] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST4] bit" newline bitfld.word 0x4 2. "OST3,Clear Flag for Oneshot [OST3] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST3] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST3] bit" newline bitfld.word 0x4 1. "OST2,Clear Flag for Oneshot [OST2] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST2] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST2] bit" newline bitfld.word 0x4 0. "OST1,Clear Flag for Oneshot [OST1] Trip Latch 0: Writing a 0 has no effect. 1: Writing a 1 will clear the TZOSTFLG[OST1] bit." "0: Writing a 0 has no effect,1: Writing a 1 will clear the TZOSTFLG[OST1] bit" group.word 0x136++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_TZFRC,Trip Zone Force Register" bitfld.word 0x0 7. "CAPEVT,Force Flag for Capture Event Output 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit." "0: Writing 0 has no effect,1: Writing 1 forces the CAPEVT event trip condition.." newline bitfld.word 0x0 6. "DCBEVT2,Force Flag for Digital Compare Output B Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT2 event trip.." newline bitfld.word 0x0 5. "DCBEVT1,Force Flag for Digital Compare Output B Event 1 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCBEVT1 event trip.." newline bitfld.word 0x0 4. "DCAEVT2,Force Flag for Digital Compare Output A Event 2 0: Writing 0 has no effect. This bit always reads back 0. 1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT2 event trip.." newline bitfld.word 0x0 3. "DCAEVT1,Force Flag for Digital Compare Output A Event 1 0: Writing 0 has no effect. This bit always reads back 0 1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit." "0: Writing 0 has no effect,1: Writing 1 forces the DCAEVT1 event trip.." newline bitfld.word 0x0 2. "OST,Force a One-Shot Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a one-shot trip event and sets the TZFLG[OST] bit." "0: Writing of 0 is ignored,1: Forces a one-shot trip event and sets the.." newline bitfld.word 0x0 1. "CBC,Force a Cycle-by-Cycle Trip Event via Software 0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit." "0: Writing of 0 is ignored,1: Forces a cycle-by-cycle trip event and sets the.." group.word 0x13A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_TZTRIPOUTSEL,Trip Zone Force Register" bitfld.word 0x0 12. "CAPEVT,CAPEVT Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 11. "DCBEVT2,DCBEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 10. "DCBEVT1,DCBEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 9. "DCAEVT2,DCAEVT2 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 8. "DCAEVT1,DCAEVT1 Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 7. "TZ6,Trip-zone 6 [TZ6] Select 0: Disable TZ6 as a TRIPOUT source for this ePWM module 1: Enable TZ6 as a TRIPOUT source for this ePWM module" "0: Disable TZ6 as a TRIPOUT source for this ePWM..,1: Enable TZ6 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 6. "TZ5,Trip-zone 5 [TZ5] Select 0: Disable TZ5 as a TRIPOUT source for this ePWM module 1: Enable TZ5 as a TRIPOUT source for this ePWM module" "0: Disable TZ5 as a TRIPOUT source for this ePWM..,1: Enable TZ5 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 5. "TZ4,Trip-zone 4 [TZ4] Select 0: Disable TZ4 as a TRIPOUT source for this ePWM module 1: Enable TZ4 as a TRIPOUT source for this ePWM module" "0: Disable TZ4 as a TRIPOUT source for this ePWM..,1: Enable TZ4 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 4. "TZ3,Trip-zone 3 [TZ3] Select 0: Disable TZ3 as a TRIPOUT source for this ePWM module 1: Enable TZ3 as a TRIPOUT source for this ePWM module" "0: Disable TZ3 as a TRIPOUT source for this ePWM..,1: Enable TZ3 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 3. "TZ2,Trip-zone 2 [TZ2] Select 0: Disable TZ2 as a TRIPOUT source for this ePWM module 1: Enable TZ2 as a TRIPOUT source for this ePWM module" "0: Disable TZ2 as a TRIPOUT source for this ePWM..,1: Enable TZ2 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 2. "TZ1,Trip-zone 1 [TZ1] Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 1. "CBC,CBC Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." newline bitfld.word 0x0 0. "OST,OST Select 0: Disable TZ1 as a TRIPOUT source for this ePWM module 1: Enable TZ1 as a TRIPOUT source for this ePWM module" "0: Disable TZ1 as a TRIPOUT source for this ePWM..,1: Enable TZ1 as a TRIPOUT source for this ePWM.." group.word 0x148++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_ETSEL,Event Trigger Selection Register" bitfld.word 0x0 15. "SOCBEN,Enable the ADC Start of Conversion B [EPWMxSOCB] Pulse 0: Disable EPWMxSOCB. 1: Enable EPWMxSOCB pulse." "0: Disable EPWMxSOCB,1: Enable EPWMxSOCB pulse" newline bitfld.word 0x0 12.--14. "SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 000: Enable DCBEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCBEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 11. "SOCAEN,Enable the ADC Start of Conversion A [EPWMxSOCA] Pulse 0: Disable EPWMxSOCA. 1: Enable EPWMxSOCA pulse." "0: Disable EPWMxSOCA,1: Enable EPWMxSOCA pulse" newline bitfld.word 0x0 8.--10. "SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 000: Enable DCAEVT1.soc event 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period.." "0: Enable DCAEVT1,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" newline bitfld.word 0x0 6. "INTSELCMP,EPWMxINT Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 5. "SOCBSELCMP,EPWMxSOCB Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 4. "SOCASELCMP,EPWMxSOCA Compare Register Selection Options 0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal.." "0: Enable event time-base counter equal to CMPA..,1: Enable event time-base counter equal to CMPC.." newline bitfld.word 0x0 3. "INTEN,Enable ePWM Interrupt [EPWMx_INT] Generation 0: Disable EPWMx_INT generation 1: Enable EPWMx_INT generation" "0: Disable EPWMx_INT generation,1: Enable EPWMx_INT generation" newline bitfld.word 0x0 0.--2. "INTSEL,ePWM Interrupt [EPWMx_INT] Selection Options 000: Reserved 001: Enable event time-base counter equal to zero. [TBCTR = 0x00] 010: Enable event time-base counter equal to period [TBCTR = TBPRD] 011: Enable event time-base counter based on.." "0: Reserved,1: Enable event time-base counter equal to zero,?,?,?,?,?,?" group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_ETPS,Event Trigger Pre-Scale Register" rbitfld.word 0x0 14.--15. "SOCBCNT,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 12.--13. "SOCBPRD,ePWM ADC Start-of-Conversion B Event [EPWMxSOCB] Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCBEN] = 1]. The.." "0: Disable the SOCB event counter,1: Generate the EPWMxSOCB pulse on the first event:..,?,?" newline rbitfld.word 0x0 10.--11. "SOCACNT,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 00: No events have occurred. 01: 1 event has occurred. 10: 2 events have occurred. 11: 3 events.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 8.--9. "SOCAPRD,ePWM ADC Start-of-Conversion A Event [EPWMxSOCA] Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated the pulse must be enabled [ETSEL[SOCAEN] = 1]. The.." "0: Disable the SOCA event counter,1: Generate the EPWMxSOCA pulse on the first event:..,?,?" newline bitfld.word 0x0 5. "SOCPSSEL,EPWMxSOC A/B Pre-Scale Selection Bits 0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2].." "0: Selects ETPS [SOCACNT/SOCBCNT] and..,1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and.." newline bitfld.word 0x0 4. "INTPSSEL,EPWMxINTn Pre-Scale Selection Bits 0: Selects ETPS [INTCNT and INTPRD] registers to determine frequency of events [interrupt once every 0-3 events]. 1: Selects ETINTPS [ INTCNT2 and INTPRD2 ] registers to determine frequency of events.." "0: Selects ETPS [INTCNT,1: Selects ETINTPS [ INTCNT2" newline rbitfld.word 0x0 2.--3. "INTCNT,ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled ETSEL[INT] = 0 or.." "0: No events have occurred,1: 1 event has occurred,?,?" newline bitfld.word 0x0 0.--1. "INTPRD,ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated the interrupt must be enabled [ETSEL[INT] = 1]. If the interrupt status flag is.." "0: Disable the interrupt event counter,1: Generate an interrupt on the first event INTCNT..,?,?" rgroup.word 0x150++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_ETFLG,Event Trigger Flag Register" bitfld.word 0x0 3. "SOCB,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCB] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCB output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 2. "SOCA,Latched ePWM ADC Start-of-Conversion A [EPWMxSOCA] Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0: Indicates no event occurred 1: Indicates that a start of conversion pulse was.." "0: Indicates no event occurred,1: Indicates that a start of conversion pulse was.." newline bitfld.word 0x0 0. "INT,Latched ePWM Interrupt [EPWMx_INT] Status Flag 0: Indicates no event occurred 1: Indicates that an ePWMx interrupt [EPWMx_INT] was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending.." "0: Indicates no event occurred,1: Indicates that an ePWMx interrupt [EPWMx_INT].." group.word 0x154++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_ETCLR,Event Trigger Clear Register" bitfld.word 0x0 3. "SOCB,ePWM ADC Start-of-Conversion A [EPWMxSOCB] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCB] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCB] flag bit" newline bitfld.word 0x0 2. "SOCA,ePWM ADC Start-of-Conversion A [EPWMxSOCA] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[SOCA] flag bit" "0: Writing a 0 has no effect,1: Clears the ETFLG[SOCA] flag bit" newline bitfld.word 0x0 0. "INT,ePWM Interrupt [EPWMx_INT] Flag Clear Bit 0: Writing a 0 has no effect. Always reads back a 0 1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated" "0: Writing a 0 has no effect,1: Clears the ETFLG[INT] flag bit and enable.." group.word 0x158++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_ETFRC,Event Trigger Force Register" bitfld.word 0x0 3. "SOCB,SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCB and set the.." newline bitfld.word 0x0 2. "SOCA,SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates a pulse on.." "0: Writing 0 to this bit will be ignored,1: Generates a pulse on EPWMxSOCA and set the.." newline bitfld.word 0x0 0. "INT,INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0: Writing 0 to this bit will be ignored. Always reads back a 0. 1: Generates an interrupt on EPWMxINT and.." "0: Writing 0 to this bit will be ignored,1: Generates an interrupt on EPWMxINT and set the.." group.word 0x15C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_ETINTPS,Event-Trigger Interrupt Pre-Scale Register" hexmask.word.byte 0x0 4.--7. 1. "INTCNT2,EPWMxINT Counter 2 When ETPS[INTPSSEL]=1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "INTPRD2,EPWMxINT Period 2 Select When ETPS[INTPSSEL] = 1 these bits select how many selected events need to occur before an interrupt is generated: 0000: Disable counter 0001: Generate interrupt on INTCNT = 1 [first event] 0010: Generate interrupt.." group.word 0x160++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_ETSOCPS,Event-Trigger SOC Pre-Scale Register" hexmask.word.byte 0x0 12.--15. 1. "SOCBCNT2,EPWMxSOCB Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 8.--11. 1. "SOCBPRD2,EPWMxSOCB Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCB pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCBCNT2 = 1 [first event] 0010: Generate.." newline hexmask.word.byte 0x0 4.--7. 1. "SOCACNT2,EPWMxSOCA Counter 2 When ETPS[SOCPSSEL] = 1 these bits indicate how many selected events have occurred: 0000: No events 0001: 1 event 0010: 2 events 0011: 3 events 0100: 4 events ... 1111: 15 events" newline hexmask.word.byte 0x0 0.--3. 1. "SOCAPRD2,EPWMxSOCA Period 2 Select When ETPS[SOCPSSEL] = 1 these bits select how many selected event need to occur before an SOCA pulse is generated: 0000: Disable counter 0001: Generate interrupt on SOCACNT2 = 1 [first event] 0010: Generate.." group.word 0x164++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_ETCNTINITCTL,Event-Trigger Counter Initialization Control Register" bitfld.word 0x0 15. "SOCBINITEN,EPWMxSOCB Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCB counter with.." newline bitfld.word 0x0 14. "SOCAINITEN,EPWMxSOCA Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxSOCA counter with.." newline bitfld.word 0x0 13. "INTINITEN,EPWMxINT Counter 2 Initialization Enable 0: Has no effect. 1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force." "0: Has no effect,1: Enable initialization of EPWMxINT counter 2 with.." newline bitfld.word 0x0 12. "SOCBINITFRC,EPWMxSOCB Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCB counter to be.." newline bitfld.word 0x0 11. "SOCAINITFRC,EPWMxSOCA Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT]." "0: Has no effect,1: This bit forces the ET EPWMxSOCA counter to be.." newline bitfld.word 0x0 10. "INTINITFRC,EPWMxINT Counter 2 Initialization Force 0: Has no effect. 1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT]." "0: Has no effect,1: This bit forces the ET EPWMxINT counter to be.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_ETCNTINIT,Event-Trigger Counter Initialization Register" hexmask.word.byte 0x0 8.--11. 1. "SOCBINIT,EPWMxSOCB Counter 2 Initialization Bits The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 4.--7. 1. "SOCAINIT,EPWMxSOCA Counter 2 Initialization Bits The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force." newline hexmask.word.byte 0x0 0.--3. 1. "INTINIT,EPWMxINT Counter 2 Initialization Bits The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force." group.word 0x16C++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_ETINTMIXEN,Event-Trigger Mixed INT Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET interrupt trigger signal [ETINTMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET interrupt trigger signal [ETINTMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET interrupt trigger signal [ETINTMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x170++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_ETSOCAMIXEN,Event-Trigger Mixed SOCA Selection" bitfld.word 0x0 10. "DCAEVT1,Enable DCAEVT1.inter to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: DCAEVT1.soc event is not enabled 1: Enable DCAEVT1.soc event" "0: DCAEVT1,1: Enable DCAEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCA trigger signal [ETSOCAMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x174++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_ETSOCBMIXEN,Event-Trigger Mixed SOCB Selection" bitfld.word 0x0 10. "DCBEVT1,Enable DCBEVT1.inter to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: DCBEVT1.soc event is not enabled 1: Enable DCBEVT1.soc event" "0: DCBEVT1,1: Enable DCBEVT1" newline bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the mixed ET SOCB trigger signal [ETSOCBMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" group.word 0x180++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_DCTRIPSEL,Digital Compare Trip Select Register" hexmask.word.byte 0x0 12.--15. 1. "DCBLCOMPSEL,Digital Compare B Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBLTRIPSEL.." newline hexmask.word.byte 0x0 8.--11. 1. "DCBHCOMPSEL,Digital Compare B High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCBHTRIPSEL.." newline hexmask.word.byte 0x0 4.--7. 1. "DCALCOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCALTRIPSEL.." newline hexmask.word.byte 0x0 0.--3. 1. "DCAHCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by DCAHTRIPSEL.." group.word 0x186++0x3 line.word 0x0 "CONTROLSS_G3_EPWM31_DCACTL,Digital Compare A Control Register" rbitfld.word 0x0 15. "EVT2LAT,Indicates the status of DCAEVT2LAT signal. 0 The DCAEVT2LAT latch is cleared. 1 The DCAEVT2LAT latch is set." "0,1" newline bitfld.word 0x0 13.--14. "EVT2LATCLRSEL,DCAEVT2 Latched clear source select: 00 CNT_ZERO event clears DCAEVT2 latch. 01 PRD_EQ event clears DCAEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 12. "EVT2LATSEL,DCAEVT2 Latched signal select: 0 Does not select the DCAEVT2 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT2.force. 1 Selects the DCAEVT2 latched signal as source of DCAEVT2.force." "0,1" newline bitfld.word 0x0 9. "EVT2FRCSYNCSEL,DCAEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 8. "EVT2SRCSEL,DCAEVT2 Source Signal Select 0: Source Is DCAEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x0 7. "EVT1LAT,Indicates the status of DCAEVT1LAT signal. 0 The DCAEVT1LAT latch is cleared. 1 The DCAEVT1LAT latch is set." "0,1" newline bitfld.word 0x0 5.--6. "EVT1LATCLRSEL,DCAEVT1 Latched clear source select: 00 CNT_ZERO event clears DCAEVT1 latch. 01 PRD_EQ event clears DCAEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x0 4. "EVT1LATSEL,DCAEVT1 Latched signal select: 0 Does not select the DCAEVT1 latched signal [Refer figure Modifications to DCAEVT1.force/DCAEVT2.force generation.] as source of DCAEVT1.force. 1 Selects the DCAEVT1 latched signal as source of DCAEVT1.force." "0,1" newline bitfld.word 0x0 3. "EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x0 2. "EVT1SOCE,DCAEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x0 1. "EVT1FRCSYNCSEL,DCAEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x0 0. "EVT1SRCSEL,DCAEVT1 Source Signal Select 0: Source Is DCAEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCEVTFILT Signal" line.word 0x2 "CONTROLSS_G3_EPWM31_DCBCTL,Digital Compare B Control Register" rbitfld.word 0x2 15. "EVT2LAT,Indicates the status of DCBEVT2LAT signal. 0 The DCBEVT2LAT latch is cleared. 1 The DCBEVT2LAT latch is set." "0,1" newline bitfld.word 0x2 13.--14. "EVT2LATCLRSEL,DCBEVT2 Latched clear source select: 00 CNT_ZERO event clears DCBEVT2 latch. 01 PRD_EQ event clears DCBEVT2 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 12. "EVT2LATSEL,DCBEVT2 Latched signal select: 0 Does not select the DCBEVT2 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT2.force. 1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force." "0,1" newline bitfld.word 0x2 9. "EVT2FRCSYNCSEL,DCBEVT2 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 8. "EVT2SRCSEL,DCBEVT2 Source Signal Select 0: Source Is DCBEVT2 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT2 Signal,1: Source Is DCEVTFILT Signal" newline rbitfld.word 0x2 7. "EVT1LAT,Indicates the status of DCBEVT1LAT signal. 0 The DCBEVT1LAT latch is cleared. 1 The DCBEVT1LAT latch is set." "0,1" newline bitfld.word 0x2 5.--6. "EVT1LATCLRSEL,DCBEVT1 Latched clear source select: 00 CNT_ZERO event clears DCBEVT1 latch. 01 PRD_EQ event clears DCBEVT1 latch. 10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch. 11 Reserved." "0,1,2,3" newline bitfld.word 0x2 4. "EVT1LATSEL,DCBEVT1 Latched signal select: 0 Does not select the DCBEVT1 latched signal [Refer figure Modifications to DCBEVT1.force/DCBEVT2.force generation.] as source of DCBEVT1.force. 1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force." "0,1" newline bitfld.word 0x2 3. "EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0: SYNC Generation Disabled 1: SYNC Generation Enabled" "0: SYNC Generation Disabled,1: SYNC Generation Enabled" newline bitfld.word 0x2 2. "EVT1SOCE,DCBEVT1 SOC Enable/Disable 0: SOC Generation Disabled 1: SOC Generation Enabled" "0: SOC Generation Disabled,1: SOC Generation Enabled" newline bitfld.word 0x2 1. "EVT1FRCSYNCSEL,DCBEVT1 Force Synchronization Signal Select 0: Source is synchronized with EPWMCLK 1: Source is passed through asynchronously" "0: Source is synchronized with EPWMCLK,1: Source is passed through asynchronously" newline bitfld.word 0x2 0. "EVT1SRCSEL,DCBEVT1 Source Signal Select 0: Source Is DCBEVT1 Signal 1: Source Is DCEVTFILT Signal" "0: Source Is DCBEVT1 Signal,1: Source Is DCEVTFILT Signal" group.word 0x18E++0x5 line.word 0x0 "CONTROLSS_G3_EPWM31_DCFCTL,Digital Compare Filter Control Register" rbitfld.word 0x0 13.--15. "EDGESTATUS,Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "EDGECOUNT,Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000: no edges reset current EDGESTATUS bits to 0 0 0 001: 1 edge 010: 2 edges 011: 3 edges 100: 4 edges 101: 5 edges 110: 6.." "0: no edges,1: 1 edge,?,?,?,?,?,?" newline bitfld.word 0x0 8.--9. "EDGEMODE,Edge Mode Select: 00: Low To High Edge 01: High To Low Edge 10: Both Edges 11: Reserved" "0: Low To High Edge,1: High To Low Edge,?,?" newline bitfld.word 0x0 6. "EDGEFILTSEL,Edge Filter Select: 0: Edge Filter Not Selected 1: Edge Filter Selected" "0: Edge Filter Not Selected,1: Edge Filter Selected" newline bitfld.word 0x0 4.--5. "PULSESEL,Pulse Select For Blanking & Capture Alignment 00: Time-base counter equal to period [TBCTR = TBPRD] 01: Time-base counter equal to zero [TBCTR = 0x00] 10: Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11: Blank.." "0: Time-base counter equal to period [TBCTR = TBPRD],1: Time-base counter equal to zero [TBCTR = 0x00],?,?" newline bitfld.word 0x0 3. "BLANKINV,Blanking Window Inversion 0: Blanking window not inverted 1: Blanking window inverted" "0: Blanking window not inverted,1: Blanking window inverted" newline bitfld.word 0x0 2. "BLANKE,Blanking Window Enable/Disable 0: Blanking window is disabled 1: Blanking window is enabled" "0: Blanking window is disabled,1: Blanking window is enabled" newline bitfld.word 0x0 0.--1. "SRCSEL,Filter Block Signal Source Select 00: Source Is DCAEVT1 Signal 01: Source Is DCAEVT2 Signal 10: Source Is DCBEVT1 Signal 11: Source Is DCBEVT2 Signal" "0: Source Is DCAEVT1 Signal,1: Source Is DCAEVT2 Signal,?,?" line.word 0x2 "CONTROLSS_G3_EPWM31_DCCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x2 15. "CAPMODE,Counter Capture Mode 0: When a DCEVTFILT occurs and the counter capture is enabled then the current TBCNT value is captured in the active register. When the respective trip event occurs further trip [capture] events are ignored until the next.." "0: When a DCEVTFILT occurs and the counter capture..,1: When a DCEVTFILT occurs and the counter capture.." newline bitfld.word 0x2 14. "CAPCLR,DC Capture Latched Status Clear Flag 0: Writing a 0 has no effect. 1: Writing a 1 will clear this CAPSTS [set] condition." "0: Writing a 0 has no effect,1: Writing a 1 will clear this CAPSTS [set] condition" newline rbitfld.word 0x2 13. "CAPSTS,Latched Status Flag for Capture Event 0: No DC capture event occurred. 1: A DC capture event has occurred." "0: No DC capture event occurred,1: A DC capture event has occurred" newline bitfld.word 0x2 1. "SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return.." "0: Enable shadow mode,1: Active Mode" newline bitfld.word 0x2 0. "CAPE,TBCTR Counter Capture Enable/Disable 0: Disable the time-base counter capture. 1: Enable the time-base counter capture." "0: Disable the time-base counter capture,1: Enable the time-base counter capture" line.word 0x4 "CONTROLSS_G3_EPWM31_DCFOFFSET,Digital Compare Filter Offset Register" hexmask.word 0x4 0.--15. 1. "DCFOFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the.." rgroup.word 0x194++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_DCFOFFSETCNT,Digital Compare Filter Offset Counter Register" hexmask.word 0x0 0.--15. 1. "DCFOFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the.." group.word 0x196++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_DCFWINDOW,Digital Compare Filter Window Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOW,Blanking Window Width 00h: No blanking window is generated. 01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs the window counter is loaded and.." rgroup.word 0x198++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word 0x0 0.--15. 1. "DCFWINDOWCNT,Blanking Window Counter These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again." group.word 0x19A++0x3 line.word 0x0 "CONTROLSS_G3_EPWM31_BLANKPULSEMIXSEL,Blanking window trigger pulse select register" bitfld.word 0x0 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x0 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x0 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x0 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x0 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x0 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [BLANKPULSEMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x0 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x0 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [BLANKPULSEMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x0 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [BLANKPULSEMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x0 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [BLANKPULSEMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" line.word 0x2 "CONTROLSS_G3_EPWM31_DCCAPMIXSEL,Capture Event pulse select register" bitfld.word 0x2 9. "CDD,Enable event time-base counter equal to CMPD when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD down-count match enable event is not enabled 1: Enable CMPD down-count match enable event" "0: CMPD down-count match enable event is not enabled,1: Enable CMPD down-count match enable event" newline bitfld.word 0x2 8. "CDU,Enable event time-base counter equal to CMPD when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPD up-count match enable event is not enabled 1: Enable CMPD up-count match enable event" "0: CMPD up-count match enable event is not enabled,1: Enable CMPD up-count match enable event" newline bitfld.word 0x2 7. "CCD,Enable event time-base counter equal to CMPC when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC down-count match enable event is not enabled 1: Enable CMPC down-count match enable event" "0: CMPC down-count match enable event is not enabled,1: Enable CMPC down-count match enable event" newline bitfld.word 0x2 6. "CCU,Enable event time-base counter equal to CMPC when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPC up-count match enable event is not enabled 1: Enable CMPC up-count match enable event" "0: CMPC up-count match enable event is not enabled,1: Enable CMPC up-count match enable event" newline bitfld.word 0x2 5. "CBD,Enable event time-base counter equal to CMPB when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPB down-count match enable event is not enabled 1: Enable CMPB down-count match enable event" "0: CMPB down-count match enable event is not enabled,1: Enable CMPB down-count match enable event" newline bitfld.word 0x2 4. "CBU,Enable event time-base counter equal to CMPB when the timer is incrementing to the mixed ET interrupt trigger signal [DCCAPMIX]. 0: CMPB up-count match enable event is not enabled 1: Enable CMPB up-count match enable event" "0: CMPB up-count match enable event is not enabled,1: Enable CMPB up-count match enable event" newline bitfld.word 0x2 3. "CAD,Enable event time-base counter equal to CMPA when the timer is decrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA down-count match enable event is not enabled 1: Enable CMPA down-count match enable event" "0: CMPA down-count match enable event is not enabled,1: Enable CMPA down-count match enable event" newline bitfld.word 0x2 2. "CAU,Enable event time-base counter equal to CMPA when the timer is incrementing to the blanking window trigger [DCCAPMIX]. 0: CMPA up-count match enable event is not enabled 1: Enable CMPA up-count match enable event" "0: CMPA up-count match enable event is not enabled,1: Enable CMPA up-count match enable event" newline bitfld.word 0x2 1. "PRD,Enable event time-base counter equal to period [TBCTR = TBPRD] to the blanking window trigger [DCCAPMIX]. 0: Period match event is not enabled 1: Enable period match event" "0: Period match event is not enabled,1: Enable period match event" newline bitfld.word 0x2 0. "ZRO,Enable event time-base counter equal to zero [TBCTR = 0x00] to the blanking window trigger [DCCAPMIX]. 0: Zero match event is not enabled 1: Enable zero match event" "0: Zero match event is not enabled,1: Enable zero match event" rgroup.word 0x19E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_DCCAP,Digital Compare Counter Capture Register" hexmask.word 0x0 0.--15. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1. If enabled reflects the value of the time-base counter [TBCTR] on the low to high edge transition of a filtered [DCEVTFLT] event." group.word 0x1A4++0xF line.word 0x0 "CONTROLSS_G3_EPWM31_DCAHTRIPSEL,Digital Compare AH Trip Select" bitfld.word 0x0 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x0 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x0 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x0 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x0 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x0 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x0 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x0 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x0 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x0 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x0 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x0 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x0 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x0 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x0 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x2 "CONTROLSS_G3_EPWM31_DCALTRIPSEL,Digital Compare AL Trip Select" bitfld.word 0x2 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x2 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x2 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x2 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x2 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x2 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x2 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x2 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x2 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x2 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x2 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x2 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x2 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x2 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x2 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x4 "CONTROLSS_G3_EPWM31_DCBHTRIPSEL,Digital Compare BH Trip Select" bitfld.word 0x4 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCBH mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x4 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCBH mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x4 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCBH mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x4 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCBH mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x4 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCBH mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x4 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCBH mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x4 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCBH mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x4 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCBH mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x4 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCBH mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x4 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCBH mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x4 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCBH mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x4 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCBH mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x4 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCBH mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x4 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCBH mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x4 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCBH mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x6 "CONTROLSS_G3_EPWM31_DCBLTRIPSEL,Digital Compare BL Trip Select" bitfld.word 0x6 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to DCAL mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0x6 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to DCAL mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0x6 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to DCAL mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0x6 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to DCAL mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0x6 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to DCAL mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0x6 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to DCAL mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0x6 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to DCAL mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0x6 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to DCAL mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0x6 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to DCAL mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0x6 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to DCAL mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0x6 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to DCAL mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0x6 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to DCAL mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0x6 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to DCAL mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0x6 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to DCAL mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0x6 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to DCAL mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0x8 "CONTROLSS_G3_EPWM31_CAPCTL,Event Capture Control Register" bitfld.word 0x8 8. "FRCLOAD,0: Writing of 0 is ignored. Always reads back a 0. 1: Forces a LOAD to occur on the DCCAP - an equivalent LOAD.active pulse" "0: Writing of 0 is ignored,1: Forces a LOAD to occur on the DCCAP" newline bitfld.word 0x8 4. "PULSECTL,Capture Input Polarity Select Mux: 0: Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1: Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture.." "0: Pulse selection determined by PULSESEL bits..,1: Pulse selection determined by CAPMIXSEL register.." newline bitfld.word 0x8 3. "CAPINPOL,Capture Input Polarity Select Mux: 0: CAPIN.sync not inverted 1: CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured" "0: CAPIN,1: CAPIN" newline bitfld.word 0x8 1.--2. "CAPGATEPOL,Capture Gate Input Polarity Select Mux: 00: Set to 1 - Gate is always ON 01: Set to 0 - Gate is always OFF 10: CAPGATE.sync 11: CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing.." "0: Set to 1,1: Set to 0,?,?" newline bitfld.word 0x8 0. "SRCSEL,Capture Logic Input Select Mux: 0: DCEVTFILT [Sync] - same as Type-4 1: CAPIN.sync" "0: DCEVTFILT [Sync],1: CAPIN" line.word 0xA "CONTROLSS_G3_EPWM31_CAPGATETRIPSEL,Event Capture Gate Trip input select" bitfld.word 0xA 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xA 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xA 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xA 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xA 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xA 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xA 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xA 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xA 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xA 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xA 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xA 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xA 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xA 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xA 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPGATE mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xC "CONTROLSS_G3_EPWM31_CAPINTRIPSEL,Event Capture Trip input select" bitfld.word 0xC 14. "TRIPINPUT15,TRIP Input 15 0: Trip Input 15 not selected as combinational ORed input 1: Trip Input 15 selected as combinational ORed input to CAPIN mux" "0: Trip Input 15 not selected as combinational ORed..,1: Trip Input 15 selected as combinational ORed.." newline bitfld.word 0xC 13. "TRIPINPUT14,TRIP Input 14 0: Trip Input 14 not selected as combinational ORed input 1: Trip Input 14 selected as combinational ORed input to CAPIN mux" "0: Trip Input 14 not selected as combinational ORed..,1: Trip Input 14 selected as combinational ORed.." newline bitfld.word 0xC 12. "TRIPINPUT13,TRIP Input 13 0: Trip Input 13 not selected as combinational ORed input 1: Trip Input 13 selected as combinational ORed input to CAPIN mux" "0: Trip Input 13 not selected as combinational ORed..,1: Trip Input 13 selected as combinational ORed.." newline bitfld.word 0xC 11. "TRIPINPUT12,TRIP Input 12 0: Trip Input 12 not selected as combinational ORed input 1: Trip Input 12 selected as combinational ORed input to CAPIN mux" "0: Trip Input 12 not selected as combinational ORed..,1: Trip Input 12 selected as combinational ORed.." newline bitfld.word 0xC 10. "TRIPINPUT11,TRIP Input 11 0: Trip Input 11 not selected as combinational ORed input 1: Trip Input 11 selected as combinational ORed input to CAPIN mux" "0: Trip Input 11 not selected as combinational ORed..,1: Trip Input 11 selected as combinational ORed.." newline bitfld.word 0xC 9. "TRIPINPUT10,TRIP Input 10 0: Trip Input 10 not selected as combinational ORed input 1: Trip Input 10 selected as combinational ORed input to CAPIN mux" "0: Trip Input 10 not selected as combinational ORed..,1: Trip Input 10 selected as combinational ORed.." newline bitfld.word 0xC 8. "TRIPINPUT9,TRIP Input 9 0: Trip Input 9 not selected as combinational ORed input 1: Trip Input 9 selected as combinational ORed input to CAPIN mux" "0: Trip Input 9 not selected as combinational ORed..,1: Trip Input 9 selected as combinational ORed.." newline bitfld.word 0xC 7. "TRIPINPUT8,TRIP Input 8 0: Trip Input 8 not selected as combinational ORed input 1: Trip Input 8 selected as combinational ORed input to CAPIN mux" "0: Trip Input 8 not selected as combinational ORed..,1: Trip Input 8 selected as combinational ORed.." newline bitfld.word 0xC 6. "TRIPINPUT7,TRIP Input 7 0: Trip Input 7 not selected as combinational ORed input 1: Trip Input 7 selected as combinational ORed input to CAPIN mux" "0: Trip Input 7 not selected as combinational ORed..,1: Trip Input 7 selected as combinational ORed.." newline bitfld.word 0xC 5. "TRIPINPUT6,TRIP Input 6 0: Trip Input 6 not selected as combinational ORed input 1: Trip Input 6 selected as combinational ORed input to CAPIN mux" "0: Trip Input 6 not selected as combinational ORed..,1: Trip Input 6 selected as combinational ORed.." newline bitfld.word 0xC 4. "TRIPINPUT5,TRIP Input 5 0: Trip Input 5 not selected as combinational ORed input 1: Trip Input 5 selected as combinational ORed input to CAPIN mux" "0: Trip Input 5 not selected as combinational ORed..,1: Trip Input 5 selected as combinational ORed.." newline bitfld.word 0xC 3. "TRIPINPUT4,TRIP Input 4 0: Trip Input 4 not selected as combinational ORed input 1: Trip Input 4 selected as combinational ORed input to CAPIN mux" "0: Trip Input 4 not selected as combinational ORed..,1: Trip Input 4 selected as combinational ORed.." newline bitfld.word 0xC 2. "TRIPINPUT3,TRIP Input 3 0: Trip Input 3 not selected as combinational ORed input 1: Trip Input 3 selected as combinational ORed input to CAPIN mux" "0: Trip Input 3 not selected as combinational ORed..,1: Trip Input 3 selected as combinational ORed.." newline bitfld.word 0xC 1. "TRIPINPUT2,TRIP Input 2 0: Trip Input 2 not selected as combinational ORed input 1: Trip Input 2 selected as combinational ORed input to CAPIN mux" "0: Trip Input 2 not selected as combinational ORed..,1: Trip Input 2 selected as combinational ORed.." newline bitfld.word 0xC 0. "TRIPINPUT1,TRIP Input 1 0: Trip Input 1 not selected as combinational ORed input 1: Trip Input 1 selected as combinational ORed input to CAPIN mux" "0: Trip Input 1 not selected as combinational ORed..,1: Trip Input 1 selected as combinational ORed.." line.word 0xE "CONTROLSS_G3_EPWM31_CAPTRIPSEL,Event Capture Signal Select" hexmask.word.byte 0xE 4.--7. 1. "CAPGATECOMPSEL,Digital Compare A Low Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." newline hexmask.word.byte 0xE 0.--3. 1. "CAPINCOMPSEL,Digital Compare A High Input Select Bits 0000: TRIPIN1 0001: TRIPIN2 0010: TRIPIN3 0011: TRIPIN4 ... 1011: TRIPIN12 1100: Reserved 1101: TRIPIN14 1110: TRIPIN15 1111: Trip combination input [all trip inputs selected by.." group.word 0x1EC++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_SPARE1,Spare1 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE1_BITS,Not used in design currently" group.word 0x1F0++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_SPARE2,Spare2 register" hexmask.word.byte 0x0 0.--7. 1. "SPARE2_BITS,Not used in design currently" group.long 0x1F4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM31_EPWMLOCK,EPWM Lock Register" hexmask.long.word 0x0 16.--31. 1. "KEY,Write to this register succeeds only if this field is written with a value of 0xa5a5 Note: [1] Due to this KEY only 32-bit writes will succeed [provided the KEY matches]. 16-bit writes to the upper or lower half of this register will be ignored" newline bitfld.long 0x0 4. "DCLOCK,0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW. 1: Digital Compare registers from 0xC0 and 0xD9 offsets are locked and not writable." "0: Digital Compare registers from 0xC0 to 0xD9..,1: Digital Compare registers from 0xC0 and 0xD9.." newline bitfld.long 0x0 3. "TZCLRLOCK,0:Digital Compare registers from 0x97 to 0x9B offsets are protected by EALLOW. 1: Digital Compare registers from 0x97 and 0x9B offsets are locked and not writable." "0: Digital Compare registers from 0x97 to 0x9B..,1: Digital Compare registers from 0x97 and 0x9B.." newline bitfld.long 0x0 2. "TZCFGLOCK,0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW. 1: TripZone registers from 0x80 and 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable." "0: TripZone registers from 0x80 to 0x8D and..,1: TripZone registers from 0x80 and 0x8D and.." newline bitfld.long 0x0 1. "GLLOCK,0:TripZone registers from 0x34 to 0x35 offsets are protected by EALLOW. 1: TripZone registers from 0x34 to 0x35 offsets are locked and not writable" "0: TripZone registers from 0x34 to 0x35 offsets are..,1: TripZone registers from 0x34 to 0x35 offsets are.." newline bitfld.long 0x0 0. "HRLOCK,0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW 1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable." "0: HRPWM registers from 0x20 to 0x2D offsets are..,1: HRPWM registers from 0x20 and 0x2D offsets are.." rgroup.word 0x1FA++0x3 line.word 0x0 "CONTROLSS_G3_EPWM31_HWVDELVAL,Hardware Valley Mode Delay Register" hexmask.word 0x0 0.--15. 1. "HWVDELVAL,Hardware Valley Delay Value Register This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time.." line.word 0x2 "CONTROLSS_G3_EPWM31_VCNTVAL,Hardware Valley Counter Register" hexmask.word 0x2 0.--15. 1. "VCNTVAL,Valley Time Base Counter Register This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register." group.long 0x400++0x3 line.long 0x0 "CONTROLSS_G3_EPWM31_XCMPCTL1,XCMP Mode Control Register" hexmask.long.byte 0x0 8.--11. 1. "XCMPB_ALLOC,XCMPn register allocation for CMPB: - 0 --> Reserved - 1 --> Reserved - 2 --> Reserved - 3 --> Reserved - 4 --> Reserved - 5 --> XCMP5 - 6 --> XCMP5 XCMP6 - 7 --> XCMP5 XCMP6 XCMP7 - 8 --> XCMP5 XCMP6 XCMP7 XCMP8 This register.." newline hexmask.long.byte 0x0 4.--7. 1. "XCMPA_ALLOC,XCMPn register allocation for CMPA: - 0 --> No XCMP - 1 --> XCMP1 - 2 --> XCMP1 XCMP2 - 3 --> XCMP1 XCMP2 XCMP3 - 4 --> XCMP1 XCMP2 XCMP3 XCMP4 - 5 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 - 6 --> XCMP1 XCMP2 XCMP3 XCMP4 XCMP5 .." newline bitfld.long 0x0 1. "XCMPSPLIT,XCMP Register Allocation Options: 0 : XCMP1-8 --> CMPA 1 : XCMP1-4 -->CMPA XCMP5-8 CMPB This register settings will take effect only when XCMPEN==1" "0: XCMP1-8 --> CMPA,1: XCMP1-4 -->CMPA" newline bitfld.long 0x0 0. "XCMPEN,XCMP Compare Register Operation Enable: 0 XCMP register operation Disabled [operation compatible to Type-4] 1 XCMP register operation Enabled [New CMPx registers are effective - section 1.3 details the operation]" "0,1" group.long 0x410++0x3 line.long 0x0 "CONTROLSS_G3_EPWM31_XLOADCTL,XCMP Mode Load Control Register" rbitfld.long 0x0 28.--30. "RPTBUF3CNT,Repeat Count Status Shadow Buffer 3: These bits indicate how many times shadow buffer 3 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline bitfld.long 0x0 24.--26. "RPTBUF3PRD,Repeat Count Shadow Buffer 3 : These bits indicate how many times shadow buffer 3 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,?,3: These bits indicate how many times shadow buffer..,?,?,?,?" newline rbitfld.long 0x0 20.--22. "RPTBUF2CNT,Repeat Count Status Shadow Buffer 2: These bits indicate how many times shadow buffer 2 has been be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Shadow buffer reset value with STARTLD and copied to Active register 0 0 1.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline bitfld.long 0x0 16.--18. "RPTBUF2PRD,Repeat Count Shadow Buffer 2 : These bits indicate how many times shadow buffer 2 will be applied before moving to the next buffer I e shadow buffer 1. 0 0 0 Apply shadow buffer once and move to the next shadow buffer on the following load.." "?,?,2: These bits indicate how many times shadow buffer..,?,?,?,?,?" newline rbitfld.long 0x0 10.--11. "SHDWBUFPTR_LOADMULTIPLE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SHDWBUFPTR_LOADONCE,Register Load event count: These bits indicate the current shadow buffer in use. 0 0 Reset value 0 1 1 Shadow buffer 1 in use 1 0 2 Shadow buffer 2 in use 1 1 3 Shadow buffer 3 in use More details in section 1.3.3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SHDWLEVEL,Shadow Register Level Allocation Options: These bits are effective only when XCMPEN is enabled. 0 0 : XXXX Shadow level is set at zero. XXXX Active register is available 0 1 : XXXX Shadow level is set at 1. XXXX_SHDW1 and Active registers are.." "0: XXXX Shadow level is set at 1,1: XXXX Shadow level is set at 1,?,?" newline bitfld.long 0x0 2. "LOADMODE,Load mode selection for Shadow registers: These bits are effective only when XCMPEN is enabled. 0 : [LOADONCE] Load occurs at every load strobe [CNT_Zero or FRCLD] from SHDWn Active registers. And STARTLD is cleared after 1 load strobe." "0: [LOADONCE] Load occurs at every load strobe..,1: [LOADMULTIPLE] Load occurs at every load strobe.." group.long 0x418++0x7 line.long 0x0 "CONTROLSS_G3_EPWM31_XLOAD,XCMP Mode Load Enable Register" bitfld.long 0x0 1. "FRCLD,Force reload event in one shot mode : Writing a 1 to this bit turn force one load event at the input of the event pre-scale counter as shown in the diagram below. This bit is intended to be used for testing and/or software force loading of the.." "0,1" newline bitfld.long 0x0 0. "STARTLD,Enable reload event : Writing a 1 to this bit turn the one shot latch condition ON. Upon occurrence of a chosen load strobe one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow load strobe.." "0,1" line.long 0x4 "CONTROLSS_G3_EPWM31_EPWMXLINKXLOAD,Link register across PWM modules" hexmask.long.byte 0x4 0.--4. 1. "XLOADLINK,XLOAD Link Bits: Writes to the XLOAD registers in the ePWM module selected by the following bit selections results in a simultaneous write to the current ePWM module's XLOAD registers 00000: ePWM1 00001: ePWM2 00010: ePWM3 00011: ePWM4.." rgroup.long 0x420++0x3 line.long 0x0 "CONTROLSS_G3_EPWM31_XREGSHDW1STS,Shadow Buffer 1 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW1FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x428++0x3 line.long 0x0 "CONTROLSS_G3_EPWM31_XREGSHDW2STS,Shadow Buffer 2 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW2FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" rgroup.long 0x430++0x3 line.long 0x0 "CONTROLSS_G3_EPWM31_XREGSHDW3STS,Shadow Buffer 3 Update Status Register" bitfld.long 0x0 14. "XMIN_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 13. "XMAX_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 12. "XAQCTLB_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 11. "XAQCTLA_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 10. "CMPD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 9. "CMPC_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 8. "XTBPRD_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 7. "XCMP8_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 6. "XCMP7_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 5. "XCMP6_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 4. "XCMP5_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 3. "XCMP4_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 2. "XCMP3_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 1. "XCMP2_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" newline bitfld.long 0x0 0. "XCMP1_SHDW3FULL,0 Shadow Register is not full yet 1 Indicates the Shadow Register is full a CPU write will over-write current Shadow value" "0,1" group.long 0x600++0x23 line.long 0x0 "CONTROLSS_G3_EPWM31_XCMP1_ACTIVE,Additional Compare 1 Active Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_ACTIVE,XCMP1_ACTIVE Register The value in the XCMP1_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_ACTIVE,XCMP1HR_ACTIVE Register The value in the XCMP1HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM31_XCMP2_ACTIVE,Additional Compare 2 Active Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_ACTIVE,XCMP2_ACTIVE Register The value in the XCMP2_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_ACTIVE,XCMP2HR_ACTIVE Register The value in the XCMP2HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM31_XCMP3_ACTIVE,Additional Compare 3 Active Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_ACTIVE,XCMP3_ACTIVE Register The value in the XCMP3_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_ACTIVE,XCMP3HR_ACTIVE Register The value in the XCMP3HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM31_XCMP4_ACTIVE,Additional Compare 4 Active Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_ACTIVE,XCMP4_ACTIVE Register The value in the XCMP4_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_ACTIVE,XCMP4HR_ACTIVE Register The value in the XCMP4HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM31_XCMP5_ACTIVE,Additional Compare 5 Active Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_ACTIVE,XCMP5_ACTIVE Register The value in the XCMP5_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_ACTIVE,XCMP5HR_ACTIVE Register The value in the XCMP5HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM31_XCMP6_ACTIVE,Additional Compare 6 Active Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_ACTIVE,XCMP6_ACTIVE Register The value in the XCMP6_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_ACTIVE,XCMP6HR_ACTIVE Register The value in the XCMP6HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM31_XCMP7_ACTIVE,Additional Compare 7 Active Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_ACTIVE,XCMP7_ACTIVE Register The value in the XCMP7_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_ACTIVE,XCMP7HR_ACTIVE Register The value in the XCMP7HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM31_XCMP8_ACTIVE,Additional Compare 8 Active Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_ACTIVE,XCMP8_ACTIVE Register The value in the XCMP8_ACTIVE register is loaded into CMPA/B [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_ACTIVE,XCMP8HR_ACTIVE Register The value in the XCMP8HR_ACTIVE register is loaded into CMPA/BHR [shadow/active] registers when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM31_XTBPRD_ACTIVE,Additional Time Base Period Active Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_ACTIVE,The value in the XTBPRD_ACTIVE register is loaded into TBPRD [shadow/active] registers when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_ACTIVE,The value in the XTBPRDHR_ACTIVE register is loaded into TBPRDHR [shadow/active] registers when shadow to active load occurs." group.word 0x630++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_XAQCTLA_ACTIVE,AQCTLA Active Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.long 0x644++0x3 line.long 0x0 "CONTROLSS_G3_EPWM31_XMINMAX_ACTIVE,XMINMAX Active Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_ACTIVE,The value in the XMIN_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_ACTIVE,The value in the XMAX_ACTIVE register is used for comparision against the threshold of the capture counter at any given time." group.long 0x680++0x23 line.long 0x0 "CONTROLSS_G3_EPWM31_XCMP1_SHDW1,Additional Compare 1 Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW1,XCMP1_SHDW1 Register The value in the XCMP1_SHDW1 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW1,XCMP1HR_SHDW1 Register The value in the XCMP1HR_SHDW1 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM31_XCMP2_SHDW1,Additional Compare 2 Shadow 1 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW1,XCMP2_SHDW1 Register The value in the XCMP2_SHDW1 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW1,XCMP2HR_SHDW1 Register The value in the XCMP2HR_SHDW1 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM31_XCMP3_SHDW1,Additional Compare 3 Shadow 1 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW1,XCMP3_SHDW1 Register The value in the XCMP3_SHDW1 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW1,XCMP3HR_SHDW1 Register The value in the XCMP3HR_SHDW1 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM31_XCMP4_SHDW1,Additional Compare 4 Shadow 1 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW1,XCMP4_SHDW1 Register The value in the XCMP4_SHDW1 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW1,XCMP4HR_SHDW1 Register The value in the XCMP4HR_SHDW1 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM31_XCMP5_SHDW1,Additional Compare 5 Shadow 1 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW1,XCMP5_SHDW1 Register The value in the XCMP5_SHDW1 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW1,XCMP5HR_SHDW1 Register The value in the XCMP5HR_SHDW1 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM31_XCMP6_SHDW1,Additional Compare 6 Shadow 1 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW1,XCMP6_SHDW1 Register The value in the XCMP6_SHDW1 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW1,XCMP6HR_SHDW1 Register The value in the XCMP6HR_SHDW1 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM31_XCMP7_SHDW1,Additional Compare 7 Shadow 1 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW1,XCMP7_SHDW1 Register The value in the XCMP7_SHDW1 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW1,XCMP7HR_SHDW1 Register The value in the XCMP7HR_SHDW1 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM31_XCMP8_SHDW1,Additional Compare 8 Shadow 1 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW1,XCMP8_SHDW1 Register The value in the XCMP8_SHDW1 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW1,XCMP8HR_SHDW1 Register The value in the XCMP8HR_SHDW1 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM31_XTBPRD_SHDW1,Additional Time Base Period Shadow 1 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW1,The value in the XTBPRD_SHDW1 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW1,The value in the XTBPRDHR_SHDW1 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x6B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM31_XAQCTLA_SHDW1,XAQCTLA Shadow 1 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM31_XAQCTLB_SHDW1,XAQCTLB Shadow 1 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x6BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_CMPC_SHDW1,CMPC Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW1,The value in the CMPC_SHDW1 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x6BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_CMPD_SHDW1,CMPD Shadow 1 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW1,The value in the CMPD_SHDW1 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x6C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM31_XMINMAX_SHDW1,XMINMAX Shadow 1 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW1,The value in the XMIN_SHDW1 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW1,The value in the XMAX_SHDW1 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x700++0x23 line.long 0x0 "CONTROLSS_G3_EPWM31_XCMP1_SHDW2,Additional Compare 1 Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW2,XCMP1_SHDW2 Register The value in the XCMP1_SHDW2 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW2,XCMP1HR_SHDW2 Register The value in the XCMP1HR_SHDW2 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM31_XCMP2_SHDW2,Additional Compare 2 Shadow 2 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW2,XCMP2_SHDW2 Register The value in the XCMP2_SHDW2 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW2,XCMP2HR_SHDW2 Register The value in the XCMP2HR_SHDW2 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM31_XCMP3_SHDW2,Additional Compare 3 Shadow 2 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW2,XCMP3_SHDW2 Register The value in the XCMP3_SHDW2 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW2,XCMP3HR_SHDW2 Register The value in the XCMP3HR_SHDW2 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM31_XCMP4_SHDW2,Additional Compare 4 Shadow 2 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW2,XCMP4_SHDW2 Register The value in the XCMP4_SHDW2 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW2,XCMP4HR_SHDW2 Register The value in the XCMP4HR_SHDW2 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM31_XCMP5_SHDW2,Additional Compare 5 Shadow 2 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW2,XCMP5_SHDW2 Register The value in the XCMP5_SHDW2 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW2,XCMP5HR_SHDW2 Register The value in the XCMP5HR_SHDW2 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM31_XCMP6_SHDW2,Additional Compare 6 Shadow 2 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW2,XCMP6_SHDW2 Register The value in the XCMP6_SHDW2 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW2,XCMP6HR_SHDW2 Register The value in the XCMP6HR_SHDW2 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM31_XCMP7_SHDW2,Additional Compare 7 Shadow 2 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW2,XCMP7_SHDW2 Register The value in the XCMP7_SHDW2 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW2,XCMP7HR_SHDW2 Register The value in the XCMP7HR_SHDW2 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM31_XCMP8_SHDW2,Additional Compare 8 Shadow 2 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW2,XCMP8_SHDW2 Register The value in the XCMP8_SHDW2 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW2,XCMP8HR_SHDW2 Register The value in the XCMP8HR_SHDW2 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM31_XTBPRD_SHDW2,Additional Time Base Period Shadow 2 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW2,The value in the XTBPRD_SHDW2 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW2,The value in the XTBPRDHR_SHDW2 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x730++0x3 line.word 0x0 "CONTROLSS_G3_EPWM31_XAQCTLA_SHDW2,XAQCTLA Shadow 2 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM31_XAQCTLB_SHDW2,XAQCTLB Shadow 2 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x73A++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_CMPC_SHDW2,CMPC Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW2,The value in the CMPC_SHDW2 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x73E++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_CMPD_SHDW2,CMPD Shadow 2 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW2,The value in the CMPD_SHDW2 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x744++0x3 line.long 0x0 "CONTROLSS_G3_EPWM31_XMINMAX_SHDW2,XMINMAX Shadow 2 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW2,The value in the XMIN_SHDW2 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW2,The value in the XMAX_SHDW2 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x780++0x23 line.long 0x0 "CONTROLSS_G3_EPWM31_XCMP1_SHDW3,Additional Compare 1 Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XCMP1_SHDW3,XCMP1_SHDW3 Register The value in the XCMP1_SHDW3 register is loaded into XCMP1_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XCMP1HR_SHDW3,XCMP1HR_SHDW3 Register The value in the XCMP1HR_SHDW3 register is loaded into XCMP1HR_ACTIVE register when shadow to active load occurs." line.long 0x4 "CONTROLSS_G3_EPWM31_XCMP2_SHDW3,Additional Compare 2 Shadow 3 Register" hexmask.long.word 0x4 16.--31. 1. "XCMP2_SHDW3,XCMP2_SHDW3 Register The value in the XCMP2_SHDW3 register is loaded into XCMP2_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x4 0.--15. 1. "XCMP2HR_SHDW3,XCMP2HR_SHDW3 Register The value in the XCMP2HR_SHDW3 register is loaded into XCMP2HR_ACTIVE register when shadow to active load occurs." line.long 0x8 "CONTROLSS_G3_EPWM31_XCMP3_SHDW3,Additional Compare 3 Shadow 3 Register" hexmask.long.word 0x8 16.--31. 1. "XCMP3_SHDW3,XCMP3_SHDW3 Register The value in the XCMP3_SHDW3 register is loaded into XCMP3_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x8 0.--15. 1. "XCMP3HR_SHDW3,XCMP3HR_SHDW3 Register The value in the XCMP3HR_SHDW3 register is loaded into XCMP3HR_ACTIVE register when shadow to active load occurs." line.long 0xC "CONTROLSS_G3_EPWM31_XCMP4_SHDW3,Additional Compare 4 Shadow 3 Register" hexmask.long.word 0xC 16.--31. 1. "XCMP4_SHDW3,XCMP4_SHDW3 Register The value in the XCMP4_SHDW3 register is loaded into XCMP4_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0xC 0.--15. 1. "XCMP4HR_SHDW3,XCMP4HR_SHDW3 Register The value in the XCMP4HR_SHDW3 register is loaded into XCMP4HR_ACTIVE register when shadow to active load occurs." line.long 0x10 "CONTROLSS_G3_EPWM31_XCMP5_SHDW3,Additional Compare 5 Shadow 3 Register" hexmask.long.word 0x10 16.--31. 1. "XCMP5_SHDW3,XCMP5_SHDW3 Register The value in the XCMP5_SHDW3 register is loaded into XCMP5_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x10 0.--15. 1. "XCMP5HR_SHDW3,XCMP5HR_SHDW3 Register The value in the XCMP5HR_SHDW3 register is loaded into XCMP5HR_ACTIVE register when shadow to active load occurs." line.long 0x14 "CONTROLSS_G3_EPWM31_XCMP6_SHDW3,Additional Compare 6 Shadow 3 Register" hexmask.long.word 0x14 16.--31. 1. "XCMP6_SHDW3,XCMP6_SHDW3 Register The value in the XCMP6_SHDW3 register is loaded into XCMP6_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x14 0.--15. 1. "XCMP6HR_SHDW3,XCMP6HR_SHDW3 Register The value in the XCMP6HR_SHDW3 register is loaded into XCMP6HR_ACTIVE register when shadow to active load occurs." line.long 0x18 "CONTROLSS_G3_EPWM31_XCMP7_SHDW3,Additional Compare 7 Shadow 3 Register" hexmask.long.word 0x18 16.--31. 1. "XCMP7_SHDW3,XCMP7_SHDW3 Register The value in the XCMP7_SHDW3 register is loaded into XCMP7_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x18 0.--15. 1. "XCMP7HR_SHDW3,XCMP7HR_SHDW3 Register The value in the XCMP7HR_SHDW3 register is loaded into XCMP7HR_ACTIVE register when shadow to active load occurs." line.long 0x1C "CONTROLSS_G3_EPWM31_XCMP8_SHDW3,Additional Compare 8 Shadow 3 Register" hexmask.long.word 0x1C 16.--31. 1. "XCMP8_SHDW3,XCMP8_SHDW3 Register The value in the XCMP8_SHDW3 register is loaded into XCMP8_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x1C 0.--15. 1. "XCMP8HR_SHDW3,XCMP8HR_SHDW3 Register The value in the XCMP8HR_SHDW3 register is loaded into XCMP8HR_ACTIVE register when shadow to active load occurs." line.long 0x20 "CONTROLSS_G3_EPWM31_XTBPRD_SHDW3,Additional Time Base Period Shadow 3 Register" hexmask.long.word 0x20 16.--31. 1. "XTBPRD_SHDW3,The value in the XTBPRD_SHDW3 register is loaded into XTBPRD_ ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x20 0.--15. 1. "XTBPRDHR_SHDW3,The value in the XTBPRDHR_SHDW3 register is loaded into XTBPRDHR_ACTIVE register when shadow to active load occurs." group.word 0x7B0++0x3 line.word 0x0 "CONTROLSS_G3_EPWM31_XAQCTLA_SHDW3,XAQCTLA Shadow 3 Register" bitfld.word 0x0 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 6.--7. "XCMP4,Action when Counter = CMP4 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 4.--5. "XCMP3,Action when Counter = CMP3 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 2.--3. "XCMP2,Action when Counter = CMP2 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x0 0.--1. "XCMP1,Action when Counter = CMP1 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" line.word 0x2 "CONTROLSS_G3_EPWM31_XAQCTLB_SHDW3,XAQCTLB Shadow 3 Register" bitfld.word 0x2 14.--15. "XCMP8,Action when Counter = CMP8 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 12.--13. "XCMP7,Action when Counter = CMP7 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 10.--11. "XCMP6,Action when Counter = CMP6 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" newline bitfld.word 0x2 8.--9. "XCMP5,Action when Counter = CMP5 0 0 Do nothing [action disabled] 0 1 Clear [low] 1 0 Set [high] 1 1 Toggle [Low -> High High -> Low]" "0,1,2,3" group.word 0x7BA++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_CMPC_SHDW3,CMPC Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPC_SHDW3,The value in the CMPC_SHDW3 register is loaded into CMPC_ACTIVE register when shadow to active load occurs." group.word 0x7BE++0x1 line.word 0x0 "CONTROLSS_G3_EPWM31_CMPD_SHDW3,CMPD Shadow 3 Register" hexmask.word 0x0 0.--15. 1. "CMPD_SHDW3,The value in the CMPD_SHDW3 register is loaded into CMPD_ACTIVE register when shadow to active load occurs." group.long 0x7C4++0x3 line.long 0x0 "CONTROLSS_G3_EPWM31_XMINMAX_SHDW3,XMINMAX Shadow 3 Register" hexmask.long.word 0x0 16.--31. 1. "XMIN_SHDW3,The value in the XMIN_SHDW3 register is loaded into XMIN_ACTIVE register when shadow to active load occurs." newline hexmask.long.word 0x0 0.--15. 1. "XMAX_SHDW3,The value in the XMAX_SHDW3 register is loaded into XMAX_ACTIVE register when shadow to active load occurs." group.long 0x800++0xB line.long 0x0 "CONTROLSS_G3_EPWM31_DECTL,DE control register" hexmask.long.byte 0x0 8.--15. 1. "REENTRYDLY,Determines the blocking window after DEACTIVE flag is cleared in which setting of DEACTIVE flag is prevented from being set. 0 : No blocking 1 : Blocked until 1 PWMSYNCOUT event 2 : Blocked until 2 PWMSYNCOUT events . . 255 : Blocked until 127.." newline bitfld.long 0x0 1. "MODE,0 : DEACTIVE flag works in cycle by cycle mode. On every PWMSYNCOUT set condition of DEACTIVE flag is evaluated. If the set condition is not present the flag is cleared. 1 : DEACTIVE flag works in one shot mode [hardware set] and software clear." "0: DEACTIVE flag works in cycle by cycle mode,1: DEACTIVE flag works in one shot mode [hardware.." newline bitfld.long 0x0 0. "ENABLE,DE function enable 0 : Diode Emulation mode functionality is disabled. DEACTIVE flag is not set on a TRIPH_OR_TRIPL event. 1 : Diode Emulation mode functionality is enabled. DEACTIVE flag is set on a TRIPH_OR_TRIPL event. Note: ENABLE bit is.." "0: Diode Emulation mode functionality is disabled,1: Diode Emulation mode functionality is enabled" line.long 0x4 "CONTROLSS_G3_EPWM31_DECOMPSEL,Used to configure the comparator whose trip sources will be used." hexmask.long.byte 0x4 16.--21. 1. "TRIPH,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPH 000010 : Input-XBAR[1] is the source of TRIPH . . 100000 : Input-XBAR[31] is the source of TRIPH 100001 : CMPSSA0 is the source of TRIPH 100010 : CMPSSA1 is the source of TRIPH . ." newline hexmask.long.byte 0x4 0.--5. 1. "TRIPL,000000 : Reserved 000001 : Input-XBAR[0] is the source of TRIPL 000010 : Input-XBAR[1] is the source of TRIPL . . 100000 : Input-XBAR[31] is the source of TRIPL 100001 : CMPSSA0 is the source of TRIPL 100010 : CMPSSA1 is the source of TRIPL . ." line.long 0x8 "CONTROLSS_G3_EPWM31_DEACTCTL,Used to configure the PWM controls when in DE mode." bitfld.long 0x8 16. "TRIPENABLE,0 : PWMTRIP does not bypass the diode emulation logic. 1 : PWMTRIP bypasses the diode emulation PWM generation logic [not complete bypass of module]" "0: PWMTRIP does not bypass the diode emulation logic,1: PWMTRIP bypasses the diode emulation PWM.." newline bitfld.long 0x8 6. "TRIPSELB,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 4.--5. "PWMB,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELB 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELB 10 : A constant 0 drives PWMB when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" newline bitfld.long 0x8 2. "TRIPSELA,0 : TRIPH 1 : TRIPL" "0: TRIPH,1: TRIPL" newline bitfld.long 0x8 0.--1. "PWMA,00 : synchronized version of TRIPH or TRIPL signal as selected by the TRIPSELA 01 : synchronized and inverted version of TRIPH or TRIPL signal as selected by the TRIPSELA 10 : A constant 0 drives PWMA when DEACTIVE flag is set. 11 : A constant 1.." "0: synchronized version of TRIPH or TRIPL signal as..,1: synchronized and inverted version of TRIPH or..,?,?" rgroup.long 0x80C++0x3 line.long 0x0 "CONTROLSS_G3_EPWM31_DESTS,DE Status register" bitfld.long 0x0 0. "DEACTIVE,0 : Diode emulation mode is not active 1 : Diode emulation mode is active" "0: Diode emulation mode is not active,1: Diode emulation mode is active" group.long 0x810++0x7 line.long 0x0 "CONTROLSS_G3_EPWM31_DEFRC,DE Status force register" bitfld.long 0x0 0. "DEACTIVE,0 : No effect. 1 : Forces DEACTIVE flag to 1." "0: No effect,1: Forces DEACTIVE flag to 1" line.long 0x4 "CONTROLSS_G3_EPWM31_DECLR,DE Status clear register" bitfld.long 0x4 0. "DEACTIVE,0 : No effect. 1 : Clears DEACTIVE flag." "0: No effect,1: Clears DEACTIVE flag" rgroup.long 0x820++0x3 line.long 0x0 "CONTROLSS_G3_EPWM31_DEMONCNT,DE trip monitor counter" hexmask.long.word 0x0 0.--15. 1. "CNT,An 16-bit counter which monitors the frequency of diode mode trip events. When TripHorTripL is active: Increment CNT [increment INCSTEP on every EPWMxSYNC] When TripHorTripL is in-active: Decrement CNT [decrement DECSTEP on every EPWMxSYNC] If[.." group.long 0x824++0xB line.long 0x0 "CONTROLSS_G3_EPWM31_DEMONCTL,DE monitor mode control" bitfld.long 0x0 0. "ENABLE,Enable bit for DE Mode Monitor counter function. 0: DE Mode Monitor counter function is disabled 1: DE Mode Monitor counter function is enabled" "0: DE Mode Monitor counter function is disabled,1: DE Mode Monitor counter function is enabled" line.long 0x4 "CONTROLSS_G3_EPWM31_DEMONSTEP,DE monitor counter step" hexmask.long.byte 0x4 16.--23. 1. "DECSTEP,Defines the decrement step of DEMONCNT.CNT counter." newline hexmask.long.byte 0x4 0.--7. 1. "INCSTEP,Defines the increment step of DEMONCNT.CNT counter." line.long 0x8 "CONTROLSS_G3_EPWM31_DEMONTHRES,DE monitor counter threshold" hexmask.long.word 0x8 0.--15. 1. "THRESHOLD,Defines the threshold of DE monitor counter." group.long 0xC00++0x7 line.long 0x0 "CONTROLSS_G3_EPWM31_MINDBCFG,Minimum dead band configuration register." bitfld.long 0x0 24. "POLSELB,Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB." "0: Select BLOCKB is inverted and ANDed with PWMB,1: Select BLOCKB is Ored with PWMB" newline hexmask.long.byte 0x0 20.--23. 1. "SELB,PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 19. "SELBLOCKB,0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB." "0: Select BLOCKB as the blocking signal on PWMB,1: Select BLOCKA as the blocking signal on PWMB" newline bitfld.long 0x0 18. "INVERTB,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 16. "ENABLEB,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" newline bitfld.long 0x0 8. "POLSELA,Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA." "0: Select BLOCKA is inverted and ANDed with PWMA,1: Select BLOCKA is Ored with PWMA" newline hexmask.long.byte 0x0 4.--7. 1. "SELA,PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWM output XBAR 0x2 : Output 2 from PWM output XBAR . . 0xf : Output 15 from PWM output XBAR" newline bitfld.long 0x0 3. "SELBLOCKA,0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB." "0: Select BLOCKA as the blocking signal on PWMA,1: Select BLOCKB as the blocking signal on PWMB" newline bitfld.long 0x0 2. "INVERTA,0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA." "0: No inversion on the selected reference signal..,1: Invert the selected reference signal which is.." newline bitfld.long 0x0 0. "ENABLEA,0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled" "0: Minimum dead band logic is disabled,1: Minimum dead band logic is enabled" line.long 0x4 "CONTROLSS_G3_EPWM31_MINDBDLY,Minimum dead band delay register" hexmask.long.word 0x4 16.--31. 1. "DELAYB,Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." newline hexmask.long.word 0x4 0.--15. 1. "DELAYA,Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0 user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied." group.long 0xC20++0x7 line.long 0x0 "CONTROLSS_G3_EPWM31_LUTCTLA,LUT control register on PWMA" bitfld.long 0x0 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x0 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x0 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTA" newline bitfld.long 0x0 0. "BYPASS,1 : Bypass LUT logic on PWMA 0 : PWMA driven by LUTA" "0: PWMA driven by LUTA,1: Bypass LUT logic on PWMA" line.long 0x4 "CONTROLSS_G3_EPWM31_LUTCTLB,LUT control register on PWMB" bitfld.long 0x4 23. "LUTDEC7,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 22. "LUTDEC6,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 21. "LUTDEC5,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 20. "LUTDEC4,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 19. "LUTDEC3,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 18. "LUTDEC2,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 17. "LUTDEC1,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline bitfld.long 0x4 16. "LUTDEC0,0 : Force 0 1 : Force 1" "0: Force 0,1: Force 1" newline hexmask.long.byte 0x4 4.--7. 1. "SELXBAR,Selects one of the 16 outputs of ICSSXBAR to feed into IN3 of LUTB" newline bitfld.long 0x4 0. "BYPASS,1 : Bypass LUT logic on PWMB 0 : PWMB driven by LUTB" "0: PWMB driven by LUTB,1: Bypass LUT logic on PWMB" tree.end tree.end tree.end tree "EQEP" tree "EQEP0" base ad:0x50270000 group.long 0x0++0xF line.long 0x0 "CONTROLSS_EQEP0_QPOSCNT" hexmask.long 0x0 0.--31. 1. "QPOSCNT,Position Counter This 32-bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point. This.." line.long 0x4 "CONTROLSS_EQEP0_QPOSINIT" hexmask.long 0x4 0.--31. 1. "QPOSINIT,Position Counter Init This register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software. Writes to this register should.." line.long 0x8 "CONTROLSS_EQEP0_QPOSMAX" hexmask.long 0x8 0.--31. 1. "QPOSMAX,Maximum Position Count This register contains the maximum position counter value. Writes to this register should always be full 32-bit writes." line.long 0xC "CONTROLSS_EQEP0_QPOSCMP" hexmask.long 0xC 0.--31. 1. "QPOSCMP,Position Compare The position-compare value in this register is compared with the position counter (QPOSCNT) to generate sync output and/or interrupt on compare match." rgroup.long 0x10++0xB line.long 0x0 "CONTROLSS_EQEP0_QPOSILAT" hexmask.long 0x0 0.--31. 1. "QPOSILAT,Index Position Latch The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits." line.long 0x4 "CONTROLSS_EQEP0_QPOSSLAT" hexmask.long 0x4 0.--31. 1. "QPOSSLAT,Strobe Position Latch The position-counter value is latched into this register on a strobe event as defined by the QEPCTL[SEL] bits." line.long 0x8 "CONTROLSS_EQEP0_QPOSLAT" hexmask.long 0x8 0.--31. 1. "QPOSLAT,Position Latch The position-counter value is latched into this register on a unit time out event." group.long 0x1C++0x7 line.long 0x0 "CONTROLSS_EQEP0_QUTMR" hexmask.long 0x0 0.--31. 1. "QUTMR,QEP Unit Timer This register acts as time base for unit time event generation. When this timer value matches the unit time period value a unit time event is generated." line.long 0x4 "CONTROLSS_EQEP0_QUPRD" hexmask.long 0x4 0.--31. 1. "QUPRD,QEP Unit Period This register contains the period count for the unit timer to generate periodic unit time events. These events latch the eQEP position information at periodic intervals and optionally generate an interrupt. Writes to this register.." group.word 0x24++0xD line.word 0x0 "CONTROLSS_EQEP0_QWDTMR" hexmask.word 0x0 0.--15. 1. "QWDTMR,QEP Watchdog Timer This register acts as time base for the watchdog to detect motor stalls. When this timer value matches with the watchdog's period value a watchdog timeout interrupt is generated. This register is reset upon edge transition in.." line.word 0x2 "CONTROLSS_EQEP0_QWDPRD" hexmask.word 0x2 0.--15. 1. "QWDPRD,QEP Watchdog Period This register contains the time-out count for the eQEP peripheral watch dog timer. When the watchdog timer value matches the watchdog period value a watchdog timeout interrupt is generated." line.word 0x4 "CONTROLSS_EQEP0_QDECCTL" bitfld.word 0x4 14.--15. "QSRC,Position-counter source selection" "0,1,2,3" bitfld.word 0x4 13. "SOEN,Sync output-enable 0 | SYNC_DISABLEDisable position-compare sync output 1 | SYNC_ENABLEEnable position-compare sync output" "0,1" bitfld.word 0x4 12. "SPSEL,Sync output pin selection 0 | INDEX_PINIndex pin is used for sync output 1 | STROBE_PINStrobe pin is used for sync output" "0,1" bitfld.word 0x4 11. "XCR,External Clock Rate 0 | XCR_2XRESOL2x resolution: Count the rising/falling edge 1 | XCR_1XRESOL1x resolution: Count the rising edge only" "0,1" bitfld.word 0x4 10. "SWAP,CLK/DIR Signal Source for Position Counter 0 | SWAP_DISABLEQuadrature-clock inputs are not swapped 1 | SWAP_ENABLEQuadrature-clock inputs are swapped" "0,1" bitfld.word 0x4 9. "IGATE,Index pulse gating option 0 | IGATE_DISABLEDisable gating of Index pulse 1 | IGATE_ENABLEGate the index pin with strobe" "0,1" newline bitfld.word 0x4 8. "QAP,QEPA input polarity 0 | QAP_NOPOLARNo effect 1 | QAP_POLARNegates QEPA input" "0,1" bitfld.word 0x4 7. "QBP,QEPB input polarity 0 | QBP_NOPOLARNo effect 1 | QBP_POLARNegates QEPB input" "0,1" bitfld.word 0x4 6. "QIP,QEPI input polarity 0 | QIP_NOPOLARNo effect 1 | QIP_POLARNegates QEPI input" "0,1" bitfld.word 0x4 5. "QSP,QEPS input polarity 0 | QSP_NOPOLARNo effect 1 | QSP_POLARNegates QEPS input" "0,1" bitfld.word 0x4 0. "QIDIRE,0 - Compatible mode Behavior same as existing devices 1 - Enhancement for Direction change during Index will be enabled" "0,1" line.word 0x6 "CONTROLSS_EQEP0_QEPCTL" bitfld.word 0x6 14.--15. "FREE_SOFT,Emulation mode 0x0 | FREE_SOFT_0QPOSCNT behavior Position counter stops immediately on emulation suspend 0h (R/W) = QWDTMR behavior Watchdog counter stops immediately 0h (R/W) = QUTMR behavior Unit timer stops immediately 0h (R/W) =.." "0,1,2,3" bitfld.word 0x6 12.--13. "PCRM,Postion counter reset 0x0 | PCRM_INDEXPosition counter reset on an index event 0x1 | PCRM_MAXPOSPosition counter reset on the maximum position 0x2 | PCRM_FIRSTINDEXPosition counter reset on the first index event 0x3 |.." "0,1,2,3" bitfld.word 0x6 10.--11. "SEI,Strobe event initialization of position counter 0x0 | SEI_NOTHING0Does nothing (action disabled) 0x1 | SEI_NOTHING1Does nothing (action disabled) 0x2 | SEI_INITQEPSRISINGInitializes the position counter on rising edge of the.." "0,1,2,3" bitfld.word 0x6 8.--9. "IEI,Index event init of position count 0x0 | IEI_NOTHING0Do nothing (action disabled) 0x1 | IEI_NOTHING1Do nothing (action disabled) 0x2 | IEI_INITRISINGInitializes the position counter on the rising edge of the QEPI signal.." "0,1,2,3" bitfld.word 0x6 7. "SWI,Software init position counter 0 | SWI_NOTHINGDo nothing (action disabled) 1 | SWI_INITPOSInitialize position counter (QPOSCNT=QPOSINIT). This bit is not cleared automatically" "0,1" bitfld.word 0x6 6. "SEL,Strobe event latch of position counter 0 | SEL_QEPSRISINGThe position counter is latched on the rising edge of QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling edge can be done by inverting the strobe input using the QSP bit in the.." "0,1" newline bitfld.word 0x6 4.--5. "IEL,Index event latch of position counter (software index marker) 0x0 | IEL_RSVDReserved 0x1 | IEL_POSRISINGLatches position counter on rising edge of the index signal 0x2 | IEL_POSFALLINGLatches position counter on falling edge.." "0,1,2,3" bitfld.word 0x6 3. "QPEN,Quadrature position counter enable/software reset 0 | QPEN_RESETReset the eQEP peripheral internal operating flags/read-only registers. Control/configuration registers are not disturbed by a software reset. When QPEN is disabled some flags.." "0,1" bitfld.word 0x6 2. "QCLM,QEP capture latch mode 0 | QCLM_CPULatch on position counter read by CPU. Capture timer and capture period values are latched into QCTMRLAT and QCPRDLAT registers when CPU reads the QPOSCNT register. 1 | QCLM_TIMEOUTLatch on unit.." "0,1" bitfld.word 0x6 1. "UTE,QEP unit timer enable 0 | UTE_DISABLEDisable eQEP unit timer 1 | UTE_ENABLEEnable unit timer" "0,1" bitfld.word 0x6 0. "WDE,QEP watchdog enable 0 | WDE_DISABLEDisable the eQEP watchdog timer 1 | WDE_ENABLEEnable the eQEP watchdog timer" "0,1" line.word 0x8 "CONTROLSS_EQEP0_QCAPCTL" bitfld.word 0x8 15. "CEN,Enable eQEP capture 0 | CEN_DISABLEeQEP capture unit is disabled 1 | CEN_ENABLEeQEP capture unit is enabled" "0,1" bitfld.word 0x8 4.--6. "CCPS,eQEP capture timer clock prescaler 0x0 | SYSCLKOUT1CAPCLK = SYSCLKOUT/1 0x1 | SYSCLKOUT2CAPCLK = SYSCLKOUT/2 0x2 | SYSCLKOUT4CAPCLK = SYSCLKOUT/4 0x3 | SYSCLKOUT8CAPCLK = SYSCLKOUT/8 0x4 | SYSCLKOUT16CAPCLK.." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x8 0.--3. 1. "UPPS,Unit position event prescaler 0x0 | QCLK1UPEVNT = QCLK/1 0x1 | QCLK2UPEVNT = QCLK/2 0x2 | QCLK4UPEVNT = QCLK/4 0x3 | QCLK8UPEVNT = QCLK/8 0x4 | QCLK16UPEVNT = QCLK/16 0x5 | QCLK32UPEVNT = QCLK/32.." line.word 0xA "CONTROLSS_EQEP0_QPOSCTL" bitfld.word 0xA 15. "PCSHDW,Position compare of shadow enable 0 | PCSHDW_DISABLEShadow disabled load Immediate 1 | PCSHDW_ENABLEShadow enabled" "0,1" bitfld.word 0xA 14. "PCLOAD,Position compare of shadow load 0 | PCLOAD_0Load on QPOSCNT = 0 1 | PCLOAD_QPOSCMPLoad when QPOSCNT = QPOSCMP" "0,1" bitfld.word 0xA 13. "PCPOL,Polarity of sync output 0 | PCPOL_HIGHActive HIGH pulse output 1 | PCPOL_LOWActive LOW pulse output" "0,1" bitfld.word 0xA 12. "PCE,Position compare enable/disable 0 | PCE_DISABLEDisable position compare unit 1 | PCE_ENABLEEnable position compare unit" "0,1" hexmask.word 0xA 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width 0x000 | SYSCLKOUT41 * 4 * SYSCLKOUT cycles 0x001 | SYSCLKOUT82 * 4 * SYSCLKOUT cycles 0xFFF | SYSCLKOUT163844096 * 4 * SYSCLKOUT cycles" line.word 0xC "CONTROLSS_EQEP0_QEINT" bitfld.word 0xC 12. "QMAE,QMA Error Interrupt enable 0 | QMAE_DISABLEInterrupt is disabled 1 | QMAE_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 11. "UTO,Unit time out interrupt enable 0 | UTO_DISABLEInterrupt is disabled 1 | UTO_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 10. "IEL,Index event latch interrupt enable 0 | IEL_DISABLEInterrupt is disabled 1 | IEL_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 9. "SEL,Strobe event latch interrupt enable 0 | SEL_DISABLEInterrupt is disabled 1 | SEL_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 8. "PCM,Position-compare match interrupt enable 0 | PCM_DISABLEInterrupt is disabled 1 | PCM_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 7. "PCR,Position-compare ready interrupt enable 0 | PCR_DISABLEInterrupt is disabled 1 | PCR_ENABLEInterrupt is enabled" "0,1" newline bitfld.word 0xC 6. "PCO,Position counter overflow interrupt enable 0 | PCO_DISABLEInterrupt is disabled 1 | PCO_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 5. "PCU,Position counter underflow interrupt enable 0 | PCU_DISABLEInterrupt is disabled 1 | PCU_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 4. "WTO,Watchdog time out interrupt enable 0 | WTO_DISABLEInterrupt is disabled 1 | WTO_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 3. "QDC,Quadrature direction change interrupt enable 0 | QDC_DISABLEInterrupt is disabled 1 | QDC_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 2. "QPE,Quadrature phase error interrupt enable 0 | QPE_DISABLEInterrupt is disabled 1 | QPE_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 1. "PCE,Position counter error interrupt enable 0 | PCE_DISABLEInterrupt is disabled 1 | PCE_ENABLEInterrupt is enabled" "0,1" rgroup.word 0x32++0x1 line.word 0x0 "CONTROLSS_EQEP0_QFLG" bitfld.word 0x0 12. "QMAE,QMA Error interrupt flag Read0 | QMAE_NOFLAGNo interrupt generated Read1 | QMAE_FLAGInterrupt was generated" "0,1" bitfld.word 0x0 11. "UTO,Unit time out interrupt flag Read0 | UTO_NOFLAGNo interrupt generated Read1 | UTO_FLAGSet by eQEP unit timer period match" "0,1" bitfld.word 0x0 10. "IEL,Index event latch interrupt flag Read0 | IEL_NOFLAGNo interrupt generated Read1 | IEL_FLAGThis bit is set after latching the QPOSCNT to QPOSILAT" "0,1" bitfld.word 0x0 9. "SEL,Strobe event latch interrupt flag Read0 | SEL_NOFLAGNo interrupt generated Read1 | SEL_FLAGThis bit is set after latching the QPOSCNT to QPOSSLAT" "0,1" bitfld.word 0x0 8. "PCM,eQEP compare match event interrupt flag Read0 | PCM_NOFLAGNo interrupt generated Read1 | PCM_FLAGThis bit is set on position-compare match" "0,1" bitfld.word 0x0 7. "PCR,Position-compare ready interrupt flag Read0 | PCR_NOFLAGNo interrupt generated Read1 | PCR_FLAGThis bit is set after transferring the shadow register value to the active position compare register" "0,1" newline bitfld.word 0x0 6. "PCO,Position counter overflow interrupt flag Read0 | PCO_NOFLAGNo interrupt generated Read1 | PCO_FLAGThis bit is set on position counter overflow." "0,1" bitfld.word 0x0 5. "PCU,Position counter underflow interrupt flag Read0 | PCU_NOFLAGNo interrupt generated Read1 | PCU_FLAGThis bit is set on position counter underflow." "0,1" bitfld.word 0x0 4. "WTO,Watchdog timeout interrupt flag Read0 | WTO_NOFLAGNo interrupt generated Read1 | WTO_FLAGSet by watchdog timeout" "0,1" bitfld.word 0x0 3. "QDC,Quadrature direction change interrupt flag Read0 | QDC_NOFLAGNo interrupt generated Read1 | QDC_FLAGInterrupt was generated" "0,1" bitfld.word 0x0 2. "PHE,Quadrature phase error interrupt flag Read0 | PHE_NOFLAGNo interrupt generated Read1 | PHE_FLAGSet on simultaneous transition of QEPA and QEPB" "0,1" bitfld.word 0x0 1. "PCE,Position counter error interrupt flag Read0 | PCE_NOFLAGNo interrupt generated Read1 | PCE_FLAGPosition counter error" "0,1" newline bitfld.word 0x0 0. "INT,Global interrupt status flag Read0 | INT_NOFLAGNo interrupt generated Read1 | INT_FLAGInterrupt was generated" "0,1" group.word 0x34++0x9 line.word 0x0 "CONTROLSS_EQEP0_QCLR" bitfld.word 0x0 12. "QMAE,Clear QMA Error interrupt flag 0 | QMAE_NOEFFECTNo effect 1 | QMAE_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 11. "UTO,Clear unit time out interrupt flag 0 | UTO_NOEFFECTNo effect 1 | UTO_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 10. "IEL,Clear index event latch interrupt flag 0 | IEL_NOEFFECTNo effect 1 | IEL_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 9. "SEL,Clear strobe event latch interrupt flag 0 | SEL_NOEFFECTNo effect 1 | SEL_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 8. "PCM,Clear eQEP compare match event interrupt flag 0 | PCM_NOEFFECTNo effect 1 | PCM_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 7. "PCR,Clear position-compare ready interrupt flag 0 | PCR_NOEFFECTNo effect 1 | PCR_CLRClears the interrupt flag" "0,1" newline bitfld.word 0x0 6. "PCO,Clear position counter overflow interrupt flag 0 | PCO_NOEFFECTNo effect 1 | PCO_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 5. "PCU,Clear position counter underflow interrupt flag 0 | PCU_NOEFFECTNo effect 1 | PCU_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 4. "WTO,Clear watchdog timeout interrupt flag 0 | WTO_NOEFFECTNo effect 1 | WTO_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 3. "QDC,Clear quadrature direction change interrupt flag 0 | QDC_NOEFFECTNo effect 1 | QDC_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 2. "PHE,Clear quadrature phase error interrupt flag 0 | PHE_NOEFFECTNo effect 1 | PHE_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 1. "PCE,Clear position counter error interrupt flag 0 | PCE_NOEFFECTNo effect 1 | PCE_CLRClears the interrupt flag" "0,1" newline bitfld.word 0x0 0. "INT,Global interrupt clear flag 0 | INT_NOEFFECTNo effect 1 | INT_CLRClears the interrupt flag" "0,1" line.word 0x2 "CONTROLSS_EQEP0_QFRC" bitfld.word 0x2 12. "QMAE,Force QMA error interrupt 0 | QMAE_NOEFFECTNo effect 1 | QMAE_FORCEForce the interrupt" "0,1" bitfld.word 0x2 11. "UTO,Force unit time out interrupt 0 | UTO_NOEFFECTNo effect 1 | UTO_FORCEForce the interrupt" "0,1" bitfld.word 0x2 10. "IEL,Force index event latch interrupt 0 | IEL_NOEFFECTNo effect 1 | IEL_FORCEForce the interrupt" "0,1" bitfld.word 0x2 9. "SEL,Force strobe event latch interrupt 0 | SEL_NOEFFECTNo effect 1 | SEL_FORCEForce the interrupt" "0,1" bitfld.word 0x2 8. "PCM,Force position-compare match interrupt 0 | PCM_NOEFFECTNo effect 1 | PCM_FORCEForce the interrupt" "0,1" bitfld.word 0x2 7. "PCR,Force position-compare ready interrupt 0 | PCR_NOEFFECTNo effect 1 | PCR_FORCEForce the interrupt" "0,1" newline bitfld.word 0x2 6. "PCO,Force position counter overflow interrupt 0 | PCO_NOEFFECTNo effect 1 | PCO_FORCEForce the interrupt" "0,1" bitfld.word 0x2 5. "PCU,Force position counter underflow interrupt 0 | PCU_NOEFFECTNo effect 1 | PCU_FORCEForce the interrupt" "0,1" bitfld.word 0x2 4. "WTO,Force watchdog time out interrupt 0 | WTO_NOEFFECTNo effect 1 | WTO_FORCEForce the interrupt" "0,1" bitfld.word 0x2 3. "QDC,Force quadrature direction change interrupt 0 | QDC_NOEFFECTNo effect 1 | QDC_FORCEForce the interrupt" "0,1" bitfld.word 0x2 2. "PHE,Force quadrature phase error interrupt 0 | PHE_NOEFFECTNo effect 1 | PHE_FORCEForce the interrupt" "0,1" bitfld.word 0x2 1. "PCE,Force position counter error interrupt 0 | PCE_NOEFFECTNo effect 1 | PCE_FORCEForce the interrupt" "0,1" line.word 0x4 "CONTROLSS_EQEP0_QEPSTS" bitfld.word 0x4 7. "UPEVNT,Unit position event flag 0 | UPEVNT_NODETCTNo unit position event detected 1 | UPEVNT_DETCTUnit position event detected. Write 1 to clear" "0,1" rbitfld.word 0x4 6. "FIDF,Direction on the first index marker Status of the direction is latched on the first index event marker. Read0 | FIDF_COUNTERCLKCounter-clockwise rotation (or reverse movement) on the first index event Read1 | FIDF_CLKClockwise.." "0,1" rbitfld.word 0x4 5. "QDF,Quadrature direction flag Read0 | QDF_COUNTERCLKCounter-clockwise rotation (or reverse movement) Read1 | QDF_CLKClockwise rotation (or forward movement)" "0,1" rbitfld.word 0x4 4. "QDLF,eQEP direction latch flag Read0 | QDLF_COUNTERCLKCounter-clockwise rotation (or reverse movement) on index event marker Read1 | QDLF_CLKClockwise rotation (or forward movement) on index event marker" "0,1" bitfld.word 0x4 3. "COEF,Capture overflow error flag 0 | COEF_WRT1Overflow has not occurred. 1 | COEF_OVFOverflow occurred in eQEP Capture timer (QEPCTMR). This bit is cleared by writing a '1'." "0,1" bitfld.word 0x4 2. "CDEF,Capture direction error flag 0 | CDEF_WRT1Capture direction error has not occurred. 1 | CDEF_DIRECTDirection change occurred between the capture position event. This bit is cleared by writing a '1'." "0,1" newline bitfld.word 0x4 1. "FIMF,First index marker flag 0 | FIMF_WRT1First index pulse has not occurred. 1 | FIMF_SETINDEXSet by first occurrence of index pulse. This bit is cleared by writing a '1'." "0,1" rbitfld.word 0x4 0. "PCEF,Position counter error flag. This bit is not sticky and it is updated for every index event. Read0 | PCEF_NOERRORNo error occurred during the last index transition Read1 | PCEF_ERRORPosition counter error" "0,1" line.word 0x6 "CONTROLSS_EQEP0_QCTMR" hexmask.word 0x6 0.--15. 1. "QCTMR,This register provides time base for edge capture unit." line.word 0x8 "CONTROLSS_EQEP0_QCPRD" hexmask.word 0x8 0.--15. 1. "QCPRD,This register holds the period count value between the last successive eQEP position events" rgroup.word 0x3E++0x3 line.word 0x0 "CONTROLSS_EQEP0_QCTMRLAT" hexmask.word 0x0 0.--15. 1. "QCTMRLAT,The eQEP capture timer value can be latched into this register on two events viz. unit timeout event reading the eQEP position counter." line.word 0x2 "CONTROLSS_EQEP0_QCPRDLAT" hexmask.word 0x2 0.--15. 1. "QCPRDLAT,eQEP capture period value can be latched into this register on two events viz. unit timeout event reading the eQEP position counter." rgroup.long 0x60++0x3 line.long 0x0 "CONTROLSS_EQEP0_REV" bitfld.long 0x0 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" group.long 0x64++0xB line.long 0x0 "CONTROLSS_EQEP0_QEPSTROBESEL" bitfld.long 0x0 0.--1. "STROBESEL,Strobe source select: 0x0 | QS_AFTER_POL_MUXQEP Strobe after polarity mux 0x1 | QS_AFTER_POL_MUXQEP Strobe after polarity mux 0x2 | ADCSOCA_AS_QSQEP Strobe after polarity mux ORed with ADCSOCA 0x3 |.." "0,1,2,3" line.long 0x4 "CONTROLSS_EQEP0_QMACTRL" bitfld.long 0x4 0.--2. "MODE,Select Mode for QMA mode: 000 : QMA Module is bypassed. 001 : QMA Mode-1 operation selected 010 : QMA Mode-2 operation selected 011 : QMA Module is bypassed (reserved) 1xx : QMA Module is bypassed (reserved)" "0: QMA Module is bypassed,1: QMA Mode-1 operation selected,?,?,?,?,?,?" line.long 0x8 "CONTROLSS_EQEP0_QEPSRCSEL" hexmask.long.byte 0x8 24.--28. 1. "QEPSSEL,QEP Strobe source select: 0x0: Device Pin (Default) 0x1 to 0x1F : To be defined in SOC context Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." hexmask.long.byte 0x8 16.--20. 1. "QEPISEL,QEP Index source select: 0x0: Device Pin (Default) 0x1 to 0x1F : To be defined in SOC context Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." hexmask.long.byte 0x8 8.--12. 1. "QEPBSEL,QEPB source select: 0x0: Device Pin (Default) 0x1 to 0x1F : To be defined in SOC context Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." hexmask.long.byte 0x8 0.--4. 1. "QEPASEL,QEPA source select: 0x0: Device Pin (Default) 0x1 to 0x1F : To be defined in SOC context Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." tree.end tree "EQEP1" base ad:0x50271000 group.long 0x0++0xF line.long 0x0 "CONTROLSS_EQEP1_QPOSCNT" hexmask.long 0x0 0.--31. 1. "QPOSCNT,Position Counter This 32-bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point. This.." line.long 0x4 "CONTROLSS_EQEP1_QPOSINIT" hexmask.long 0x4 0.--31. 1. "QPOSINIT,Position Counter Init This register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software. Writes to this register should.." line.long 0x8 "CONTROLSS_EQEP1_QPOSMAX" hexmask.long 0x8 0.--31. 1. "QPOSMAX,Maximum Position Count This register contains the maximum position counter value. Writes to this register should always be full 32-bit writes." line.long 0xC "CONTROLSS_EQEP1_QPOSCMP" hexmask.long 0xC 0.--31. 1. "QPOSCMP,Position Compare The position-compare value in this register is compared with the position counter (QPOSCNT) to generate sync output and/or interrupt on compare match." rgroup.long 0x10++0xB line.long 0x0 "CONTROLSS_EQEP1_QPOSILAT" hexmask.long 0x0 0.--31. 1. "QPOSILAT,Index Position Latch The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits." line.long 0x4 "CONTROLSS_EQEP1_QPOSSLAT" hexmask.long 0x4 0.--31. 1. "QPOSSLAT,Strobe Position Latch The position-counter value is latched into this register on a strobe event as defined by the QEPCTL[SEL] bits." line.long 0x8 "CONTROLSS_EQEP1_QPOSLAT" hexmask.long 0x8 0.--31. 1. "QPOSLAT,Position Latch The position-counter value is latched into this register on a unit time out event." group.long 0x1C++0x7 line.long 0x0 "CONTROLSS_EQEP1_QUTMR" hexmask.long 0x0 0.--31. 1. "QUTMR,QEP Unit Timer This register acts as time base for unit time event generation. When this timer value matches the unit time period value a unit time event is generated." line.long 0x4 "CONTROLSS_EQEP1_QUPRD" hexmask.long 0x4 0.--31. 1. "QUPRD,QEP Unit Period This register contains the period count for the unit timer to generate periodic unit time events. These events latch the eQEP position information at periodic intervals and optionally generate an interrupt. Writes to this register.." group.word 0x24++0xD line.word 0x0 "CONTROLSS_EQEP1_QWDTMR" hexmask.word 0x0 0.--15. 1. "QWDTMR,QEP Watchdog Timer This register acts as time base for the watchdog to detect motor stalls. When this timer value matches with the watchdog's period value a watchdog timeout interrupt is generated. This register is reset upon edge transition in.." line.word 0x2 "CONTROLSS_EQEP1_QWDPRD" hexmask.word 0x2 0.--15. 1. "QWDPRD,QEP Watchdog Period This register contains the time-out count for the eQEP peripheral watch dog timer. When the watchdog timer value matches the watchdog period value a watchdog timeout interrupt is generated." line.word 0x4 "CONTROLSS_EQEP1_QDECCTL" bitfld.word 0x4 14.--15. "QSRC,Position-counter source selection" "0,1,2,3" bitfld.word 0x4 13. "SOEN,Sync output-enable 0 | SYNC_DISABLEDisable position-compare sync output 1 | SYNC_ENABLEEnable position-compare sync output" "0,1" bitfld.word 0x4 12. "SPSEL,Sync output pin selection 0 | INDEX_PINIndex pin is used for sync output 1 | STROBE_PINStrobe pin is used for sync output" "0,1" bitfld.word 0x4 11. "XCR,External Clock Rate 0 | XCR_2XRESOL2x resolution: Count the rising/falling edge 1 | XCR_1XRESOL1x resolution: Count the rising edge only" "0,1" bitfld.word 0x4 10. "SWAP,CLK/DIR Signal Source for Position Counter 0 | SWAP_DISABLEQuadrature-clock inputs are not swapped 1 | SWAP_ENABLEQuadrature-clock inputs are swapped" "0,1" bitfld.word 0x4 9. "IGATE,Index pulse gating option 0 | IGATE_DISABLEDisable gating of Index pulse 1 | IGATE_ENABLEGate the index pin with strobe" "0,1" newline bitfld.word 0x4 8. "QAP,QEPA input polarity 0 | QAP_NOPOLARNo effect 1 | QAP_POLARNegates QEPA input" "0,1" bitfld.word 0x4 7. "QBP,QEPB input polarity 0 | QBP_NOPOLARNo effect 1 | QBP_POLARNegates QEPB input" "0,1" bitfld.word 0x4 6. "QIP,QEPI input polarity 0 | QIP_NOPOLARNo effect 1 | QIP_POLARNegates QEPI input" "0,1" bitfld.word 0x4 5. "QSP,QEPS input polarity 0 | QSP_NOPOLARNo effect 1 | QSP_POLARNegates QEPS input" "0,1" bitfld.word 0x4 0. "QIDIRE,0 - Compatible mode Behavior same as existing devices 1 - Enhancement for Direction change during Index will be enabled" "0,1" line.word 0x6 "CONTROLSS_EQEP1_QEPCTL" bitfld.word 0x6 14.--15. "FREE_SOFT,Emulation mode 0x0 | FREE_SOFT_0QPOSCNT behavior Position counter stops immediately on emulation suspend 0h (R/W) = QWDTMR behavior Watchdog counter stops immediately 0h (R/W) = QUTMR behavior Unit timer stops immediately 0h (R/W) =.." "0,1,2,3" bitfld.word 0x6 12.--13. "PCRM,Postion counter reset 0x0 | PCRM_INDEXPosition counter reset on an index event 0x1 | PCRM_MAXPOSPosition counter reset on the maximum position 0x2 | PCRM_FIRSTINDEXPosition counter reset on the first index event 0x3 |.." "0,1,2,3" bitfld.word 0x6 10.--11. "SEI,Strobe event initialization of position counter 0x0 | SEI_NOTHING0Does nothing (action disabled) 0x1 | SEI_NOTHING1Does nothing (action disabled) 0x2 | SEI_INITQEPSRISINGInitializes the position counter on rising edge of the.." "0,1,2,3" bitfld.word 0x6 8.--9. "IEI,Index event init of position count 0x0 | IEI_NOTHING0Do nothing (action disabled) 0x1 | IEI_NOTHING1Do nothing (action disabled) 0x2 | IEI_INITRISINGInitializes the position counter on the rising edge of the QEPI signal.." "0,1,2,3" bitfld.word 0x6 7. "SWI,Software init position counter 0 | SWI_NOTHINGDo nothing (action disabled) 1 | SWI_INITPOSInitialize position counter (QPOSCNT=QPOSINIT). This bit is not cleared automatically" "0,1" bitfld.word 0x6 6. "SEL,Strobe event latch of position counter 0 | SEL_QEPSRISINGThe position counter is latched on the rising edge of QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling edge can be done by inverting the strobe input using the QSP bit in the.." "0,1" newline bitfld.word 0x6 4.--5. "IEL,Index event latch of position counter (software index marker) 0x0 | IEL_RSVDReserved 0x1 | IEL_POSRISINGLatches position counter on rising edge of the index signal 0x2 | IEL_POSFALLINGLatches position counter on falling edge.." "0,1,2,3" bitfld.word 0x6 3. "QPEN,Quadrature position counter enable/software reset 0 | QPEN_RESETReset the eQEP peripheral internal operating flags/read-only registers. Control/configuration registers are not disturbed by a software reset. When QPEN is disabled some flags.." "0,1" bitfld.word 0x6 2. "QCLM,QEP capture latch mode 0 | QCLM_CPULatch on position counter read by CPU. Capture timer and capture period values are latched into QCTMRLAT and QCPRDLAT registers when CPU reads the QPOSCNT register. 1 | QCLM_TIMEOUTLatch on unit.." "0,1" bitfld.word 0x6 1. "UTE,QEP unit timer enable 0 | UTE_DISABLEDisable eQEP unit timer 1 | UTE_ENABLEEnable unit timer" "0,1" bitfld.word 0x6 0. "WDE,QEP watchdog enable 0 | WDE_DISABLEDisable the eQEP watchdog timer 1 | WDE_ENABLEEnable the eQEP watchdog timer" "0,1" line.word 0x8 "CONTROLSS_EQEP1_QCAPCTL" bitfld.word 0x8 15. "CEN,Enable eQEP capture 0 | CEN_DISABLEeQEP capture unit is disabled 1 | CEN_ENABLEeQEP capture unit is enabled" "0,1" bitfld.word 0x8 4.--6. "CCPS,eQEP capture timer clock prescaler 0x0 | SYSCLKOUT1CAPCLK = SYSCLKOUT/1 0x1 | SYSCLKOUT2CAPCLK = SYSCLKOUT/2 0x2 | SYSCLKOUT4CAPCLK = SYSCLKOUT/4 0x3 | SYSCLKOUT8CAPCLK = SYSCLKOUT/8 0x4 | SYSCLKOUT16CAPCLK.." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x8 0.--3. 1. "UPPS,Unit position event prescaler 0x0 | QCLK1UPEVNT = QCLK/1 0x1 | QCLK2UPEVNT = QCLK/2 0x2 | QCLK4UPEVNT = QCLK/4 0x3 | QCLK8UPEVNT = QCLK/8 0x4 | QCLK16UPEVNT = QCLK/16 0x5 | QCLK32UPEVNT = QCLK/32.." line.word 0xA "CONTROLSS_EQEP1_QPOSCTL" bitfld.word 0xA 15. "PCSHDW,Position compare of shadow enable 0 | PCSHDW_DISABLEShadow disabled load Immediate 1 | PCSHDW_ENABLEShadow enabled" "0,1" bitfld.word 0xA 14. "PCLOAD,Position compare of shadow load 0 | PCLOAD_0Load on QPOSCNT = 0 1 | PCLOAD_QPOSCMPLoad when QPOSCNT = QPOSCMP" "0,1" bitfld.word 0xA 13. "PCPOL,Polarity of sync output 0 | PCPOL_HIGHActive HIGH pulse output 1 | PCPOL_LOWActive LOW pulse output" "0,1" bitfld.word 0xA 12. "PCE,Position compare enable/disable 0 | PCE_DISABLEDisable position compare unit 1 | PCE_ENABLEEnable position compare unit" "0,1" hexmask.word 0xA 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width 0x000 | SYSCLKOUT41 * 4 * SYSCLKOUT cycles 0x001 | SYSCLKOUT82 * 4 * SYSCLKOUT cycles 0xFFF | SYSCLKOUT163844096 * 4 * SYSCLKOUT cycles" line.word 0xC "CONTROLSS_EQEP1_QEINT" bitfld.word 0xC 12. "QMAE,QMA Error Interrupt enable 0 | QMAE_DISABLEInterrupt is disabled 1 | QMAE_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 11. "UTO,Unit time out interrupt enable 0 | UTO_DISABLEInterrupt is disabled 1 | UTO_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 10. "IEL,Index event latch interrupt enable 0 | IEL_DISABLEInterrupt is disabled 1 | IEL_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 9. "SEL,Strobe event latch interrupt enable 0 | SEL_DISABLEInterrupt is disabled 1 | SEL_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 8. "PCM,Position-compare match interrupt enable 0 | PCM_DISABLEInterrupt is disabled 1 | PCM_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 7. "PCR,Position-compare ready interrupt enable 0 | PCR_DISABLEInterrupt is disabled 1 | PCR_ENABLEInterrupt is enabled" "0,1" newline bitfld.word 0xC 6. "PCO,Position counter overflow interrupt enable 0 | PCO_DISABLEInterrupt is disabled 1 | PCO_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 5. "PCU,Position counter underflow interrupt enable 0 | PCU_DISABLEInterrupt is disabled 1 | PCU_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 4. "WTO,Watchdog time out interrupt enable 0 | WTO_DISABLEInterrupt is disabled 1 | WTO_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 3. "QDC,Quadrature direction change interrupt enable 0 | QDC_DISABLEInterrupt is disabled 1 | QDC_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 2. "QPE,Quadrature phase error interrupt enable 0 | QPE_DISABLEInterrupt is disabled 1 | QPE_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 1. "PCE,Position counter error interrupt enable 0 | PCE_DISABLEInterrupt is disabled 1 | PCE_ENABLEInterrupt is enabled" "0,1" rgroup.word 0x32++0x1 line.word 0x0 "CONTROLSS_EQEP1_QFLG" bitfld.word 0x0 12. "QMAE,QMA Error interrupt flag Read0 | QMAE_NOFLAGNo interrupt generated Read1 | QMAE_FLAGInterrupt was generated" "0,1" bitfld.word 0x0 11. "UTO,Unit time out interrupt flag Read0 | UTO_NOFLAGNo interrupt generated Read1 | UTO_FLAGSet by eQEP unit timer period match" "0,1" bitfld.word 0x0 10. "IEL,Index event latch interrupt flag Read0 | IEL_NOFLAGNo interrupt generated Read1 | IEL_FLAGThis bit is set after latching the QPOSCNT to QPOSILAT" "0,1" bitfld.word 0x0 9. "SEL,Strobe event latch interrupt flag Read0 | SEL_NOFLAGNo interrupt generated Read1 | SEL_FLAGThis bit is set after latching the QPOSCNT to QPOSSLAT" "0,1" bitfld.word 0x0 8. "PCM,eQEP compare match event interrupt flag Read0 | PCM_NOFLAGNo interrupt generated Read1 | PCM_FLAGThis bit is set on position-compare match" "0,1" bitfld.word 0x0 7. "PCR,Position-compare ready interrupt flag Read0 | PCR_NOFLAGNo interrupt generated Read1 | PCR_FLAGThis bit is set after transferring the shadow register value to the active position compare register" "0,1" newline bitfld.word 0x0 6. "PCO,Position counter overflow interrupt flag Read0 | PCO_NOFLAGNo interrupt generated Read1 | PCO_FLAGThis bit is set on position counter overflow." "0,1" bitfld.word 0x0 5. "PCU,Position counter underflow interrupt flag Read0 | PCU_NOFLAGNo interrupt generated Read1 | PCU_FLAGThis bit is set on position counter underflow." "0,1" bitfld.word 0x0 4. "WTO,Watchdog timeout interrupt flag Read0 | WTO_NOFLAGNo interrupt generated Read1 | WTO_FLAGSet by watchdog timeout" "0,1" bitfld.word 0x0 3. "QDC,Quadrature direction change interrupt flag Read0 | QDC_NOFLAGNo interrupt generated Read1 | QDC_FLAGInterrupt was generated" "0,1" bitfld.word 0x0 2. "PHE,Quadrature phase error interrupt flag Read0 | PHE_NOFLAGNo interrupt generated Read1 | PHE_FLAGSet on simultaneous transition of QEPA and QEPB" "0,1" bitfld.word 0x0 1. "PCE,Position counter error interrupt flag Read0 | PCE_NOFLAGNo interrupt generated Read1 | PCE_FLAGPosition counter error" "0,1" newline bitfld.word 0x0 0. "INT,Global interrupt status flag Read0 | INT_NOFLAGNo interrupt generated Read1 | INT_FLAGInterrupt was generated" "0,1" group.word 0x34++0x9 line.word 0x0 "CONTROLSS_EQEP1_QCLR" bitfld.word 0x0 12. "QMAE,Clear QMA Error interrupt flag 0 | QMAE_NOEFFECTNo effect 1 | QMAE_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 11. "UTO,Clear unit time out interrupt flag 0 | UTO_NOEFFECTNo effect 1 | UTO_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 10. "IEL,Clear index event latch interrupt flag 0 | IEL_NOEFFECTNo effect 1 | IEL_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 9. "SEL,Clear strobe event latch interrupt flag 0 | SEL_NOEFFECTNo effect 1 | SEL_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 8. "PCM,Clear eQEP compare match event interrupt flag 0 | PCM_NOEFFECTNo effect 1 | PCM_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 7. "PCR,Clear position-compare ready interrupt flag 0 | PCR_NOEFFECTNo effect 1 | PCR_CLRClears the interrupt flag" "0,1" newline bitfld.word 0x0 6. "PCO,Clear position counter overflow interrupt flag 0 | PCO_NOEFFECTNo effect 1 | PCO_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 5. "PCU,Clear position counter underflow interrupt flag 0 | PCU_NOEFFECTNo effect 1 | PCU_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 4. "WTO,Clear watchdog timeout interrupt flag 0 | WTO_NOEFFECTNo effect 1 | WTO_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 3. "QDC,Clear quadrature direction change interrupt flag 0 | QDC_NOEFFECTNo effect 1 | QDC_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 2. "PHE,Clear quadrature phase error interrupt flag 0 | PHE_NOEFFECTNo effect 1 | PHE_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 1. "PCE,Clear position counter error interrupt flag 0 | PCE_NOEFFECTNo effect 1 | PCE_CLRClears the interrupt flag" "0,1" newline bitfld.word 0x0 0. "INT,Global interrupt clear flag 0 | INT_NOEFFECTNo effect 1 | INT_CLRClears the interrupt flag" "0,1" line.word 0x2 "CONTROLSS_EQEP1_QFRC" bitfld.word 0x2 12. "QMAE,Force QMA error interrupt 0 | QMAE_NOEFFECTNo effect 1 | QMAE_FORCEForce the interrupt" "0,1" bitfld.word 0x2 11. "UTO,Force unit time out interrupt 0 | UTO_NOEFFECTNo effect 1 | UTO_FORCEForce the interrupt" "0,1" bitfld.word 0x2 10. "IEL,Force index event latch interrupt 0 | IEL_NOEFFECTNo effect 1 | IEL_FORCEForce the interrupt" "0,1" bitfld.word 0x2 9. "SEL,Force strobe event latch interrupt 0 | SEL_NOEFFECTNo effect 1 | SEL_FORCEForce the interrupt" "0,1" bitfld.word 0x2 8. "PCM,Force position-compare match interrupt 0 | PCM_NOEFFECTNo effect 1 | PCM_FORCEForce the interrupt" "0,1" bitfld.word 0x2 7. "PCR,Force position-compare ready interrupt 0 | PCR_NOEFFECTNo effect 1 | PCR_FORCEForce the interrupt" "0,1" newline bitfld.word 0x2 6. "PCO,Force position counter overflow interrupt 0 | PCO_NOEFFECTNo effect 1 | PCO_FORCEForce the interrupt" "0,1" bitfld.word 0x2 5. "PCU,Force position counter underflow interrupt 0 | PCU_NOEFFECTNo effect 1 | PCU_FORCEForce the interrupt" "0,1" bitfld.word 0x2 4. "WTO,Force watchdog time out interrupt 0 | WTO_NOEFFECTNo effect 1 | WTO_FORCEForce the interrupt" "0,1" bitfld.word 0x2 3. "QDC,Force quadrature direction change interrupt 0 | QDC_NOEFFECTNo effect 1 | QDC_FORCEForce the interrupt" "0,1" bitfld.word 0x2 2. "PHE,Force quadrature phase error interrupt 0 | PHE_NOEFFECTNo effect 1 | PHE_FORCEForce the interrupt" "0,1" bitfld.word 0x2 1. "PCE,Force position counter error interrupt 0 | PCE_NOEFFECTNo effect 1 | PCE_FORCEForce the interrupt" "0,1" line.word 0x4 "CONTROLSS_EQEP1_QEPSTS" bitfld.word 0x4 7. "UPEVNT,Unit position event flag 0 | UPEVNT_NODETCTNo unit position event detected 1 | UPEVNT_DETCTUnit position event detected. Write 1 to clear" "0,1" rbitfld.word 0x4 6. "FIDF,Direction on the first index marker Status of the direction is latched on the first index event marker. Read0 | FIDF_COUNTERCLKCounter-clockwise rotation (or reverse movement) on the first index event Read1 | FIDF_CLKClockwise.." "0,1" rbitfld.word 0x4 5. "QDF,Quadrature direction flag Read0 | QDF_COUNTERCLKCounter-clockwise rotation (or reverse movement) Read1 | QDF_CLKClockwise rotation (or forward movement)" "0,1" rbitfld.word 0x4 4. "QDLF,eQEP direction latch flag Read0 | QDLF_COUNTERCLKCounter-clockwise rotation (or reverse movement) on index event marker Read1 | QDLF_CLKClockwise rotation (or forward movement) on index event marker" "0,1" bitfld.word 0x4 3. "COEF,Capture overflow error flag 0 | COEF_WRT1Overflow has not occurred. 1 | COEF_OVFOverflow occurred in eQEP Capture timer (QEPCTMR). This bit is cleared by writing a '1'." "0,1" bitfld.word 0x4 2. "CDEF,Capture direction error flag 0 | CDEF_WRT1Capture direction error has not occurred. 1 | CDEF_DIRECTDirection change occurred between the capture position event. This bit is cleared by writing a '1'." "0,1" newline bitfld.word 0x4 1. "FIMF,First index marker flag 0 | FIMF_WRT1First index pulse has not occurred. 1 | FIMF_SETINDEXSet by first occurrence of index pulse. This bit is cleared by writing a '1'." "0,1" rbitfld.word 0x4 0. "PCEF,Position counter error flag. This bit is not sticky and it is updated for every index event. Read0 | PCEF_NOERRORNo error occurred during the last index transition Read1 | PCEF_ERRORPosition counter error" "0,1" line.word 0x6 "CONTROLSS_EQEP1_QCTMR" hexmask.word 0x6 0.--15. 1. "QCTMR,This register provides time base for edge capture unit." line.word 0x8 "CONTROLSS_EQEP1_QCPRD" hexmask.word 0x8 0.--15. 1. "QCPRD,This register holds the period count value between the last successive eQEP position events" rgroup.word 0x3E++0x3 line.word 0x0 "CONTROLSS_EQEP1_QCTMRLAT" hexmask.word 0x0 0.--15. 1. "QCTMRLAT,The eQEP capture timer value can be latched into this register on two events viz. unit timeout event reading the eQEP position counter." line.word 0x2 "CONTROLSS_EQEP1_QCPRDLAT" hexmask.word 0x2 0.--15. 1. "QCPRDLAT,eQEP capture period value can be latched into this register on two events viz. unit timeout event reading the eQEP position counter." rgroup.long 0x60++0x3 line.long 0x0 "CONTROLSS_EQEP1_REV" bitfld.long 0x0 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" group.long 0x64++0xB line.long 0x0 "CONTROLSS_EQEP1_QEPSTROBESEL" bitfld.long 0x0 0.--1. "STROBESEL,Strobe source select: 0x0 | QS_AFTER_POL_MUXQEP Strobe after polarity mux 0x1 | QS_AFTER_POL_MUXQEP Strobe after polarity mux 0x2 | ADCSOCA_AS_QSQEP Strobe after polarity mux ORed with ADCSOCA 0x3 |.." "0,1,2,3" line.long 0x4 "CONTROLSS_EQEP1_QMACTRL" bitfld.long 0x4 0.--2. "MODE,Select Mode for QMA mode: 000 : QMA Module is bypassed. 001 : QMA Mode-1 operation selected 010 : QMA Mode-2 operation selected 011 : QMA Module is bypassed (reserved) 1xx : QMA Module is bypassed (reserved)" "0: QMA Module is bypassed,1: QMA Mode-1 operation selected,?,?,?,?,?,?" line.long 0x8 "CONTROLSS_EQEP1_QEPSRCSEL" hexmask.long.byte 0x8 24.--28. 1. "QEPSSEL,QEP Strobe source select: 0x0: Device Pin (Default) 0x1 to 0x1F : To be defined in SOC context Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." hexmask.long.byte 0x8 16.--20. 1. "QEPISEL,QEP Index source select: 0x0: Device Pin (Default) 0x1 to 0x1F : To be defined in SOC context Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." hexmask.long.byte 0x8 8.--12. 1. "QEPBSEL,QEPB source select: 0x0: Device Pin (Default) 0x1 to 0x1F : To be defined in SOC context Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." hexmask.long.byte 0x8 0.--4. 1. "QEPASEL,QEPA source select: 0x0: Device Pin (Default) 0x1 to 0x1F : To be defined in SOC context Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." tree.end tree "EQEP2" base ad:0x50272000 group.long 0x0++0xF line.long 0x0 "CONTROLSS_EQEP2_QPOSCNT" hexmask.long 0x0 0.--31. 1. "QPOSCNT,Position Counter This 32-bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point. This.." line.long 0x4 "CONTROLSS_EQEP2_QPOSINIT" hexmask.long 0x4 0.--31. 1. "QPOSINIT,Position Counter Init This register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software. Writes to this register should.." line.long 0x8 "CONTROLSS_EQEP2_QPOSMAX" hexmask.long 0x8 0.--31. 1. "QPOSMAX,Maximum Position Count This register contains the maximum position counter value. Writes to this register should always be full 32-bit writes." line.long 0xC "CONTROLSS_EQEP2_QPOSCMP" hexmask.long 0xC 0.--31. 1. "QPOSCMP,Position Compare The position-compare value in this register is compared with the position counter (QPOSCNT) to generate sync output and/or interrupt on compare match." rgroup.long 0x10++0xB line.long 0x0 "CONTROLSS_EQEP2_QPOSILAT" hexmask.long 0x0 0.--31. 1. "QPOSILAT,Index Position Latch The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits." line.long 0x4 "CONTROLSS_EQEP2_QPOSSLAT" hexmask.long 0x4 0.--31. 1. "QPOSSLAT,Strobe Position Latch The position-counter value is latched into this register on a strobe event as defined by the QEPCTL[SEL] bits." line.long 0x8 "CONTROLSS_EQEP2_QPOSLAT" hexmask.long 0x8 0.--31. 1. "QPOSLAT,Position Latch The position-counter value is latched into this register on a unit time out event." group.long 0x1C++0x7 line.long 0x0 "CONTROLSS_EQEP2_QUTMR" hexmask.long 0x0 0.--31. 1. "QUTMR,QEP Unit Timer This register acts as time base for unit time event generation. When this timer value matches the unit time period value a unit time event is generated." line.long 0x4 "CONTROLSS_EQEP2_QUPRD" hexmask.long 0x4 0.--31. 1. "QUPRD,QEP Unit Period This register contains the period count for the unit timer to generate periodic unit time events. These events latch the eQEP position information at periodic intervals and optionally generate an interrupt. Writes to this register.." group.word 0x24++0xD line.word 0x0 "CONTROLSS_EQEP2_QWDTMR" hexmask.word 0x0 0.--15. 1. "QWDTMR,QEP Watchdog Timer This register acts as time base for the watchdog to detect motor stalls. When this timer value matches with the watchdog's period value a watchdog timeout interrupt is generated. This register is reset upon edge transition in.." line.word 0x2 "CONTROLSS_EQEP2_QWDPRD" hexmask.word 0x2 0.--15. 1. "QWDPRD,QEP Watchdog Period This register contains the time-out count for the eQEP peripheral watch dog timer. When the watchdog timer value matches the watchdog period value a watchdog timeout interrupt is generated." line.word 0x4 "CONTROLSS_EQEP2_QDECCTL" bitfld.word 0x4 14.--15. "QSRC,Position-counter source selection" "0,1,2,3" bitfld.word 0x4 13. "SOEN,Sync output-enable 0 | SYNC_DISABLEDisable position-compare sync output 1 | SYNC_ENABLEEnable position-compare sync output" "0,1" bitfld.word 0x4 12. "SPSEL,Sync output pin selection 0 | INDEX_PINIndex pin is used for sync output 1 | STROBE_PINStrobe pin is used for sync output" "0,1" bitfld.word 0x4 11. "XCR,External Clock Rate 0 | XCR_2XRESOL2x resolution: Count the rising/falling edge 1 | XCR_1XRESOL1x resolution: Count the rising edge only" "0,1" bitfld.word 0x4 10. "SWAP,CLK/DIR Signal Source for Position Counter 0 | SWAP_DISABLEQuadrature-clock inputs are not swapped 1 | SWAP_ENABLEQuadrature-clock inputs are swapped" "0,1" bitfld.word 0x4 9. "IGATE,Index pulse gating option 0 | IGATE_DISABLEDisable gating of Index pulse 1 | IGATE_ENABLEGate the index pin with strobe" "0,1" newline bitfld.word 0x4 8. "QAP,QEPA input polarity 0 | QAP_NOPOLARNo effect 1 | QAP_POLARNegates QEPA input" "0,1" bitfld.word 0x4 7. "QBP,QEPB input polarity 0 | QBP_NOPOLARNo effect 1 | QBP_POLARNegates QEPB input" "0,1" bitfld.word 0x4 6. "QIP,QEPI input polarity 0 | QIP_NOPOLARNo effect 1 | QIP_POLARNegates QEPI input" "0,1" bitfld.word 0x4 5. "QSP,QEPS input polarity 0 | QSP_NOPOLARNo effect 1 | QSP_POLARNegates QEPS input" "0,1" bitfld.word 0x4 0. "QIDIRE,0 - Compatible mode Behavior same as existing devices 1 - Enhancement for Direction change during Index will be enabled" "0,1" line.word 0x6 "CONTROLSS_EQEP2_QEPCTL" bitfld.word 0x6 14.--15. "FREE_SOFT,Emulation mode 0x0 | FREE_SOFT_0QPOSCNT behavior Position counter stops immediately on emulation suspend 0h (R/W) = QWDTMR behavior Watchdog counter stops immediately 0h (R/W) = QUTMR behavior Unit timer stops immediately 0h (R/W) =.." "0,1,2,3" bitfld.word 0x6 12.--13. "PCRM,Postion counter reset 0x0 | PCRM_INDEXPosition counter reset on an index event 0x1 | PCRM_MAXPOSPosition counter reset on the maximum position 0x2 | PCRM_FIRSTINDEXPosition counter reset on the first index event 0x3 |.." "0,1,2,3" bitfld.word 0x6 10.--11. "SEI,Strobe event initialization of position counter 0x0 | SEI_NOTHING0Does nothing (action disabled) 0x1 | SEI_NOTHING1Does nothing (action disabled) 0x2 | SEI_INITQEPSRISINGInitializes the position counter on rising edge of the.." "0,1,2,3" bitfld.word 0x6 8.--9. "IEI,Index event init of position count 0x0 | IEI_NOTHING0Do nothing (action disabled) 0x1 | IEI_NOTHING1Do nothing (action disabled) 0x2 | IEI_INITRISINGInitializes the position counter on the rising edge of the QEPI signal.." "0,1,2,3" bitfld.word 0x6 7. "SWI,Software init position counter 0 | SWI_NOTHINGDo nothing (action disabled) 1 | SWI_INITPOSInitialize position counter (QPOSCNT=QPOSINIT). This bit is not cleared automatically" "0,1" bitfld.word 0x6 6. "SEL,Strobe event latch of position counter 0 | SEL_QEPSRISINGThe position counter is latched on the rising edge of QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling edge can be done by inverting the strobe input using the QSP bit in the.." "0,1" newline bitfld.word 0x6 4.--5. "IEL,Index event latch of position counter (software index marker) 0x0 | IEL_RSVDReserved 0x1 | IEL_POSRISINGLatches position counter on rising edge of the index signal 0x2 | IEL_POSFALLINGLatches position counter on falling edge.." "0,1,2,3" bitfld.word 0x6 3. "QPEN,Quadrature position counter enable/software reset 0 | QPEN_RESETReset the eQEP peripheral internal operating flags/read-only registers. Control/configuration registers are not disturbed by a software reset. When QPEN is disabled some flags.." "0,1" bitfld.word 0x6 2. "QCLM,QEP capture latch mode 0 | QCLM_CPULatch on position counter read by CPU. Capture timer and capture period values are latched into QCTMRLAT and QCPRDLAT registers when CPU reads the QPOSCNT register. 1 | QCLM_TIMEOUTLatch on unit.." "0,1" bitfld.word 0x6 1. "UTE,QEP unit timer enable 0 | UTE_DISABLEDisable eQEP unit timer 1 | UTE_ENABLEEnable unit timer" "0,1" bitfld.word 0x6 0. "WDE,QEP watchdog enable 0 | WDE_DISABLEDisable the eQEP watchdog timer 1 | WDE_ENABLEEnable the eQEP watchdog timer" "0,1" line.word 0x8 "CONTROLSS_EQEP2_QCAPCTL" bitfld.word 0x8 15. "CEN,Enable eQEP capture 0 | CEN_DISABLEeQEP capture unit is disabled 1 | CEN_ENABLEeQEP capture unit is enabled" "0,1" bitfld.word 0x8 4.--6. "CCPS,eQEP capture timer clock prescaler 0x0 | SYSCLKOUT1CAPCLK = SYSCLKOUT/1 0x1 | SYSCLKOUT2CAPCLK = SYSCLKOUT/2 0x2 | SYSCLKOUT4CAPCLK = SYSCLKOUT/4 0x3 | SYSCLKOUT8CAPCLK = SYSCLKOUT/8 0x4 | SYSCLKOUT16CAPCLK.." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x8 0.--3. 1. "UPPS,Unit position event prescaler 0x0 | QCLK1UPEVNT = QCLK/1 0x1 | QCLK2UPEVNT = QCLK/2 0x2 | QCLK4UPEVNT = QCLK/4 0x3 | QCLK8UPEVNT = QCLK/8 0x4 | QCLK16UPEVNT = QCLK/16 0x5 | QCLK32UPEVNT = QCLK/32.." line.word 0xA "CONTROLSS_EQEP2_QPOSCTL" bitfld.word 0xA 15. "PCSHDW,Position compare of shadow enable 0 | PCSHDW_DISABLEShadow disabled load Immediate 1 | PCSHDW_ENABLEShadow enabled" "0,1" bitfld.word 0xA 14. "PCLOAD,Position compare of shadow load 0 | PCLOAD_0Load on QPOSCNT = 0 1 | PCLOAD_QPOSCMPLoad when QPOSCNT = QPOSCMP" "0,1" bitfld.word 0xA 13. "PCPOL,Polarity of sync output 0 | PCPOL_HIGHActive HIGH pulse output 1 | PCPOL_LOWActive LOW pulse output" "0,1" bitfld.word 0xA 12. "PCE,Position compare enable/disable 0 | PCE_DISABLEDisable position compare unit 1 | PCE_ENABLEEnable position compare unit" "0,1" hexmask.word 0xA 0.--11. 1. "PCSPW,Select-position-compare sync output pulse width 0x000 | SYSCLKOUT41 * 4 * SYSCLKOUT cycles 0x001 | SYSCLKOUT82 * 4 * SYSCLKOUT cycles 0xFFF | SYSCLKOUT163844096 * 4 * SYSCLKOUT cycles" line.word 0xC "CONTROLSS_EQEP2_QEINT" bitfld.word 0xC 12. "QMAE,QMA Error Interrupt enable 0 | QMAE_DISABLEInterrupt is disabled 1 | QMAE_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 11. "UTO,Unit time out interrupt enable 0 | UTO_DISABLEInterrupt is disabled 1 | UTO_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 10. "IEL,Index event latch interrupt enable 0 | IEL_DISABLEInterrupt is disabled 1 | IEL_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 9. "SEL,Strobe event latch interrupt enable 0 | SEL_DISABLEInterrupt is disabled 1 | SEL_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 8. "PCM,Position-compare match interrupt enable 0 | PCM_DISABLEInterrupt is disabled 1 | PCM_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 7. "PCR,Position-compare ready interrupt enable 0 | PCR_DISABLEInterrupt is disabled 1 | PCR_ENABLEInterrupt is enabled" "0,1" newline bitfld.word 0xC 6. "PCO,Position counter overflow interrupt enable 0 | PCO_DISABLEInterrupt is disabled 1 | PCO_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 5. "PCU,Position counter underflow interrupt enable 0 | PCU_DISABLEInterrupt is disabled 1 | PCU_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 4. "WTO,Watchdog time out interrupt enable 0 | WTO_DISABLEInterrupt is disabled 1 | WTO_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 3. "QDC,Quadrature direction change interrupt enable 0 | QDC_DISABLEInterrupt is disabled 1 | QDC_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 2. "QPE,Quadrature phase error interrupt enable 0 | QPE_DISABLEInterrupt is disabled 1 | QPE_ENABLEInterrupt is enabled" "0,1" bitfld.word 0xC 1. "PCE,Position counter error interrupt enable 0 | PCE_DISABLEInterrupt is disabled 1 | PCE_ENABLEInterrupt is enabled" "0,1" rgroup.word 0x32++0x1 line.word 0x0 "CONTROLSS_EQEP2_QFLG" bitfld.word 0x0 12. "QMAE,QMA Error interrupt flag Read0 | QMAE_NOFLAGNo interrupt generated Read1 | QMAE_FLAGInterrupt was generated" "0,1" bitfld.word 0x0 11. "UTO,Unit time out interrupt flag Read0 | UTO_NOFLAGNo interrupt generated Read1 | UTO_FLAGSet by eQEP unit timer period match" "0,1" bitfld.word 0x0 10. "IEL,Index event latch interrupt flag Read0 | IEL_NOFLAGNo interrupt generated Read1 | IEL_FLAGThis bit is set after latching the QPOSCNT to QPOSILAT" "0,1" bitfld.word 0x0 9. "SEL,Strobe event latch interrupt flag Read0 | SEL_NOFLAGNo interrupt generated Read1 | SEL_FLAGThis bit is set after latching the QPOSCNT to QPOSSLAT" "0,1" bitfld.word 0x0 8. "PCM,eQEP compare match event interrupt flag Read0 | PCM_NOFLAGNo interrupt generated Read1 | PCM_FLAGThis bit is set on position-compare match" "0,1" bitfld.word 0x0 7. "PCR,Position-compare ready interrupt flag Read0 | PCR_NOFLAGNo interrupt generated Read1 | PCR_FLAGThis bit is set after transferring the shadow register value to the active position compare register" "0,1" newline bitfld.word 0x0 6. "PCO,Position counter overflow interrupt flag Read0 | PCO_NOFLAGNo interrupt generated Read1 | PCO_FLAGThis bit is set on position counter overflow." "0,1" bitfld.word 0x0 5. "PCU,Position counter underflow interrupt flag Read0 | PCU_NOFLAGNo interrupt generated Read1 | PCU_FLAGThis bit is set on position counter underflow." "0,1" bitfld.word 0x0 4. "WTO,Watchdog timeout interrupt flag Read0 | WTO_NOFLAGNo interrupt generated Read1 | WTO_FLAGSet by watchdog timeout" "0,1" bitfld.word 0x0 3. "QDC,Quadrature direction change interrupt flag Read0 | QDC_NOFLAGNo interrupt generated Read1 | QDC_FLAGInterrupt was generated" "0,1" bitfld.word 0x0 2. "PHE,Quadrature phase error interrupt flag Read0 | PHE_NOFLAGNo interrupt generated Read1 | PHE_FLAGSet on simultaneous transition of QEPA and QEPB" "0,1" bitfld.word 0x0 1. "PCE,Position counter error interrupt flag Read0 | PCE_NOFLAGNo interrupt generated Read1 | PCE_FLAGPosition counter error" "0,1" newline bitfld.word 0x0 0. "INT,Global interrupt status flag Read0 | INT_NOFLAGNo interrupt generated Read1 | INT_FLAGInterrupt was generated" "0,1" group.word 0x34++0x9 line.word 0x0 "CONTROLSS_EQEP2_QCLR" bitfld.word 0x0 12. "QMAE,Clear QMA Error interrupt flag 0 | QMAE_NOEFFECTNo effect 1 | QMAE_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 11. "UTO,Clear unit time out interrupt flag 0 | UTO_NOEFFECTNo effect 1 | UTO_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 10. "IEL,Clear index event latch interrupt flag 0 | IEL_NOEFFECTNo effect 1 | IEL_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 9. "SEL,Clear strobe event latch interrupt flag 0 | SEL_NOEFFECTNo effect 1 | SEL_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 8. "PCM,Clear eQEP compare match event interrupt flag 0 | PCM_NOEFFECTNo effect 1 | PCM_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 7. "PCR,Clear position-compare ready interrupt flag 0 | PCR_NOEFFECTNo effect 1 | PCR_CLRClears the interrupt flag" "0,1" newline bitfld.word 0x0 6. "PCO,Clear position counter overflow interrupt flag 0 | PCO_NOEFFECTNo effect 1 | PCO_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 5. "PCU,Clear position counter underflow interrupt flag 0 | PCU_NOEFFECTNo effect 1 | PCU_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 4. "WTO,Clear watchdog timeout interrupt flag 0 | WTO_NOEFFECTNo effect 1 | WTO_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 3. "QDC,Clear quadrature direction change interrupt flag 0 | QDC_NOEFFECTNo effect 1 | QDC_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 2. "PHE,Clear quadrature phase error interrupt flag 0 | PHE_NOEFFECTNo effect 1 | PHE_CLRClears the interrupt flag" "0,1" bitfld.word 0x0 1. "PCE,Clear position counter error interrupt flag 0 | PCE_NOEFFECTNo effect 1 | PCE_CLRClears the interrupt flag" "0,1" newline bitfld.word 0x0 0. "INT,Global interrupt clear flag 0 | INT_NOEFFECTNo effect 1 | INT_CLRClears the interrupt flag" "0,1" line.word 0x2 "CONTROLSS_EQEP2_QFRC" bitfld.word 0x2 12. "QMAE,Force QMA error interrupt 0 | QMAE_NOEFFECTNo effect 1 | QMAE_FORCEForce the interrupt" "0,1" bitfld.word 0x2 11. "UTO,Force unit time out interrupt 0 | UTO_NOEFFECTNo effect 1 | UTO_FORCEForce the interrupt" "0,1" bitfld.word 0x2 10. "IEL,Force index event latch interrupt 0 | IEL_NOEFFECTNo effect 1 | IEL_FORCEForce the interrupt" "0,1" bitfld.word 0x2 9. "SEL,Force strobe event latch interrupt 0 | SEL_NOEFFECTNo effect 1 | SEL_FORCEForce the interrupt" "0,1" bitfld.word 0x2 8. "PCM,Force position-compare match interrupt 0 | PCM_NOEFFECTNo effect 1 | PCM_FORCEForce the interrupt" "0,1" bitfld.word 0x2 7. "PCR,Force position-compare ready interrupt 0 | PCR_NOEFFECTNo effect 1 | PCR_FORCEForce the interrupt" "0,1" newline bitfld.word 0x2 6. "PCO,Force position counter overflow interrupt 0 | PCO_NOEFFECTNo effect 1 | PCO_FORCEForce the interrupt" "0,1" bitfld.word 0x2 5. "PCU,Force position counter underflow interrupt 0 | PCU_NOEFFECTNo effect 1 | PCU_FORCEForce the interrupt" "0,1" bitfld.word 0x2 4. "WTO,Force watchdog time out interrupt 0 | WTO_NOEFFECTNo effect 1 | WTO_FORCEForce the interrupt" "0,1" bitfld.word 0x2 3. "QDC,Force quadrature direction change interrupt 0 | QDC_NOEFFECTNo effect 1 | QDC_FORCEForce the interrupt" "0,1" bitfld.word 0x2 2. "PHE,Force quadrature phase error interrupt 0 | PHE_NOEFFECTNo effect 1 | PHE_FORCEForce the interrupt" "0,1" bitfld.word 0x2 1. "PCE,Force position counter error interrupt 0 | PCE_NOEFFECTNo effect 1 | PCE_FORCEForce the interrupt" "0,1" line.word 0x4 "CONTROLSS_EQEP2_QEPSTS" bitfld.word 0x4 7. "UPEVNT,Unit position event flag 0 | UPEVNT_NODETCTNo unit position event detected 1 | UPEVNT_DETCTUnit position event detected. Write 1 to clear" "0,1" rbitfld.word 0x4 6. "FIDF,Direction on the first index marker Status of the direction is latched on the first index event marker. Read0 | FIDF_COUNTERCLKCounter-clockwise rotation (or reverse movement) on the first index event Read1 | FIDF_CLKClockwise.." "0,1" rbitfld.word 0x4 5. "QDF,Quadrature direction flag Read0 | QDF_COUNTERCLKCounter-clockwise rotation (or reverse movement) Read1 | QDF_CLKClockwise rotation (or forward movement)" "0,1" rbitfld.word 0x4 4. "QDLF,eQEP direction latch flag Read0 | QDLF_COUNTERCLKCounter-clockwise rotation (or reverse movement) on index event marker Read1 | QDLF_CLKClockwise rotation (or forward movement) on index event marker" "0,1" bitfld.word 0x4 3. "COEF,Capture overflow error flag 0 | COEF_WRT1Overflow has not occurred. 1 | COEF_OVFOverflow occurred in eQEP Capture timer (QEPCTMR). This bit is cleared by writing a '1'." "0,1" bitfld.word 0x4 2. "CDEF,Capture direction error flag 0 | CDEF_WRT1Capture direction error has not occurred. 1 | CDEF_DIRECTDirection change occurred between the capture position event. This bit is cleared by writing a '1'." "0,1" newline bitfld.word 0x4 1. "FIMF,First index marker flag 0 | FIMF_WRT1First index pulse has not occurred. 1 | FIMF_SETINDEXSet by first occurrence of index pulse. This bit is cleared by writing a '1'." "0,1" rbitfld.word 0x4 0. "PCEF,Position counter error flag. This bit is not sticky and it is updated for every index event. Read0 | PCEF_NOERRORNo error occurred during the last index transition Read1 | PCEF_ERRORPosition counter error" "0,1" line.word 0x6 "CONTROLSS_EQEP2_QCTMR" hexmask.word 0x6 0.--15. 1. "QCTMR,This register provides time base for edge capture unit." line.word 0x8 "CONTROLSS_EQEP2_QCPRD" hexmask.word 0x8 0.--15. 1. "QCPRD,This register holds the period count value between the last successive eQEP position events" rgroup.word 0x3E++0x3 line.word 0x0 "CONTROLSS_EQEP2_QCTMRLAT" hexmask.word 0x0 0.--15. 1. "QCTMRLAT,The eQEP capture timer value can be latched into this register on two events viz. unit timeout event reading the eQEP position counter." line.word 0x2 "CONTROLSS_EQEP2_QCPRDLAT" hexmask.word 0x2 0.--15. 1. "QCPRDLAT,eQEP capture period value can be latched into this register on two events viz. unit timeout event reading the eQEP position counter." rgroup.long 0x60++0x3 line.long 0x0 "CONTROLSS_EQEP2_REV" bitfld.long 0x0 3.--5. "MINOR,This field specifies the Minor Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "MAJOR,This field specifies the Major Revision number for the eQEP IP." "0,1,2,3,4,5,6,7" group.long 0x64++0xB line.long 0x0 "CONTROLSS_EQEP2_QEPSTROBESEL" bitfld.long 0x0 0.--1. "STROBESEL,Strobe source select: 0x0 | QS_AFTER_POL_MUXQEP Strobe after polarity mux 0x1 | QS_AFTER_POL_MUXQEP Strobe after polarity mux 0x2 | ADCSOCA_AS_QSQEP Strobe after polarity mux ORed with ADCSOCA 0x3 |.." "0,1,2,3" line.long 0x4 "CONTROLSS_EQEP2_QMACTRL" bitfld.long 0x4 0.--2. "MODE,Select Mode for QMA mode: 000 : QMA Module is bypassed. 001 : QMA Mode-1 operation selected 010 : QMA Mode-2 operation selected 011 : QMA Module is bypassed (reserved) 1xx : QMA Module is bypassed (reserved)" "0: QMA Module is bypassed,1: QMA Mode-1 operation selected,?,?,?,?,?,?" line.long 0x8 "CONTROLSS_EQEP2_QEPSRCSEL" hexmask.long.byte 0x8 24.--28. 1. "QEPSSEL,QEP Strobe source select: 0x0: Device Pin (Default) 0x1 to 0x1F : To be defined in SOC context Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." hexmask.long.byte 0x8 16.--20. 1. "QEPISEL,QEP Index source select: 0x0: Device Pin (Default) 0x1 to 0x1F : To be defined in SOC context Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." hexmask.long.byte 0x8 8.--12. 1. "QEPBSEL,QEPB source select: 0x0: Device Pin (Default) 0x1 to 0x1F : To be defined in SOC context Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." hexmask.long.byte 0x8 0.--4. 1. "QEPASEL,QEPA source select: 0x0: Device Pin (Default) 0x1 to 0x1F : To be defined in SOC context Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running." tree.end tree.end tree "FSI" tree "FSI0" tree "FSI0_RX0" base ad:0x50290000 group.word 0x0++0x1 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_MASTER_CTRL_ALTC_" hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x0 4. "DATA_FILTER_EN,Data Filter Enable Bit. 0h (R/W) = Data filtering is disabled. 1h (R/W) = Data filtering is enabled." "0,1" bitfld.word 0x0 3. "INPUT_ISOLATE,When set to 1 the FSI RX inputs (RXCLK RXD0 and RXD1) will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of.." "0,1" newline bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behavior Enable bit This bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module acting as a SPI master to clock data into the.." "0,1" bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable bit This bit enables the internal loopback functionality of the FSI receiver. By enabling this bit a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset bit This bit controls the receiver master core reset. In order to receive any frame this bit must be cleared. Note: For reset to take affect the FSI RX module must be held in reset for at least 4 SYSCLK cycles. 0h.." "0,1" group.word 0x8++0x1 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_OPER_CTRL" bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select bit This bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame. 0h (R/W) = The ping watchdog.." "0,1" bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select bit This bit selects between whether the ECC computation is done on 16-bit or 32-bit words. 0h (R/W) = 32-bit ECC is used. 1h (R/W) = 16-bit ECC is used." "0,1" hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to Receive This field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the.." newline bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable bit This bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive.." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select bit These bits decide the number of data lines used for receiving data. 0h (R/W) = Data will be received on one data line RXD0. 1h (R/W) = Data will be received on two data lines RXD0 and RXD1. 2h 3h (R/W) =.." "0,1,2,3" rgroup.word 0xC++0x3 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_FRAME_INFO" hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type This field indicates the type of frame that was successfully received last. 0000b (R/W) = A ping frame was received 0100b (R/W) = A DATA_1_WORD frame was received (16-bit data). 0101b (R/W) = A DATA_2_WORD frame was.." line.word 0x2 "CONTROLSS_FSI0_RX0_RX_FRAME_TAG_UDATA" hexmask.word.byte 0x2 8.--15. 1. "USER_DATA,Received User Data This field contains the 8-bit user data field of the last successfully received frame." hexmask.word.byte 0x2 1.--4. 1. "FRAME_TAG,Received Frame Tag This field contains the 4-bit frame tag from the last successfully received frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x2 0. "RESERVED,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the FRAME_TAG and ZERO bits of this register (bits 4:0) application software can directly index into an array of 32-bit data." "0,1" group.word 0x10++0x1 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_DMA_CTRL" bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable a DMA Event to be generated upon the completion of a frame reception. 0h (R/W) = A DMA event will not be generated. 1h (R/W) = A DMA event will be generated upon the reception of a frame. Note: The.." "0,1" rgroup.word 0x14++0x3 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_EVT_STS_ALT1_" bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag This bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag This bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No tag-matched.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag This bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No tag-matched.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag This bit indicates that an data frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No data frame has been received. 1h (R) = A data frame has been.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag This bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag This bit indicates that an ping frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No ping frame has been received. 1h (R) = A ping frame has been.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag This bit indicates that an error frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No error frame has been received. 1h (R) = An error frame has been.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag This bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag This bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No frame has been successfully received. 1h (R) = A.." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag This bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Receive buffer overrun has not.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag This bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Invalid end-of-frame has not been received. 1h.." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag This bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Invalid frame type has not been received. 1h (R) = Invalid.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag This bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by writing to the RX_EVT_FRC.." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag This bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Frame watchdog timeout has not occured. 1h (R) = Frame.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag This bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Ping watchdog timeout has not occured. 1h (R) = Ping.." "0,1" line.word 0x2 "CONTROLSS_FSI0_RX0_RX_CRC_INFO" hexmask.word.byte 0x2 8.--15. 1. "CALC_CRC,Harware Calculated CRC Value This bitfield contains the CRC value that was calculated on the last received data. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for.." hexmask.word.byte 0x2 0.--7. 1. "RX_CRC,Received CRC Value This bitfield contains the CRC value that was last received a frame. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping and error frames." wgroup.word 0x18++0x3 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_EVT_CLR_ALT1_" bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Glag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (R/W) = Writing a 0 to this bit will have no effect. 1h (R/W) = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" line.word 0x2 "CONTROLSS_FSI0_RX0_RX_EVT_FRC_ALT1_" bitfld.word 0x2 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 13. "DATA_TAG_MATCH,Data Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 12. "PING_TAG_MATCH,Ping Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" newline bitfld.word 0x2 11. "DATA_FRAME,Data Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 10. "FRAME_OVERRUN,Frame Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 9. "PING_FRAME,Ping Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" newline bitfld.word 0x2 8. "ERR_FRAME,Error Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 6. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W) =.." "0,1" newline bitfld.word 0x2 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 4. "EOF_ERR,End-of-Frame Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W).." "0,1" bitfld.word 0x2 3. "TYPE_ERR,Frame Type Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W).." "0,1" newline bitfld.word 0x2 2. "CRC_ERR,CRC Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W) =.." "0,1" bitfld.word 0x2 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_BUF_PTR_LOAD" hexmask.word.byte 0x0 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load. This is the value to be loaded into the receive word pointer when written. This is to allow software to force the receiver to start storing the received data starting at a specific location in the buffer. NOTE: The.." rgroup.word 0x1E++0x1 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_BUF_PTR_STS" hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Available in the Receive Buffer This bitfield indicates the number of valid data words present in the receive buffer that have not been read by the application software. This bitfield is only valid when there is no active transfer." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x20++0x1 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_FRAME_WD_CTRL" bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable bit This bit will enable or disable the frame watchdog counter. The counter (RX_FRAME_WD_CNT) will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value (RX_FRAME_WD_REF).." "0,1" bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset bit This bit will reset the frame watchdog counter to 0. Writing a 1 to this bit will reset the frame watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to.." "0,1" group.long 0x24++0x3 line.long 0x0 "CONTROLSS_FSI0_RX0_RX_FRAME_WD_REF" hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value This is the 32-bit reference value for the frame watchdog timeout counter. The counter will count up starting from 0 at a valid start-of-frame pattern and continue counting until this value is reached." rgroup.long 0x28++0x3 line.long 0x0 "CONTROLSS_FSI0_RX0_RX_FRAME_WD_CNT" hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the frame watchdog counter. This counter is reset to 0 in a variety of ways: A write to FRME_WD_CNT_RST a match with FRAME_WD_REF or the.." group.word 0x2C++0x1 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_PING_WD_CTRL" bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable bit This bit will enable or disable the ping watchdog counter. The counter (RX_PING_WD_CNT) will begin counting from 0 when it is enabled. When the reference value (RX_PING_WD_REF) is reached it will generate a.." "0,1" bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset bit This bit will reset the ping watchdog counter to 0. Writing a 1 to this bit will reset the ping watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be.." "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_PING_TAG" hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Received Ping Frame Tag This field contains the 4-bit frame tag from the last successfully received ping frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x0 0. "RESERVED,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the PING_TAG and ZERO bits of this register (bits 4:0) application software can directly index into an array of 32-bit data." "0,1" group.long 0x30++0x3 line.long 0x0 "CONTROLSS_FSI0_RX0_RX_PING_WD_REF" hexmask.long 0x0 0.--31. 1. "PING_WD_REF,Ping Watchdog Counter Reference Value This is the 32-bit reference value for the ping watchdog timeout counter. The counter will count up starting from 0 and continue counting until this value is reached." rgroup.long 0x34++0x3 line.long 0x0 "CONTROLSS_FSI0_RX0_RX_PING_WD_CNT" hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the ping watchdog counter. This counter is reset to 0 in a variety of ways: A write to PING_WD_RST a match with PING_WD_REF or the reception.." group.word 0x38++0x5 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_INT1_CTRL_ALT1_" bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt.." "0,1" bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A.." "0,1" bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" newline bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable ERROR Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A.." "0,1" bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A frame.." "0,1" newline bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = An.." "0,1" bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A.." "0,1" newline bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A CRC error.." "0,1" bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h.." "0,1" bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h.." "0,1" line.word 0x2 "CONTROLSS_FSI0_RX0_RX_INT2_CTRL_ALT1_" bitfld.word 0x2 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt.." "0,1" bitfld.word 0x2 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x2 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x2 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W).." "0,1" bitfld.word 0x2 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" bitfld.word 0x2 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W).." "0,1" newline bitfld.word 0x2 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W).." "0,1" bitfld.word 0x2 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" bitfld.word 0x2 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A frame.." "0,1" newline bitfld.word 0x2 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" bitfld.word 0x2 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = An.." "0,1" bitfld.word 0x2 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" newline bitfld.word 0x2 2. "INT2_EN_CRC_ERR,Enable CRC Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A CRC error.." "0,1" bitfld.word 0x2 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h.." "0,1" bitfld.word 0x2 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h.." "0,1" line.word 0x4 "CONTROLSS_FSI0_RX0_RX_LOCK_CTRL" hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the receive control registers that support a lock protection. Once locked further writes will not take effect until SYSRS unlocks the register. Once set further writes even to.." "0,1" group.long 0x40++0x3 line.long 0x0 "CONTROLSS_FSI0_RX0_RX_ECC_DATA" hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." group.word 0x44++0x1 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_ECC_VAL" hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,ECC Value for SEC-DED check This field contains the ECC value to be used for SEC-DED either for 16-bit or 32-bit data in the RX_ECC_DATA register." rgroup.long 0x48++0x3 line.long 0x0 "CONTROLSS_FSI0_RX0_RX_ECC_SEC_DATA" hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data The ECC corrected data will be available in this register. This value is valid only when there are no bit errors or a single bit error was detected. Otherwise the contents of this register are invalid and should.." rgroup.word 0x4C++0x1 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_ECC_LOG" bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected This bit indicates the occurrence of multiple bit errors.The data is corrupted and cannot be corrected. If this bit is set the data present in RX_ECC_SEC_DATA is invalid and should not be used. 0h (R) Multiple Bit.." "0,1" bitfld.word 0x0 0. "SBE,Single Bit Error Detected This bit indicates the occurrence of a single bit error in the data. The data is autocorrected and placed into the RX_ECC_SEC_DATA register. This bit is valid only if MBE is 0. 0h (R) No bit errors were detected. The value.." "0,1" group.word 0x50++0x3 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_FRAME_TAG_CMP" bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable bit Set this bit to enable the comparison of an incoming frame tag and the value stored in the frame tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming frame tag will trigger the.." "0,1" hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only for.." newline hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming frame tag. This reference value is used only for non-ping frames." line.word 0x2 "CONTROLSS_FSI0_RX0_RX_PING_TAG_CMP" bitfld.word 0x2 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x2 8. "CMP_EN,Ping Tag Compare Enable bit Set this bit to enable the comparison of an incoming ping tag and the value stored in the ping tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming ping tag will trigger a ping frame.." "0,1" hexmask.word.byte 0x2 4.--7. 1. "TAG_MASK,Ping Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming ping frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only.." newline hexmask.word.byte 0x2 0.--3. 1. "TAG_REF,Ping Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming ping tag. This reference value is used only for ping frames." group.long 0x58++0x7 line.long 0x0 "CONTROLSS_FSI0_RX0_RX_TRIG_CTRL_0" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "CONTROLSS_FSI0_RX0_RX_TRIG_WIDTH_0" hexmask.long.word 0x4 0.--15. 1. "RX_TRIG_WIDTH,This register decides the width(in SYSCLK cycles) of wide pulse output of the RX trigger module." group.word 0x60++0x1 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_DLYLINE_CTRL" hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1 This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the RXD1 path. RXD1 is taken directly from.." hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0 This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the RXD0 path. RXD0 is taken directly from.." hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the RXCLK path. RXCLK is taken directly.." group.long 0x64++0xB line.long 0x0 "CONTROLSS_FSI0_RX0_RX_TRIG_CTRL_1" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "CONTROLSS_FSI0_RX0_RX_TRIG_CTRL_2" hexmask.long.tbyte 0x4 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x4 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x4 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x8 "CONTROLSS_FSI0_RX0_RX_TRIG_CTRL_3" hexmask.long.tbyte 0x8 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x8 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x8 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" rgroup.long 0x70++0x3 line.long 0x0 "CONTROLSS_FSI0_RX0_RX_VIS_1" bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status bit This bit indicates the status of the receiver core. If this bit is set the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has.." "0,1" group.word 0x74++0x1 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_UDATA_FILTER" hexmask.word.byte 0x0 8.--15. 1. "UDATA_MASK,Bit Mask to be used for comparing the USERDATA field when filtering is enabled. Every bit that is '1' in this register will be masked for comparison. If a bit position is '1' then it will be considered a successful match for that bit position." hexmask.word.byte 0x0 0.--7. 1. "UDATA_REG,Reference to be used for comparing the USERDATA field when filtering is enabled." rgroup.word 0x80++0x1 line.word 0x0 "CONTROLSS_FSI0_RX0_RX_BUF_BASE" hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address This is the base address of the 16-word data buffer used by the receiver." tree.end tree "FSI0_RX1" base ad:0x50291000 group.word 0x0++0x1 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_MASTER_CTRL_ALTC_" hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x0 4. "DATA_FILTER_EN,Data Filter Enable Bit. 0h (R/W) = Data filtering is disabled. 1h (R/W) = Data filtering is enabled." "0,1" bitfld.word 0x0 3. "INPUT_ISOLATE,When set to 1 the FSI RX inputs (RXCLK RXD0 and RXD1) will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of.." "0,1" newline bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behavior Enable bit This bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module acting as a SPI master to clock data into the.." "0,1" bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable bit This bit enables the internal loopback functionality of the FSI receiver. By enabling this bit a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset bit This bit controls the receiver master core reset. In order to receive any frame this bit must be cleared. Note: For reset to take affect the FSI RX module must be held in reset for at least 4 SYSCLK cycles. 0h.." "0,1" group.word 0x8++0x1 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_OPER_CTRL" bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select bit This bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame. 0h (R/W) = The ping watchdog.." "0,1" bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select bit This bit selects between whether the ECC computation is done on 16-bit or 32-bit words. 0h (R/W) = 32-bit ECC is used. 1h (R/W) = 16-bit ECC is used." "0,1" hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to Receive This field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the.." newline bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable bit This bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive.." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select bit These bits decide the number of data lines used for receiving data. 0h (R/W) = Data will be received on one data line RXD0. 1h (R/W) = Data will be received on two data lines RXD0 and RXD1. 2h 3h (R/W) =.." "0,1,2,3" rgroup.word 0xC++0x3 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_FRAME_INFO" hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type This field indicates the type of frame that was successfully received last. 0000b (R/W) = A ping frame was received 0100b (R/W) = A DATA_1_WORD frame was received (16-bit data). 0101b (R/W) = A DATA_2_WORD frame was.." line.word 0x2 "CONTROLSS_FSI0_RX1_RX_FRAME_TAG_UDATA" hexmask.word.byte 0x2 8.--15. 1. "USER_DATA,Received User Data This field contains the 8-bit user data field of the last successfully received frame." hexmask.word.byte 0x2 1.--4. 1. "FRAME_TAG,Received Frame Tag This field contains the 4-bit frame tag from the last successfully received frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x2 0. "RESERVED,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the FRAME_TAG and ZERO bits of this register (bits 4:0) application software can directly index into an array of 32-bit data." "0,1" group.word 0x10++0x1 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_DMA_CTRL" bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable a DMA Event to be generated upon the completion of a frame reception. 0h (R/W) = A DMA event will not be generated. 1h (R/W) = A DMA event will be generated upon the reception of a frame. Note: The.." "0,1" rgroup.word 0x14++0x3 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_EVT_STS_ALT1_" bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag This bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag This bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No tag-matched.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag This bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No tag-matched.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag This bit indicates that an data frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No data frame has been received. 1h (R) = A data frame has been.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag This bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag This bit indicates that an ping frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No ping frame has been received. 1h (R) = A ping frame has been.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag This bit indicates that an error frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No error frame has been received. 1h (R) = An error frame has been.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag This bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag This bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No frame has been successfully received. 1h (R) = A.." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag This bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Receive buffer overrun has not.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag This bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Invalid end-of-frame has not been received. 1h.." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag This bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Invalid frame type has not been received. 1h (R) = Invalid.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag This bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by writing to the RX_EVT_FRC.." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag This bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Frame watchdog timeout has not occured. 1h (R) = Frame.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag This bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Ping watchdog timeout has not occured. 1h (R) = Ping.." "0,1" line.word 0x2 "CONTROLSS_FSI0_RX1_RX_CRC_INFO" hexmask.word.byte 0x2 8.--15. 1. "CALC_CRC,Harware Calculated CRC Value This bitfield contains the CRC value that was calculated on the last received data. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for.." hexmask.word.byte 0x2 0.--7. 1. "RX_CRC,Received CRC Value This bitfield contains the CRC value that was last received a frame. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping and error frames." wgroup.word 0x18++0x3 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_EVT_CLR_ALT1_" bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Glag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (R/W) = Writing a 0 to this bit will have no effect. 1h (R/W) = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" line.word 0x2 "CONTROLSS_FSI0_RX1_RX_EVT_FRC_ALT1_" bitfld.word 0x2 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 13. "DATA_TAG_MATCH,Data Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 12. "PING_TAG_MATCH,Ping Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" newline bitfld.word 0x2 11. "DATA_FRAME,Data Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 10. "FRAME_OVERRUN,Frame Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 9. "PING_FRAME,Ping Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" newline bitfld.word 0x2 8. "ERR_FRAME,Error Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 6. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W) =.." "0,1" newline bitfld.word 0x2 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 4. "EOF_ERR,End-of-Frame Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W).." "0,1" bitfld.word 0x2 3. "TYPE_ERR,Frame Type Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W).." "0,1" newline bitfld.word 0x2 2. "CRC_ERR,CRC Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W) =.." "0,1" bitfld.word 0x2 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_BUF_PTR_LOAD" hexmask.word.byte 0x0 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load. This is the value to be loaded into the receive word pointer when written. This is to allow software to force the receiver to start storing the received data starting at a specific location in the buffer. NOTE: The.." rgroup.word 0x1E++0x1 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_BUF_PTR_STS" hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Available in the Receive Buffer This bitfield indicates the number of valid data words present in the receive buffer that have not been read by the application software. This bitfield is only valid when there is no active transfer." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x20++0x1 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_FRAME_WD_CTRL" bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable bit This bit will enable or disable the frame watchdog counter. The counter (RX_FRAME_WD_CNT) will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value (RX_FRAME_WD_REF).." "0,1" bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset bit This bit will reset the frame watchdog counter to 0. Writing a 1 to this bit will reset the frame watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to.." "0,1" group.long 0x24++0x3 line.long 0x0 "CONTROLSS_FSI0_RX1_RX_FRAME_WD_REF" hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value This is the 32-bit reference value for the frame watchdog timeout counter. The counter will count up starting from 0 at a valid start-of-frame pattern and continue counting until this value is reached." rgroup.long 0x28++0x3 line.long 0x0 "CONTROLSS_FSI0_RX1_RX_FRAME_WD_CNT" hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the frame watchdog counter. This counter is reset to 0 in a variety of ways: A write to FRME_WD_CNT_RST a match with FRAME_WD_REF or the.." group.word 0x2C++0x1 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_PING_WD_CTRL" bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable bit This bit will enable or disable the ping watchdog counter. The counter (RX_PING_WD_CNT) will begin counting from 0 when it is enabled. When the reference value (RX_PING_WD_REF) is reached it will generate a.." "0,1" bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset bit This bit will reset the ping watchdog counter to 0. Writing a 1 to this bit will reset the ping watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be.." "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_PING_TAG" hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Received Ping Frame Tag This field contains the 4-bit frame tag from the last successfully received ping frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x0 0. "RESERVED,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the PING_TAG and ZERO bits of this register (bits 4:0) application software can directly index into an array of 32-bit data." "0,1" group.long 0x30++0x3 line.long 0x0 "CONTROLSS_FSI0_RX1_RX_PING_WD_REF" hexmask.long 0x0 0.--31. 1. "PING_WD_REF,Ping Watchdog Counter Reference Value This is the 32-bit reference value for the ping watchdog timeout counter. The counter will count up starting from 0 and continue counting until this value is reached." rgroup.long 0x34++0x3 line.long 0x0 "CONTROLSS_FSI0_RX1_RX_PING_WD_CNT" hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the ping watchdog counter. This counter is reset to 0 in a variety of ways: A write to PING_WD_RST a match with PING_WD_REF or the reception.." group.word 0x38++0x5 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_INT1_CTRL_ALT1_" bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt.." "0,1" bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A.." "0,1" bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" newline bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable ERROR Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A.." "0,1" bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A frame.." "0,1" newline bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = An.." "0,1" bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A.." "0,1" newline bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A CRC error.." "0,1" bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h.." "0,1" bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h.." "0,1" line.word 0x2 "CONTROLSS_FSI0_RX1_RX_INT2_CTRL_ALT1_" bitfld.word 0x2 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt.." "0,1" bitfld.word 0x2 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x2 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x2 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W).." "0,1" bitfld.word 0x2 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" bitfld.word 0x2 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W).." "0,1" newline bitfld.word 0x2 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W).." "0,1" bitfld.word 0x2 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" bitfld.word 0x2 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A frame.." "0,1" newline bitfld.word 0x2 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" bitfld.word 0x2 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = An.." "0,1" bitfld.word 0x2 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" newline bitfld.word 0x2 2. "INT2_EN_CRC_ERR,Enable CRC Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A CRC error.." "0,1" bitfld.word 0x2 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h.." "0,1" bitfld.word 0x2 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h.." "0,1" line.word 0x4 "CONTROLSS_FSI0_RX1_RX_LOCK_CTRL" hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the receive control registers that support a lock protection. Once locked further writes will not take effect until SYSRS unlocks the register. Once set further writes even to.." "0,1" group.long 0x40++0x3 line.long 0x0 "CONTROLSS_FSI0_RX1_RX_ECC_DATA" hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." group.word 0x44++0x1 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_ECC_VAL" hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,ECC Value for SEC-DED check This field contains the ECC value to be used for SEC-DED either for 16-bit or 32-bit data in the RX_ECC_DATA register." rgroup.long 0x48++0x3 line.long 0x0 "CONTROLSS_FSI0_RX1_RX_ECC_SEC_DATA" hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data The ECC corrected data will be available in this register. This value is valid only when there are no bit errors or a single bit error was detected. Otherwise the contents of this register are invalid and should.." rgroup.word 0x4C++0x1 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_ECC_LOG" bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected This bit indicates the occurrence of multiple bit errors.The data is corrupted and cannot be corrected. If this bit is set the data present in RX_ECC_SEC_DATA is invalid and should not be used. 0h (R) Multiple Bit.." "0,1" bitfld.word 0x0 0. "SBE,Single Bit Error Detected This bit indicates the occurrence of a single bit error in the data. The data is autocorrected and placed into the RX_ECC_SEC_DATA register. This bit is valid only if MBE is 0. 0h (R) No bit errors were detected. The value.." "0,1" group.word 0x50++0x3 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_FRAME_TAG_CMP" bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable bit Set this bit to enable the comparison of an incoming frame tag and the value stored in the frame tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming frame tag will trigger the.." "0,1" hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only for.." newline hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming frame tag. This reference value is used only for non-ping frames." line.word 0x2 "CONTROLSS_FSI0_RX1_RX_PING_TAG_CMP" bitfld.word 0x2 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x2 8. "CMP_EN,Ping Tag Compare Enable bit Set this bit to enable the comparison of an incoming ping tag and the value stored in the ping tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming ping tag will trigger a ping frame.." "0,1" hexmask.word.byte 0x2 4.--7. 1. "TAG_MASK,Ping Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming ping frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only.." newline hexmask.word.byte 0x2 0.--3. 1. "TAG_REF,Ping Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming ping tag. This reference value is used only for ping frames." group.long 0x58++0x7 line.long 0x0 "CONTROLSS_FSI0_RX1_RX_TRIG_CTRL_0" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "CONTROLSS_FSI0_RX1_RX_TRIG_WIDTH_0" hexmask.long.word 0x4 0.--15. 1. "RX_TRIG_WIDTH,This register decides the width(in SYSCLK cycles) of wide pulse output of the RX trigger module." group.word 0x60++0x1 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_DLYLINE_CTRL" hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1 This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the RXD1 path. RXD1 is taken directly from.." hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0 This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the RXD0 path. RXD0 is taken directly from.." hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the RXCLK path. RXCLK is taken directly.." group.long 0x64++0xB line.long 0x0 "CONTROLSS_FSI0_RX1_RX_TRIG_CTRL_1" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "CONTROLSS_FSI0_RX1_RX_TRIG_CTRL_2" hexmask.long.tbyte 0x4 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x4 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x4 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x8 "CONTROLSS_FSI0_RX1_RX_TRIG_CTRL_3" hexmask.long.tbyte 0x8 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x8 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x8 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" rgroup.long 0x70++0x3 line.long 0x0 "CONTROLSS_FSI0_RX1_RX_VIS_1" bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status bit This bit indicates the status of the receiver core. If this bit is set the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has.." "0,1" group.word 0x74++0x1 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_UDATA_FILTER" hexmask.word.byte 0x0 8.--15. 1. "UDATA_MASK,Bit Mask to be used for comparing the USERDATA field when filtering is enabled. Every bit that is '1' in this register will be masked for comparison. If a bit position is '1' then it will be considered a successful match for that bit position." hexmask.word.byte 0x0 0.--7. 1. "UDATA_REG,Reference to be used for comparing the USERDATA field when filtering is enabled." rgroup.word 0x80++0x1 line.word 0x0 "CONTROLSS_FSI0_RX1_RX_BUF_BASE" hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address This is the base address of the 16-word data buffer used by the receiver." tree.end tree "FSI0_TX0" base ad:0x50280000 group.word 0x0++0x1 line.word 0x0 "CONTROLSS_FSI0_TX0_TX_MASTER_CTRL" hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key In order to write to any bit in this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x0 1. "FLUSH,Flush Operation Start bit This bit will cause the transmitter to initiate a flush pattern of a single toggle on the TXD0 and TXD1 followed by five full cycles of TXCLK. This bit should be written only when the CORE_RST bit is 0 and the clock to the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Transmitter Master Core Reset bit This bit controls the transmitter master core reset. In order to send any frame this bit must be cleared. 0h (R/W) = Transmitter core is not in reset and can transmit frames. 1h (R/W) = Transmitter core is.." "0,1" group.word 0x4++0x1 line.word 0x0 "CONTROLSS_FSI0_TX0_TX_CLK_CTRL" hexmask.word.byte 0x0 2.--9. 1. "PRESCALE_VAL,Clock Divider Prescale Value The input clock is divided by this 8-bit value and fed into the transmitter core. This divided clock is the rate at which TXCLK will operate. 0h (R/W) = Reserved 1h (R/W) = Input clock /1 2h (R/W) = Input clock.." bitfld.word 0x0 1. "CLK_EN,Clock Divider Enable bit This bit will enable and disable the input clock divider and start the clock to the transmitter core. 0h (R/W) = The input clock divider is not enabled and the clock is not connected to the transmitter core. 1h (R/W) =.." "0,1" bitfld.word 0x0 0. "CLK_RST,Clock Divider Reset bit This bit will reset the clock counter in the clock divider. 0h (R/W) = The clock divider is set based on the value in PRESCALE_VAL. The input clock will be divided by PRESCALE_VAL if CLK_EN is set. 1h (R/W) = The clock.." "0,1" group.word 0x8++0x9 line.word 0x0 "CONTROLSS_FSI0_TX0_TX_OPER_CTRL_LO_ALT2_" bitfld.word 0x0 10. "SEL_TDM_IN,Input TDM port Select bit This bit selects the input port for the transmitter core between the TDM input pins or the RX module. When this bit is '0' the inputs selected for TDM are from the TDM input pins. When this bit is '1' then inputs.." "0,1" bitfld.word 0x0 9. "TDM_ENABLE,Transmit TDM Mode Enable bit. This bit enables the TDM Mode for multi-slave TDM operation. 0h (R/W) Transmit TDM Mode is not enabled. 1h (R/W) Transmit TDM Mode is enabled." "0,1" bitfld.word 0x0 8. "SEL_PLLCLK,Input Clock Select bit This bit selects the input clock source for the transmitter core. 0h (R/W) = SYSCLK is the source of the transmitter clock into the clock prescaler. 1h (R/W) = PLLRAWCLK is the source of the transmitter core clock into.." "0,1" bitfld.word 0x0 7. "PING_TO_MODE,Ping Counter Reset Mode Select bit This bit selects when the ping counter will reset. 0h (R/W) = The ping counter will reset and restart only on hardware initiated ping frames when ping counter has timed out. 1h (R/W) = The ping counter.." "0,1" newline bitfld.word 0x0 6. "SW_CRC,CRC Source Select bit This bit selects the source of the CRC value that is transmitted. 0h (R/W) = The transmitted CRC value is computed by hardware. 1h (R/W) = The transmitted CRC value is sourced from the value programmed in the TX_USER_CRC.." "0,1" bitfld.word 0x0 3.--5. "START_MODE,Transmission Start Mode Select bit These bits select the method by which a new frame transmission is started. 0h (R/W) = Only a software write to TX_FRAME_CTRL.START initiate a new transmission. 1h (R/W) = The configured external trigger will.." "0,1,2,3,4,5,6,7" bitfld.word 0x0 2. "SPI_MODE,SPI Mode Select bit This bit enables and disables SPI compatibility mode. 0h (R/W) = FSI is in normal mode of operation. 1h (R/W) = FSI is operating in SPI compatibility mode." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Transmit Data Width Select bits These bits define the number of data lines used by the transmitter. 0h (R/W) = Data will be transmitted on one data line (TXD0) 1h (R/W) = Data will be transmitted on two data lines (TXD0 and TXD1). The format.." "0,1,2,3" line.word 0x2 "CONTROLSS_FSI0_TX0_TX_OPER_CTRL_HI_ALT1_" hexmask.word.byte 0x2 7.--12. 1. "EXT_TRIG_SEL,External Trigger Select bit These bits define which of the 64 external inputs will be used as the source for the external input trigger. 00h (R/W) = Trigger 1 is the source. 01h (R/W) = Trigger 2 is the source. 02h (R/W) = Trigger 3 is the.." bitfld.word 0x2 6. "ECC_SEL,ECC Data Width Select bit This bit selects between 16-bit and 32-bit ECC computation. 0h (R/W) = 32-bit ECC is used. 1h (R/W) = 16-bit ECC is used." "0,1" bitfld.word 0x2 5. "FORCE_ERR,Error Frame Force bit This bit will force the the CRC value of the transmitted data frame to 0 whenever there is a buffer overrun or underrun condition. This can be used to force a corrupted CRC as the data is not guaranteed to be reliable. The.." "0,1" line.word 0x4 "CONTROLSS_FSI0_TX0_TX_FRAME_CTRL" bitfld.word 0x4 15. "START,Start Transmission bit This bit will cause the FSI to start transmitting the next frame. 0h (R/W) = Writing a 0 to this bit will have no effect. 1h (R/W) = Start the next transmission. This bit will be cleared by hardware." "0,1" hexmask.word.byte 0x4 4.--7. 1. "N_WORDS,Number of Words to be Transmitted This field defines the number of words which will be transmitted in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the receiver. Set this bitfield to be one less than.." hexmask.word.byte 0x4 0.--3. 1. "FRAME_TYPE,Transmit Frame Type This field determines the type of frame that will be transmitted next. 0000b (R/W) = Ping Frame. This frame can be sent either by software or automatically by hardware. 0100b (R/W) = DATA_1_WORD Frame. One word data frame.." line.word 0x6 "CONTROLSS_FSI0_TX0_TX_FRAME_TAG_UDATA" hexmask.word.byte 0x6 8.--15. 1. "USER_DATA,User Data bits This is a user-defined value that will be loaded into the the user data phase of the frame. This 8-bit value can be used by the receiver for any application need. This value will not impact any hardware behavior." hexmask.word.byte 0x6 0.--3. 1. "FRAME_TAG,This will be used only for software initiated transmissions. Frame tag bits This is a user-defined value that will be loaded into the frame tag phase of the next transmission. The receiver may use the frame tag for any application need. This.." line.word 0x8 "CONTROLSS_FSI0_TX0_TX_BUF_PTR_LOAD" hexmask.word.byte 0x8 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load bits These bits are used to force the transmit buffer pointer to a desired index within the transmit buffer. The next transmission will begin picking data from this index and increment appropriately. This value will be.." rgroup.word 0x12++0x1 line.word 0x0 "CONTROLSS_FSI0_TX0_TX_BUF_PTR_STS" hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Remaining in the transmit buffer This value indicates the number of words present in the data buffer which have not yet been transmitted. This value is only valid when there is no active transmission. Note: This value will not be.." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x14++0x3 line.word 0x0 "CONTROLSS_FSI0_TX0_TX_PING_CTRL_ALT1_" hexmask.word.byte 0x0 3.--8. 1. "EXT_TRIG_SEL,External Trigger Select bits This bitfield will select one of the 64 external trigger inputs to as the source to generate a ping frame. A ping frame will only be generated if the EXT_TRIG_EN bit is set. 0h (R/W) = Trigger 1 will be used to.." bitfld.word 0x0 2. "EXT_TRIG_EN,External Trigger Enable bit This bit will allow the external trigger logic to generate a ping frame. 0h (R/W) = External triggers will not be used to generate ping frames. 1h (R/W) = The selected external trigger (selected by EXT_TRIG_SEL.." "0,1" bitfld.word 0x0 1. "TIMER_EN,Ping Timer Enable bit This bit will enable the ping timer for generating periodic ping frames. 0h (R/W) = The ping timer is disabled and will not generate ping frames. 1h (R/W) = The ping timer is enabled and can be used to generate ping.." "0,1" bitfld.word 0x0 0. "CNT_RST,Ping Counter Reset bit Writing a 1 to this bit will reset the ping counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be cleared to 0 to use the counter. 0h (R/W) = Clear the CNT_RST. 1h (R/W) = The.." "0,1" line.word 0x2 "CONTROLSS_FSI0_TX0_TX_PING_TAG" hexmask.word.byte 0x2 0.--3. 1. "TAG,Ping Frame Tag This field contains a 4-bit tag which will be sent in any ping frame that is initiated by an external trigger or the ping timer. This field is user-defined and can be set based on the application requirement. If a ping frame is.." group.long 0x18++0x3 line.long 0x0 "CONTROLSS_FSI0_TX0_TX_PING_TO_REF" hexmask.long 0x0 0.--31. 1. "TO_REF,Ping Timer Reference Value. This is the 32-bit reference value for the ping timer. The timer will increment the counter starting from 0. When the reference value is reached it will generate a timeout event triggering a ping frame transmission." rgroup.long 0x1C++0x3 line.long 0x0 "CONTROLSS_FSI0_TX0_TX_PING_TO_CNT" hexmask.long 0x0 0.--31. 1. "TO_CNT,Ping Timer Counter Value This register contains the current value of the ping timer counter. After reset this counter will increment until it reaches the reference value (TX_PING_TO_REF) at which point it generates a ping frame transmission." group.word 0x20++0x5 line.word 0x0 "CONTROLSS_FSI0_TX0_TX_INT_CTRL" bitfld.word 0x0 11. "INT2_EN_PING_TO,Enable PING Timer Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = The ping timer event will trigger an interrupt on TX_INT2." "0,1" bitfld.word 0x0 10. "INT2_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 9. "INT2_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 8. "INT2_EN_FRAME_DONE,Enable Frame Done interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = A Frame Done event will trigger an interrupt on TX_INT2." "0,1" newline bitfld.word 0x0 3. "INT1_EN_PING_TO,Enable Ping Timer Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = The ping timer event will trigger an interrupt on TX_INT1." "0,1" bitfld.word 0x0 2. "INT1_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 1. "INT1_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 0. "INT1_EN_FRAME_DONE,Enable Frame Done interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = A Frame Done event will trigger an interrupt on TX_INT1." "0,1" line.word 0x2 "CONTROLSS_FSI0_TX0_TX_DMA_CTRL" bitfld.word 0x2 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable the DMA event to be generated upon the completion of a transmit frame. 0h (R/W) = A DMA event will not be generated. 1h (R/W) = A DMA event will be generated upon the completion of a transmitted.." "0,1" line.word 0x4 "CONTROLSS_FSI0_TX0_TX_LOCK_CTRL" hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the transmit control registers that support a lock protection. Once locked further writes will not take effect until a SYSRS has reset this register. Once set further writes to.." "0,1" rgroup.word 0x28++0x1 line.word 0x0 "CONTROLSS_FSI0_TX0_TX_EVT_STS" bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Bit This bit indicates that a ping frame has been triggered. This bit is set by hardware when either the ping timer or an external trigger event have occured. Software can also force this bit to get set by writing.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Bit This bit inditcates that buffer overrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = Buffer Overrun has not occured. 1h (R) = Buffer Overrun has occured. To.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Bit This bit inditcates that buffer underrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = Buffer Underrun has not occured. 1h (R) = Buffer Underrun has.." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Bit This bit inditcates a Frame Done condition. This bit is set by hardware when a frame transmission has been completed. Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = Frame Done.." "0,1" wgroup.word 0x2C++0x3 line.word 0x0 "CONTROLSS_FSI0_TX0_TX_EVT_CLR" bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0." "0,1" line.word 0x2 "CONTROLSS_FSI0_TX0_TX_EVT_FRC" bitfld.word 0x2 3. "PING_TRIGGERED,Ping Frame Triggered Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 2. "BUF_OVERRUN,Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 1. "BUF_UNDERRUN,Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 0. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W) =.." "0,1" group.word 0x30++0x1 line.word 0x0 "CONTROLSS_FSI0_TX0_TX_USER_CRC" hexmask.word.byte 0x0 0.--7. 1. "USER_CRC,User-defined CRC This register contains the 8-bit CRC value to be transmitted in the next frame if the transmission is set for user-defined CRC option (TX_OPER_CTRL_LO.SW_CRC = 1). This register is ignored if the hardware CRC generation is.." group.long 0x40++0x3 line.long 0x0 "CONTROLSS_FSI0_TX0_TX_ECC_DATA" hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." rgroup.word 0x44++0x1 line.word 0x0 "CONTROLSS_FSI0_TX0_TX_ECC_VAL" hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value This field contains the ECC value computed using SEC-DED either for 16-bit or 32-bit data in the TX_ECC_DATA register." group.word 0x48++0x1 line.word 0x0 "CONTROLSS_FSI0_TX0_TX_DLYLINE_CTRL" hexmask.word.byte 0x0 10.--14. 1. "TXD1_DLY,Delay Line Tap Select for TXD1 This bitfield selects the number of delay elements inserted into the TXD1 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the TXD1 path. TXD1 is taken directly from.." hexmask.word.byte 0x0 5.--9. 1. "TXD0_DLY,Delay Line Tap Select for TXD0 This bitfield selects the number of delay elements inserted into the TXD0 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the TXD0 path. TXD0 is taken directly from.." hexmask.word.byte 0x0 0.--4. 1. "TXCLK_DLY,Delay Line Tap Select for TXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the TXCLK path. TXCLK is taken directly.." group.word 0x80++0x1 line.word 0x0 "CONTROLSS_FSI0_TX0_TX_BUF_BASE" hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Transmit Data Buffer Base Address This is the base address of the 16-word data buffer used by the transmitter." tree.end tree "FSI0_TX1" base ad:0x50281000 group.word 0x0++0x1 line.word 0x0 "CONTROLSS_FSI0_TX1_TX_MASTER_CTRL" hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key In order to write to any bit in this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x0 1. "FLUSH,Flush Operation Start bit This bit will cause the transmitter to initiate a flush pattern of a single toggle on the TXD0 and TXD1 followed by five full cycles of TXCLK. This bit should be written only when the CORE_RST bit is 0 and the clock to the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Transmitter Master Core Reset bit This bit controls the transmitter master core reset. In order to send any frame this bit must be cleared. 0h (R/W) = Transmitter core is not in reset and can transmit frames. 1h (R/W) = Transmitter core is.." "0,1" group.word 0x4++0x1 line.word 0x0 "CONTROLSS_FSI0_TX1_TX_CLK_CTRL" hexmask.word.byte 0x0 2.--9. 1. "PRESCALE_VAL,Clock Divider Prescale Value The input clock is divided by this 8-bit value and fed into the transmitter core. This divided clock is the rate at which TXCLK will operate. 0h (R/W) = Reserved 1h (R/W) = Input clock /1 2h (R/W) = Input clock.." bitfld.word 0x0 1. "CLK_EN,Clock Divider Enable bit This bit will enable and disable the input clock divider and start the clock to the transmitter core. 0h (R/W) = The input clock divider is not enabled and the clock is not connected to the transmitter core. 1h (R/W) =.." "0,1" bitfld.word 0x0 0. "CLK_RST,Clock Divider Reset bit This bit will reset the clock counter in the clock divider. 0h (R/W) = The clock divider is set based on the value in PRESCALE_VAL. The input clock will be divided by PRESCALE_VAL if CLK_EN is set. 1h (R/W) = The clock.." "0,1" group.word 0x8++0x9 line.word 0x0 "CONTROLSS_FSI0_TX1_TX_OPER_CTRL_LO_ALT2_" bitfld.word 0x0 10. "SEL_TDM_IN,Input TDM port Select bit This bit selects the input port for the transmitter core between the TDM input pins or the RX module. When this bit is '0' the inputs selected for TDM are from the TDM input pins. When this bit is '1' then inputs.." "0,1" bitfld.word 0x0 9. "TDM_ENABLE,Transmit TDM Mode Enable bit. This bit enables the TDM Mode for multi-slave TDM operation. 0h (R/W) Transmit TDM Mode is not enabled. 1h (R/W) Transmit TDM Mode is enabled." "0,1" bitfld.word 0x0 8. "SEL_PLLCLK,Input Clock Select bit This bit selects the input clock source for the transmitter core. 0h (R/W) = SYSCLK is the source of the transmitter clock into the clock prescaler. 1h (R/W) = PLLRAWCLK is the source of the transmitter core clock into.." "0,1" bitfld.word 0x0 7. "PING_TO_MODE,Ping Counter Reset Mode Select bit This bit selects when the ping counter will reset. 0h (R/W) = The ping counter will reset and restart only on hardware initiated ping frames when ping counter has timed out. 1h (R/W) = The ping counter.." "0,1" newline bitfld.word 0x0 6. "SW_CRC,CRC Source Select bit This bit selects the source of the CRC value that is transmitted. 0h (R/W) = The transmitted CRC value is computed by hardware. 1h (R/W) = The transmitted CRC value is sourced from the value programmed in the TX_USER_CRC.." "0,1" bitfld.word 0x0 3.--5. "START_MODE,Transmission Start Mode Select bit These bits select the method by which a new frame transmission is started. 0h (R/W) = Only a software write to TX_FRAME_CTRL.START initiate a new transmission. 1h (R/W) = The configured external trigger will.." "0,1,2,3,4,5,6,7" bitfld.word 0x0 2. "SPI_MODE,SPI Mode Select bit This bit enables and disables SPI compatibility mode. 0h (R/W) = FSI is in normal mode of operation. 1h (R/W) = FSI is operating in SPI compatibility mode." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Transmit Data Width Select bits These bits define the number of data lines used by the transmitter. 0h (R/W) = Data will be transmitted on one data line (TXD0) 1h (R/W) = Data will be transmitted on two data lines (TXD0 and TXD1). The format.." "0,1,2,3" line.word 0x2 "CONTROLSS_FSI0_TX1_TX_OPER_CTRL_HI_ALT1_" hexmask.word.byte 0x2 7.--12. 1. "EXT_TRIG_SEL,External Trigger Select bit These bits define which of the 64 external inputs will be used as the source for the external input trigger. 00h (R/W) = Trigger 1 is the source. 01h (R/W) = Trigger 2 is the source. 02h (R/W) = Trigger 3 is the.." bitfld.word 0x2 6. "ECC_SEL,ECC Data Width Select bit This bit selects between 16-bit and 32-bit ECC computation. 0h (R/W) = 32-bit ECC is used. 1h (R/W) = 16-bit ECC is used." "0,1" bitfld.word 0x2 5. "FORCE_ERR,Error Frame Force bit This bit will force the the CRC value of the transmitted data frame to 0 whenever there is a buffer overrun or underrun condition. This can be used to force a corrupted CRC as the data is not guaranteed to be reliable. The.." "0,1" line.word 0x4 "CONTROLSS_FSI0_TX1_TX_FRAME_CTRL" bitfld.word 0x4 15. "START,Start Transmission bit This bit will cause the FSI to start transmitting the next frame. 0h (R/W) = Writing a 0 to this bit will have no effect. 1h (R/W) = Start the next transmission. This bit will be cleared by hardware." "0,1" hexmask.word.byte 0x4 4.--7. 1. "N_WORDS,Number of Words to be Transmitted This field defines the number of words which will be transmitted in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the receiver. Set this bitfield to be one less than.." hexmask.word.byte 0x4 0.--3. 1. "FRAME_TYPE,Transmit Frame Type This field determines the type of frame that will be transmitted next. 0000b (R/W) = Ping Frame. This frame can be sent either by software or automatically by hardware. 0100b (R/W) = DATA_1_WORD Frame. One word data frame.." line.word 0x6 "CONTROLSS_FSI0_TX1_TX_FRAME_TAG_UDATA" hexmask.word.byte 0x6 8.--15. 1. "USER_DATA,User Data bits This is a user-defined value that will be loaded into the the user data phase of the frame. This 8-bit value can be used by the receiver for any application need. This value will not impact any hardware behavior." hexmask.word.byte 0x6 0.--3. 1. "FRAME_TAG,This will be used only for software initiated transmissions. Frame tag bits This is a user-defined value that will be loaded into the frame tag phase of the next transmission. The receiver may use the frame tag for any application need. This.." line.word 0x8 "CONTROLSS_FSI0_TX1_TX_BUF_PTR_LOAD" hexmask.word.byte 0x8 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load bits These bits are used to force the transmit buffer pointer to a desired index within the transmit buffer. The next transmission will begin picking data from this index and increment appropriately. This value will be.." rgroup.word 0x12++0x1 line.word 0x0 "CONTROLSS_FSI0_TX1_TX_BUF_PTR_STS" hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Remaining in the transmit buffer This value indicates the number of words present in the data buffer which have not yet been transmitted. This value is only valid when there is no active transmission. Note: This value will not be.." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x14++0x3 line.word 0x0 "CONTROLSS_FSI0_TX1_TX_PING_CTRL_ALT1_" hexmask.word.byte 0x0 3.--8. 1. "EXT_TRIG_SEL,External Trigger Select bits This bitfield will select one of the 64 external trigger inputs to as the source to generate a ping frame. A ping frame will only be generated if the EXT_TRIG_EN bit is set. 0h (R/W) = Trigger 1 will be used to.." bitfld.word 0x0 2. "EXT_TRIG_EN,External Trigger Enable bit This bit will allow the external trigger logic to generate a ping frame. 0h (R/W) = External triggers will not be used to generate ping frames. 1h (R/W) = The selected external trigger (selected by EXT_TRIG_SEL.." "0,1" bitfld.word 0x0 1. "TIMER_EN,Ping Timer Enable bit This bit will enable the ping timer for generating periodic ping frames. 0h (R/W) = The ping timer is disabled and will not generate ping frames. 1h (R/W) = The ping timer is enabled and can be used to generate ping.." "0,1" bitfld.word 0x0 0. "CNT_RST,Ping Counter Reset bit Writing a 1 to this bit will reset the ping counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be cleared to 0 to use the counter. 0h (R/W) = Clear the CNT_RST. 1h (R/W) = The.." "0,1" line.word 0x2 "CONTROLSS_FSI0_TX1_TX_PING_TAG" hexmask.word.byte 0x2 0.--3. 1. "TAG,Ping Frame Tag This field contains a 4-bit tag which will be sent in any ping frame that is initiated by an external trigger or the ping timer. This field is user-defined and can be set based on the application requirement. If a ping frame is.." group.long 0x18++0x3 line.long 0x0 "CONTROLSS_FSI0_TX1_TX_PING_TO_REF" hexmask.long 0x0 0.--31. 1. "TO_REF,Ping Timer Reference Value. This is the 32-bit reference value for the ping timer. The timer will increment the counter starting from 0. When the reference value is reached it will generate a timeout event triggering a ping frame transmission." rgroup.long 0x1C++0x3 line.long 0x0 "CONTROLSS_FSI0_TX1_TX_PING_TO_CNT" hexmask.long 0x0 0.--31. 1. "TO_CNT,Ping Timer Counter Value This register contains the current value of the ping timer counter. After reset this counter will increment until it reaches the reference value (TX_PING_TO_REF) at which point it generates a ping frame transmission." group.word 0x20++0x5 line.word 0x0 "CONTROLSS_FSI0_TX1_TX_INT_CTRL" bitfld.word 0x0 11. "INT2_EN_PING_TO,Enable PING Timer Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = The ping timer event will trigger an interrupt on TX_INT2." "0,1" bitfld.word 0x0 10. "INT2_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 9. "INT2_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 8. "INT2_EN_FRAME_DONE,Enable Frame Done interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = A Frame Done event will trigger an interrupt on TX_INT2." "0,1" newline bitfld.word 0x0 3. "INT1_EN_PING_TO,Enable Ping Timer Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = The ping timer event will trigger an interrupt on TX_INT1." "0,1" bitfld.word 0x0 2. "INT1_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 1. "INT1_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 0. "INT1_EN_FRAME_DONE,Enable Frame Done interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = A Frame Done event will trigger an interrupt on TX_INT1." "0,1" line.word 0x2 "CONTROLSS_FSI0_TX1_TX_DMA_CTRL" bitfld.word 0x2 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable the DMA event to be generated upon the completion of a transmit frame. 0h (R/W) = A DMA event will not be generated. 1h (R/W) = A DMA event will be generated upon the completion of a transmitted.." "0,1" line.word 0x4 "CONTROLSS_FSI0_TX1_TX_LOCK_CTRL" hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the transmit control registers that support a lock protection. Once locked further writes will not take effect until a SYSRS has reset this register. Once set further writes to.." "0,1" rgroup.word 0x28++0x1 line.word 0x0 "CONTROLSS_FSI0_TX1_TX_EVT_STS" bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Bit This bit indicates that a ping frame has been triggered. This bit is set by hardware when either the ping timer or an external trigger event have occured. Software can also force this bit to get set by writing.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Bit This bit inditcates that buffer overrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = Buffer Overrun has not occured. 1h (R) = Buffer Overrun has occured. To.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Bit This bit inditcates that buffer underrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = Buffer Underrun has not occured. 1h (R) = Buffer Underrun has.." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Bit This bit inditcates a Frame Done condition. This bit is set by hardware when a frame transmission has been completed. Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = Frame Done.." "0,1" wgroup.word 0x2C++0x3 line.word 0x0 "CONTROLSS_FSI0_TX1_TX_EVT_CLR" bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0." "0,1" line.word 0x2 "CONTROLSS_FSI0_TX1_TX_EVT_FRC" bitfld.word 0x2 3. "PING_TRIGGERED,Ping Frame Triggered Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 2. "BUF_OVERRUN,Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 1. "BUF_UNDERRUN,Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 0. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W) =.." "0,1" group.word 0x30++0x1 line.word 0x0 "CONTROLSS_FSI0_TX1_TX_USER_CRC" hexmask.word.byte 0x0 0.--7. 1. "USER_CRC,User-defined CRC This register contains the 8-bit CRC value to be transmitted in the next frame if the transmission is set for user-defined CRC option (TX_OPER_CTRL_LO.SW_CRC = 1). This register is ignored if the hardware CRC generation is.." group.long 0x40++0x3 line.long 0x0 "CONTROLSS_FSI0_TX1_TX_ECC_DATA" hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." rgroup.word 0x44++0x1 line.word 0x0 "CONTROLSS_FSI0_TX1_TX_ECC_VAL" hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value This field contains the ECC value computed using SEC-DED either for 16-bit or 32-bit data in the TX_ECC_DATA register." group.word 0x48++0x1 line.word 0x0 "CONTROLSS_FSI0_TX1_TX_DLYLINE_CTRL" hexmask.word.byte 0x0 10.--14. 1. "TXD1_DLY,Delay Line Tap Select for TXD1 This bitfield selects the number of delay elements inserted into the TXD1 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the TXD1 path. TXD1 is taken directly from.." hexmask.word.byte 0x0 5.--9. 1. "TXD0_DLY,Delay Line Tap Select for TXD0 This bitfield selects the number of delay elements inserted into the TXD0 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the TXD0 path. TXD0 is taken directly from.." hexmask.word.byte 0x0 0.--4. 1. "TXCLK_DLY,Delay Line Tap Select for TXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the TXCLK path. TXCLK is taken directly.." group.word 0x80++0x1 line.word 0x0 "CONTROLSS_FSI0_TX1_TX_BUF_BASE" hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Transmit Data Buffer Base Address This is the base address of the 16-word data buffer used by the transmitter." tree.end tree.end tree "FSI1" tree "FSI1_RX2" base ad:0x502B0000 group.word 0x0++0x1 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_MASTER_CTRL_ALTC_" hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x0 4. "DATA_FILTER_EN,Data Filter Enable Bit. 0h (R/W) = Data filtering is disabled. 1h (R/W) = Data filtering is enabled." "0,1" bitfld.word 0x0 3. "INPUT_ISOLATE,When set to 1 the FSI RX inputs (RXCLK RXD0 and RXD1) will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of.." "0,1" newline bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behavior Enable bit This bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module acting as a SPI master to clock data into the.." "0,1" bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable bit This bit enables the internal loopback functionality of the FSI receiver. By enabling this bit a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset bit This bit controls the receiver master core reset. In order to receive any frame this bit must be cleared. Note: For reset to take affect the FSI RX module must be held in reset for at least 4 SYSCLK cycles. 0h.." "0,1" group.word 0x8++0x1 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_OPER_CTRL" bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select bit This bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame. 0h (R/W) = The ping watchdog.." "0,1" bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select bit This bit selects between whether the ECC computation is done on 16-bit or 32-bit words. 0h (R/W) = 32-bit ECC is used. 1h (R/W) = 16-bit ECC is used." "0,1" hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to Receive This field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the.." newline bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable bit This bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive.." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select bit These bits decide the number of data lines used for receiving data. 0h (R/W) = Data will be received on one data line RXD0. 1h (R/W) = Data will be received on two data lines RXD0 and RXD1. 2h 3h (R/W) =.." "0,1,2,3" rgroup.word 0xC++0x3 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_FRAME_INFO" hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type This field indicates the type of frame that was successfully received last. 0000b (R/W) = A ping frame was received 0100b (R/W) = A DATA_1_WORD frame was received (16-bit data). 0101b (R/W) = A DATA_2_WORD frame was.." line.word 0x2 "CONTROLSS_FSI1_RX2_RX_FRAME_TAG_UDATA" hexmask.word.byte 0x2 8.--15. 1. "USER_DATA,Received User Data This field contains the 8-bit user data field of the last successfully received frame." hexmask.word.byte 0x2 1.--4. 1. "FRAME_TAG,Received Frame Tag This field contains the 4-bit frame tag from the last successfully received frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x2 0. "RESERVED,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the FRAME_TAG and ZERO bits of this register (bits 4:0) application software can directly index into an array of 32-bit data." "0,1" group.word 0x10++0x1 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_DMA_CTRL" bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable a DMA Event to be generated upon the completion of a frame reception. 0h (R/W) = A DMA event will not be generated. 1h (R/W) = A DMA event will be generated upon the reception of a frame. Note: The.." "0,1" rgroup.word 0x14++0x3 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_EVT_STS_ALT1_" bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag This bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag This bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No tag-matched.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag This bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No tag-matched.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag This bit indicates that an data frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No data frame has been received. 1h (R) = A data frame has been.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag This bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag This bit indicates that an ping frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No ping frame has been received. 1h (R) = A ping frame has been.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag This bit indicates that an error frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No error frame has been received. 1h (R) = An error frame has been.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag This bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag This bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No frame has been successfully received. 1h (R) = A.." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag This bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Receive buffer overrun has not.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag This bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Invalid end-of-frame has not been received. 1h.." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag This bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Invalid frame type has not been received. 1h (R) = Invalid.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag This bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by writing to the RX_EVT_FRC.." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag This bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Frame watchdog timeout has not occured. 1h (R) = Frame.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag This bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Ping watchdog timeout has not occured. 1h (R) = Ping.." "0,1" line.word 0x2 "CONTROLSS_FSI1_RX2_RX_CRC_INFO" hexmask.word.byte 0x2 8.--15. 1. "CALC_CRC,Harware Calculated CRC Value This bitfield contains the CRC value that was calculated on the last received data. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for.." hexmask.word.byte 0x2 0.--7. 1. "RX_CRC,Received CRC Value This bitfield contains the CRC value that was last received a frame. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping and error frames." wgroup.word 0x18++0x3 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_EVT_CLR_ALT1_" bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Glag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (R/W) = Writing a 0 to this bit will have no effect. 1h (R/W) = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" line.word 0x2 "CONTROLSS_FSI1_RX2_RX_EVT_FRC_ALT1_" bitfld.word 0x2 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 13. "DATA_TAG_MATCH,Data Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 12. "PING_TAG_MATCH,Ping Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" newline bitfld.word 0x2 11. "DATA_FRAME,Data Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 10. "FRAME_OVERRUN,Frame Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 9. "PING_FRAME,Ping Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" newline bitfld.word 0x2 8. "ERR_FRAME,Error Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 6. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W) =.." "0,1" newline bitfld.word 0x2 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 4. "EOF_ERR,End-of-Frame Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W).." "0,1" bitfld.word 0x2 3. "TYPE_ERR,Frame Type Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W).." "0,1" newline bitfld.word 0x2 2. "CRC_ERR,CRC Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W) =.." "0,1" bitfld.word 0x2 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_BUF_PTR_LOAD" hexmask.word.byte 0x0 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load. This is the value to be loaded into the receive word pointer when written. This is to allow software to force the receiver to start storing the received data starting at a specific location in the buffer. NOTE: The.." rgroup.word 0x1E++0x1 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_BUF_PTR_STS" hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Available in the Receive Buffer This bitfield indicates the number of valid data words present in the receive buffer that have not been read by the application software. This bitfield is only valid when there is no active transfer." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x20++0x1 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_FRAME_WD_CTRL" bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable bit This bit will enable or disable the frame watchdog counter. The counter (RX_FRAME_WD_CNT) will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value (RX_FRAME_WD_REF).." "0,1" bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset bit This bit will reset the frame watchdog counter to 0. Writing a 1 to this bit will reset the frame watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to.." "0,1" group.long 0x24++0x3 line.long 0x0 "CONTROLSS_FSI1_RX2_RX_FRAME_WD_REF" hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value This is the 32-bit reference value for the frame watchdog timeout counter. The counter will count up starting from 0 at a valid start-of-frame pattern and continue counting until this value is reached." rgroup.long 0x28++0x3 line.long 0x0 "CONTROLSS_FSI1_RX2_RX_FRAME_WD_CNT" hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the frame watchdog counter. This counter is reset to 0 in a variety of ways: A write to FRME_WD_CNT_RST a match with FRAME_WD_REF or the.." group.word 0x2C++0x1 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_PING_WD_CTRL" bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable bit This bit will enable or disable the ping watchdog counter. The counter (RX_PING_WD_CNT) will begin counting from 0 when it is enabled. When the reference value (RX_PING_WD_REF) is reached it will generate a.." "0,1" bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset bit This bit will reset the ping watchdog counter to 0. Writing a 1 to this bit will reset the ping watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be.." "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_PING_TAG" hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Received Ping Frame Tag This field contains the 4-bit frame tag from the last successfully received ping frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x0 0. "RESERVED,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the PING_TAG and ZERO bits of this register (bits 4:0) application software can directly index into an array of 32-bit data." "0,1" group.long 0x30++0x3 line.long 0x0 "CONTROLSS_FSI1_RX2_RX_PING_WD_REF" hexmask.long 0x0 0.--31. 1. "PING_WD_REF,Ping Watchdog Counter Reference Value This is the 32-bit reference value for the ping watchdog timeout counter. The counter will count up starting from 0 and continue counting until this value is reached." rgroup.long 0x34++0x3 line.long 0x0 "CONTROLSS_FSI1_RX2_RX_PING_WD_CNT" hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the ping watchdog counter. This counter is reset to 0 in a variety of ways: A write to PING_WD_RST a match with PING_WD_REF or the reception.." group.word 0x38++0x5 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_INT1_CTRL_ALT1_" bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt.." "0,1" bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A.." "0,1" bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" newline bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable ERROR Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A.." "0,1" bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A frame.." "0,1" newline bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = An.." "0,1" bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A.." "0,1" newline bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A CRC error.." "0,1" bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h.." "0,1" bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h.." "0,1" line.word 0x2 "CONTROLSS_FSI1_RX2_RX_INT2_CTRL_ALT1_" bitfld.word 0x2 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt.." "0,1" bitfld.word 0x2 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x2 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x2 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W).." "0,1" bitfld.word 0x2 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" bitfld.word 0x2 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W).." "0,1" newline bitfld.word 0x2 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W).." "0,1" bitfld.word 0x2 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" bitfld.word 0x2 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A frame.." "0,1" newline bitfld.word 0x2 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" bitfld.word 0x2 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = An.." "0,1" bitfld.word 0x2 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" newline bitfld.word 0x2 2. "INT2_EN_CRC_ERR,Enable CRC Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A CRC error.." "0,1" bitfld.word 0x2 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h.." "0,1" bitfld.word 0x2 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h.." "0,1" line.word 0x4 "CONTROLSS_FSI1_RX2_RX_LOCK_CTRL" hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the receive control registers that support a lock protection. Once locked further writes will not take effect until SYSRS unlocks the register. Once set further writes even to.." "0,1" group.long 0x40++0x3 line.long 0x0 "CONTROLSS_FSI1_RX2_RX_ECC_DATA" hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." group.word 0x44++0x1 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_ECC_VAL" hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,ECC Value for SEC-DED check This field contains the ECC value to be used for SEC-DED either for 16-bit or 32-bit data in the RX_ECC_DATA register." rgroup.long 0x48++0x3 line.long 0x0 "CONTROLSS_FSI1_RX2_RX_ECC_SEC_DATA" hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data The ECC corrected data will be available in this register. This value is valid only when there are no bit errors or a single bit error was detected. Otherwise the contents of this register are invalid and should.." rgroup.word 0x4C++0x1 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_ECC_LOG" bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected This bit indicates the occurrence of multiple bit errors.The data is corrupted and cannot be corrected. If this bit is set the data present in RX_ECC_SEC_DATA is invalid and should not be used. 0h (R) Multiple Bit.." "0,1" bitfld.word 0x0 0. "SBE,Single Bit Error Detected This bit indicates the occurrence of a single bit error in the data. The data is autocorrected and placed into the RX_ECC_SEC_DATA register. This bit is valid only if MBE is 0. 0h (R) No bit errors were detected. The value.." "0,1" group.word 0x50++0x3 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_FRAME_TAG_CMP" bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable bit Set this bit to enable the comparison of an incoming frame tag and the value stored in the frame tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming frame tag will trigger the.." "0,1" hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only for.." newline hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming frame tag. This reference value is used only for non-ping frames." line.word 0x2 "CONTROLSS_FSI1_RX2_RX_PING_TAG_CMP" bitfld.word 0x2 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x2 8. "CMP_EN,Ping Tag Compare Enable bit Set this bit to enable the comparison of an incoming ping tag and the value stored in the ping tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming ping tag will trigger a ping frame.." "0,1" hexmask.word.byte 0x2 4.--7. 1. "TAG_MASK,Ping Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming ping frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only.." newline hexmask.word.byte 0x2 0.--3. 1. "TAG_REF,Ping Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming ping tag. This reference value is used only for ping frames." group.long 0x58++0x7 line.long 0x0 "CONTROLSS_FSI1_RX2_RX_TRIG_CTRL_0" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "CONTROLSS_FSI1_RX2_RX_TRIG_WIDTH_0" hexmask.long.word 0x4 0.--15. 1. "RX_TRIG_WIDTH,This register decides the width(in SYSCLK cycles) of wide pulse output of the RX trigger module." group.word 0x60++0x1 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_DLYLINE_CTRL" hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1 This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the RXD1 path. RXD1 is taken directly from.." hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0 This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the RXD0 path. RXD0 is taken directly from.." hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the RXCLK path. RXCLK is taken directly.." group.long 0x64++0xB line.long 0x0 "CONTROLSS_FSI1_RX2_RX_TRIG_CTRL_1" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "CONTROLSS_FSI1_RX2_RX_TRIG_CTRL_2" hexmask.long.tbyte 0x4 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x4 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x4 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x8 "CONTROLSS_FSI1_RX2_RX_TRIG_CTRL_3" hexmask.long.tbyte 0x8 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x8 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x8 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" rgroup.long 0x70++0x3 line.long 0x0 "CONTROLSS_FSI1_RX2_RX_VIS_1" bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status bit This bit indicates the status of the receiver core. If this bit is set the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has.." "0,1" group.word 0x74++0x1 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_UDATA_FILTER" hexmask.word.byte 0x0 8.--15. 1. "UDATA_MASK,Bit Mask to be used for comparing the USERDATA field when filtering is enabled. Every bit that is '1' in this register will be masked for comparison. If a bit position is '1' then it will be considered a successful match for that bit position." hexmask.word.byte 0x0 0.--7. 1. "UDATA_REG,Reference to be used for comparing the USERDATA field when filtering is enabled." rgroup.word 0x80++0x1 line.word 0x0 "CONTROLSS_FSI1_RX2_RX_BUF_BASE" hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address This is the base address of the 16-word data buffer used by the receiver." tree.end tree "FSI1_RX3" base ad:0x502B1000 group.word 0x0++0x1 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_MASTER_CTRL_ALTC_" hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x0 4. "DATA_FILTER_EN,Data Filter Enable Bit. 0h (R/W) = Data filtering is disabled. 1h (R/W) = Data filtering is enabled." "0,1" bitfld.word 0x0 3. "INPUT_ISOLATE,When set to 1 the FSI RX inputs (RXCLK RXD0 and RXD1) will be isolated from what is driven from the device pins and will be held at inactive level of '1'.This isolation facilitates the user to switch the RX inputs to a different set of.." "0,1" newline bitfld.word 0x0 2. "SPI_PAIRING,Clock Pairing for SPI-like Behavior Enable bit This bit enables the internal clock pairing with the FSI TX module. This feature internally connects the TXCLK to RXCLK allowing the FSI TX module acting as a SPI master to clock data into the.." "0,1" bitfld.word 0x0 1. "INT_LOOPBACK,Internal Loopback Enable bit This bit enables the internal loopback functionality of the FSI receiver. By enabling this bit a mux will select the signals coming directly from the corresponding FSI transmitter module rather than from the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Receiver Master Core Reset bit This bit controls the receiver master core reset. In order to receive any frame this bit must be cleared. Note: For reset to take affect the FSI RX module must be held in reset for at least 4 SYSCLK cycles. 0h.." "0,1" group.word 0x8++0x1 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_OPER_CTRL" bitfld.word 0x0 8. "PING_WD_RST_MODE,Ping Watchdog Timeout Mode Select bit This bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame. 0h (R/W) = The ping watchdog.." "0,1" bitfld.word 0x0 7. "ECC_SEL,ECC Data Width Select bit This bit selects between whether the ECC computation is done on 16-bit or 32-bit words. 0h (R/W) = 32-bit ECC is used. 1h (R/W) = 16-bit ECC is used." "0,1" hexmask.word.byte 0x0 3.--6. 1. "N_WORDS,Number of Words to Receive This field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the.." newline bitfld.word 0x0 2. "SPI_MODE,SPI Mode Enable bit This bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive.." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Receive Data Width Select bit These bits decide the number of data lines used for receiving data. 0h (R/W) = Data will be received on one data line RXD0. 1h (R/W) = Data will be received on two data lines RXD0 and RXD1. 2h 3h (R/W) =.." "0,1,2,3" rgroup.word 0xC++0x3 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_FRAME_INFO" hexmask.word.byte 0x0 0.--3. 1. "FRAME_TYPE,Received Frame Type This field indicates the type of frame that was successfully received last. 0000b (R/W) = A ping frame was received 0100b (R/W) = A DATA_1_WORD frame was received (16-bit data). 0101b (R/W) = A DATA_2_WORD frame was.." line.word 0x2 "CONTROLSS_FSI1_RX3_RX_FRAME_TAG_UDATA" hexmask.word.byte 0x2 8.--15. 1. "USER_DATA,Received User Data This field contains the 8-bit user data field of the last successfully received frame." hexmask.word.byte 0x2 1.--4. 1. "FRAME_TAG,Received Frame Tag This field contains the 4-bit frame tag from the last successfully received frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x2 0. "RESERVED,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the FRAME_TAG and ZERO bits of this register (bits 4:0) application software can directly index into an array of 32-bit data." "0,1" group.word 0x10++0x1 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_DMA_CTRL" bitfld.word 0x0 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable a DMA Event to be generated upon the completion of a frame reception. 0h (R/W) = A DMA event will not be generated. 1h (R/W) = A DMA event will be generated upon the reception of a frame. Note: The.." "0,1" rgroup.word 0x14++0x3 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_EVT_STS_ALT1_" bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Flag This bit indicates that an error frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag This bit indicates that a dataframe was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No tag-matched.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag This bit indicates that a ping frame was received with a tag comparison matching the masked tag reference. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No tag-matched.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag This bit indicates that an data frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No data frame has been received. 1h (R) = A data frame has been.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag This bit indicates that a frame overrun condition has occured. This bit gets set to 1 when a new DATA/ERROR frame is received and the corresponding DATA_FRAME_RCVD/ERROR_FRAME_RCVD flag is still set to 1. Software can.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag This bit indicates that an ping frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No ping frame has been received. 1h (R) = A ping frame has been.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag This bit indicates that an error frame has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No error frame has been received. 1h (R) = An error frame has been.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag This bit indicates that a buffer underrun condition has occured in the receive buffer. This will happen when software reads the buffer which is empty and has no valid data. Software can also force this bit to get.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag This bit indicates that a frame has been successfully received without error. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = No frame has been successfully received. 1h (R) = A.." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag This bit indicates that a buffer overrun condition has occured in the receive buffer. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Receive buffer overrun has not.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag This bit indicates that an invalid end-of-frame bit pattern has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Invalid end-of-frame has not been received. 1h.." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag This bit inditcates that an invalid frame type has been received. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Invalid frame type has not been received. 1h (R) = Invalid.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag This bit indicates that a CRC error has occured. A CRC error will be generated on a data frame where the received CRC and the computed CRC do not match. Software can also force this bit to get set by writing to the RX_EVT_FRC.." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag This bit indicates that the frame watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Frame watchdog timeout has not occured. 1h (R) = Frame.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag This bit indicates that the ping watchdog timer has timed out. Software can also force this bit to get set by writing to the RX_EVT_FRC register. 0h (R) = Ping watchdog timeout has not occured. 1h (R) = Ping.." "0,1" line.word 0x2 "CONTROLSS_FSI1_RX3_RX_CRC_INFO" hexmask.word.byte 0x2 8.--15. 1. "CALC_CRC,Harware Calculated CRC Value This bitfield contains the CRC value that was calculated on the last received data. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for.." hexmask.word.byte 0x2 0.--7. 1. "RX_CRC,Received CRC Value This bitfield contains the CRC value that was last received a frame. The contents of this bitfield are valid only when data frames are received. Note: The contents of this bitfield are invalid for ping and error frames." wgroup.word 0x18++0x3 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_EVT_CLR_ALT1_" bitfld.word 0x0 14. "ERROR_TAG_MATCH,Error Tag Match Glag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 13. "DATA_TAG_MATCH,Data Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 12. "PING_TAG_MATCH,Ping Tag Match Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 11. "DATA_FRAME,Data Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 10. "FRAME_OVERRUN,Frame Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 9. "PING_FRAME,Ping Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" newline bitfld.word 0x0 8. "ERR_FRAME,Error Frame Received Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (R/W) = Writing a 0 to this bit will have no effect. 1h (R/W) = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1" bitfld.word 0x0 6. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" newline bitfld.word 0x0 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 4. "EOF_ERR,End-of-Frame Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 3. "TYPE_ERR,Frame Type Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register.." "0,1" newline bitfld.word 0x0 2. "CRC_ERR,CRC Error Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS register to 0." "0,1" bitfld.word 0x0 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" bitfld.word 0x0 0. "PING_WD_TO,Ping Watchdog Timeout Flag Clear bit This bit clears the corresponding bit in the RX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the RX_EVT_STS.." "0,1" line.word 0x2 "CONTROLSS_FSI1_RX3_RX_EVT_FRC_ALT1_" bitfld.word 0x2 14. "ERROR_TAG_MATCH,Error Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 13. "DATA_TAG_MATCH,Data Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 12. "PING_TAG_MATCH,Ping Tag Match Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" newline bitfld.word 0x2 11. "DATA_FRAME,Data Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 10. "FRAME_OVERRUN,Frame Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 9. "PING_FRAME,Ping Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" newline bitfld.word 0x2 8. "ERR_FRAME,Error Frame Received Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 7. "BUF_UNDERRUN,Receive Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 6. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W) =.." "0,1" newline bitfld.word 0x2 5. "BUF_OVERRUN,Receive Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 4. "EOF_ERR,End-of-Frame Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W).." "0,1" bitfld.word 0x2 3. "TYPE_ERR,Frame Type Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W).." "0,1" newline bitfld.word 0x2 2. "CRC_ERR,CRC Error Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W) =.." "0,1" bitfld.word 0x2 1. "FRAME_WD_TO,Frame Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" bitfld.word 0x2 0. "PING_WD_TO,Ping Watchdog Timeout Flag Force bit This bit will cause the corresponding bit in the RX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR." "0,1" group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_BUF_PTR_LOAD" hexmask.word.byte 0x0 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load. This is the value to be loaded into the receive word pointer when written. This is to allow software to force the receiver to start storing the received data starting at a specific location in the buffer. NOTE: The.." rgroup.word 0x1E++0x1 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_BUF_PTR_STS" hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Available in the Receive Buffer This bitfield indicates the number of valid data words present in the receive buffer that have not been read by the application software. This bitfield is only valid when there is no active transfer." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x20++0x1 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_FRAME_WD_CTRL" bitfld.word 0x0 1. "FRAME_WD_EN,Frame Watchdog Counter Enable bit This bit will enable or disable the frame watchdog counter. The counter (RX_FRAME_WD_CNT) will begin counting from 0 when a valid start-of-frame pattern is received. When the reference value (RX_FRAME_WD_REF).." "0,1" bitfld.word 0x0 0. "FRAME_WD_CNT_RST,Frame Watchdog Counter Reset bit This bit will reset the frame watchdog counter to 0. Writing a 1 to this bit will reset the frame watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to.." "0,1" group.long 0x24++0x3 line.long 0x0 "CONTROLSS_FSI1_RX3_RX_FRAME_WD_REF" hexmask.long 0x0 0.--31. 1. "FRAME_WD_REF,Frame Watchdog Counter Reference Value This is the 32-bit reference value for the frame watchdog timeout counter. The counter will count up starting from 0 at a valid start-of-frame pattern and continue counting until this value is reached." rgroup.long 0x28++0x3 line.long 0x0 "CONTROLSS_FSI1_RX3_RX_FRAME_WD_CNT" hexmask.long 0x0 0.--31. 1. "FRAME_WD_CNT,Frame Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the frame watchdog counter. This counter is reset to 0 in a variety of ways: A write to FRME_WD_CNT_RST a match with FRAME_WD_REF or the.." group.word 0x2C++0x1 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_PING_WD_CTRL" bitfld.word 0x0 1. "PING_WD_EN,Ping Watchdog Counter Enable bit This bit will enable or disable the ping watchdog counter. The counter (RX_PING_WD_CNT) will begin counting from 0 when it is enabled. When the reference value (RX_PING_WD_REF) is reached it will generate a.." "0,1" bitfld.word 0x0 0. "PING_WD_RST,Ping Watchdog Counter Reset bit This bit will reset the ping watchdog counter to 0. Writing a 1 to this bit will reset the ping watchdog counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be.." "0,1" rgroup.word 0x2E++0x1 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_PING_TAG" hexmask.word.byte 0x0 1.--4. 1. "PING_TAG,Received Ping Frame Tag This field contains the 4-bit frame tag from the last successfully received ping frame. This is intentionally shifted into bits 4:1 so that the register can be used as a 32-bit address index based on the received tag." bitfld.word 0x0 0. "RESERVED,Zero bit This bit will always read as 0. This is intentionally provided to create a 32-bit offset if required. Using the PING_TAG and ZERO bits of this register (bits 4:0) application software can directly index into an array of 32-bit data." "0,1" group.long 0x30++0x3 line.long 0x0 "CONTROLSS_FSI1_RX3_RX_PING_WD_REF" hexmask.long 0x0 0.--31. 1. "PING_WD_REF,Ping Watchdog Counter Reference Value This is the 32-bit reference value for the ping watchdog timeout counter. The counter will count up starting from 0 and continue counting until this value is reached." rgroup.long 0x34++0x3 line.long 0x0 "CONTROLSS_FSI1_RX3_RX_PING_WD_CNT" hexmask.long 0x0 0.--31. 1. "PING_WD_CNT,Ping Watchdog Counter Value This is the 32-bit read-only register which shows the current value of the ping watchdog counter. This counter is reset to 0 in a variety of ways: A write to PING_WD_RST a match with PING_WD_REF or the reception.." group.word 0x38++0x5 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_INT1_CTRL_ALT1_" bitfld.word 0x0 14. "INT1_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt.." "0,1" bitfld.word 0x0 13. "INT1_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x0 12. "INT1_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x0 11. "INT1_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" bitfld.word 0x0 10. "INT1_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A.." "0,1" bitfld.word 0x0 9. "INT1_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" newline bitfld.word 0x0 8. "INT1_EN_ERR_FRAME,Enable ERROR Frame Received Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" bitfld.word 0x0 7. "INT1_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A.." "0,1" bitfld.word 0x0 6. "INT1_EN_FRAME_DONE,Enable Frame Done Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A frame.." "0,1" newline bitfld.word 0x0 5. "INT1_EN_OVERRUN,Enable Receive Buffer Overrun Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W).." "0,1" bitfld.word 0x0 4. "INT1_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = An.." "0,1" bitfld.word 0x0 3. "INT1_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A.." "0,1" newline bitfld.word 0x0 2. "INT1_EN_CRC_ERR,Enable CRC Error Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h (R/W) = A CRC error.." "0,1" bitfld.word 0x0 1. "INT1_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h.." "0,1" bitfld.word 0x0 0. "INT1_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT1 bit This is an enable register which decides whether an interrupt (RX_INT1) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT1. 1h.." "0,1" line.word 0x2 "CONTROLSS_FSI1_RX3_RX_INT2_CTRL_ALT1_" bitfld.word 0x2 14. "INT2_EN_ERROR_TAG_MATCH,Enable Error Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt.." "0,1" bitfld.word 0x2 13. "INT2_EN_DATA_TAG_MATCH,Enable Data Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" bitfld.word 0x2 12. "INT2_EN_PING_TAG_MATCH,Enable Ping Frame Received with Tag Match Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on.." "0,1" newline bitfld.word 0x2 11. "INT2_EN_DATA_FRAME,Enable Data Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W).." "0,1" bitfld.word 0x2 10. "INT2_EN_FRAME_OVERRUN,Enable Frame Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" bitfld.word 0x2 9. "INT2_EN_PING_FRAME,Enable Ping Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W).." "0,1" newline bitfld.word 0x2 8. "INT2_EN_ERR_FRAME,Enable Error Frame Received Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W).." "0,1" bitfld.word 0x2 7. "INT2_EN_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" bitfld.word 0x2 6. "INT2_EN_FRAME_DONE,Enable Frame Done Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A frame.." "0,1" newline bitfld.word 0x2 5. "INT2_EN_OVERRUN,Enable Buffer Overrun Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" bitfld.word 0x2 4. "INT2_EN_EOF_ERR,Enable End-of-Frame Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = An.." "0,1" bitfld.word 0x2 3. "INT2_EN_TYPE_ERR,Enable Frame Type Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A.." "0,1" newline bitfld.word 0x2 2. "INT2_EN_CRC_ERR,Enable CRC Error Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h (R/W) = A CRC error.." "0,1" bitfld.word 0x2 1. "INT2_EN_FRAME_WD_TO,Enable Frame Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h.." "0,1" bitfld.word 0x2 0. "INT2_EN_PING_WD_TO,Enable Ping Watchdog Timeout Interrupt to INT2 bit This is an enable register which decides whether an interrupt (RX_INT2) will be generated on the enabled event. 0h (R/W) = This event will not trigger an interrupt on RX_INT2. 1h.." "0,1" line.word 0x4 "CONTROLSS_FSI1_RX3_RX_LOCK_CTRL" hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key. In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the receive control registers that support a lock protection. Once locked further writes will not take effect until SYSRS unlocks the register. Once set further writes even to.." "0,1" group.long 0x40++0x3 line.long 0x0 "CONTROLSS_FSI1_RX3_RX_ECC_DATA" hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." group.word 0x44++0x1 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_ECC_VAL" hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,ECC Value for SEC-DED check This field contains the ECC value to be used for SEC-DED either for 16-bit or 32-bit data in the RX_ECC_DATA register." rgroup.long 0x48++0x3 line.long 0x0 "CONTROLSS_FSI1_RX3_RX_ECC_SEC_DATA" hexmask.long 0x0 0.--31. 1. "SEC_DATA,ECC Single Error Corrected Data The ECC corrected data will be available in this register. This value is valid only when there are no bit errors or a single bit error was detected. Otherwise the contents of this register are invalid and should.." rgroup.word 0x4C++0x1 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_ECC_LOG" bitfld.word 0x0 1. "MBE,Multiple Bit Errors Detected This bit indicates the occurrence of multiple bit errors.The data is corrupted and cannot be corrected. If this bit is set the data present in RX_ECC_SEC_DATA is invalid and should not be used. 0h (R) Multiple Bit.." "0,1" bitfld.word 0x0 0. "SBE,Single Bit Error Detected This bit indicates the occurrence of a single bit error in the data. The data is autocorrected and placed into the RX_ECC_SEC_DATA register. This bit is valid only if MBE is 0. 0h (R) No bit errors were detected. The value.." "0,1" group.word 0x50++0x3 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_FRAME_TAG_CMP" bitfld.word 0x0 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x0 8. "CMP_EN,Frame Tag Compare Enable bit Set this bit to enable the comparison of an incoming frame tag and the value stored in the frame tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming frame tag will trigger the.." "0,1" hexmask.word.byte 0x0 4.--7. 1. "TAG_MASK,Frame Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only for.." newline hexmask.word.byte 0x0 0.--3. 1. "TAG_REF,Frame Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming frame tag. This reference value is used only for non-ping frames." line.word 0x2 "CONTROLSS_FSI1_RX3_RX_PING_TAG_CMP" bitfld.word 0x2 9. "BROADCAST_EN,Broadcast Enable bit This will enable the reception of a ping frame broadcast. When this bit is set bit 3 of the received tag will be treated as a broadcast notification. If bit 3 of the received tag is set to 1 a ping tag match event will.." "0,1" bitfld.word 0x2 8. "CMP_EN,Ping Tag Compare Enable bit Set this bit to enable the comparison of an incoming ping tag and the value stored in the ping tag reference. A match caused by the comparison of TAG_MASK TAG_REF and the incoming ping tag will trigger a ping frame.." "0,1" hexmask.word.byte 0x2 4.--7. 1. "TAG_MASK,Ping Tag Mask Any bit position in this register set to 0 will be used in the comparison of the incoming ping frame tag and the value stored in TAG_REF. A bit position set to 1 will be ignored in the tag comparison. This mask value is used only.." newline hexmask.word.byte 0x2 0.--3. 1. "TAG_REF,Ping Tag Reference The reference tag to check against when comparing the TAG_MASK and the incoming ping tag. This reference value is used only for ping frames." group.long 0x58++0x7 line.long 0x0 "CONTROLSS_FSI1_RX3_RX_TRIG_CTRL_0" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "CONTROLSS_FSI1_RX3_RX_TRIG_WIDTH_0" hexmask.long.word 0x4 0.--15. 1. "RX_TRIG_WIDTH,This register decides the width(in SYSCLK cycles) of wide pulse output of the RX trigger module." group.word 0x60++0x1 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_DLYLINE_CTRL" hexmask.word.byte 0x0 10.--14. 1. "RXD1_DLY,Delay Line Tap Select for RXD1 This bitfield selects the number of delay elements inserted into the RXD1 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the RXD1 path. RXD1 is taken directly from.." hexmask.word.byte 0x0 5.--9. 1. "RXD0_DLY,Delay Line Tap Select for RXD0 This bitfield selects the number of delay elements inserted into the RXD0 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the RXD0 path. RXD0 is taken directly from.." hexmask.word.byte 0x0 0.--4. 1. "RXCLK_DLY,Delay Line Tap Select for RXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the RXCLK path. RXCLK is taken directly.." group.long 0x64++0xB line.long 0x0 "CONTROLSS_FSI1_RX3_RX_TRIG_CTRL_1" hexmask.long.tbyte 0x0 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x0 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x0 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x4 "CONTROLSS_FSI1_RX3_RX_TRIG_CTRL_2" hexmask.long.tbyte 0x4 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x4 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x4 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" line.long 0x8 "CONTROLSS_FSI1_RX3_RX_TRIG_CTRL_3" hexmask.long.tbyte 0x8 8.--31. 1. "RX_TRIG_DLY,This is the 24 bit count of the trigger delay in SYSCLK cycles. If enabled the Trigger-1 output of the trigger module will generate a 3 SYSCLK wide trigger pulse after the selected input trigger source sees a rising edge with a delay defined.." hexmask.long.byte 0x8 1.--4. 1. "TRIG_SEL,This is the mux select value which selects which of the inputs will be used as the trigger source." bitfld.long 0x8 0. "TRIG_EN,This is the enable for the RX output trigger generation. The output triggers will be generated only if this bit is set to 1. If this bit is 0 then no trigger will be generated by this module." "0,1" rgroup.long 0x70++0x3 line.long 0x0 "CONTROLSS_FSI1_RX3_RX_VIS_1" bitfld.long 0x0 3. "RX_CORE_STS,Receiver Core Status bit This bit indicates the status of the receiver core. If this bit is set the receiver should undergo a reset and subsequent resynchronization with the transmitter. This bit will be always be set when the receiver has.." "0,1" group.word 0x74++0x1 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_UDATA_FILTER" hexmask.word.byte 0x0 8.--15. 1. "UDATA_MASK,Bit Mask to be used for comparing the USERDATA field when filtering is enabled. Every bit that is '1' in this register will be masked for comparison. If a bit position is '1' then it will be considered a successful match for that bit position." hexmask.word.byte 0x0 0.--7. 1. "UDATA_REG,Reference to be used for comparing the USERDATA field when filtering is enabled." rgroup.word 0x80++0x1 line.word 0x0 "CONTROLSS_FSI1_RX3_RX_BUF_BASE" hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Receive Data Buffer Base Address This is the base address of the 16-word data buffer used by the receiver." tree.end tree "FSI1_TX2" base ad:0x502A0000 group.word 0x0++0x1 line.word 0x0 "CONTROLSS_FSI1_TX2_TX_MASTER_CTRL" hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key In order to write to any bit in this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x0 1. "FLUSH,Flush Operation Start bit This bit will cause the transmitter to initiate a flush pattern of a single toggle on the TXD0 and TXD1 followed by five full cycles of TXCLK. This bit should be written only when the CORE_RST bit is 0 and the clock to the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Transmitter Master Core Reset bit This bit controls the transmitter master core reset. In order to send any frame this bit must be cleared. 0h (R/W) = Transmitter core is not in reset and can transmit frames. 1h (R/W) = Transmitter core is.." "0,1" group.word 0x4++0x1 line.word 0x0 "CONTROLSS_FSI1_TX2_TX_CLK_CTRL" hexmask.word.byte 0x0 2.--9. 1. "PRESCALE_VAL,Clock Divider Prescale Value The input clock is divided by this 8-bit value and fed into the transmitter core. This divided clock is the rate at which TXCLK will operate. 0h (R/W) = Reserved 1h (R/W) = Input clock /1 2h (R/W) = Input clock.." bitfld.word 0x0 1. "CLK_EN,Clock Divider Enable bit This bit will enable and disable the input clock divider and start the clock to the transmitter core. 0h (R/W) = The input clock divider is not enabled and the clock is not connected to the transmitter core. 1h (R/W) =.." "0,1" bitfld.word 0x0 0. "CLK_RST,Clock Divider Reset bit This bit will reset the clock counter in the clock divider. 0h (R/W) = The clock divider is set based on the value in PRESCALE_VAL. The input clock will be divided by PRESCALE_VAL if CLK_EN is set. 1h (R/W) = The clock.." "0,1" group.word 0x8++0x9 line.word 0x0 "CONTROLSS_FSI1_TX2_TX_OPER_CTRL_LO_ALT2_" bitfld.word 0x0 10. "SEL_TDM_IN,Input TDM port Select bit This bit selects the input port for the transmitter core between the TDM input pins or the RX module. When this bit is '0' the inputs selected for TDM are from the TDM input pins. When this bit is '1' then inputs.." "0,1" bitfld.word 0x0 9. "TDM_ENABLE,Transmit TDM Mode Enable bit. This bit enables the TDM Mode for multi-slave TDM operation. 0h (R/W) Transmit TDM Mode is not enabled. 1h (R/W) Transmit TDM Mode is enabled." "0,1" bitfld.word 0x0 8. "SEL_PLLCLK,Input Clock Select bit This bit selects the input clock source for the transmitter core. 0h (R/W) = SYSCLK is the source of the transmitter clock into the clock prescaler. 1h (R/W) = PLLRAWCLK is the source of the transmitter core clock into.." "0,1" bitfld.word 0x0 7. "PING_TO_MODE,Ping Counter Reset Mode Select bit This bit selects when the ping counter will reset. 0h (R/W) = The ping counter will reset and restart only on hardware initiated ping frames when ping counter has timed out. 1h (R/W) = The ping counter.." "0,1" newline bitfld.word 0x0 6. "SW_CRC,CRC Source Select bit This bit selects the source of the CRC value that is transmitted. 0h (R/W) = The transmitted CRC value is computed by hardware. 1h (R/W) = The transmitted CRC value is sourced from the value programmed in the TX_USER_CRC.." "0,1" bitfld.word 0x0 3.--5. "START_MODE,Transmission Start Mode Select bit These bits select the method by which a new frame transmission is started. 0h (R/W) = Only a software write to TX_FRAME_CTRL.START initiate a new transmission. 1h (R/W) = The configured external trigger will.." "0,1,2,3,4,5,6,7" bitfld.word 0x0 2. "SPI_MODE,SPI Mode Select bit This bit enables and disables SPI compatibility mode. 0h (R/W) = FSI is in normal mode of operation. 1h (R/W) = FSI is operating in SPI compatibility mode." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Transmit Data Width Select bits These bits define the number of data lines used by the transmitter. 0h (R/W) = Data will be transmitted on one data line (TXD0) 1h (R/W) = Data will be transmitted on two data lines (TXD0 and TXD1). The format.." "0,1,2,3" line.word 0x2 "CONTROLSS_FSI1_TX2_TX_OPER_CTRL_HI_ALT1_" hexmask.word.byte 0x2 7.--12. 1. "EXT_TRIG_SEL,External Trigger Select bit These bits define which of the 64 external inputs will be used as the source for the external input trigger. 00h (R/W) = Trigger 1 is the source. 01h (R/W) = Trigger 2 is the source. 02h (R/W) = Trigger 3 is the.." bitfld.word 0x2 6. "ECC_SEL,ECC Data Width Select bit This bit selects between 16-bit and 32-bit ECC computation. 0h (R/W) = 32-bit ECC is used. 1h (R/W) = 16-bit ECC is used." "0,1" bitfld.word 0x2 5. "FORCE_ERR,Error Frame Force bit This bit will force the the CRC value of the transmitted data frame to 0 whenever there is a buffer overrun or underrun condition. This can be used to force a corrupted CRC as the data is not guaranteed to be reliable. The.." "0,1" line.word 0x4 "CONTROLSS_FSI1_TX2_TX_FRAME_CTRL" bitfld.word 0x4 15. "START,Start Transmission bit This bit will cause the FSI to start transmitting the next frame. 0h (R/W) = Writing a 0 to this bit will have no effect. 1h (R/W) = Start the next transmission. This bit will be cleared by hardware." "0,1" hexmask.word.byte 0x4 4.--7. 1. "N_WORDS,Number of Words to be Transmitted This field defines the number of words which will be transmitted in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the receiver. Set this bitfield to be one less than.." hexmask.word.byte 0x4 0.--3. 1. "FRAME_TYPE,Transmit Frame Type This field determines the type of frame that will be transmitted next. 0000b (R/W) = Ping Frame. This frame can be sent either by software or automatically by hardware. 0100b (R/W) = DATA_1_WORD Frame. One word data frame.." line.word 0x6 "CONTROLSS_FSI1_TX2_TX_FRAME_TAG_UDATA" hexmask.word.byte 0x6 8.--15. 1. "USER_DATA,User Data bits This is a user-defined value that will be loaded into the the user data phase of the frame. This 8-bit value can be used by the receiver for any application need. This value will not impact any hardware behavior." hexmask.word.byte 0x6 0.--3. 1. "FRAME_TAG,This will be used only for software initiated transmissions. Frame tag bits This is a user-defined value that will be loaded into the frame tag phase of the next transmission. The receiver may use the frame tag for any application need. This.." line.word 0x8 "CONTROLSS_FSI1_TX2_TX_BUF_PTR_LOAD" hexmask.word.byte 0x8 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load bits These bits are used to force the transmit buffer pointer to a desired index within the transmit buffer. The next transmission will begin picking data from this index and increment appropriately. This value will be.." rgroup.word 0x12++0x1 line.word 0x0 "CONTROLSS_FSI1_TX2_TX_BUF_PTR_STS" hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Remaining in the transmit buffer This value indicates the number of words present in the data buffer which have not yet been transmitted. This value is only valid when there is no active transmission. Note: This value will not be.." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x14++0x3 line.word 0x0 "CONTROLSS_FSI1_TX2_TX_PING_CTRL_ALT1_" hexmask.word.byte 0x0 3.--8. 1. "EXT_TRIG_SEL,External Trigger Select bits This bitfield will select one of the 64 external trigger inputs to as the source to generate a ping frame. A ping frame will only be generated if the EXT_TRIG_EN bit is set. 0h (R/W) = Trigger 1 will be used to.." bitfld.word 0x0 2. "EXT_TRIG_EN,External Trigger Enable bit This bit will allow the external trigger logic to generate a ping frame. 0h (R/W) = External triggers will not be used to generate ping frames. 1h (R/W) = The selected external trigger (selected by EXT_TRIG_SEL.." "0,1" bitfld.word 0x0 1. "TIMER_EN,Ping Timer Enable bit This bit will enable the ping timer for generating periodic ping frames. 0h (R/W) = The ping timer is disabled and will not generate ping frames. 1h (R/W) = The ping timer is enabled and can be used to generate ping.." "0,1" bitfld.word 0x0 0. "CNT_RST,Ping Counter Reset bit Writing a 1 to this bit will reset the ping counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be cleared to 0 to use the counter. 0h (R/W) = Clear the CNT_RST. 1h (R/W) = The.." "0,1" line.word 0x2 "CONTROLSS_FSI1_TX2_TX_PING_TAG" hexmask.word.byte 0x2 0.--3. 1. "TAG,Ping Frame Tag This field contains a 4-bit tag which will be sent in any ping frame that is initiated by an external trigger or the ping timer. This field is user-defined and can be set based on the application requirement. If a ping frame is.." group.long 0x18++0x3 line.long 0x0 "CONTROLSS_FSI1_TX2_TX_PING_TO_REF" hexmask.long 0x0 0.--31. 1. "TO_REF,Ping Timer Reference Value. This is the 32-bit reference value for the ping timer. The timer will increment the counter starting from 0. When the reference value is reached it will generate a timeout event triggering a ping frame transmission." rgroup.long 0x1C++0x3 line.long 0x0 "CONTROLSS_FSI1_TX2_TX_PING_TO_CNT" hexmask.long 0x0 0.--31. 1. "TO_CNT,Ping Timer Counter Value This register contains the current value of the ping timer counter. After reset this counter will increment until it reaches the reference value (TX_PING_TO_REF) at which point it generates a ping frame transmission." group.word 0x20++0x5 line.word 0x0 "CONTROLSS_FSI1_TX2_TX_INT_CTRL" bitfld.word 0x0 11. "INT2_EN_PING_TO,Enable PING Timer Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = The ping timer event will trigger an interrupt on TX_INT2." "0,1" bitfld.word 0x0 10. "INT2_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 9. "INT2_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 8. "INT2_EN_FRAME_DONE,Enable Frame Done interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = A Frame Done event will trigger an interrupt on TX_INT2." "0,1" newline bitfld.word 0x0 3. "INT1_EN_PING_TO,Enable Ping Timer Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = The ping timer event will trigger an interrupt on TX_INT1." "0,1" bitfld.word 0x0 2. "INT1_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 1. "INT1_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 0. "INT1_EN_FRAME_DONE,Enable Frame Done interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = A Frame Done event will trigger an interrupt on TX_INT1." "0,1" line.word 0x2 "CONTROLSS_FSI1_TX2_TX_DMA_CTRL" bitfld.word 0x2 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable the DMA event to be generated upon the completion of a transmit frame. 0h (R/W) = A DMA event will not be generated. 1h (R/W) = A DMA event will be generated upon the completion of a transmitted.." "0,1" line.word 0x4 "CONTROLSS_FSI1_TX2_TX_LOCK_CTRL" hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the transmit control registers that support a lock protection. Once locked further writes will not take effect until a SYSRS has reset this register. Once set further writes to.." "0,1" rgroup.word 0x28++0x1 line.word 0x0 "CONTROLSS_FSI1_TX2_TX_EVT_STS" bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Bit This bit indicates that a ping frame has been triggered. This bit is set by hardware when either the ping timer or an external trigger event have occured. Software can also force this bit to get set by writing.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Bit This bit inditcates that buffer overrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = Buffer Overrun has not occured. 1h (R) = Buffer Overrun has occured. To.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Bit This bit inditcates that buffer underrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = Buffer Underrun has not occured. 1h (R) = Buffer Underrun has.." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Bit This bit inditcates a Frame Done condition. This bit is set by hardware when a frame transmission has been completed. Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = Frame Done.." "0,1" wgroup.word 0x2C++0x3 line.word 0x0 "CONTROLSS_FSI1_TX2_TX_EVT_CLR" bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0." "0,1" line.word 0x2 "CONTROLSS_FSI1_TX2_TX_EVT_FRC" bitfld.word 0x2 3. "PING_TRIGGERED,Ping Frame Triggered Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 2. "BUF_OVERRUN,Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 1. "BUF_UNDERRUN,Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 0. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W) =.." "0,1" group.word 0x30++0x1 line.word 0x0 "CONTROLSS_FSI1_TX2_TX_USER_CRC" hexmask.word.byte 0x0 0.--7. 1. "USER_CRC,User-defined CRC This register contains the 8-bit CRC value to be transmitted in the next frame if the transmission is set for user-defined CRC option (TX_OPER_CTRL_LO.SW_CRC = 1). This register is ignored if the hardware CRC generation is.." group.long 0x40++0x3 line.long 0x0 "CONTROLSS_FSI1_TX2_TX_ECC_DATA" hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." rgroup.word 0x44++0x1 line.word 0x0 "CONTROLSS_FSI1_TX2_TX_ECC_VAL" hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value This field contains the ECC value computed using SEC-DED either for 16-bit or 32-bit data in the TX_ECC_DATA register." group.word 0x48++0x1 line.word 0x0 "CONTROLSS_FSI1_TX2_TX_DLYLINE_CTRL" hexmask.word.byte 0x0 10.--14. 1. "TXD1_DLY,Delay Line Tap Select for TXD1 This bitfield selects the number of delay elements inserted into the TXD1 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the TXD1 path. TXD1 is taken directly from.." hexmask.word.byte 0x0 5.--9. 1. "TXD0_DLY,Delay Line Tap Select for TXD0 This bitfield selects the number of delay elements inserted into the TXD0 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the TXD0 path. TXD0 is taken directly from.." hexmask.word.byte 0x0 0.--4. 1. "TXCLK_DLY,Delay Line Tap Select for TXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the TXCLK path. TXCLK is taken directly.." group.word 0x80++0x1 line.word 0x0 "CONTROLSS_FSI1_TX2_TX_BUF_BASE" hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Transmit Data Buffer Base Address This is the base address of the 16-word data buffer used by the transmitter." tree.end tree "FSI1_TX3" base ad:0x502A1000 group.word 0x0++0x1 line.word 0x0 "CONTROLSS_FSI1_TX3_TX_MASTER_CTRL" hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Key In order to write to any bit in this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x0 1. "FLUSH,Flush Operation Start bit This bit will cause the transmitter to initiate a flush pattern of a single toggle on the TXD0 and TXD1 followed by five full cycles of TXCLK. This bit should be written only when the CORE_RST bit is 0 and the clock to the.." "0,1" bitfld.word 0x0 0. "CORE_RST,Transmitter Master Core Reset bit This bit controls the transmitter master core reset. In order to send any frame this bit must be cleared. 0h (R/W) = Transmitter core is not in reset and can transmit frames. 1h (R/W) = Transmitter core is.." "0,1" group.word 0x4++0x1 line.word 0x0 "CONTROLSS_FSI1_TX3_TX_CLK_CTRL" hexmask.word.byte 0x0 2.--9. 1. "PRESCALE_VAL,Clock Divider Prescale Value The input clock is divided by this 8-bit value and fed into the transmitter core. This divided clock is the rate at which TXCLK will operate. 0h (R/W) = Reserved 1h (R/W) = Input clock /1 2h (R/W) = Input clock.." bitfld.word 0x0 1. "CLK_EN,Clock Divider Enable bit This bit will enable and disable the input clock divider and start the clock to the transmitter core. 0h (R/W) = The input clock divider is not enabled and the clock is not connected to the transmitter core. 1h (R/W) =.." "0,1" bitfld.word 0x0 0. "CLK_RST,Clock Divider Reset bit This bit will reset the clock counter in the clock divider. 0h (R/W) = The clock divider is set based on the value in PRESCALE_VAL. The input clock will be divided by PRESCALE_VAL if CLK_EN is set. 1h (R/W) = The clock.." "0,1" group.word 0x8++0x9 line.word 0x0 "CONTROLSS_FSI1_TX3_TX_OPER_CTRL_LO_ALT2_" bitfld.word 0x0 10. "SEL_TDM_IN,Input TDM port Select bit This bit selects the input port for the transmitter core between the TDM input pins or the RX module. When this bit is '0' the inputs selected for TDM are from the TDM input pins. When this bit is '1' then inputs.." "0,1" bitfld.word 0x0 9. "TDM_ENABLE,Transmit TDM Mode Enable bit. This bit enables the TDM Mode for multi-slave TDM operation. 0h (R/W) Transmit TDM Mode is not enabled. 1h (R/W) Transmit TDM Mode is enabled." "0,1" bitfld.word 0x0 8. "SEL_PLLCLK,Input Clock Select bit This bit selects the input clock source for the transmitter core. 0h (R/W) = SYSCLK is the source of the transmitter clock into the clock prescaler. 1h (R/W) = PLLRAWCLK is the source of the transmitter core clock into.." "0,1" bitfld.word 0x0 7. "PING_TO_MODE,Ping Counter Reset Mode Select bit This bit selects when the ping counter will reset. 0h (R/W) = The ping counter will reset and restart only on hardware initiated ping frames when ping counter has timed out. 1h (R/W) = The ping counter.." "0,1" newline bitfld.word 0x0 6. "SW_CRC,CRC Source Select bit This bit selects the source of the CRC value that is transmitted. 0h (R/W) = The transmitted CRC value is computed by hardware. 1h (R/W) = The transmitted CRC value is sourced from the value programmed in the TX_USER_CRC.." "0,1" bitfld.word 0x0 3.--5. "START_MODE,Transmission Start Mode Select bit These bits select the method by which a new frame transmission is started. 0h (R/W) = Only a software write to TX_FRAME_CTRL.START initiate a new transmission. 1h (R/W) = The configured external trigger will.." "0,1,2,3,4,5,6,7" bitfld.word 0x0 2. "SPI_MODE,SPI Mode Select bit This bit enables and disables SPI compatibility mode. 0h (R/W) = FSI is in normal mode of operation. 1h (R/W) = FSI is operating in SPI compatibility mode." "0,1" bitfld.word 0x0 0.--1. "DATA_WIDTH,Transmit Data Width Select bits These bits define the number of data lines used by the transmitter. 0h (R/W) = Data will be transmitted on one data line (TXD0) 1h (R/W) = Data will be transmitted on two data lines (TXD0 and TXD1). The format.." "0,1,2,3" line.word 0x2 "CONTROLSS_FSI1_TX3_TX_OPER_CTRL_HI_ALT1_" hexmask.word.byte 0x2 7.--12. 1. "EXT_TRIG_SEL,External Trigger Select bit These bits define which of the 64 external inputs will be used as the source for the external input trigger. 00h (R/W) = Trigger 1 is the source. 01h (R/W) = Trigger 2 is the source. 02h (R/W) = Trigger 3 is the.." bitfld.word 0x2 6. "ECC_SEL,ECC Data Width Select bit This bit selects between 16-bit and 32-bit ECC computation. 0h (R/W) = 32-bit ECC is used. 1h (R/W) = 16-bit ECC is used." "0,1" bitfld.word 0x2 5. "FORCE_ERR,Error Frame Force bit This bit will force the the CRC value of the transmitted data frame to 0 whenever there is a buffer overrun or underrun condition. This can be used to force a corrupted CRC as the data is not guaranteed to be reliable. The.." "0,1" line.word 0x4 "CONTROLSS_FSI1_TX3_TX_FRAME_CTRL" bitfld.word 0x4 15. "START,Start Transmission bit This bit will cause the FSI to start transmitting the next frame. 0h (R/W) = Writing a 0 to this bit will have no effect. 1h (R/W) = Start the next transmission. This bit will be cleared by hardware." "0,1" hexmask.word.byte 0x4 4.--7. 1. "N_WORDS,Number of Words to be Transmitted This field defines the number of words which will be transmitted in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the receiver. Set this bitfield to be one less than.." hexmask.word.byte 0x4 0.--3. 1. "FRAME_TYPE,Transmit Frame Type This field determines the type of frame that will be transmitted next. 0000b (R/W) = Ping Frame. This frame can be sent either by software or automatically by hardware. 0100b (R/W) = DATA_1_WORD Frame. One word data frame.." line.word 0x6 "CONTROLSS_FSI1_TX3_TX_FRAME_TAG_UDATA" hexmask.word.byte 0x6 8.--15. 1. "USER_DATA,User Data bits This is a user-defined value that will be loaded into the the user data phase of the frame. This 8-bit value can be used by the receiver for any application need. This value will not impact any hardware behavior." hexmask.word.byte 0x6 0.--3. 1. "FRAME_TAG,This will be used only for software initiated transmissions. Frame tag bits This is a user-defined value that will be loaded into the frame tag phase of the next transmission. The receiver may use the frame tag for any application need. This.." line.word 0x8 "CONTROLSS_FSI1_TX3_TX_BUF_PTR_LOAD" hexmask.word.byte 0x8 0.--3. 1. "BUF_PTR_LOAD,Buffer Pointer Load bits These bits are used to force the transmit buffer pointer to a desired index within the transmit buffer. The next transmission will begin picking data from this index and increment appropriately. This value will be.." rgroup.word 0x12++0x1 line.word 0x0 "CONTROLSS_FSI1_TX3_TX_BUF_PTR_STS" hexmask.word.byte 0x0 8.--12. 1. "CURR_WORD_CNT,Words Remaining in the transmit buffer This value indicates the number of words present in the data buffer which have not yet been transmitted. This value is only valid when there is no active transmission. Note: This value will not be.." hexmask.word.byte 0x0 0.--3. 1. "CURR_BUF_PTR,Current Buffer Pointer Index This bitfield will show the current index of the buffer pointer. This value is only valid when there is no active transmission." group.word 0x14++0x3 line.word 0x0 "CONTROLSS_FSI1_TX3_TX_PING_CTRL_ALT1_" hexmask.word.byte 0x0 3.--8. 1. "EXT_TRIG_SEL,External Trigger Select bits This bitfield will select one of the 64 external trigger inputs to as the source to generate a ping frame. A ping frame will only be generated if the EXT_TRIG_EN bit is set. 0h (R/W) = Trigger 1 will be used to.." bitfld.word 0x0 2. "EXT_TRIG_EN,External Trigger Enable bit This bit will allow the external trigger logic to generate a ping frame. 0h (R/W) = External triggers will not be used to generate ping frames. 1h (R/W) = The selected external trigger (selected by EXT_TRIG_SEL.." "0,1" bitfld.word 0x0 1. "TIMER_EN,Ping Timer Enable bit This bit will enable the ping timer for generating periodic ping frames. 0h (R/W) = The ping timer is disabled and will not generate ping frames. 1h (R/W) = The ping timer is enabled and can be used to generate ping.." "0,1" bitfld.word 0x0 0. "CNT_RST,Ping Counter Reset bit Writing a 1 to this bit will reset the ping counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be cleared to 0 to use the counter. 0h (R/W) = Clear the CNT_RST. 1h (R/W) = The.." "0,1" line.word 0x2 "CONTROLSS_FSI1_TX3_TX_PING_TAG" hexmask.word.byte 0x2 0.--3. 1. "TAG,Ping Frame Tag This field contains a 4-bit tag which will be sent in any ping frame that is initiated by an external trigger or the ping timer. This field is user-defined and can be set based on the application requirement. If a ping frame is.." group.long 0x18++0x3 line.long 0x0 "CONTROLSS_FSI1_TX3_TX_PING_TO_REF" hexmask.long 0x0 0.--31. 1. "TO_REF,Ping Timer Reference Value. This is the 32-bit reference value for the ping timer. The timer will increment the counter starting from 0. When the reference value is reached it will generate a timeout event triggering a ping frame transmission." rgroup.long 0x1C++0x3 line.long 0x0 "CONTROLSS_FSI1_TX3_TX_PING_TO_CNT" hexmask.long 0x0 0.--31. 1. "TO_CNT,Ping Timer Counter Value This register contains the current value of the ping timer counter. After reset this counter will increment until it reaches the reference value (TX_PING_TO_REF) at which point it generates a ping frame transmission." group.word 0x20++0x5 line.word 0x0 "CONTROLSS_FSI1_TX3_TX_INT_CTRL" bitfld.word 0x0 11. "INT2_EN_PING_TO,Enable PING Timer Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = The ping timer event will trigger an interrupt on TX_INT2." "0,1" bitfld.word 0x0 10. "INT2_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 9. "INT2_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 8. "INT2_EN_FRAME_DONE,Enable Frame Done interrupt to INT2 This bit allows the event to generate an interrupt on the INT2 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT2. 1h (R/W) = A Frame Done event will trigger an interrupt on TX_INT2." "0,1" newline bitfld.word 0x0 3. "INT1_EN_PING_TO,Enable Ping Timer Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = The ping timer event will trigger an interrupt on TX_INT1." "0,1" bitfld.word 0x0 2. "INT1_EN_BUF_OVERRUN,Enable Buffer Overrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = A Buffer Overrun condition will trigger an.." "0,1" bitfld.word 0x0 1. "INT1_EN_BUF_UNDERRUN,Enable Buffer Underrun Interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = A Buffer Underrun condition will trigger an.." "0,1" bitfld.word 0x0 0. "INT1_EN_FRAME_DONE,Enable Frame Done interrupt to INT1 This bit allows the event to generate an interrupt on the INT1 line. 0h (R/W) = This event will not trigger an interrupt on TX_INT1. 1h (R/W) = A Frame Done event will trigger an interrupt on TX_INT1." "0,1" line.word 0x2 "CONTROLSS_FSI1_TX3_TX_DMA_CTRL" bitfld.word 0x2 0. "DMA_EVT_EN,DMA Event Enable bit This bit will enable the DMA event to be generated upon the completion of a transmit frame. 0h (R/W) = A DMA event will not be generated. 1h (R/W) = A DMA event will be generated upon the completion of a transmitted.." "0,1" line.word 0x4 "CONTROLSS_FSI1_TX3_TX_LOCK_CTRL" hexmask.word.byte 0x4 8.--15. 1. "KEY,Write Key In order to write to this register 0xA5 must be written to this field at the same time. Otherwise writes are ignored. The key is cleared immediately after writing so it must be written again for every change to this register." bitfld.word 0x4 0. "LOCK,Control Register Lock Enable bit This bit locks the contents of all the transmit control registers that support a lock protection. Once locked further writes will not take effect until a SYSRS has reset this register. Once set further writes to.." "0,1" rgroup.word 0x28++0x1 line.word 0x0 "CONTROLSS_FSI1_TX3_TX_EVT_STS" bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Bit This bit indicates that a ping frame has been triggered. This bit is set by hardware when either the ping timer or an external trigger event have occured. Software can also force this bit to get set by writing.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Bit This bit inditcates that buffer overrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = Buffer Overrun has not occured. 1h (R) = Buffer Overrun has occured. To.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Bit This bit inditcates that buffer underrun has occured.Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = Buffer Underrun has not occured. 1h (R) = Buffer Underrun has.." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Bit This bit inditcates a Frame Done condition. This bit is set by hardware when a frame transmission has been completed. Software can also force this bit to get set by writing to the TX_EVT_FRC register. 0h (R) = Frame Done.." "0,1" wgroup.word 0x2C++0x3 line.word 0x0 "CONTROLSS_FSI1_TX3_TX_EVT_CLR" bitfld.word 0x0 3. "PING_TRIGGERED,Ping Frame Triggered Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the.." "0,1" bitfld.word 0x0 2. "BUF_OVERRUN,Buffer Overrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 1. "BUF_UNDERRUN,Buffer Underrun Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS.." "0,1" bitfld.word 0x0 0. "FRAME_DONE,Frame Done Flag Clear bit This bit clears the corresponding bit in the TX_EVT_STS register. 0h (W) = Writing a 0 to this bit will have no effect. 1h (W) = Writing a 1 to this bit will clear the corresponding bit in the TX_EVT_STS register to 0." "0,1" line.word 0x2 "CONTROLSS_FSI1_TX3_TX_EVT_FRC" bitfld.word 0x2 3. "PING_TRIGGERED,Ping Frame Triggered Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated.." "0,1" bitfld.word 0x2 2. "BUF_OVERRUN,Buffer Overrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 1. "BUF_UNDERRUN,Buffer Underrun Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h.." "0,1" bitfld.word 0x2 0. "FRAME_DONE,Frame Done Flag Force bit This bit will cause the corresponding bit in the TX_EVT_STS register to get set. The purpose of this register is to allow software to simulate the effect of the event and test the associated software/ISR. 0h (W) =.." "0,1" group.word 0x30++0x1 line.word 0x0 "CONTROLSS_FSI1_TX3_TX_USER_CRC" hexmask.word.byte 0x0 0.--7. 1. "USER_CRC,User-defined CRC This register contains the 8-bit CRC value to be transmitted in the next frame if the transmission is set for user-defined CRC option (TX_OPER_CTRL_LO.SW_CRC = 1). This register is ignored if the hardware CRC generation is.." group.long 0x40++0x3 line.long 0x0 "CONTROLSS_FSI1_TX3_TX_ECC_DATA" hexmask.long.word 0x0 16.--31. 1. "DATA_HIGH,Upper 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) the entire 32-bit register and update TX_ECC_VAL register with the results. Software should write to these 16 bits of the register in a.." hexmask.long.word 0x0 0.--15. 1. "DATA_LOW,Lower 16 bits of ECC Data Writing to this bitfield will cause the ECC logic to compute the ECC(SEC-DED) for these 16 bits and update the TX_ECC_VAL register with the results. Software should write to these register bits as a 16-bit write when.." rgroup.word 0x44++0x1 line.word 0x0 "CONTROLSS_FSI1_TX3_TX_ECC_VAL" hexmask.word.byte 0x0 0.--6. 1. "ECC_VAL,Computed ECC Value This field contains the ECC value computed using SEC-DED either for 16-bit or 32-bit data in the TX_ECC_DATA register." group.word 0x48++0x1 line.word 0x0 "CONTROLSS_FSI1_TX3_TX_DLYLINE_CTRL" hexmask.word.byte 0x0 10.--14. 1. "TXD1_DLY,Delay Line Tap Select for TXD1 This bitfield selects the number of delay elements inserted into the TXD1 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the TXD1 path. TXD1 is taken directly from.." hexmask.word.byte 0x0 5.--9. 1. "TXD0_DLY,Delay Line Tap Select for TXD0 This bitfield selects the number of delay elements inserted into the TXD0 path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the TXD0 path. TXD0 is taken directly from.." hexmask.word.byte 0x0 0.--4. 1. "TXCLK_DLY,Delay Line Tap Select for TXCLK This bitfield selects the number of delay elements inserted into the RXCLK path from the pin boundary to the receiver core. 0h (R/W) Zero delay elements are included in the TXCLK path. TXCLK is taken directly.." group.word 0x80++0x1 line.word 0x0 "CONTROLSS_FSI1_TX3_TX_BUF_BASE" hexmask.word 0x0 0.--15. 1. "BASE_ADDRESS,Transmit Data Buffer Base Address This is the base address of the 16-word data buffer used by the transmitter." tree.end tree.end tree.end tree "ICLXBAR" base ad:0x502D4000 rgroup.long 0x0++0x3 line.long 0x0 "CONTROLSS_ICLXBAR_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,Not Defined" hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,Not Defined" bitfld.long 0x0 8.--10. "PID_MAJOR,Not Defined" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "PID_CUSTOM,Not Defined" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,Not Defined" group.long 0x100++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR0_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar0 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR0_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar0 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR0_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar0 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x140++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR1_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar1 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR1_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar1 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR1_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar1 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x180++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR2_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar2 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR2_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar2 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR2_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar2 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x1C0++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR3_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar3 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR3_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar3 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR3_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar3 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x200++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR4_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar4 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR4_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar4 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR4_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar4 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x240++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR5_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar5 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR5_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar5 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR5_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar5 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x280++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR6_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar6 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR6_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar6 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR6_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar6 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x2C0++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR7_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar7 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR7_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar7 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR7_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar7 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x300++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR8_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar8 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR8_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar8 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR8_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar8 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x340++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR9_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar9 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR9_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar9 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR9_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar9 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x380++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR10_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar10 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR10_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar10 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR10_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar10 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x3C0++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR11_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar11 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR11_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar11 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR11_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar11 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x400++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR12_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar12 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR12_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar12 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR12_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar12 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x440++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR13_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar13 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR13_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar13 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR13_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar13 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x480++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR14_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar14 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR14_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar14 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR14_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar14 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x4C0++0xB line.long 0x0 "CONTROLSS_ICLXBAR_ICLXBAR15_G0" hexmask.long 0x0 0.--31. 1. "SEL,ICL XBar15 G0 input bit select. Input source is PWMA hr select1: PWMA hr bit[x] selected0: PWMA hr bit[x] is de-selected" line.long 0x4 "CONTROLSS_ICLXBAR_ICLXBAR15_G1" hexmask.long 0x4 0.--31. 1. "SEL,ICL XBar15 G1 input bit select. Input source is PWMB hr select1: PWMB hr bit[x] selected0: PWMB hr bit[x] is de-selected" line.long 0x8 "CONTROLSS_ICLXBAR_ICLXBAR15_G2" hexmask.long 0x8 0.--31. 1. "SEL,ICL XBar15 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" tree.end tree "INPUTXBAR" base ad:0x502D0000 rgroup.long 0x0++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,Not Defined" hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,Not Defined" bitfld.long 0x0 8.--10. "PID_MAJOR,Not Defined" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "PID_CUSTOM,Not Defined" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,Not Defined" group.long 0x100++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR0_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x104++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR0_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x108++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR0_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x140++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR1_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x144++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR1_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x148++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR1_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x180++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR2_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x184++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR2_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x188++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR2_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x1C0++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR3_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x1C4++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR3_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x1C8++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR3_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x200++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR4_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x204++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR4_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x208++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR4_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x240++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR5_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x244++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR5_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x248++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR5_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x280++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR6_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x284++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR6_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x288++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR6_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x2C0++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR7_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x2C4++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR7_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x2C8++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR7_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x300++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR8_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x304++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR8_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x308++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR8_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x340++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR9_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x344++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR9_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x348++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR9_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x380++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR10_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x384++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR10_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x388++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR10_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x3C0++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR11_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x3C4++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR11_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x3C8++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR11_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x400++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR12_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x404++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR12_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x408++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR12_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x440++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR13_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x444++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR13_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x448++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR13_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x480++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR14_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x484++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR14_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x488++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR14_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x4C0++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR15_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x4C4++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR15_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x4C8++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR15_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x500++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR16_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x504++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR16_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x508++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR16_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x540++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR17_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x544++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR17_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x548++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR17_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x580++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR18_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x584++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR18_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x588++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR18_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x5C0++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR19_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x5C4++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR19_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x5C8++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR19_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x600++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR20_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x604++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR20_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x608++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR20_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x640++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR21_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x644++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR21_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x648++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR21_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x680++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR22_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x684++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR22_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x688++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR22_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x6C0++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR23_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x6C4++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR23_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x6C8++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR23_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x700++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR24_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x704++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR24_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x708++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR24_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x740++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR25_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x744++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR25_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x748++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR25_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x780++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR26_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x784++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR26_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x788++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR26_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x7C0++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR27_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x7C4++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR27_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x7C8++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR27_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x800++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR28_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x804++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR28_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x808++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR28_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x840++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR29_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x844++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR29_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x848++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR29_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x880++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR30_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x884++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR30_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x888++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR30_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" group.long 0x8C0++0x3 line.long 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR31_GSEL" bitfld.long 0x0 0. "GSEL,Select input source Group:0 G0 selected1 G1 selected" "0,1" group.byte 0x8C4++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR31_G0" hexmask.byte 0x0 0.--7. 1. "SEL,Select input source:0 G0.0 selected..x G0.x selected" group.byte 0x8C8++0x0 line.byte 0x0 "CONTROLSS_INPUTXBAR_INPUTXBAR31_G1" hexmask.byte 0x0 0.--4. 1. "SEL,Select input source:0 G1.0 selected..31 G1.31 selected" tree.end tree "INTXBAR" base ad:0x502D5000 rgroup.long 0x0++0x3 line.long 0x0 "CONTROLSS_INTXBAR_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,Not Defined" hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,Not Defined" bitfld.long 0x0 8.--10. "PID_MAJOR,Not Defined" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "PID_CUSTOM,Not Defined" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,Not Defined" group.long 0x100++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR0_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR0_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR0_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x10C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR0_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x110++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR0_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x114++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR0_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x118++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR0_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x140++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR1_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR1_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR1_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x14C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR1_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x150++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR1_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x154++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR1_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x158++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR1_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x180++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR2_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR2_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR2_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x18C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR2_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x190++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR2_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x194++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR2_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x198++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR2_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x1C0++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR3_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR3_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR3_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x1CC++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR3_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x1D0++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR3_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x1D4++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR3_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x1D8++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR3_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x200++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR4_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR4_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR4_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x20C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR4_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x210++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR4_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x214++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR4_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x218++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR4_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x240++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR5_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR5_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR5_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x24C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR5_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x250++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR5_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x254++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR5_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x258++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR5_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x280++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR6_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR6_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR6_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x28C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR6_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x290++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR6_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x294++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR6_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x298++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR6_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x2C0++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR7_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR7_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR7_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x2CC++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR7_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x2D0++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR7_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x2D4++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR7_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x2D8++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR7_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x300++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR8_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR8_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR8_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x30C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR8_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x310++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR8_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x314++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR8_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x318++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR8_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x340++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR9_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR9_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR9_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x34C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR9_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x350++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR9_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x354++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR9_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x358++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR9_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x380++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR10_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR10_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR10_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x38C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR10_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x390++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR10_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x394++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR10_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x398++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR10_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x3C0++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR11_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR11_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR11_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x3CC++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR11_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x3D0++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR11_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x3D4++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR11_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x3D8++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR11_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x400++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR12_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR12_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR12_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x40C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR12_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x410++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR12_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x414++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR12_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x418++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR12_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x440++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR13_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR13_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR13_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x44C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR13_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x450++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR13_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x454++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR13_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x458++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR13_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x480++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR14_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR14_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR14_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x48C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR14_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x490++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR14_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x494++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR14_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x498++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR14_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x4C0++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR15_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR15_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR15_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x4CC++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR15_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x4D0++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR15_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x4D4++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR15_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x4D8++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR15_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x500++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR16_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR16_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR16_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x50C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR16_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x510++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR16_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x514++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR16_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x518++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR16_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x540++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR17_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR17_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR17_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x54C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR17_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x550++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR17_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x554++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR17_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x558++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR17_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x580++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR18_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR18_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR18_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x58C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR18_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x590++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR18_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x594++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR18_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x598++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR18_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x5C0++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR19_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR19_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR19_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x5CC++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR19_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x5D0++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR19_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x5D4++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR19_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x5D8++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR19_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x600++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR20_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR20_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR20_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x60C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR20_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x610++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR20_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x614++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR20_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x618++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR20_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x640++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR21_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR21_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR21_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x64C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR21_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x650++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR21_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x654++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR21_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x658++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR21_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x680++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR22_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR22_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR22_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x68C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR22_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x690++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR22_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x694++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR22_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x698++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR22_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x6C0++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR23_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR23_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR23_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x6CC++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR23_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x6D0++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR23_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x6D4++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR23_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x6D8++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR23_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x700++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR24_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR24_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR24_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x70C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR24_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x710++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR24_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x714++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR24_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x718++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR24_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x740++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR25_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR25_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR25_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x74C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR25_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x750++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR25_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x754++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR25_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x758++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR25_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x780++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR26_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR26_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR26_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x78C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR26_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x790++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR26_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x794++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR26_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x798++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR26_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x7C0++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR27_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR27_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR27_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x7CC++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR27_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x7D0++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR27_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x7D4++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR27_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x7D8++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR27_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x800++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR28_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR28_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR28_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x80C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR28_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x810++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR28_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x814++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR28_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x818++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR28_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x840++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR29_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR29_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR29_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x84C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR29_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x850++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR29_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x854++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR29_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x858++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR29_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x880++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR30_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR30_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR30_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x88C++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR30_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x890++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR30_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x894++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR30_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x898++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR30_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" group.long 0x8C0++0xB line.long 0x0 "CONTROLSS_INTXBAR_INTXBAR31_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM INT interrupt to corresponding xbar1: PWMx.INT is selected0: PWMx.INT is de-selected" line.long 0x4 "CONTROLSS_INTXBAR_INTXBAR31_G1" hexmask.long 0x4 0.--31. 1. "SEL,ETPWM TZINT interrupt to corresponding xbar1: PWMx.TZINT is selected0: PWMx.TZINT is de-selected" line.long 0x8 "CONTROLSS_INTXBAR_INTXBAR31_G2" hexmask.long 0x8 0.--24. 1. "SEL,Corresponding INT XBar G2 Input Select0: ADC0.INT11: ADC0.INT22: ADC0.INT33: ADC0.INT44: ADC0.EVTINT5: ADC1.INT16: ADC1.INT27: ADC1.INT38: ADC1.INT49: ADC1.EVTINT10: ADC2.INT111: ADC2.INT212: ADC2.INT313: ADC2.INT414: ADC2.EVTINT15: ADC3.INT116:.." group.word 0x8CC++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR31_G3" hexmask.word 0x0 0.--15. 1. "SEL,Corresponding INT XBar G3 Input Select0: FSIRX0.INT1N1: FSIRX0.INT2N2: FSIRX1.INT1N3: FSIRX1.INT2N4: FSIRX2.INT1N5: FSIRX2.INT2N6: FSIRX3.INT1N7: FSIRX3.INT2N8: FSITX0.INT1N9: FSITX0.INT2N10: FSITX1.INT1N11: FSITX1.INT2N12: FSITX2.INT1N13:.." group.word 0x8D0++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR31_G4" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G4 Input Select0: SD0.ERR1: SD0.FILT1.DRINT2: SD0.FILT2.DRINT3: SD0.FILT3.DRINT4: SD0.FILT4.DRINT5: SD1.ERR6: SD1.FILT1.DRINT7: SD1.FILT2.DRINT8: SD1.FILT3.DRINT9: SD1.FILT4.DRINT" group.word 0x8D4++0x1 line.word 0x0 "CONTROLSS_INTXBAR_INTXBAR31_G5" hexmask.word 0x0 0.--9. 1. "SEL,Corresponding INT XBar G5 Input Select0: ECAP0.INT1: ECAP1.INT2: ECAP2.INT3: ECAP3.INT4: ECAP4.INT5: ECAP5.INT6: ECAP6.INT7: ECAP7.INT8: ECAP8.INT9: ECAP9.INT" group.byte 0x8D8++0x0 line.byte 0x0 "CONTROLSS_INTXBAR_INTXBAR31_G6" bitfld.byte 0x0 0.--2. "SEL,Corresponding INT XBar G6 Input Select0: EQEP0.INT1: EQEP1.INT2: EQEP2.INT" "0,1,2,3,4,5,6,7" tree.end tree "MDLXBAR" base ad:0x502D3000 rgroup.long 0x0++0x3 line.long 0x0 "CONTROLSS_MDLXBAR_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,Not Defined" hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,Not Defined" bitfld.long 0x0 8.--10. "PID_MAJOR,Not Defined" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "PID_CUSTOM,Not Defined" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,Not Defined" group.long 0x100++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR0_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar0 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR0_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar0 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR0_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar0 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x140++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR1_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar1 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR1_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar1 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR1_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar1 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x180++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR2_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar2 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR2_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar2 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR2_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar2 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x1C0++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR3_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar3 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR3_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar3 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR3_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar3 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x200++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR4_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar4 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR4_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar4 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR4_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar4 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x240++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR5_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar5 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR5_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar5 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR5_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar5 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x280++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR6_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar6 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR6_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar6 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR6_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar6 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x2C0++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR7_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar7 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR7_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar7 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR7_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar7 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x300++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR8_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar8 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR8_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar8 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR8_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar8 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x340++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR9_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar9 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR9_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar9 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR9_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar9 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x380++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR10_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar10 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR10_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar10 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR10_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar10 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x3C0++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR11_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar11 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR11_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar11 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR11_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar11 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x400++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR12_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar12 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR12_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar12 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR12_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar12 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x440++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR13_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar13 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR13_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar13 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR13_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar13 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x480++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR14_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar14 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR14_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar14 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR14_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar14 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" group.long 0x4C0++0xB line.long 0x0 "CONTROLSS_MDLXBAR_MDLXBAR15_G0" hexmask.long 0x0 0.--31. 1. "SEL,MDL XBar15 G0 input bit select. Input source is PWMA sclk select1: PWMA sclk bit[x] selected0: PWMA sclk bit[x] is de-selected" line.long 0x4 "CONTROLSS_MDLXBAR_MDLXBAR15_G1" hexmask.long 0x4 0.--31. 1. "SEL,MDL XBar15 G1 input bit select. Input source is PWMB sclk select1: PWMB sclk bit[x] selected0: PWMB sclk bit[x] is de-selected" line.long 0x8 "CONTROLSS_MDLXBAR_MDLXBAR15_G2" hexmask.long 0x8 0.--31. 1. "SEL,MDL XBar15 G2 input bit select. Input source is ICSS GPO selecty=0 when x =0 to 15 y=1 when x=16 to 311: ICSS_PORT[y].GPO[x] selected.0: ICSS_PORT[y].GPO[x] is de-selected" tree.end base ad:0x0 tree "OTTOCAL" tree "OTTOCAL0" base ad:0x502E0000 group.word 0x42++0xB line.word 0x0 "CONTROLSS_OTTOCAL0_HRPWR" bitfld.word 0x0 15. "CALPWRON,MEP Calibration Power Bits (only available on ePWM1) 0: Disables MEP calibration logic in the HRPWM and reduces power consumption. 1: Enables MEP calibration logic" "0: Disables MEP calibration logic in the HRPWM and..,1: Enables MEP calibration logic" hexmask.word.byte 0x0 6.--9. 1. "CALSEL,EPWM Delay Line Selection for Calibration:" bitfld.word 0x0 5. "TESTSEL,Test Mode Select Bit: This bit selects if a dummy delay is added in Oscillator Calibration mode to help reducing frequency when small delays are used:" "0,1" rbitfld.word 0x0 4. "CALSTS,Calibration Status Bit: This bit when set to 1 indicates that calibration is in progress. It is set to 0 when:" "0,1" bitfld.word 0x0 3. "CNTSEL,Counter Select Bit: Functionality of this bit has changed. When HRCNT0 or HRCNT1 reaches 0xFFFF both counters are frozen. This bit will have an effect on when calibration starts:" "0,1" bitfld.word 0x0 2. "CALSTART,Calibration Start/Stop Bit:" "0,1" newline bitfld.word 0x0 0.--1. "CALMODE,Note: CALMODE bits in HRPWM Module. Not used here." "0,1,2,3" line.word 0x2 "CONTROLSS_OTTOCAL0_HRCAL" hexmask.word.byte 0x2 0.--7. 1. "HRCAL,These 8-bits are used to select the number of delay elements during oscillator calibration for the calibration delay line (DCAL) only. The user configures the desired delay and then initiates a calibration run. Based on the calibration run result .." line.word 0x4 "CONTROLSS_OTTOCAL0_HRPRD" hexmask.word 0x4 0.--15. 1. "HRPRD,These 8-bits are used to select the number of delay elements during oscillator calibration for the calibration delay line (DCAL) only." line.word 0x6 "CONTROLSS_OTTOCAL0_HRCNT0" hexmask.word 0x6 0.--15. 1. "HRCNT0,The HRCNT0 counter increments on every ring oscillator clock pulse." line.word 0x8 "CONTROLSS_OTTOCAL0_HRCNT1" hexmask.word 0x8 0.--15. 1. "HRCNT1,The HRCNT1 counter increments on every system clock pulse." line.word 0xA "CONTROLSS_OTTOCAL0_HRMSTEP" hexmask.word.byte 0xA 0.--7. 1. "HRMSTEP,High Resolution MEP Step When auto-conversion is enabled (HRCNFG[AUTOCONV] = 1) This 8-bit field contains the MEP_ScaleFactor (number of MEP steps per coarse steps) used by the hardware to automatically convert the value in the CMPAHR CMPBHR .." tree.end tree "OTTOCAL1" base ad:0x502E1000 group.word 0x42++0xB line.word 0x0 "CONTROLSS_OTTOCAL1_HRPWR" bitfld.word 0x0 15. "CALPWRON,MEP Calibration Power Bits (only available on ePWM1) 0: Disables MEP calibration logic in the HRPWM and reduces power consumption. 1: Enables MEP calibration logic" "0: Disables MEP calibration logic in the HRPWM and..,1: Enables MEP calibration logic" hexmask.word.byte 0x0 6.--9. 1. "CALSEL,EPWM Delay Line Selection for Calibration:" bitfld.word 0x0 5. "TESTSEL,Test Mode Select Bit: This bit selects if a dummy delay is added in Oscillator Calibration mode to help reducing frequency when small delays are used:" "0,1" rbitfld.word 0x0 4. "CALSTS,Calibration Status Bit: This bit when set to 1 indicates that calibration is in progress. It is set to 0 when:" "0,1" bitfld.word 0x0 3. "CNTSEL,Counter Select Bit: Functionality of this bit has changed. When HRCNT0 or HRCNT1 reaches 0xFFFF both counters are frozen. This bit will have an effect on when calibration starts:" "0,1" bitfld.word 0x0 2. "CALSTART,Calibration Start/Stop Bit:" "0,1" newline bitfld.word 0x0 0.--1. "CALMODE,Note: CALMODE bits in HRPWM Module. Not used here." "0,1,2,3" line.word 0x2 "CONTROLSS_OTTOCAL1_HRCAL" hexmask.word.byte 0x2 0.--7. 1. "HRCAL,These 8-bits are used to select the number of delay elements during oscillator calibration for the calibration delay line (DCAL) only. The user configures the desired delay and then initiates a calibration run. Based on the calibration run result .." line.word 0x4 "CONTROLSS_OTTOCAL1_HRPRD" hexmask.word 0x4 0.--15. 1. "HRPRD,These 8-bits are used to select the number of delay elements during oscillator calibration for the calibration delay line (DCAL) only." line.word 0x6 "CONTROLSS_OTTOCAL1_HRCNT0" hexmask.word 0x6 0.--15. 1. "HRCNT0,The HRCNT0 counter increments on every ring oscillator clock pulse." line.word 0x8 "CONTROLSS_OTTOCAL1_HRCNT1" hexmask.word 0x8 0.--15. 1. "HRCNT1,The HRCNT1 counter increments on every system clock pulse." line.word 0xA "CONTROLSS_OTTOCAL1_HRMSTEP" hexmask.word.byte 0xA 0.--7. 1. "HRMSTEP,High Resolution MEP Step When auto-conversion is enabled (HRCNFG[AUTOCONV] = 1) This 8-bit field contains the MEP_ScaleFactor (number of MEP steps per coarse steps) used by the hardware to automatically convert the value in the CMPAHR CMPBHR .." tree.end tree "OTTOCAL2" base ad:0x502E2000 group.word 0x42++0xB line.word 0x0 "CONTROLSS_OTTOCAL2_HRPWR" bitfld.word 0x0 15. "CALPWRON,MEP Calibration Power Bits (only available on ePWM1) 0: Disables MEP calibration logic in the HRPWM and reduces power consumption. 1: Enables MEP calibration logic" "0: Disables MEP calibration logic in the HRPWM and..,1: Enables MEP calibration logic" hexmask.word.byte 0x0 6.--9. 1. "CALSEL,EPWM Delay Line Selection for Calibration:" bitfld.word 0x0 5. "TESTSEL,Test Mode Select Bit: This bit selects if a dummy delay is added in Oscillator Calibration mode to help reducing frequency when small delays are used:" "0,1" rbitfld.word 0x0 4. "CALSTS,Calibration Status Bit: This bit when set to 1 indicates that calibration is in progress. It is set to 0 when:" "0,1" bitfld.word 0x0 3. "CNTSEL,Counter Select Bit: Functionality of this bit has changed. When HRCNT0 or HRCNT1 reaches 0xFFFF both counters are frozen. This bit will have an effect on when calibration starts:" "0,1" bitfld.word 0x0 2. "CALSTART,Calibration Start/Stop Bit:" "0,1" newline bitfld.word 0x0 0.--1. "CALMODE,Note: CALMODE bits in HRPWM Module. Not used here." "0,1,2,3" line.word 0x2 "CONTROLSS_OTTOCAL2_HRCAL" hexmask.word.byte 0x2 0.--7. 1. "HRCAL,These 8-bits are used to select the number of delay elements during oscillator calibration for the calibration delay line (DCAL) only. The user configures the desired delay and then initiates a calibration run. Based on the calibration run result .." line.word 0x4 "CONTROLSS_OTTOCAL2_HRPRD" hexmask.word 0x4 0.--15. 1. "HRPRD,These 8-bits are used to select the number of delay elements during oscillator calibration for the calibration delay line (DCAL) only." line.word 0x6 "CONTROLSS_OTTOCAL2_HRCNT0" hexmask.word 0x6 0.--15. 1. "HRCNT0,The HRCNT0 counter increments on every ring oscillator clock pulse." line.word 0x8 "CONTROLSS_OTTOCAL2_HRCNT1" hexmask.word 0x8 0.--15. 1. "HRCNT1,The HRCNT1 counter increments on every system clock pulse." line.word 0xA "CONTROLSS_OTTOCAL2_HRMSTEP" hexmask.word.byte 0xA 0.--7. 1. "HRMSTEP,High Resolution MEP Step When auto-conversion is enabled (HRCNFG[AUTOCONV] = 1) This 8-bit field contains the MEP_ScaleFactor (number of MEP steps per coarse steps) used by the hardware to automatically convert the value in the CMPAHR CMPBHR .." tree.end tree "OTTOCAL3" base ad:0x502E3000 group.word 0x42++0xB line.word 0x0 "CONTROLSS_OTTOCAL3_HRPWR" bitfld.word 0x0 15. "CALPWRON,MEP Calibration Power Bits (only available on ePWM1) 0: Disables MEP calibration logic in the HRPWM and reduces power consumption. 1: Enables MEP calibration logic" "0: Disables MEP calibration logic in the HRPWM and..,1: Enables MEP calibration logic" hexmask.word.byte 0x0 6.--9. 1. "CALSEL,EPWM Delay Line Selection for Calibration:" bitfld.word 0x0 5. "TESTSEL,Test Mode Select Bit: This bit selects if a dummy delay is added in Oscillator Calibration mode to help reducing frequency when small delays are used:" "0,1" rbitfld.word 0x0 4. "CALSTS,Calibration Status Bit: This bit when set to 1 indicates that calibration is in progress. It is set to 0 when:" "0,1" bitfld.word 0x0 3. "CNTSEL,Counter Select Bit: Functionality of this bit has changed. When HRCNT0 or HRCNT1 reaches 0xFFFF both counters are frozen. This bit will have an effect on when calibration starts:" "0,1" bitfld.word 0x0 2. "CALSTART,Calibration Start/Stop Bit:" "0,1" newline bitfld.word 0x0 0.--1. "CALMODE,Note: CALMODE bits in HRPWM Module. Not used here." "0,1,2,3" line.word 0x2 "CONTROLSS_OTTOCAL3_HRCAL" hexmask.word.byte 0x2 0.--7. 1. "HRCAL,These 8-bits are used to select the number of delay elements during oscillator calibration for the calibration delay line (DCAL) only. The user configures the desired delay and then initiates a calibration run. Based on the calibration run result .." line.word 0x4 "CONTROLSS_OTTOCAL3_HRPRD" hexmask.word 0x4 0.--15. 1. "HRPRD,These 8-bits are used to select the number of delay elements during oscillator calibration for the calibration delay line (DCAL) only." line.word 0x6 "CONTROLSS_OTTOCAL3_HRCNT0" hexmask.word 0x6 0.--15. 1. "HRCNT0,The HRCNT0 counter increments on every ring oscillator clock pulse." line.word 0x8 "CONTROLSS_OTTOCAL3_HRCNT1" hexmask.word 0x8 0.--15. 1. "HRCNT1,The HRCNT1 counter increments on every system clock pulse." line.word 0xA "CONTROLSS_OTTOCAL3_HRMSTEP" hexmask.word.byte 0xA 0.--7. 1. "HRMSTEP,High Resolution MEP Step When auto-conversion is enabled (HRCNFG[AUTOCONV] = 1) This 8-bit field contains the MEP_ScaleFactor (number of MEP steps per coarse steps) used by the hardware to automatically convert the value in the CMPAHR CMPBHR .." tree.end tree.end tree "OUTPUTXBAR" base ad:0x502D8000 rgroup.long 0x0++0x3 line.long 0x0 "CONTROLSS_OUTPUTXBAR_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,Not Defined" hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,Not Defined" bitfld.long 0x0 8.--10. "PID_MAJOR,Not Defined" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "PID_CUSTOM,Not Defined" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,Not Defined" rgroup.word 0x10++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_STATUS" hexmask.word 0x0 0.--15. 1. "STS,Status" group.word 0x14++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAGINVERT" hexmask.word 0x0 0.--15. 1. "INVERT,FlagInvert" group.word 0x18++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAG" bitfld.word 0x0 15. "BIT15,output xbar flag" "0,1" bitfld.word 0x0 14. "BIT14,output xbar flag" "0,1" bitfld.word 0x0 13. "BIT13,output xbar flag" "0,1" bitfld.word 0x0 12. "BIT12,output xbar flag" "0,1" bitfld.word 0x0 11. "BIT11,output xbar flag" "0,1" bitfld.word 0x0 10. "BIT10,output xbar flag" "0,1" newline bitfld.word 0x0 9. "BIT9,output xbar flag" "0,1" bitfld.word 0x0 8. "BIT8,output xbar flag" "0,1" bitfld.word 0x0 7. "BIT7,output xbar flag" "0,1" bitfld.word 0x0 6. "BIT6,output xbar flag" "0,1" bitfld.word 0x0 5. "BIT5,output xbar flag" "0,1" bitfld.word 0x0 4. "BIT4,output xbar flag" "0,1" newline bitfld.word 0x0 3. "BIT3,output xbar flag" "0,1" bitfld.word 0x0 2. "BIT2,output xbar flag" "0,1" bitfld.word 0x0 1. "BIT1,output xbar flag" "0,1" bitfld.word 0x0 0. "BIT0,output xbar flag" "0,1" group.word 0x1C++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAG_CLR" bitfld.word 0x0 15. "BIT15,output xbar flag clear" "0,1" bitfld.word 0x0 14. "BIT14,output xbar flag clear" "0,1" bitfld.word 0x0 13. "BIT13,output xbar flag clear" "0,1" bitfld.word 0x0 12. "BIT12,output xbar flag clear" "0,1" bitfld.word 0x0 11. "BIT11,output xbar flag clear" "0,1" bitfld.word 0x0 10. "BIT10,output xbar flag clear" "0,1" newline bitfld.word 0x0 9. "BIT9,output xbar flag clear" "0,1" bitfld.word 0x0 8. "BIT8,output xbar flag clear" "0,1" bitfld.word 0x0 7. "BIT7,output xbar flag clear" "0,1" bitfld.word 0x0 6. "BIT6,output xbar flag clear" "0,1" bitfld.word 0x0 5. "BIT5,output xbar flag clear" "0,1" bitfld.word 0x0 4. "BIT4,output xbar flag clear" "0,1" newline bitfld.word 0x0 3. "BIT3,output xbar flag clear" "0,1" bitfld.word 0x0 2. "BIT2,output xbar flag clear" "0,1" bitfld.word 0x0 1. "BIT1,output xbar flag clear" "0,1" bitfld.word 0x0 0. "BIT0,output xbar flag clear" "0,1" group.word 0x20++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_FLAGFORCE" hexmask.word 0x0 0.--15. 1. "FRC,FlagForce" group.word 0x24++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTLATCH" hexmask.word 0x0 0.--15. 1. "LATCHSEL,OutLatch" group.word 0x28++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTSTRETCH" hexmask.word 0x0 0.--15. 1. "STRETCHSEL,OutStretch" group.word 0x2C++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTLENGTH" hexmask.word 0x0 0.--15. 1. "LENGTHSEL,OutLength" group.word 0x30++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR_OUTINVERT" hexmask.word 0x0 0.--15. 1. "OUTINVERT,OutInvert" group.long 0x100++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar0 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar0 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar0 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar0 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar0 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x114++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar0 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x118++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar0 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x11C++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar0 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x120++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar0 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x124++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar0 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x128++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR0_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar0 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" group.long 0x140++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR1_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar1 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR1_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar1 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR1_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar1 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR1_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar1 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR1_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar1 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x154++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR1_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar1 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x158++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR1_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar1 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x15C++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR1_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar1 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x160++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR1_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar1 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x164++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR1_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar1 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x168++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR1_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar1 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" group.long 0x180++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR2_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar2 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR2_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar2 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR2_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar2 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR2_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar2 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR2_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar2 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x194++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR2_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar2 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x198++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR2_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar2 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x19C++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR2_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar2 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x1A0++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR2_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar2 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x1A4++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR2_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar2 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x1A8++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR2_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar2 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" group.long 0x1C0++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR3_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar3 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR3_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar3 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR3_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar3 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR3_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar3 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR3_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar3 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x1D4++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR3_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar3 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x1D8++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR3_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar3 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x1DC++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR3_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar3 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x1E0++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR3_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar3 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x1E4++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR3_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar3 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x1E8++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR3_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar3 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" group.long 0x200++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR4_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar4 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR4_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar4 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR4_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar4 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR4_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar4 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR4_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar4 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x214++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR4_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar4 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x218++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR4_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar4 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x21C++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR4_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar4 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x220++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR4_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar4 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x224++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR4_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar4 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x228++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR4_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar4 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" group.long 0x240++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR5_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar5 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR5_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar5 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR5_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar5 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR5_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar5 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR5_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar5 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x254++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR5_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar5 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x258++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR5_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar5 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x25C++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR5_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar5 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x260++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR5_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar5 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x264++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR5_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar5 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x268++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR5_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar5 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" group.long 0x280++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR6_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar6 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR6_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar6 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR6_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar6 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR6_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar6 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR6_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar6 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x294++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR6_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar6 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x298++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR6_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar6 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x29C++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR6_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar6 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x2A0++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR6_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar6 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x2A4++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR6_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar6 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x2A8++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR6_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar6 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" group.long 0x2C0++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR7_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar7 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR7_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar7 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR7_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar7 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR7_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar7 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR7_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar7 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x2D4++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR7_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar7 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x2D8++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR7_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar7 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x2DC++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR7_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar7 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x2E0++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR7_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar7 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x2E4++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR7_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar7 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x2E8++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR7_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar7 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" group.long 0x300++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR8_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar8 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR8_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar8 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR8_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar8 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR8_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar8 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR8_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar8 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x314++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR8_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar8 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x318++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR8_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar8 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x31C++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR8_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar8 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x320++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR8_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar8 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x324++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR8_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar8 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x328++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR8_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar8 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" group.long 0x340++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR9_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar9 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR9_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar9 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR9_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar9 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR9_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar9 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR9_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar9 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x354++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR9_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar9 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x358++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR9_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar9 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x35C++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR9_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar9 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x360++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR9_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar9 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x364++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR9_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar9 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x368++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR9_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar9 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" group.long 0x380++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR10_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar10 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR10_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar10 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR10_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar10 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR10_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar10 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR10_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar10 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x394++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR10_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar10 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x398++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR10_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar10 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x39C++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR10_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar10 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x3A0++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR10_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar10 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x3A4++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR10_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar10 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x3A8++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR10_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar10 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" group.long 0x3C0++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR11_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar11 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR11_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar11 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR11_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar11 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR11_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar11 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR11_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar11 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x3D4++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR11_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar11 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x3D8++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR11_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar11 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x3DC++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR11_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar11 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x3E0++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR11_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar11 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x3E4++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR11_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar11 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x3E8++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR11_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar11 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" group.long 0x400++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR12_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar12 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR12_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar12 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR12_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar12 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR12_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar12 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR12_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar12 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x414++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR12_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar12 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x418++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR12_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar12 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x41C++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR12_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar12 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x420++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR12_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar12 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x424++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR12_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar12 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x428++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR12_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar12 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" group.long 0x440++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR13_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar13 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR13_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar13 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR13_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar13 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR13_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar13 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR13_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar13 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x454++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR13_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar13 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x458++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR13_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar13 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x45C++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR13_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar13 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x460++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR13_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar13 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x464++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR13_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar13 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x468++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR13_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar13 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" group.long 0x480++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR14_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar14 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR14_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar14 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR14_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar14 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR14_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar14 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR14_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar14 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x494++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR14_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar14 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x498++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR14_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar14 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x49C++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR14_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar14 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x4A0++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR14_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar14 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x4A4++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR14_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar14 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x4A8++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR14_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar14 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" group.long 0x4C0++0x13 line.long 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR15_G0" hexmask.long 0x0 0.--31. 1. "SEL,G0: PWM XBar15 G0 input bit select. Input source is PWM[x].TRIPOUT1: PWM[x] TRIPOUT selected0: PWM[x] TRIPOUT is de-selected" line.long 0x4 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR15_G1" hexmask.long 0x4 0.--31. 1. "SEL,G1: OUTPUT XBar15 G1 input bit select. Input source is PWM[x].SOCA1: PWM[x] SOCA selected0: PWM[x] SOCA is de-selected" line.long 0x8 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR15_G2" hexmask.long 0x8 0.--31. 1. "SEL,G2: OUTPUT XBar15 G2 input bit select. Input source is PWM[x].SOCB1: PWM[x] SOCB selected0: PWM[x] SOCB is de-selected" line.long 0xC "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR15_G3" hexmask.long 0xC 0.--31. 1. "SEL,G3: OUTPUT XBar15 G3 input bit select. Input source is DEL[x].ACTIVE1: DEL[x] ACTIVE selected0: DEL[x] ACTIVE is de-selected" line.long 0x10 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR15_G4" hexmask.long 0x10 0.--31. 1. "SEL,G4: OUTPUT XBar15 G4 input bit select. Input source is DEL[x].TRIP1: DEL[x] TRIP selected0: DEL[x] TRIP is de-selected" group.tbyte 0x4D4++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR15_G5" hexmask.tbyte 0x0 0.--23. 1. "SEL,G5: OUTPUT XBar15 G5 input bit select.0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110:.." group.tbyte 0x4D8++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR15_G6" hexmask.tbyte 0x0 0.--19. 1. "SEL,G6: OUTPUT XBar15 G6 Input Select0: CMP12SS0.CTRIPOUTL1: CMP12SS0.CTRIPOUTH2: CMP12SS1.CTRIPOUTL3: CMP12SS1.CTRIPOUTH4: CMP12SS2.CTRIPOUTL5: CMP12SS2.CTRIPOUTH6: CMP12SS3.CTRIPOUTL7: CMP12SS3.CTRIPOUTH8: CMP12SS4.CTRIPOUTL9: CMP12SS4.CTRIPOUTH10:.." group.tbyte 0x4DC++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR15_G7" hexmask.tbyte 0x0 0.--19. 1. "SEL,G7: OUTPUT XBar15 G7 Input Select0: CMP8SS0.CTRIPOUTL1: CMP8SS0.CTRIPOUTH2: CMP8SS1.CTRIPOUTL3: CMP8SS1.CTRIPOUTH4: CMP8SS2.CTRIPOUTL5: CMP8SS2.CTRIPOUTH6: CMP8SS3.CTRIPOUTL7: CMP8SS3.CTRIPOUTH8: CMP8SS4.CTRIPOUTL9: CMP8SS4.CTRIPOUTH10:.." group.tbyte 0x4E0++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR15_G8" hexmask.tbyte 0x0 0.--19. 1. "SEL,G8: OUTPUT XBar15 G8 Input Select0: ADC0.EVT11: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1 EVT48: ADC2.EVT19: ADC2 EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117:.." group.tbyte 0x4E4++0x2 line.tbyte 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR15_G9" hexmask.tbyte 0x0 0.--19. 1. "SEL,G9: OUTPUT XBar15 G9 Input Select0: PWMSyncOutXBar.SYNCOUT01: PWMSyncOutXBar.SYNCOUT12: PWMSyncOutXBar.SYNCOUT23: PWMSyncOutXBar.SYNCOUT34: EQEP0.I_OUT5: EQEP0.S_OUT6: EQEP1.I_OUT7: EQEP1.S_OUT8: EQEP2.I_OUT9: EQEP2.S_OUT10: ECAP0.OUT11: ECAP1.OUT12:.." group.word 0x4E8++0x1 line.word 0x0 "CONTROLSS_OUTPUTXBAR_OUTPUTXBAR15_G10" hexmask.word 0x0 0.--15. 1. "SEL,G10: OUTPUT XBar15 G10 Input Select3:0: FSIRX0.RX_TRIG07:4: FSIRX1.RX_TRIG011:8: FSIRX2.RX_TRIG015:12: FSIRX3.RX_TRIG0" tree.end tree "PWMSYNCOUTXBAR" base ad:0x502D2000 rgroup.long 0x0++0x3 line.long 0x0 "CONTROLSS_PWMSYNCOUTXBAR_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,Not Defined" hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,Not Defined" bitfld.long 0x0 8.--10. "PID_MAJOR,Not Defined" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "PID_CUSTOM,Not Defined" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,Not Defined" group.long 0x100++0x3 line.long 0x0 "CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR0_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM pwmsyncout xbar0 select1: PWM[x] SYNCOUT selected0: PWM[x] SYNCOUT is de-selected" group.long 0x140++0x3 line.long 0x0 "CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR1_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM pwmsyncout xbar1 select1: PWM[x] SYNCOUT selected0: PWM[x] SYNCOUT is de-selected" group.long 0x180++0x3 line.long 0x0 "CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR2_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM pwmsyncout xbar2 select1: PWM[x] SYNCOUT selected0: PWM[x] SYNCOUT is de-selected" group.long 0x1C0++0x3 line.long 0x0 "CONTROLSS_PWMSYNCOUTXBAR_PWMSYNCOUTXBAR3_G0" hexmask.long 0x0 0.--31. 1. "SEL,ETPWM pwmsyncout xbar3 select1: PWM[x] SYNCOUT selected0: PWM[x] SYNCOUT is de-selected" tree.end tree "PWMXBAR" base ad:0x502D1000 rgroup.long 0x0++0x3 line.long 0x0 "CONTROLSS_PWMXBAR_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,Not Defined" hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,Not Defined" bitfld.long 0x0 8.--10. "PID_MAJOR,Not Defined" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "PID_CUSTOM,Not Defined" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,Not Defined" rgroup.long 0x10++0x3 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR_STATUS" hexmask.long 0x0 0.--29. 1. "STS,Output Signal Status" group.long 0x14++0xB line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR_FLAGINVERT" hexmask.long 0x0 0.--29. 1. "INVERT,Output Signal Invert Before Latch" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR_FLAG" bitfld.long 0x4 29. "BIT29,Output Signal Latched Flag" "0,1" bitfld.long 0x4 28. "BIT28,Output Signal Latched Flag" "0,1" bitfld.long 0x4 27. "BIT27,Output Signal Latched Flag" "0,1" bitfld.long 0x4 26. "BIT26,Output Signal Latched Flag" "0,1" bitfld.long 0x4 25. "BIT25,Output Signal Latched Flag" "0,1" bitfld.long 0x4 24. "BIT24,Output Signal Latched Flag" "0,1" bitfld.long 0x4 23. "BIT23,Output Signal Latched Flag" "0,1" newline bitfld.long 0x4 22. "BIT22,Output Signal Latched Flag" "0,1" bitfld.long 0x4 21. "BIT21,Output Signal Latched Flag" "0,1" bitfld.long 0x4 20. "BIT20,Output Signal Latched Flag" "0,1" bitfld.long 0x4 19. "BIT19,Output Signal Latched Flag" "0,1" bitfld.long 0x4 18. "BIT18,Output Signal Latched Flag" "0,1" bitfld.long 0x4 17. "BIT17,Output Signal Latched Flag" "0,1" bitfld.long 0x4 16. "BIT16,Output Signal Latched Flag" "0,1" newline bitfld.long 0x4 15. "BIT15,Output Signal Latched Flag" "0,1" bitfld.long 0x4 14. "BIT14,Output Signal Latched Flag" "0,1" bitfld.long 0x4 13. "BIT13,Output Signal Latched Flag" "0,1" bitfld.long 0x4 12. "BIT12,Output Signal Latched Flag" "0,1" bitfld.long 0x4 11. "BIT11,Output Signal Latched Flag" "0,1" bitfld.long 0x4 10. "BIT10,Output Signal Latched Flag" "0,1" bitfld.long 0x4 9. "BIT9,Output Signal Latched Flag" "0,1" newline bitfld.long 0x4 8. "BIT8,Output Signal Latched Flag" "0,1" bitfld.long 0x4 7. "BIT7,Output Signal Latched Flag" "0,1" bitfld.long 0x4 6. "BIT6,Output Signal Latched Flag" "0,1" bitfld.long 0x4 5. "BIT5,Output Signal Latched Flag" "0,1" bitfld.long 0x4 4. "BIT4,Output Signal Latched Flag" "0,1" bitfld.long 0x4 3. "BIT3,Output Signal Latched Flag" "0,1" bitfld.long 0x4 2. "BIT2,Output Signal Latched Flag" "0,1" newline bitfld.long 0x4 1. "BIT1,Output Signal Latched Flag" "0,1" bitfld.long 0x4 0. "BIT0,Output Signal Latched Flag" "0,1" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR_FLAG_CLR" bitfld.long 0x8 29. "BIT29,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 28. "BIT28,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 27. "BIT27,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 26. "BIT26,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 25. "BIT25,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 24. "BIT24,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 23. "BIT23,Output Signal Latched Flag Clear" "0,1" newline bitfld.long 0x8 22. "BIT22,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 21. "BIT21,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 20. "BIT20,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 19. "BIT19,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 18. "BIT18,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 17. "BIT17,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 16. "BIT16,Output Signal Latched Flag Clear" "0,1" newline bitfld.long 0x8 15. "BIT15,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 14. "BIT14,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 13. "BIT13,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 12. "BIT12,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 11. "BIT11,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 10. "BIT10,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 9. "BIT9,Output Signal Latched Flag Clear" "0,1" newline bitfld.long 0x8 8. "BIT8,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 7. "BIT7,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 6. "BIT6,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 5. "BIT5,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 4. "BIT4,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 3. "BIT3,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 2. "BIT2,Output Signal Latched Flag Clear" "0,1" newline bitfld.long 0x8 1. "BIT1,Output Signal Latched Flag Clear" "0,1" bitfld.long 0x8 0. "BIT0,Output Signal Latched Flag Clear" "0,1" group.tbyte 0x100++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR0_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar0 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x104++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR0_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar0 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x108++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR0_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar0 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x10C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR0_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar0 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x110++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR0_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar0 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR0_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar0 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR0_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar0 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR0_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar0 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR0_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar0 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG428:19: ECAP[9:0].TRIPOUT" group.tbyte 0x140++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR1_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar1 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x144++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR1_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar1 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x148++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR1_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar1 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x14C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR1_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar1 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x150++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR1_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar1 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR1_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar1 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR1_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar1 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR1_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar1 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR1_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar1 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x180++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR2_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar2 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x184++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR2_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar2 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x188++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR2_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar2 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x18C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR2_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar2 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x190++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR2_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar2 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR2_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar2 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR2_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar2 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR2_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar2 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR2_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar2 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x1C0++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR3_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar3 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x1C4++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR3_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar3 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x1C8++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR3_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar3 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x1CC++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR3_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar3 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x1D0++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR3_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar3 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR3_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar3 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR3_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar3 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR3_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar3 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR3_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar3 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x200++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR4_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar4 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x204++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR4_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar4 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x208++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR4_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar4 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x20C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR4_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar4 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x210++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR4_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar4 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR4_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar4 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR4_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar4 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR4_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar4 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR4_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar4 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x240++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR5_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar5 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x244++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR5_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar5 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x248++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR5_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar5 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x24C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR5_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar5 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x250++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR5_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar5 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR5_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar5 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR5_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar5 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR5_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar5 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR5_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar5 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x280++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR6_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar6 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x284++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR6_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar6 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x288++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR6_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar6 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x28C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR6_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar6 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x290++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR6_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar6 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR6_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar6 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR6_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar6 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR6_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar6 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR6_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar6 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x2C0++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR7_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar7 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x2C4++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR7_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar7 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x2C8++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR7_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar7 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x2CC++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR7_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar7 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x2D0++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR7_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar7 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR7_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar7 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR7_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar7 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR7_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar7 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR7_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar7 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x300++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR8_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar8 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x304++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR8_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar8 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x308++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR8_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar8 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x30C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR8_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar8 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x310++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR8_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar8 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR8_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar8 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR8_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar8 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR8_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar8 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR8_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar8 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x340++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR9_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar9 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x344++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR9_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar9 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x348++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR9_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar9 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x34C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR9_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar9 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x350++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR9_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar9 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR9_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar9 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR9_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar9 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR9_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar9 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR9_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar9 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x380++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR10_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar10 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x384++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR10_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar10 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x388++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR10_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar10 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x38C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR10_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar10 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x390++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR10_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar10 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR10_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar10 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR10_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar10 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR10_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar10 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR10_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar10 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x3C0++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR11_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar11 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x3C4++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR11_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar11 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x3C8++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR11_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar11 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x3CC++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR11_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar11 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x3D0++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR11_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar11 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR11_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar11 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR11_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar11 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR11_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar11 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR11_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar11 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x400++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR12_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar12 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x404++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR12_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar12 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x408++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR12_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar12 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x40C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR12_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar12 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x410++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR12_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar12 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR12_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar12 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR12_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar12 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR12_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar12 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR12_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar12 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x440++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR13_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar13 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x444++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR13_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar13 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x448++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR13_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar13 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x44C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR13_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar13 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x450++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR13_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar13 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR13_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar13 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR13_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar13 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR13_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar13 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR13_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar13 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x480++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR14_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar14 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x484++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR14_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar14 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x488++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR14_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar14 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x48C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR14_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar14 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x490++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR14_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar14 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR14_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar14 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR14_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar14 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR14_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar14 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR14_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar14 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x4C0++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR15_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar15 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x4C4++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR15_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar15 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x4C8++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR15_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar15 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x4CC++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR15_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar15 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x4D0++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR15_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar15 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR15_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar15 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR15_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar15 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR15_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar15 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR15_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar15 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x500++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR16_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar16 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x504++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR16_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar16 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x508++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR16_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar16 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x50C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR16_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar16 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x510++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR16_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar16 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR16_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar16 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR16_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar16 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR16_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar16 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR16_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar16 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x540++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR17_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar17 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x544++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR17_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar17 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x548++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR17_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar17 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x54C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR17_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar17 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x550++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR17_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar17 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR17_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar17 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR17_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar17 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR17_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar17 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR17_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar17 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x580++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR18_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar18 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x584++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR18_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar18 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x588++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR18_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar18 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x58C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR18_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar18 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x590++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR18_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar18 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR18_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar18 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR18_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar18 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR18_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar18 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR18_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar18 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x5C0++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR19_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar19 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x5C4++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR19_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar19 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x5C8++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR19_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar19 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x5CC++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR19_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar19 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x5D0++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR19_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar19 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR19_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar19 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR19_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar19 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR19_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar19 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR19_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar19 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x600++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR20_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar20 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x604++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR20_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar20 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x608++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR20_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar20 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x60C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR20_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar20 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x610++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR20_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar20 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR20_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar20 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR20_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar20 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR20_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar20 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR20_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar20 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x640++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR21_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar21 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x644++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR21_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar21 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x648++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR21_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar21 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x64C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR21_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar21 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x650++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR21_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar21 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR21_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar21 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR21_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar21 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR21_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar21 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR21_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar21 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x680++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR22_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar22 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x684++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR22_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar22 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x688++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR22_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar22 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x68C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR22_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar22 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x690++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR22_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar22 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR22_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar22 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR22_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar22 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR22_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar22 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR22_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar22 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x6C0++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR23_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar23 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x6C4++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR23_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar23 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x6C8++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR23_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar23 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x6CC++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR23_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar23 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x6D0++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR23_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar23 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR23_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar23 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR23_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar23 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR23_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar23 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR23_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar23 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x700++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR24_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar24 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x704++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR24_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar24 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x708++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR24_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar24 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x70C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR24_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar24 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x710++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR24_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar24 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR24_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar24 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR24_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar24 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR24_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar24 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR24_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar24 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x740++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR25_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar25 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x744++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR25_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar25 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x748++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR25_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar25 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x74C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR25_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar25 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x750++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR25_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar25 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR25_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar25 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR25_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar25 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR25_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar25 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR25_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar25 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x780++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR26_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar26 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x784++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR26_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar26 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x788++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR26_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar26 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x78C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR26_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar26 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x790++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR26_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar26 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR26_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar26 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR26_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar26 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR26_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar26 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR26_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar26 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x7C0++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR27_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar27 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x7C4++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR27_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar27 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x7C8++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR27_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar27 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x7CC++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR27_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar27 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x7D0++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR27_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar27 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR27_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar27 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR27_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar27 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR27_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar27 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR27_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar27 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x800++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR28_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar28 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x804++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR28_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar28 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x808++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR28_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar28 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x80C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR28_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar28 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x810++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR28_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar28 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR28_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar28 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR28_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar28 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR28_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar28 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR28_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar28 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" group.tbyte 0x840++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR29_G0" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar29 G0 Input Select0: CMP12SS0.CTRIPL1: CMP12SS0.CTRIPH2: CMP12SS1.CTRIPL3: CMP12SS1.CTRIPH4: CMP12SS2.CTRIPL5: CMP12SS2.CTRIPH6: CMP12SS3.CTRIPL7: CMP12SS3.CTRIPH8: CMP12SS4.CTRIPL9: CMP12SS4.CTRIPH10: CMP12SS5.CTRIPL11: CMP12SS5.CTRIPH12:.." group.tbyte 0x844++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR29_G1" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar29 G1 Input Select0: CMP8SS0.CTRIPL1: CMP8SS0.CTRIPH2: CMP8SS1.CTRIPL3: CMP8SS1.CTRIPH4: CMP8SS2.CTRIPL5: CMP8SS2.CTRIPH6: CMP8SS3.CTRIPL7: CMP8SS3.CTRIPH8: CMP8SS4.CTRIPL9: CMP8SS4.CTRIPH10: CMP8SS5.CTRIPL11: CMP8SS5.CTRIPH12:.." group.tbyte 0x848++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR29_G2" hexmask.tbyte 0x0 0.--23. 1. "SEL,PWM XBar29 G2 Input Select0: SDFM0.FILT1CEVT11: SDFM0.FILT1CEVT22: SDFM0.FILT1COMPHZ3: SDFM0.FILT2CEVT14: SDFM0.FILT2CEVT25: SDFM0.FILT2COMPHZ6: SDFM0.FILT3CEVT17: SDFM0.FILT3CEVT28: SDFM0.FILT3COMPHZ9: SDFM0.FILT4CEVT110: SDFM0.FILT4CEVT211:.." group.tbyte 0x84C++0x2 line.tbyte 0x0 "CONTROLSS_PWMXBAR_PWMXBAR29_G3" hexmask.tbyte 0x0 0.--19. 1. "SEL,PWM XBar29 G3 Input Select1: ADC0.EVT22: ADC0.EVT33: ADC0.EVT44: ADC1.EVT15: ADC1.EVT26: ADC1.EVT37: ADC1.EVT48: ADC2.EVT19: ADC2.EVT210: ADC2.EVT311: ADC2.EVT412: ADC3.EVT113: ADC3.EVT214: ADC3.EVT315: ADC3.EVT416: ADC4.EVT117: ADC4.EVT218:.." group.long 0x850++0x13 line.long 0x0 "CONTROLSS_PWMXBAR_PWMXBAR29_G4" hexmask.long 0x0 0.--31. 1. "SEL,PWM XBar29 G4 input bit select. Input source is INPUT XBAR.1: INPUT XBAR output bit[x] selected0: INPUT XBAR output bit[x] is de-selected" line.long 0x4 "CONTROLSS_PWMXBAR_PWMXBAR29_G5" hexmask.long 0x4 0.--31. 1. "SEL,PWM XBar29 G5 input bit select. Input source is PWM TRIPOUT.1: PWM TRIPOUT bit[x] selected0: PWM TRIPOUT bit[x] is de-selected" line.long 0x8 "CONTROLSS_PWMXBAR_PWMXBAR29_G6" hexmask.long 0x8 0.--31. 1. "SEL,PWM XBar29 G6 input bit select. Input source is PWM DEL TRIP1: PWM DEL TRIP bit[x] selected0: PWM DEL TRIP bit[x] is de-selected" line.long 0xC "CONTROLSS_PWMXBAR_PWMXBAR29_G7" hexmask.long 0xC 0.--31. 1. "SEL,PWM XBar29 G7 input bit select. Input source is PWM DEL ACTIVE1: PWM DEL ACTIVE bit[x] selected0: PWM DEL ACTIVE bit[x] is de-selected" line.long 0x10 "CONTROLSS_PWMXBAR_PWMXBAR29_G8" hexmask.long 0x10 0.--28. 1. "SEL,PWM XBar29 G8 Input Select0: EQEP0.ERR1: EQEP1.ERR2: EQEP2.ERR6:3: FSIRX0.RX_TRIG410:7: FSIRX1.RX_TRIG414:11: FSIRX2.RX_TRIG418:15: FSIRX3.RX_TRIG4 28:19: ECAP[9:0].TRIPOUT" tree.end base ad:0x0 tree "SDFM" tree "SDFM0" base ad:0x50268000 rgroup.long 0x0++0x3 line.long 0x0 "CONTROLSS_SDFM0_SDIFLG" bitfld.long 0x0 31. "MIF,Set whenever any 'error' interrupt (MF1-4 IFL1-4 IFH1-4 SDFFOVF1-4) is active" "0,1" newline bitfld.long 0x0 23. "SDFFINT4,SDFIFO data ready interrupt for Ch4" "0,1" newline bitfld.long 0x0 22. "SDFFINT3,SDFIFO data ready interrupt for Ch3" "0,1" newline bitfld.long 0x0 21. "SDFFINT2,SDFIFO data ready interrupt for Ch2" "0,1" newline bitfld.long 0x0 20. "SDFFINT1,SDFIFO data ready interrupt for Ch1 0: SDFIFO data ready interrupt has NOT occurred 1: SDFIFO data ready interrupt has occurred" "0: SDFIFO data ready interrupt has NOT occurred,1: SDFIFO data ready interrupt has occurred" newline bitfld.long 0x0 19. "SDFFOVF4,FIFO Overflow Flag for Ch4" "0,1" newline bitfld.long 0x0 18. "SDFFOVF3,FIFO Overflow Flag for Ch3" "0,1" newline bitfld.long 0x0 17. "SDFFOVF2,FIFO Overflow Flag for Ch2" "0,1" newline bitfld.long 0x0 16. "SDFFOVF1,FIFO Overflow Flag for Ch1 0 - FIFO has not overflowed 1 - FIFO overflowed. # words received in FIFO ' FIFO depth (16) NEW word is lost" "0,1" newline bitfld.long 0x0 15. "AF4,Acknowledge flag for Filter 4 0: No new data available for Filter (in non-FIFO mode) 1: New data available for Filter (in non-FIFO mode)" "0: No new data available for Filter,1: New data available for Filter" newline bitfld.long 0x0 14. "AF3,Acknowledge flag for Filter 3 0: No new data available for Filter (in non-FIFO mode) 1: New data available for Filter (in non-FIFO mode)" "0: No new data available for Filter,1: New data available for Filter" newline bitfld.long 0x0 13. "AF2,Acknowledge flag for Filter 2 0: No new data available for Filter (in non-FIFO mode) 1: New data available for Filter (in non-FIFO mode)" "0: No new data available for Filter,1: New data available for Filter" newline bitfld.long 0x0 12. "AF1,Acknowledge flag for Filter 1 0: No new data available for Filter (in non-FIFO mode) 1: New data available for Filter (in non-FIFO mode)" "0: No new data available for Filter,1: New data available for Filter" newline bitfld.long 0x0 11. "MF4,Modulator Failure for Filter 4 0: Modulator is operating normally for Filter 1: Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 10. "MF3,Modulator Failure for Filter 3 0: Modulator is operating normally for Filter 1: Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 9. "MF2,Modulator Failure for Filter 2 0: Modulator is operating normally for Filter 1: Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 8. "MF1,Modulator Failure for Filter 1 0: Modulator is operating normally for Filter 1: Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 7. "FLT4_FLG_CEVT2,CEVT2 Interrupt flag for filter4 0: CEVT2 event has not occured 1: CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 6. "FLT4_FLG_CEVT1,CEVT1 Interrupt flag for filter4 0: CEVT1 event has not occured 1: CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" newline bitfld.long 0x0 5. "FLT3_FLG_CEVT2,CEVT2 Interrupt flag for filter3 0: CEVT2 event has not occured 1: CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 4. "FLT3_FLG_CEVT1,CEVT1 Interrupt flag for filter3 0: CEVT1 event has not occured 1: CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" newline bitfld.long 0x0 3. "FLT2_FLG_CEVT2,CEVT2 Interrupt flag for filter2 0: CEVT2 event has not occured 1: CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 2. "FLT2_FLG_CEVT1,CEVT1 Interrupt flag for filter2 0: CEVT1 event has not occured 1: CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" newline bitfld.long 0x0 1. "FLT1_FLG_CEVT2,CEVT2 Interrupt flag for filter1 0: CEVT2 event has not occured 1: CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 0. "FLT1_FLG_CEVT1,CEVT1 Interrupt flag for filter1 0: CEVT1 event has not occured 1: CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" group.long 0x4++0x3 line.long 0x0 "CONTROLSS_SDFM0_SDIFLGCLR" bitfld.long 0x0 31. "MIF,Flag-clear bit for SDFM Master Interrupt flag. Writing a 1 to clear MIF flag in SDIFLG register Writes of '0' are ignored. Note: If the MIF flag is cleared and other Interrupts are still pending MIF will again be set to 1 on the following.." "0,1" newline bitfld.long 0x0 23. "SDFFINT4,SDFIFO data ready Interrupt flag-clear bit for Ch4" "0,1" newline bitfld.long 0x0 22. "SDFFINT3,SDFIFO data ready Interrupt flag-clear bit for Ch3" "0,1" newline bitfld.long 0x0 21. "SDFFINT2,SDFIFO data ready Interrupt flag-clear bit for Ch2" "0,1" newline bitfld.long 0x0 20. "SDFFINT1,SDFIFO data ready Interrupt flag-clear bit for Ch1" "0,1" newline bitfld.long 0x0 19. "SDFFOVF4,SDFIFO overflow clear Ch4" "0,1" newline bitfld.long 0x0 18. "SDFFOVF3,SDFIFO overflow clear Ch3" "0,1" newline bitfld.long 0x0 17. "SDFFOVF2,SDFIFO overflow clear Ch2" "0,1" newline bitfld.long 0x0 16. "SDFFOVF1,SDFIFO overflow clear Ch1" "0,1" newline bitfld.long 0x0 15. "AF4,Flag-clear bit for Acknowledge flag for Filter 4" "0,1" newline bitfld.long 0x0 14. "AF3,Flag Clear bit for AF3" "0,1" newline bitfld.long 0x0 13. "AF2,Flag Clear bit for AF2" "0,1" newline bitfld.long 0x0 12. "AF1,Flag Clear bit for AF1" "0,1" newline bitfld.long 0x0 11. "MF4,Flag Clear bit for MF4" "0,1" newline bitfld.long 0x0 10. "MF3,Flag Clear bit for MF3" "0,1" newline bitfld.long 0x0 9. "MF2,Flag Clear bit for MF2" "0,1" newline bitfld.long 0x0 8. "MF1,Flag Clear bit for MF1" "0,1" newline bitfld.long 0x0 7. "FLT4_FLG_CEVT2,Flag Clear bit for FLT4_FLG_CEVT2" "0,1" newline bitfld.long 0x0 6. "FLT4_FLG_CEVT1,Flag Clear bit for FLT4_FLG_CEVT1" "0,1" newline bitfld.long 0x0 5. "FLT3_FLG_CEVT2,Flag Clear bit for FLT3_FLG_CEVT2" "0,1" newline bitfld.long 0x0 4. "FLT3_FLG_CEVT1,Flag Clear bit for FLT3_FLG_CEVT1" "0,1" newline bitfld.long 0x0 3. "FLT2_FLG_CEVT2,Flag Clear bit for FLT2_FLG_CEVT2" "0,1" newline bitfld.long 0x0 2. "FLT2_FLG_CEVT1,Flag Clear bit for FLT2_FLG_CEVT1" "0,1" newline bitfld.long 0x0 1. "FLT1_FLG_CEVT2,Flag Clear bit for FLT1_FLG_CEVT2" "0,1" newline bitfld.long 0x0 0. "FLT1_FLG_CEVT1,Flag Clear bit for FLT1_FLG_CEVT1" "0,1" group.word 0x8++0x1 line.word 0x0 "CONTROLSS_SDFM0_SDCTL" bitfld.word 0x0 13. "MIE,Master SDy_ERR interrupt enable 0: SDy_ERR Interrupt and interrupt flags are disabled 1: SDy_ERR Interrupt and interrupt flags are enabled" "0: SDy_ERR Interrupt and interrupt flags are disabled,1: SDy_ERR Interrupt and interrupt flags are enabled" newline bitfld.word 0x0 3. "HZ4,Flag Clear bit for HZ4" "0,1" newline bitfld.word 0x0 2. "HZ3,Flag Clear bit for HZ3" "0,1" newline bitfld.word 0x0 1. "HZ2,Flag Clear bit for HZ2" "0,1" newline bitfld.word 0x0 0. "HZ1,Flag Clear bit for HZ1" "0,1" group.word 0xC++0x1 line.word 0x0 "CONTROLSS_SDFM0_SDMFILEN" bitfld.word 0x0 11. "MFE,Master Filter Enable 0: All the four data filter units of SDFM module are disabled. All FIFOs are cleared 1: Data filter units can be enabled if bit FEN is '1'." "0: All the four data filter units of SDFM module..,1: Data filter units can be enabled if bit FEN is '1'" rgroup.word 0xE++0x1 line.word 0x0 "CONTROLSS_SDFM0_SDSTATUS" bitfld.word 0x0 3. "HZ4,High-level Threshold crossing (Z) flag Ch4 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0: Comparator filter output ' SDCMPHZ4.HLTZ 1:.." "0: Comparator filter output ' SDCMPHZ4,1: Comparator filter output '= SDCMPHZ4" newline bitfld.word 0x0 2. "HZ3,High-level Threshold crossing (Z) flag Ch3 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0: Comparator filter output ' SDCMPHZ3.HLTZ 1:.." "0: Comparator filter output ' SDCMPHZ3,1: Comparator filter output '= SDCMPHZ3" newline bitfld.word 0x0 1. "HZ2,High-level Threshold crossing (Z) flag Ch2 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0: Comparator filter output ' SDCMPHZ2.HLTZ 1:.." "0: Comparator filter output ' SDCMPHZ2,1: Comparator filter output '= SDCMPHZ2" newline bitfld.word 0x0 0. "HZ1,High-level Threshold crossing (Z) flag Ch1 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0: Comparator filter output ' SDCMPHZ1.HLTZ 1:.." "0: Comparator filter output ' SDCMPHZ1,1: Comparator filter output '= SDCMPHZ1" group.word 0x20++0xB line.word 0x0 "CONTROLSS_SDFM0_SDCTLPARM1" bitfld.word 0x0 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1: SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0x0 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1: SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0x0 3. "SDCLKSEL,SD1 Clock source select. 0: Clock source to SDFM filter is its channel clock. 1: Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0x0 0.--1. "MOD,Modulator clock modes 0: Mode 0: Modulator clock running at 1x data rate 1: Reserved 2: Reserved 3: Reserved" "0: Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0x2 "CONTROLSS_SDFM0_SDDFPARM1" bitfld.word 0x2 12. "SDSYNCEN,PWM synchronization (SDSYNC) of data filter 0: PWM synchronization of data filter is disabled 1: PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0x2 10.--11. "SST,Data filter structure 00: Data filter runs with a Sincfast structure 01: Data filter runs with a Sinc1 structure 10: Data filter runs with a Sinc2 structure 11: Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x2 9. "AE,Data filter Acknowledge Enable 0: Acknowledge flag is disabled for the particular filter 1: Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0x2 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0x2 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0x4 "CONTROLSS_SDFM0_SDDPARM1" hexmask.word.byte 0x4 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0x4 10. "DR,Data filter Data representation 0: Data stored in 16b 2's complement 1: Data stored in 32b 2's complement" "0: Data stored in 16b 2's complement,1: Data stored in 32b 2's complement" line.word 0x6 "CONTROLSS_SDFM0_SDFLT1CMPH1" hexmask.word 0x6 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x8 "CONTROLSS_SDFM0_SDFLT1CMPL1" hexmask.word 0x8 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0xA "CONTROLSS_SDFM0_SDCPARM1" bitfld.word 0xA 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01: COMPL1 OR COMPH1 10: COMPL2 11: COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0xA 13. "CEN,Comparator Filter enable 0: Disable comparator filter 1: Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0xA 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01: COMPL1 OR COMPH1 10: COMPH2 11: COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0xA 10. "HZEN,High level (Z) Threshold crossing output enable 0: Disable Higher level Threshold (Z) crossing 1: Enable Higher level Threhold (Z) crossing" "0: Disable Higher level Threshold,1: Enable Higher level Threhold" newline bitfld.word 0xA 9. "MFIE,Modulator Failure Interrupt Enable 0: Disable modulator failure interrupt and its flag 1: Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0xA 7.--8. "CS1_CS0,Comparator filter structure 00: Comparator filter runs with a sincfast structure 01: Comparator filter runs with a Sinc1 structure 10: Comparator filter runs with a Sinc2 structure 11: Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xA 6. "EN_CEVT2,CEVT2 interrupt enable 0: Disable CEVT2 interrupt 1: Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0xA 5. "EN_CEVT1,CEVT1 interrupt enable 0: Disable CEVT1 interrupt 1: Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0xA 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x2C++0x7 line.long 0x0 "CONTROLSS_SDFM0_SDDATA1" hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" line.long 0x4 "CONTROLSS_SDFM0_SDDATFIFO1" hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" rgroup.word 0x34++0x1 line.word 0x0 "CONTROLSS_SDFM0_SDCDATA1" hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only" group.word 0x36++0x15 line.word 0x0 "CONTROLSS_SDFM0_SDFLT1CMPH2" hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "CONTROLSS_SDFM0_SDFLT1CMPHZ" hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold (Z) for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "CONTROLSS_SDFM0_SDFIFOCTL1" bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0: SDFIFO Overflow condition will not generate an interrupt 1: SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt (DRINT) source select 0 = AF1 (Select non-FIFO data-ready interrupt) 1 = SDFFINT1 (Select FIFO data-ready interrupt)" "0: AF1,1: SDFFINT1" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status (SDFFST) '= FIFO level (SDFFIL )" line.word 0x6 "CONTROLSS_SDFM0_SDSYNC1" bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0: WTSYNFLG can only be cleared manually (using WTSYNCLR bit) 1: WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0: SDFIFO is not automaticaly cleared upon receiving SDSYNC 1: SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear (always reads 0) 0: Write of 0 has no affect 1: Write of 1 clears WTSYNFLG" "0: Write of 0 has no affect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0: SDSYNC event has not occurred 1: SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0: Incoming Data written to SDFIFO on every Data-Ready (DR) Event 1: Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "CONTROLSS_SDFM0_SDFLT1CMPL2" hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." line.word 0xA "CONTROLSS_SDFM0_SDCTLPARM2" bitfld.word 0xA 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1: SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0xA 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1: SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0xA 3. "SDCLKSEL,SD2 Clock source select. 0: Clock source to SDFM filter is its channel clock. 1: Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0xA 0.--1. "MOD,Modulator clock modes 0: Mode 0: Modulator clock running at 1x data rate 1: Reserved 2: Reserved 3: Reserved" "0: Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0xC "CONTROLSS_SDFM0_SDDFPARM2" bitfld.word 0xC 12. "SDSYNCEN,PWM synchronization (SDSYNC) of data filter 0: PWM synchronization of data filter is disabled 1: PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0xC 10.--11. "SST,Data filter structure 00: Data filter runs with a Sincfast structure 01: Data filter runs with a Sinc1 structure 10: Data filter runs with a Sinc2 structure 11: Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xC 9. "AE,Data filter Acknowledge Enable 0: Acknowledge flag is disabled for the particular filter 1: Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0xC 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0xC 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0xE "CONTROLSS_SDFM0_SDDPARM2" hexmask.word.byte 0xE 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0xE 10. "DR,Data filter Data representation 0: Data stored in 16b 2's complement 1: Data stored in 32b 2's complement" "0: Data stored in 16b 2's complement,1: Data stored in 32b 2's complement" line.word 0x10 "CONTROLSS_SDFM0_SDFLT2CMPH1" hexmask.word 0x10 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x12 "CONTROLSS_SDFM0_SDFLT2CMPL1" hexmask.word 0x12 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0x14 "CONTROLSS_SDFM0_SDCPARM2" bitfld.word 0x14 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01: COMPL1 OR COMPH1 10: COMPL2 11: COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 13. "CEN,Comparator Filter enable 0: Disable comparator filter 1: Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0x14 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01: COMPL1 OR COMPH1 10: COMPH2 11: COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 10. "HZEN,High level (Z) Threshold crossing output enable 0: Disable Higher level Threshold (Z) crossing 1: Enable Higher level Threhold (Z) crossing" "0: Disable Higher level Threshold,1: Enable Higher level Threhold" newline bitfld.word 0x14 9. "MFIE,Modulator Failure Interrupt Enable 0: Disable modulator failure interrupt and its flag 1: Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0x14 7.--8. "CS1_CS0,Comparator filter structure 00: Comparator filter runs with a sincfast structure 01: Comparator filter runs with a Sinc1 structure 10: Comparator filter runs with a Sinc2 structure 11: Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x14 6. "EN_CEVT2,CEVT2 interrupt enable 0: Disable CEVT2 interrupt 1: Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0x14 5. "EN_CEVT1,CEVT1 interrupt enable 0: Disable CEVT1 interrupt 1: Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0x14 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x4C++0x7 line.long 0x0 "CONTROLSS_SDFM0_SDDATA2" hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" line.long 0x4 "CONTROLSS_SDFM0_SDDATFIFO2" hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" rgroup.word 0x54++0x1 line.word 0x0 "CONTROLSS_SDFM0_SDCDATA2" hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only" group.word 0x56++0x15 line.word 0x0 "CONTROLSS_SDFM0_SDFLT2CMPH2" hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "CONTROLSS_SDFM0_SDFLT2CMPHZ" hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold (Z) for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "CONTROLSS_SDFM0_SDFIFOCTL2" bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0: SDFIFO Overflow condition will not generate an interrupt 1: SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt (DRINT) source select 0 = AF1 (Select non-FIFO data-ready interrupt) 1 = SDFFINT1 (Select FIFO data-ready interrupt)" "0: AF1,1: SDFFINT1" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status (SDFFST) '= FIFO level (SDFFIL )" line.word 0x6 "CONTROLSS_SDFM0_SDSYNC2" bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0: WTSYNFLG can only be cleared manually (using WTSYNCLR bit) 1: WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0: SDFIFO is not automaticaly cleared upon receiving SDSYNC 1: SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear (always reads 0) 0: Write of 0 has no affect 1: Write of 1 clears WTSYNFLG" "0: Write of 0 has no affect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0: SDSYNC event has not occurred 1: SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0: Incoming Data written to SDFIFO on every Data-Ready (DR) Event 1: Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "CONTROLSS_SDFM0_SDFLT2CMPL2" hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." line.word 0xA "CONTROLSS_SDFM0_SDCTLPARM3" bitfld.word 0xA 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1: SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0xA 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1: SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0xA 3. "SDCLKSEL,SD3 Clock source select. 0: Clock source to SDFM filter is its channel clock. 1: Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0xA 0.--1. "MOD,Modulator clock modes 0: Mode 0: Modulator clock running at 1x data rate 1: Reserved 2: Reserved 3: Reserved" "0: Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0xC "CONTROLSS_SDFM0_SDDFPARM3" bitfld.word 0xC 12. "SDSYNCEN,PWM synchronization (SDSYNC) of data filter 0: PWM synchronization of data filter is disabled 1: PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0xC 10.--11. "SST,Data filter structure 00: Data filter runs with a Sincfast structure 01: Data filter runs with a Sinc1 structure 10: Data filter runs with a Sinc2 structure 11: Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xC 9. "AE,Data filter Acknowledge Enable 0: Acknowledge flag is disabled for the particular filter 1: Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0xC 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0xC 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0xE "CONTROLSS_SDFM0_SDDPARM3" hexmask.word.byte 0xE 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0xE 10. "DR,Data filter Data representation 0: Data stored in 16b 2's complement 1: Data stored in 32b 2's complement" "0: Data stored in 16b 2's complement,1: Data stored in 32b 2's complement" line.word 0x10 "CONTROLSS_SDFM0_SDFLT3CMPH1" hexmask.word 0x10 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x12 "CONTROLSS_SDFM0_SDFLT3CMPL1" hexmask.word 0x12 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0x14 "CONTROLSS_SDFM0_SDCPARM3" bitfld.word 0x14 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01: COMPL1 OR COMPH1 10: COMPL2 11: COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 13. "CEN,Comparator Filter enable 0: Disable comparator filter 1: Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0x14 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01: COMPL1 OR COMPH1 10: COMPH2 11: COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 10. "HZEN,High level (Z) Threshold crossing output enable 0: Disable Higher level Threshold (Z) crossing 1: Enable Higher level Threhold (Z) crossing" "0: Disable Higher level Threshold,1: Enable Higher level Threhold" newline bitfld.word 0x14 9. "MFIE,Modulator Failure Interrupt Enable 0: Disable modulator failure interrupt and its flag 1: Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0x14 7.--8. "CS1_CS0,Comparator filter structure 00: Comparator filter runs with a sincfast structure 01: Comparator filter runs with a Sinc1 structure 10: Comparator filter runs with a Sinc2 structure 11: Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x14 6. "EN_CEVT2,CEVT2 interrupt enable 0: Disable CEVT2 interrupt 1: Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0x14 5. "EN_CEVT1,CEVT1 interrupt enable 0: Disable CEVT1 interrupt 1: Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0x14 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x6C++0x7 line.long 0x0 "CONTROLSS_SDFM0_SDDATA3" hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" line.long 0x4 "CONTROLSS_SDFM0_SDDATFIFO3" hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" rgroup.word 0x74++0x1 line.word 0x0 "CONTROLSS_SDFM0_SDCDATA3" hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only" group.word 0x76++0x15 line.word 0x0 "CONTROLSS_SDFM0_SDFLT3CMPH2" hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "CONTROLSS_SDFM0_SDFLT3CMPHZ" hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold (Z) for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "CONTROLSS_SDFM0_SDFIFOCTL3" bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0: SDFIFO Overflow condition will not generate an interrupt 1: SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt (DRINT) source select 0 = AF1 (Select non-FIFO data-ready interrupt) 1 = SDFFINT1 (Select FIFO data-ready interrupt)" "0: AF1,1: SDFFINT1" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status (SDFFST) '= FIFO level (SDFFIL )" line.word 0x6 "CONTROLSS_SDFM0_SDSYNC3" bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0: WTSYNFLG can only be cleared manually (using WTSYNCLR bit) 1: WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0: SDFIFO is not automaticaly cleared upon receiving SDSYNC 1: SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear (always reads 0) 0: Write of 0 has no affect 1: Write of 1 clears WTSYNFLG" "0: Write of 0 has no affect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0: SDSYNC event has not occurred 1: SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0: Incoming Data written to SDFIFO on every Data-Ready (DR) Event 1: Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "CONTROLSS_SDFM0_SDFLT3CMPL2" hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." line.word 0xA "CONTROLSS_SDFM0_SDCTLPARM4" bitfld.word 0xA 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1: SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0xA 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1: SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0xA 3. "SDCLKSEL,SD4 Clock source select. 0: Clock source to SDFM filter is its channel clock. 1: Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0xA 0.--1. "MOD,Modulator clock modes 0: Mode 0: Modulator clock running at 1x data rate 1: Reserved 2: Reserved 3: Reserved" "0: Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0xC "CONTROLSS_SDFM0_SDDFPARM4" bitfld.word 0xC 12. "SDSYNCEN,PWM synchronization (SDSYNC) of data filter 0: PWM synchronization of data filter is disabled 1: PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0xC 10.--11. "SST,Data filter structure 00: Data filter runs with a Sincfast structure 01: Data filter runs with a Sinc1 structure 10: Data filter runs with a Sinc2 structure 11: Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xC 9. "AE,Data filter Acknowledge Enable 0: Acknowledge flag is disabled for the particular filter 1: Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0xC 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0xC 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0xE "CONTROLSS_SDFM0_SDDPARM4" hexmask.word.byte 0xE 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0xE 10. "DR,Data filter Data representation 0: Data stored in 16b 2's complement 1: Data stored in 32b 2's complement" "0: Data stored in 16b 2's complement,1: Data stored in 32b 2's complement" line.word 0x10 "CONTROLSS_SDFM0_SDFLT4CMPH1" hexmask.word 0x10 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x12 "CONTROLSS_SDFM0_SDFLT4CMPL1" hexmask.word 0x12 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0x14 "CONTROLSS_SDFM0_SDCPARM4" bitfld.word 0x14 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01: COMPL1 OR COMPH1 10: COMPL2 11: COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 13. "CEN,Comparator Filter enable 0: Disable comparator filter 1: Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0x14 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01: COMPL1 OR COMPH1 10: COMPH2 11: COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 10. "HZEN,High level (Z) Threshold crossing output enable 0: Disable Higher level Threshold (Z) crossing 1: Enable Higher level Threhold (Z) crossing" "0: Disable Higher level Threshold,1: Enable Higher level Threhold" newline bitfld.word 0x14 9. "MFIE,Modulator Failure Interrupt Enable 0: Disable modulator failure interrupt and its flag 1: Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0x14 7.--8. "CS1_CS0,Comparator filter structure 00: Comparator filter runs with a sincfast structure 01: Comparator filter runs with a Sinc1 structure 10: Comparator filter runs with a Sinc2 structure 11: Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x14 6. "EN_CEVT2,CEVT2 interrupt enable 0: Disable CEVT2 interrupt 1: Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0x14 5. "EN_CEVT1,CEVT1 interrupt enable 0: Disable CEVT1 interrupt 1: Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0x14 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x8C++0x7 line.long 0x0 "CONTROLSS_SDFM0_SDDATA4" hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" line.long 0x4 "CONTROLSS_SDFM0_SDDATFIFO4" hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" rgroup.word 0x94++0x1 line.word 0x0 "CONTROLSS_SDFM0_SDCDATA4" hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only" group.word 0x96++0x9 line.word 0x0 "CONTROLSS_SDFM0_SDFLT4CMPH2" hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "CONTROLSS_SDFM0_SDFLT4CMPHZ" hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold (Z) for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "CONTROLSS_SDFM0_SDFIFOCTL4" bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0: SDFIFO Overflow condition will not generate an interrupt 1: SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt (DRINT) source select 0 = AF1 (Select non-FIFO data-ready interrupt) 1 = SDFFINT1 (Select FIFO data-ready interrupt)" "0: AF1,1: SDFFINT1" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status (SDFFST) '= FIFO level (SDFFIL )" line.word 0x6 "CONTROLSS_SDFM0_SDSYNC4" bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0: WTSYNFLG can only be cleared manually (using WTSYNCLR bit) 1: WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0: SDFIFO is not automaticaly cleared upon receiving SDSYNC 1: SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear (always reads 0) 0: Write of 0 has no affect 1: Write of 1 clears WTSYNFLG" "0: Write of 0 has no affect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0: SDSYNC event has not occurred 1: SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0: Incoming Data written to SDFIFO on every Data-Ready (DR) Event 1: Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "CONTROLSS_SDFM0_SDFLT4CMPL2" hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." group.word 0xC0++0x9 line.word 0x0 "CONTROLSS_SDFM0_SDCOMP1CTL" bitfld.word 0x0 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x0 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x2 "CONTROLSS_SDFM0_SDCOMP1EVT2FLTCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_SDFM0_SDCOMP1EVT2FLTCLKCTL" hexmask.word 0x4 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x6 "CONTROLSS_SDFM0_SDCOMP1EVT1FLTCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_SDFM0_SDCOMP1EVT1FLTCLKCTL" hexmask.word 0x8 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xCE++0xB line.word 0x0 "CONTROLSS_SDFM0_SDCOMP1LOCK" bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP1EVT1/2FLTTCTL and COMP1FILCLKCTL registers. 0 SDCOMP1EVT1/2FLTCTL and SDCOMP1EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP1EVT1/2FLTCTL and SDCOMP1EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP1CTL,Lock write-access to the SDCOMP1CTL register. 0 SDCOMP1CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP1CTL register is locked. Only a system reset can clear this bit." "0,1" line.word 0x2 "CONTROLSS_SDFM0_SDCOMP2CTL" bitfld.word 0x2 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x2 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x4 "CONTROLSS_SDFM0_SDCOMP2EVT2FLTCTL" bitfld.word 0x4 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x4 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x6 "CONTROLSS_SDFM0_SDCOMP2EVT2FLTCLKCTL" hexmask.word 0x6 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x8 "CONTROLSS_SDFM0_SDCOMP2EVT1FLTCTL" bitfld.word 0x8 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x8 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x8 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0xA "CONTROLSS_SDFM0_SDCOMP2EVT1FLTCLKCTL" hexmask.word 0xA 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xDE++0xB line.word 0x0 "CONTROLSS_SDFM0_SDCOMP2LOCK" bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP2EVT1/2FLTTCTL and COMP2FILCLKCTL registers. 0 SDCOMP2EVT1/2FLTCTL and SDCOMP2EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP2EVT1/2FLTCTL and SDCOMP2EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP2CTL,Lock write-access to the SDCOMP2CTL register. 0 SDCOMP2CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP2CTL register is locked. Only a system reset can clear this bit." "0,1" line.word 0x2 "CONTROLSS_SDFM0_SDCOMP3CTL" bitfld.word 0x2 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x2 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x4 "CONTROLSS_SDFM0_SDCOMP3EVT2FLTCTL" bitfld.word 0x4 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x4 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x6 "CONTROLSS_SDFM0_SDCOMP3EVT2FLTCLKCTL" hexmask.word 0x6 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x8 "CONTROLSS_SDFM0_SDCOMP3EVT1FLTCTL" bitfld.word 0x8 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x8 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x8 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0xA "CONTROLSS_SDFM0_SDCOMP3EVT1FLTCLKCTL" hexmask.word 0xA 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xEE++0xB line.word 0x0 "CONTROLSS_SDFM0_SDCOMP3LOCK" bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP3EVT1/2FLTTCTL and COMP3FILCLKCTL registers. 0 SDCOMP3EVT1/2FLTCTL and SDCOMP3EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP3EVT1/2FLTCTL and SDCOMP3EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP3CTL,Lock write-access to the SDCOMP3CTL register. 0 SDCOMP3CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP3CTL register is locked. Only a system reset can clear this bit." "0,1" line.word 0x2 "CONTROLSS_SDFM0_SDCOMP4CTL" bitfld.word 0x2 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x2 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x4 "CONTROLSS_SDFM0_SDCOMP4EVT2FLTCTL" bitfld.word 0x4 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x4 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x6 "CONTROLSS_SDFM0_SDCOMP4EVT2FLTCLKCTL" hexmask.word 0x6 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x8 "CONTROLSS_SDFM0_SDCOMP4EVT1FLTCTL" bitfld.word 0x8 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x8 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x8 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0xA "CONTROLSS_SDFM0_SDCOMP4EVT1FLTCLKCTL" hexmask.word 0xA 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xFE++0x1 line.word 0x0 "CONTROLSS_SDFM0_SDCOMP4LOCK" bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP4EVT1/2FLTTCTL and COMP4FILCLKCTL registers. 0 SDCOMP4EVT1/2FLTCTL and SDCOMP4EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP4EVT1/2FLTCTL and SDCOMP4EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP4CTL,Lock write-access to the SDCOMP4CTL register. 0 SDCOMP4CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP4CTL register is locked. Only a system reset can clear this bit." "0,1" tree.end tree "SDFM1" base ad:0x50269000 rgroup.long 0x0++0x3 line.long 0x0 "CONTROLSS_SDFM1_SDIFLG" bitfld.long 0x0 31. "MIF,Set whenever any 'error' interrupt (MF1-4 IFL1-4 IFH1-4 SDFFOVF1-4) is active" "0,1" newline bitfld.long 0x0 23. "SDFFINT4,SDFIFO data ready interrupt for Ch4" "0,1" newline bitfld.long 0x0 22. "SDFFINT3,SDFIFO data ready interrupt for Ch3" "0,1" newline bitfld.long 0x0 21. "SDFFINT2,SDFIFO data ready interrupt for Ch2" "0,1" newline bitfld.long 0x0 20. "SDFFINT1,SDFIFO data ready interrupt for Ch1 0: SDFIFO data ready interrupt has NOT occurred 1: SDFIFO data ready interrupt has occurred" "0: SDFIFO data ready interrupt has NOT occurred,1: SDFIFO data ready interrupt has occurred" newline bitfld.long 0x0 19. "SDFFOVF4,FIFO Overflow Flag for Ch4" "0,1" newline bitfld.long 0x0 18. "SDFFOVF3,FIFO Overflow Flag for Ch3" "0,1" newline bitfld.long 0x0 17. "SDFFOVF2,FIFO Overflow Flag for Ch2" "0,1" newline bitfld.long 0x0 16. "SDFFOVF1,FIFO Overflow Flag for Ch1 0 - FIFO has not overflowed 1 - FIFO overflowed. # words received in FIFO ' FIFO depth (16) NEW word is lost" "0,1" newline bitfld.long 0x0 15. "AF4,Acknowledge flag for Filter 4 0: No new data available for Filter (in non-FIFO mode) 1: New data available for Filter (in non-FIFO mode)" "0: No new data available for Filter,1: New data available for Filter" newline bitfld.long 0x0 14. "AF3,Acknowledge flag for Filter 3 0: No new data available for Filter (in non-FIFO mode) 1: New data available for Filter (in non-FIFO mode)" "0: No new data available for Filter,1: New data available for Filter" newline bitfld.long 0x0 13. "AF2,Acknowledge flag for Filter 2 0: No new data available for Filter (in non-FIFO mode) 1: New data available for Filter (in non-FIFO mode)" "0: No new data available for Filter,1: New data available for Filter" newline bitfld.long 0x0 12. "AF1,Acknowledge flag for Filter 1 0: No new data available for Filter (in non-FIFO mode) 1: New data available for Filter (in non-FIFO mode)" "0: No new data available for Filter,1: New data available for Filter" newline bitfld.long 0x0 11. "MF4,Modulator Failure for Filter 4 0: Modulator is operating normally for Filter 1: Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 10. "MF3,Modulator Failure for Filter 3 0: Modulator is operating normally for Filter 1: Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 9. "MF2,Modulator Failure for Filter 2 0: Modulator is operating normally for Filter 1: Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 8. "MF1,Modulator Failure for Filter 1 0: Modulator is operating normally for Filter 1: Modulator failure for Filter" "0: Modulator is operating normally for Filter,1: Modulator failure for Filter" newline bitfld.long 0x0 7. "FLT4_FLG_CEVT2,CEVT2 Interrupt flag for filter4 0: CEVT2 event has not occured 1: CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 6. "FLT4_FLG_CEVT1,CEVT1 Interrupt flag for filter4 0: CEVT1 event has not occured 1: CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" newline bitfld.long 0x0 5. "FLT3_FLG_CEVT2,CEVT2 Interrupt flag for filter3 0: CEVT2 event has not occured 1: CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 4. "FLT3_FLG_CEVT1,CEVT1 Interrupt flag for filter3 0: CEVT1 event has not occured 1: CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" newline bitfld.long 0x0 3. "FLT2_FLG_CEVT2,CEVT2 Interrupt flag for filter2 0: CEVT2 event has not occured 1: CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 2. "FLT2_FLG_CEVT1,CEVT1 Interrupt flag for filter2 0: CEVT1 event has not occured 1: CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" newline bitfld.long 0x0 1. "FLT1_FLG_CEVT2,CEVT2 Interrupt flag for filter1 0: CEVT2 event has not occured 1: CEVT2 event has occurred" "0: CEVT2 event has not occured,1: CEVT2 event has occurred" newline bitfld.long 0x0 0. "FLT1_FLG_CEVT1,CEVT1 Interrupt flag for filter1 0: CEVT1 event has not occured 1: CEVT1 event has occurred" "0: CEVT1 event has not occured,1: CEVT1 event has occurred" group.long 0x4++0x3 line.long 0x0 "CONTROLSS_SDFM1_SDIFLGCLR" bitfld.long 0x0 31. "MIF,Flag-clear bit for SDFM Master Interrupt flag. Writing a 1 to clear MIF flag in SDIFLG register Writes of '0' are ignored. Note: If the MIF flag is cleared and other Interrupts are still pending MIF will again be set to 1 on the following.." "0,1" newline bitfld.long 0x0 23. "SDFFINT4,SDFIFO data ready Interrupt flag-clear bit for Ch4" "0,1" newline bitfld.long 0x0 22. "SDFFINT3,SDFIFO data ready Interrupt flag-clear bit for Ch3" "0,1" newline bitfld.long 0x0 21. "SDFFINT2,SDFIFO data ready Interrupt flag-clear bit for Ch2" "0,1" newline bitfld.long 0x0 20. "SDFFINT1,SDFIFO data ready Interrupt flag-clear bit for Ch1" "0,1" newline bitfld.long 0x0 19. "SDFFOVF4,SDFIFO overflow clear Ch4" "0,1" newline bitfld.long 0x0 18. "SDFFOVF3,SDFIFO overflow clear Ch3" "0,1" newline bitfld.long 0x0 17. "SDFFOVF2,SDFIFO overflow clear Ch2" "0,1" newline bitfld.long 0x0 16. "SDFFOVF1,SDFIFO overflow clear Ch1" "0,1" newline bitfld.long 0x0 15. "AF4,Flag-clear bit for Acknowledge flag for Filter 4" "0,1" newline bitfld.long 0x0 14. "AF3,Flag Clear bit for AF3" "0,1" newline bitfld.long 0x0 13. "AF2,Flag Clear bit for AF2" "0,1" newline bitfld.long 0x0 12. "AF1,Flag Clear bit for AF1" "0,1" newline bitfld.long 0x0 11. "MF4,Flag Clear bit for MF4" "0,1" newline bitfld.long 0x0 10. "MF3,Flag Clear bit for MF3" "0,1" newline bitfld.long 0x0 9. "MF2,Flag Clear bit for MF2" "0,1" newline bitfld.long 0x0 8. "MF1,Flag Clear bit for MF1" "0,1" newline bitfld.long 0x0 7. "FLT4_FLG_CEVT2,Flag Clear bit for FLT4_FLG_CEVT2" "0,1" newline bitfld.long 0x0 6. "FLT4_FLG_CEVT1,Flag Clear bit for FLT4_FLG_CEVT1" "0,1" newline bitfld.long 0x0 5. "FLT3_FLG_CEVT2,Flag Clear bit for FLT3_FLG_CEVT2" "0,1" newline bitfld.long 0x0 4. "FLT3_FLG_CEVT1,Flag Clear bit for FLT3_FLG_CEVT1" "0,1" newline bitfld.long 0x0 3. "FLT2_FLG_CEVT2,Flag Clear bit for FLT2_FLG_CEVT2" "0,1" newline bitfld.long 0x0 2. "FLT2_FLG_CEVT1,Flag Clear bit for FLT2_FLG_CEVT1" "0,1" newline bitfld.long 0x0 1. "FLT1_FLG_CEVT2,Flag Clear bit for FLT1_FLG_CEVT2" "0,1" newline bitfld.long 0x0 0. "FLT1_FLG_CEVT1,Flag Clear bit for FLT1_FLG_CEVT1" "0,1" group.word 0x8++0x1 line.word 0x0 "CONTROLSS_SDFM1_SDCTL" bitfld.word 0x0 13. "MIE,Master SDy_ERR interrupt enable 0: SDy_ERR Interrupt and interrupt flags are disabled 1: SDy_ERR Interrupt and interrupt flags are enabled" "0: SDy_ERR Interrupt and interrupt flags are disabled,1: SDy_ERR Interrupt and interrupt flags are enabled" newline bitfld.word 0x0 3. "HZ4,Flag Clear bit for HZ4" "0,1" newline bitfld.word 0x0 2. "HZ3,Flag Clear bit for HZ3" "0,1" newline bitfld.word 0x0 1. "HZ2,Flag Clear bit for HZ2" "0,1" newline bitfld.word 0x0 0. "HZ1,Flag Clear bit for HZ1" "0,1" group.word 0xC++0x1 line.word 0x0 "CONTROLSS_SDFM1_SDMFILEN" bitfld.word 0x0 11. "MFE,Master Filter Enable 0: All the four data filter units of SDFM module are disabled. All FIFOs are cleared 1: Data filter units can be enabled if bit FEN is '1'." "0: All the four data filter units of SDFM module..,1: Data filter units can be enabled if bit FEN is '1'" rgroup.word 0xE++0x1 line.word 0x0 "CONTROLSS_SDFM1_SDSTATUS" bitfld.word 0x0 3. "HZ4,High-level Threshold crossing (Z) flag Ch4 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0: Comparator filter output ' SDCMPHZ4.HLTZ 1:.." "0: Comparator filter output ' SDCMPHZ4,1: Comparator filter output '= SDCMPHZ4" newline bitfld.word 0x0 2. "HZ3,High-level Threshold crossing (Z) flag Ch3 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0: Comparator filter output ' SDCMPHZ3.HLTZ 1:.." "0: Comparator filter output ' SDCMPHZ3,1: Comparator filter output '= SDCMPHZ3" newline bitfld.word 0x0 1. "HZ2,High-level Threshold crossing (Z) flag Ch2 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0: Comparator filter output ' SDCMPHZ2.HLTZ 1:.." "0: Comparator filter output ' SDCMPHZ2,1: Comparator filter output '= SDCMPHZ2" newline bitfld.word 0x0 0. "HZ1,High-level Threshold crossing (Z) flag Ch1 Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator IFHx flag it does not have the ability to generate an interrupt. 0: Comparator filter output ' SDCMPHZ1.HLTZ 1:.." "0: Comparator filter output ' SDCMPHZ1,1: Comparator filter output '= SDCMPHZ1" group.word 0x20++0xB line.word 0x0 "CONTROLSS_SDFM1_SDCTLPARM1" bitfld.word 0x0 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1: SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0x0 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1: SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0x0 3. "SDCLKSEL,SD1 Clock source select. 0: Clock source to SDFM filter is its channel clock. 1: Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0x0 0.--1. "MOD,Modulator clock modes 0: Mode 0: Modulator clock running at 1x data rate 1: Reserved 2: Reserved 3: Reserved" "0: Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0x2 "CONTROLSS_SDFM1_SDDFPARM1" bitfld.word 0x2 12. "SDSYNCEN,PWM synchronization (SDSYNC) of data filter 0: PWM synchronization of data filter is disabled 1: PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0x2 10.--11. "SST,Data filter structure 00: Data filter runs with a Sincfast structure 01: Data filter runs with a Sinc1 structure 10: Data filter runs with a Sinc2 structure 11: Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x2 9. "AE,Data filter Acknowledge Enable 0: Acknowledge flag is disabled for the particular filter 1: Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0x2 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0x2 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0x4 "CONTROLSS_SDFM1_SDDPARM1" hexmask.word.byte 0x4 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0x4 10. "DR,Data filter Data representation 0: Data stored in 16b 2's complement 1: Data stored in 32b 2's complement" "0: Data stored in 16b 2's complement,1: Data stored in 32b 2's complement" line.word 0x6 "CONTROLSS_SDFM1_SDFLT1CMPH1" hexmask.word 0x6 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x8 "CONTROLSS_SDFM1_SDFLT1CMPL1" hexmask.word 0x8 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0xA "CONTROLSS_SDFM1_SDCPARM1" bitfld.word 0xA 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01: COMPL1 OR COMPH1 10: COMPL2 11: COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0xA 13. "CEN,Comparator Filter enable 0: Disable comparator filter 1: Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0xA 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01: COMPL1 OR COMPH1 10: COMPH2 11: COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0xA 10. "HZEN,High level (Z) Threshold crossing output enable 0: Disable Higher level Threshold (Z) crossing 1: Enable Higher level Threhold (Z) crossing" "0: Disable Higher level Threshold,1: Enable Higher level Threhold" newline bitfld.word 0xA 9. "MFIE,Modulator Failure Interrupt Enable 0: Disable modulator failure interrupt and its flag 1: Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0xA 7.--8. "CS1_CS0,Comparator filter structure 00: Comparator filter runs with a sincfast structure 01: Comparator filter runs with a Sinc1 structure 10: Comparator filter runs with a Sinc2 structure 11: Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xA 6. "EN_CEVT2,CEVT2 interrupt enable 0: Disable CEVT2 interrupt 1: Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0xA 5. "EN_CEVT1,CEVT1 interrupt enable 0: Disable CEVT1 interrupt 1: Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0xA 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x2C++0x7 line.long 0x0 "CONTROLSS_SDFM1_SDDATA1" hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" line.long 0x4 "CONTROLSS_SDFM1_SDDATFIFO1" hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" rgroup.word 0x34++0x1 line.word 0x0 "CONTROLSS_SDFM1_SDCDATA1" hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only" group.word 0x36++0x15 line.word 0x0 "CONTROLSS_SDFM1_SDFLT1CMPH2" hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "CONTROLSS_SDFM1_SDFLT1CMPHZ" hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold (Z) for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "CONTROLSS_SDFM1_SDFIFOCTL1" bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0: SDFIFO Overflow condition will not generate an interrupt 1: SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt (DRINT) source select 0 = AF1 (Select non-FIFO data-ready interrupt) 1 = SDFFINT1 (Select FIFO data-ready interrupt)" "0: AF1,1: SDFFINT1" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status (SDFFST) '= FIFO level (SDFFIL )" line.word 0x6 "CONTROLSS_SDFM1_SDSYNC1" bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0: WTSYNFLG can only be cleared manually (using WTSYNCLR bit) 1: WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0: SDFIFO is not automaticaly cleared upon receiving SDSYNC 1: SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear (always reads 0) 0: Write of 0 has no affect 1: Write of 1 clears WTSYNFLG" "0: Write of 0 has no affect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0: SDSYNC event has not occurred 1: SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0: Incoming Data written to SDFIFO on every Data-Ready (DR) Event 1: Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "CONTROLSS_SDFM1_SDFLT1CMPL2" hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." line.word 0xA "CONTROLSS_SDFM1_SDCTLPARM2" bitfld.word 0xA 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1: SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0xA 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1: SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0xA 3. "SDCLKSEL,SD2 Clock source select. 0: Clock source to SDFM filter is its channel clock. 1: Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0xA 0.--1. "MOD,Modulator clock modes 0: Mode 0: Modulator clock running at 1x data rate 1: Reserved 2: Reserved 3: Reserved" "0: Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0xC "CONTROLSS_SDFM1_SDDFPARM2" bitfld.word 0xC 12. "SDSYNCEN,PWM synchronization (SDSYNC) of data filter 0: PWM synchronization of data filter is disabled 1: PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0xC 10.--11. "SST,Data filter structure 00: Data filter runs with a Sincfast structure 01: Data filter runs with a Sinc1 structure 10: Data filter runs with a Sinc2 structure 11: Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xC 9. "AE,Data filter Acknowledge Enable 0: Acknowledge flag is disabled for the particular filter 1: Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0xC 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0xC 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0xE "CONTROLSS_SDFM1_SDDPARM2" hexmask.word.byte 0xE 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0xE 10. "DR,Data filter Data representation 0: Data stored in 16b 2's complement 1: Data stored in 32b 2's complement" "0: Data stored in 16b 2's complement,1: Data stored in 32b 2's complement" line.word 0x10 "CONTROLSS_SDFM1_SDFLT2CMPH1" hexmask.word 0x10 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x12 "CONTROLSS_SDFM1_SDFLT2CMPL1" hexmask.word 0x12 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0x14 "CONTROLSS_SDFM1_SDCPARM2" bitfld.word 0x14 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01: COMPL1 OR COMPH1 10: COMPL2 11: COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 13. "CEN,Comparator Filter enable 0: Disable comparator filter 1: Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0x14 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01: COMPL1 OR COMPH1 10: COMPH2 11: COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 10. "HZEN,High level (Z) Threshold crossing output enable 0: Disable Higher level Threshold (Z) crossing 1: Enable Higher level Threhold (Z) crossing" "0: Disable Higher level Threshold,1: Enable Higher level Threhold" newline bitfld.word 0x14 9. "MFIE,Modulator Failure Interrupt Enable 0: Disable modulator failure interrupt and its flag 1: Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0x14 7.--8. "CS1_CS0,Comparator filter structure 00: Comparator filter runs with a sincfast structure 01: Comparator filter runs with a Sinc1 structure 10: Comparator filter runs with a Sinc2 structure 11: Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x14 6. "EN_CEVT2,CEVT2 interrupt enable 0: Disable CEVT2 interrupt 1: Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0x14 5. "EN_CEVT1,CEVT1 interrupt enable 0: Disable CEVT1 interrupt 1: Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0x14 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x4C++0x7 line.long 0x0 "CONTROLSS_SDFM1_SDDATA2" hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" line.long 0x4 "CONTROLSS_SDFM1_SDDATFIFO2" hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" rgroup.word 0x54++0x1 line.word 0x0 "CONTROLSS_SDFM1_SDCDATA2" hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only" group.word 0x56++0x15 line.word 0x0 "CONTROLSS_SDFM1_SDFLT2CMPH2" hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "CONTROLSS_SDFM1_SDFLT2CMPHZ" hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold (Z) for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "CONTROLSS_SDFM1_SDFIFOCTL2" bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0: SDFIFO Overflow condition will not generate an interrupt 1: SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt (DRINT) source select 0 = AF1 (Select non-FIFO data-ready interrupt) 1 = SDFFINT1 (Select FIFO data-ready interrupt)" "0: AF1,1: SDFFINT1" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status (SDFFST) '= FIFO level (SDFFIL )" line.word 0x6 "CONTROLSS_SDFM1_SDSYNC2" bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0: WTSYNFLG can only be cleared manually (using WTSYNCLR bit) 1: WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0: SDFIFO is not automaticaly cleared upon receiving SDSYNC 1: SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear (always reads 0) 0: Write of 0 has no affect 1: Write of 1 clears WTSYNFLG" "0: Write of 0 has no affect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0: SDSYNC event has not occurred 1: SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0: Incoming Data written to SDFIFO on every Data-Ready (DR) Event 1: Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "CONTROLSS_SDFM1_SDFLT2CMPL2" hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." line.word 0xA "CONTROLSS_SDFM1_SDCTLPARM3" bitfld.word 0xA 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1: SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0xA 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1: SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0xA 3. "SDCLKSEL,SD3 Clock source select. 0: Clock source to SDFM filter is its channel clock. 1: Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0xA 0.--1. "MOD,Modulator clock modes 0: Mode 0: Modulator clock running at 1x data rate 1: Reserved 2: Reserved 3: Reserved" "0: Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0xC "CONTROLSS_SDFM1_SDDFPARM3" bitfld.word 0xC 12. "SDSYNCEN,PWM synchronization (SDSYNC) of data filter 0: PWM synchronization of data filter is disabled 1: PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0xC 10.--11. "SST,Data filter structure 00: Data filter runs with a Sincfast structure 01: Data filter runs with a Sinc1 structure 10: Data filter runs with a Sinc2 structure 11: Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xC 9. "AE,Data filter Acknowledge Enable 0: Acknowledge flag is disabled for the particular filter 1: Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0xC 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0xC 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0xE "CONTROLSS_SDFM1_SDDPARM3" hexmask.word.byte 0xE 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0xE 10. "DR,Data filter Data representation 0: Data stored in 16b 2's complement 1: Data stored in 32b 2's complement" "0: Data stored in 16b 2's complement,1: Data stored in 32b 2's complement" line.word 0x10 "CONTROLSS_SDFM1_SDFLT3CMPH1" hexmask.word 0x10 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x12 "CONTROLSS_SDFM1_SDFLT3CMPL1" hexmask.word 0x12 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0x14 "CONTROLSS_SDFM1_SDCPARM3" bitfld.word 0x14 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01: COMPL1 OR COMPH1 10: COMPL2 11: COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 13. "CEN,Comparator Filter enable 0: Disable comparator filter 1: Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0x14 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01: COMPL1 OR COMPH1 10: COMPH2 11: COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 10. "HZEN,High level (Z) Threshold crossing output enable 0: Disable Higher level Threshold (Z) crossing 1: Enable Higher level Threhold (Z) crossing" "0: Disable Higher level Threshold,1: Enable Higher level Threhold" newline bitfld.word 0x14 9. "MFIE,Modulator Failure Interrupt Enable 0: Disable modulator failure interrupt and its flag 1: Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0x14 7.--8. "CS1_CS0,Comparator filter structure 00: Comparator filter runs with a sincfast structure 01: Comparator filter runs with a Sinc1 structure 10: Comparator filter runs with a Sinc2 structure 11: Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x14 6. "EN_CEVT2,CEVT2 interrupt enable 0: Disable CEVT2 interrupt 1: Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0x14 5. "EN_CEVT1,CEVT1 interrupt enable 0: Disable CEVT1 interrupt 1: Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0x14 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x6C++0x7 line.long 0x0 "CONTROLSS_SDFM1_SDDATA3" hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" line.long 0x4 "CONTROLSS_SDFM1_SDDATFIFO3" hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" rgroup.word 0x74++0x1 line.word 0x0 "CONTROLSS_SDFM1_SDCDATA3" hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only" group.word 0x76++0x15 line.word 0x0 "CONTROLSS_SDFM1_SDFLT3CMPH2" hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "CONTROLSS_SDFM1_SDFLT3CMPHZ" hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold (Z) for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "CONTROLSS_SDFM1_SDFIFOCTL3" bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0: SDFIFO Overflow condition will not generate an interrupt 1: SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt (DRINT) source select 0 = AF1 (Select non-FIFO data-ready interrupt) 1 = SDFFINT1 (Select FIFO data-ready interrupt)" "0: AF1,1: SDFFINT1" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status (SDFFST) '= FIFO level (SDFFIL )" line.word 0x6 "CONTROLSS_SDFM1_SDSYNC3" bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0: WTSYNFLG can only be cleared manually (using WTSYNCLR bit) 1: WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0: SDFIFO is not automaticaly cleared upon receiving SDSYNC 1: SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear (always reads 0) 0: Write of 0 has no affect 1: Write of 1 clears WTSYNFLG" "0: Write of 0 has no affect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0: SDSYNC event has not occurred 1: SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0: Incoming Data written to SDFIFO on every Data-Ready (DR) Event 1: Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "CONTROLSS_SDFM1_SDFLT3CMPL2" hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." line.word 0xA "CONTROLSS_SDFM1_SDCTLPARM4" bitfld.word 0xA 6. "SDDATASYNC,0: SD Data is not passed through a synchronizer. 1: SD Data is passed through a synchronizer." "0: SD Data is not passed through a synchronizer,1: SD Data is passed through a synchronizer" newline bitfld.word 0xA 4. "SDCLKSYNC,0: SD Clock is not passed through a synchronizer. 1: SD Clock is passed through a synchronizer." "0: SD Clock is not passed through a synchronizer,1: SD Clock is passed through a synchronizer" newline bitfld.word 0xA 3. "SDCLKSEL,SD4 Clock source select. 0: Clock source to SDFM filter is its channel clock. 1: Clock source to SDFM filter is SD1 filter clock." "0: Clock source to SDFM filter is its channel clock,1: Clock source to SDFM filter is SD1 filter clock" newline bitfld.word 0xA 0.--1. "MOD,Modulator clock modes 0: Mode 0: Modulator clock running at 1x data rate 1: Reserved 2: Reserved 3: Reserved" "0: Modulator clock running at 1x data rate,1: Reserved,2: Reserved,3: Reserved" line.word 0xC "CONTROLSS_SDFM1_SDDFPARM4" bitfld.word 0xC 12. "SDSYNCEN,PWM synchronization (SDSYNC) of data filter 0: PWM synchronization of data filter is disabled 1: PWM synchronization of data filter is enabled Note: SDSYNCx.SYNCSEL bits define which PWM signal is used to synchronize PWMs" "0: PWM synchronization of data filter is disabled,1: PWM synchronization of data filter is enabled.." newline bitfld.word 0xC 10.--11. "SST,Data filter structure 00: Data filter runs with a Sincfast structure 01: Data filter runs with a Sinc1 structure 10: Data filter runs with a Sinc2 structure 11: Data filter runs with a Sinc3 structure" "0: Data filter runs with a Sincfast structure,1: Data filter runs with a Sinc1 structure,?,?" newline bitfld.word 0xC 9. "AE,Data filter Acknowledge Enable 0: Acknowledge flag is disabled for the particular filter 1: Acknowledge flag is enabled for the particular filter" "0: Acknowledge flag is disabled for the particular..,1: Acknowledge flag is enabled for the particular.." newline bitfld.word 0xC 8. "FEN,Filter Enable 0: The data filter is disabled and no data is produced 1: The data filter is enabled and data are produced in the data filter Note: When filter is disabled DOSR counter held in reset filter data erased. Also resets FIFO.." "0: The data filter is disabled and no data is..,1: The data filter is enabled and data are produced.." newline hexmask.word.byte 0xC 0.--7. 1. "DOSR,Data filter Oversampling ratio The actual oversampling ratio of data filter is DOSR + 1 These bits set the oversampling ratio of the data filter. 0x0FF represents an oversampling ratio of 256." line.word 0xE "CONTROLSS_SDFM1_SDDPARM4" hexmask.word.byte 0xE 11.--15. 1. "SH,Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen." newline bitfld.word 0xE 10. "DR,Data filter Data representation 0: Data stored in 16b 2's complement 1: Data stored in 32b 2's complement" "0: Data stored in 16b 2's complement,1: Data stored in 32b 2's complement" line.word 0x10 "CONTROLSS_SDFM1_SDFLT4CMPH1" hexmask.word 0x10 0.--14. 1. "HLT,Unsigned high-level threshold for the comparator filter output." line.word 0x12 "CONTROLSS_SDFM1_SDFLT4CMPL1" hexmask.word 0x12 0.--14. 1. "LLT,Unsigned low-level threshold for the comparator filter output." line.word 0x14 "CONTROLSS_SDFM1_SDCPARM4" bitfld.word 0x14 14.--15. "CEVT2SEL,Comparator Event2 Select 00: COMPL1 01: COMPL1 OR COMPH1 10: COMPL2 11: COMPL2 OR COMPH2" "0: COMPL1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 13. "CEN,Comparator Filter enable 0: Disable comparator filter 1: Enable comparator filter" "0: Disable comparator filter,1: Enable comparator filter" newline bitfld.word 0x14 11.--12. "CEVT1SEL,Comparator Event1 Select 00: COMPH1 01: COMPL1 OR COMPH1 10: COMPH2 11: COMPL2 OR COMPH2" "0: COMPH1,1: COMPL1 OR COMPH1,?,?" newline bitfld.word 0x14 10. "HZEN,High level (Z) Threshold crossing output enable 0: Disable Higher level Threshold (Z) crossing 1: Enable Higher level Threhold (Z) crossing" "0: Disable Higher level Threshold,1: Enable Higher level Threhold" newline bitfld.word 0x14 9. "MFIE,Modulator Failure Interrupt Enable 0: Disable modulator failure interrupt and its flag 1: Enable modulator failure interrupt and its flag" "0: Disable modulator failure interrupt and its flag,1: Enable modulator failure interrupt and its flag" newline bitfld.word 0x14 7.--8. "CS1_CS0,Comparator filter structure 00: Comparator filter runs with a sincfast structure 01: Comparator filter runs with a Sinc1 structure 10: Comparator filter runs with a Sinc2 structure 11: Comparator filter runs with a Sinc3 structure" "0: Comparator filter runs with a sincfast structure,1: Comparator filter runs with a Sinc1 structure,?,?" newline bitfld.word 0x14 6. "EN_CEVT2,CEVT2 interrupt enable 0: Disable CEVT2 interrupt 1: Enable CEVT2 interrupt" "0: Disable CEVT2 interrupt,1: Enable CEVT2 interrupt" newline bitfld.word 0x14 5. "EN_CEVT1,CEVT1 interrupt enable 0: Disable CEVT1 interrupt 1: Enable CEVT1 interrupt" "0: Disable CEVT1 interrupt,1: Enable CEVT1 interrupt" newline hexmask.word.byte 0x14 0.--4. 1. "COSR,Comparator Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 32" rgroup.long 0x8C++0x7 line.long 0x0 "CONTROLSS_SDFM1_SDDATA4" hexmask.long.word 0x0 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x0 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" line.long 0x4 "CONTROLSS_SDFM1_SDDATFIFO4" hexmask.long.word 0x4 16.--31. 1. "DATA32HI,Hi-order 16b in 32b mode 16-bit Data in 16b mode" newline hexmask.long.word 0x4 0.--15. 1. "DATA16,Lo-order 16b in 32b mode" rgroup.word 0x94++0x1 line.word 0x0 "CONTROLSS_SDFM1_SDCDATA4" hexmask.word 0x0 0.--15. 1. "DATA16,Comparator Data output - 16b only" group.word 0x96++0x9 line.word 0x0 "CONTROLSS_SDFM1_SDFLT4CMPH2" hexmask.word 0x0 0.--14. 1. "HLT2,Second Unsigned high-level threshold for the comparator filter output." line.word 0x2 "CONTROLSS_SDFM1_SDFLT4CMPHZ" hexmask.word 0x2 0.--14. 1. "HLTZ,Unsigned High-level threshold (Z) for the comparator filter output Primarily intended for detecting 'zero'-crossing events. Unlike the primary comparator SDCMPHx it does not have the ability to generate an interrupt." line.word 0x4 "CONTROLSS_SDFM1_SDFIFOCTL4" bitfld.word 0x4 15. "OVFIEN,SDFIFO Overflow interrupt enable 0: SDFIFO Overflow condition will not generate an interrupt 1: SDFIFO overflow condition generates an interrupt on SDy_ERR" "0: SDFIFO Overflow condition will not generate an..,1: SDFIFO overflow condition generates an interrupt.." newline bitfld.word 0x4 14. "DRINTSEL,Data-Ready Interrupt (DRINT) source select 0 = AF1 (Select non-FIFO data-ready interrupt) 1 = SDFFINT1 (Select FIFO data-ready interrupt)" "0: AF1,1: SDFFINT1" newline bitfld.word 0x4 13. "FFEN,SDFIFO Enable 0: Disable FIFO operation 1: Enable FIFO operation Note: When FIFO is disabled FIFO contents are cleared" "0: Disable FIFO operation,1: Enable FIFO operation Note: When FIFO is disabled" newline bitfld.word 0x4 12. "FFIEN,SDFIFO data ready Interrupt Enable" "0,1" newline hexmask.word.byte 0x4 6.--10. 1. "SDFFST,SDFIFO Status 00000 FIFO empty 00001 FIFO has 1 word . . . . 10000 FIFO has 16 words" newline hexmask.word.byte 0x4 0.--4. 1. "SDFFIL,SDFIFO interrupt level bits The FIFO will generate an interrupt when the FIFO status (SDFFST) '= FIFO level (SDFFIL )" line.word 0x6 "CONTROLSS_SDFM1_SDSYNC4" bitfld.word 0x6 10. "WTSCLREN,WTSYNFLG Clear-on-FIFOINT Enable 0: WTSYNFLG can only be cleared manually (using WTSYNCLR bit) 1: WTSYNFLG is cleared automatically on SDFFINT" "0: WTSYNFLG can only be cleared manually,1: WTSYNFLG is cleared automatically on SDFFINT" newline bitfld.word 0x6 9. "FFSYNCCLREN,FIFO Clear-on-SDSYNC Enable 0: SDFIFO is not automaticaly cleared upon receiving SDSYNC 1: SDFIFO is automaticaly cleared upon receiving SDSYNC" "0: SDFIFO is not automaticaly cleared upon..,1: SDFIFO is automaticaly cleared upon receiving.." newline bitfld.word 0x6 8. "WTSYNCLR,Wait-for-Sync Flag Clear (always reads 0) 0: Write of 0 has no affect 1: Write of 1 clears WTSYNFLG" "0: Write of 0 has no affect,1: Write of 1 clears WTSYNFLG" newline rbitfld.word 0x6 7. "WTSYNFLG,Wait-for-Sync Flag 0: SDSYNC event has not occurred 1: SDSYNC event occurred." "0: SDSYNC event has not occurred,1: SDSYNC event occurred" newline bitfld.word 0x6 6. "WTSYNCEN,Wait-for-Sync Enable 0: Incoming Data written to SDFIFO on every Data-Ready (DR) Event 1: Incoming Data written to SDFIFO on DR event only after SDSYNC event occurs" "0: Incoming Data written to SDFIFO on every..,1: Incoming Data written to SDFIFO on DR event only.." newline hexmask.word.byte 0x6 0.--5. 1. "SYNCSEL,Defines source for the SDSYNC Input on this channel Refer SDSYNCx.SYNCSEL table" line.word 0x8 "CONTROLSS_SDFM1_SDFLT4CMPL2" hexmask.word 0x8 0.--14. 1. "LLT2,Second Unsigned low-level threshold for the comparator filter output." group.word 0xC0++0x9 line.word 0x0 "CONTROLSS_SDFM1_SDCOMP1CTL" bitfld.word 0x0 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x0 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x2 "CONTROLSS_SDFM1_SDCOMP1EVT2FLTCTL" bitfld.word 0x2 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x2 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x2 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x4 "CONTROLSS_SDFM1_SDCOMP1EVT2FLTCLKCTL" hexmask.word 0x4 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x6 "CONTROLSS_SDFM1_SDCOMP1EVT1FLTCTL" bitfld.word 0x6 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x6 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x6 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x8 "CONTROLSS_SDFM1_SDCOMP1EVT1FLTCLKCTL" hexmask.word 0x8 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xCE++0xB line.word 0x0 "CONTROLSS_SDFM1_SDCOMP1LOCK" bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP1EVT1/2FLTTCTL and COMP1FILCLKCTL registers. 0 SDCOMP1EVT1/2FLTCTL and SDCOMP1EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP1EVT1/2FLTCTL and SDCOMP1EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP1CTL,Lock write-access to the SDCOMP1CTL register. 0 SDCOMP1CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP1CTL register is locked. Only a system reset can clear this bit." "0,1" line.word 0x2 "CONTROLSS_SDFM1_SDCOMP2CTL" bitfld.word 0x2 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x2 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x4 "CONTROLSS_SDFM1_SDCOMP2EVT2FLTCTL" bitfld.word 0x4 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x4 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x6 "CONTROLSS_SDFM1_SDCOMP2EVT2FLTCLKCTL" hexmask.word 0x6 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x8 "CONTROLSS_SDFM1_SDCOMP2EVT1FLTCTL" bitfld.word 0x8 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x8 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x8 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0xA "CONTROLSS_SDFM1_SDCOMP2EVT1FLTCLKCTL" hexmask.word 0xA 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xDE++0xB line.word 0x0 "CONTROLSS_SDFM1_SDCOMP2LOCK" bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP2EVT1/2FLTTCTL and COMP2FILCLKCTL registers. 0 SDCOMP2EVT1/2FLTCTL and SDCOMP2EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP2EVT1/2FLTCTL and SDCOMP2EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP2CTL,Lock write-access to the SDCOMP2CTL register. 0 SDCOMP2CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP2CTL register is locked. Only a system reset can clear this bit." "0,1" line.word 0x2 "CONTROLSS_SDFM1_SDCOMP3CTL" bitfld.word 0x2 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x2 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x4 "CONTROLSS_SDFM1_SDCOMP3EVT2FLTCTL" bitfld.word 0x4 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x4 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x6 "CONTROLSS_SDFM1_SDCOMP3EVT2FLTCLKCTL" hexmask.word 0x6 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x8 "CONTROLSS_SDFM1_SDCOMP3EVT1FLTCTL" bitfld.word 0x8 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x8 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x8 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0xA "CONTROLSS_SDFM1_SDCOMP3EVT1FLTCLKCTL" hexmask.word 0xA 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xEE++0xB line.word 0x0 "CONTROLSS_SDFM1_SDCOMP3LOCK" bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP3EVT1/2FLTTCTL and COMP3FILCLKCTL registers. 0 SDCOMP3EVT1/2FLTCTL and SDCOMP3EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP3EVT1/2FLTCTL and SDCOMP3EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP3CTL,Lock write-access to the SDCOMP3CTL register. 0 SDCOMP3CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP3CTL register is locked. Only a system reset can clear this bit." "0,1" line.word 0x2 "CONTROLSS_SDFM1_SDCOMP4CTL" bitfld.word 0x2 10.--11. "CEVT2DIGFILTSEL,High comparator COMPH source select. 0 CEVT2 output drives COMPLOUT 1 Reserved 2 Output of digital filter drives COMPLOUT 3 Reserved" "0,1,2,3" newline bitfld.word 0x2 2.--3. "CEVT1DIGFILTSEL,High comparator COMPH source select. 0 CEVT1 output drives COMPHOUT 1 Reserved 2 Output of digital filter drives COMPHOUT 3 Reserved" "0,1,2,3" line.word 0x4 "CONTROLSS_SDFM1_SDCOMP4EVT2FLTCTL" bitfld.word 0x4 15. "FILINIT,Low filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x4 9.--13. 1. "THRESH,Low filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x4 4.--8. 1. "SAMPWIN,Low filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0x6 "CONTROLSS_SDFM1_SDCOMP4EVT2FLTCLKCTL" hexmask.word 0x6 0.--9. 1. "CLKPRESCALE,Low filter sample clock prescale. Number of system clocks between samples." line.word 0x8 "CONTROLSS_SDFM1_SDCOMP4EVT1FLTCTL" bitfld.word 0x8 15. "FILINIT,High filter initialization. 0 No effect 1 Initialize all samples to the filter input value" "0,1" newline hexmask.word.byte 0x8 9.--13. 1. "THRESH,High filter majority voting threshold. At least THRESH samples of the opposite state must appear within the sample window in order for the output to change state." newline hexmask.word.byte 0x8 4.--8. 1. "SAMPWIN,High filter sample window size. Number of samples to monitor is SAMPWIN+1." line.word 0xA "CONTROLSS_SDFM1_SDCOMP4EVT1FLTCLKCTL" hexmask.word 0xA 0.--9. 1. "CLKPRESCALE,High filter sample clock prescale. Number of system clocks between samples." group.word 0xFE++0x1 line.word 0x0 "CONTROLSS_SDFM1_SDCOMP4LOCK" bitfld.word 0x0 3. "COMP,Lock write-access to the SDCOMP4EVT1/2FLTTCTL and COMP4FILCLKCTL registers. 0 SDCOMP4EVT1/2FLTCTL and SDCOMP4EVT1/2FLTCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 SDCOMP4EVT1/2FLTCTL and SDCOMP4EVT1/2FLTCLKCTL.." "0,1" newline bitfld.word 0x0 0. "SDCOMP4CTL,Lock write-access to the SDCOMP4CTL register. 0 SDCOMP4CTL register is not locked. Write 0 to this bit has no effect. 1 SDCOMP4CTL register is locked. Only a system reset can clear this bit." "0,1" tree.end tree.end tree.end tree "CPSW" base ad:0x52800000 rgroup.long 0x0++0x3 line.long 0x0 "CPSW0_CPSW_NUSS_IDVER_REG" hexmask.long.word 0x0 16.--31. 1. "IDENT,Identification value" hexmask.long.byte 0x0 11.--15. 1. "RTL_VER,RTL version value" newline bitfld.long 0x0 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--7. 1. "MINOR_VER,Minor version value" group.long 0x4++0x3 line.long 0x0 "CPSW0_SS_SYNCE_COUNT_REG" hexmask.long 0x0 0.--31. 1. "SYNCE_CNT,Sync E Count Value" group.byte 0x8++0x0 line.byte 0x0 "CPSW0_SS_SYNCE_MUX_REG" hexmask.byte 0x0 0.--5. 1. "SYNCE_SEL,Sync E Select Value" group.byte 0xC++0x0 line.byte 0x0 "CPSW0_SS_CONTROL_REG" bitfld.byte 0x0 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode: 0=The low power indicate state includes gating off the CPPI_GCLK to the CPSW 1=The low power indicate state does not gate the clock to the CPSW" "0: The low power indicate state includes gating off..,1: The low power indicate state does not gate the.." bitfld.byte 0x0 0. "EEE_EN,Energy Efficient Ethernet Enable: 0=EEE is disabled 1=EEE is enabled" "0: EEE is disabled,1: EEE is enabled" group.long 0x18++0x3 line.long 0x0 "CPSW0_SS_INT_CONTROL_REG" bitfld.long 0x0 31. "INT_TEST,Interrupt Test" "0,1" bitfld.long 0x0 30. "INT_SEL_VEC_EN,Interrupt Sel Vector Enable" "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "INT_BYPASS,Interrupt Bypass Value" hexmask.long.word 0x0 0.--11. 1. "INT_PRESCALE,Interrupt Prescale Value" rgroup.long 0x1C++0x7 line.long 0x0 "CPSW0_SS_STATUS_REG" bitfld.long 0x0 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW" "0,1" line.long 0x4 "CPSW0_SUBSYSTEM_CONFIG_REG" hexmask.long.byte 0x4 20.--27. 1. "XGMII,The Number of XGMII Ports included in the CPSW_NUSS" bitfld.long 0x4 19. "QSGMII,QSGMII is included in the CPSW_NUSS" "0,1" newline bitfld.long 0x4 18. "SGMII,SGMII is included in the CPSW_NUSS" "0,1" bitfld.long 0x4 17. "RGMII,RGMII is included in the CPSW_NUSS" "0,1" newline bitfld.long 0x4 16. "RMII,RMII is included in the CPSW_NUSS" "0,1" hexmask.long.byte 0x4 8.--12. 1. "NUM_GENF,The number of CPTS GENF outputs" newline hexmask.long.byte 0x4 0.--7. 1. "NUM_PORTS,The total number of ports including the host port 0" rgroup.byte 0x30++0x0 line.byte 0x0 "CPSW0_RGMII1_STATUS_REG" bitfld.byte 0x0 3. "FULLDUPLEX,Rgmii1 full dulex: 0=Half-duplex 1=Full-duplex" "0: Half-duplex,1: Full-duplex" bitfld.byte 0x0 1.--2. "SPEED,Rgmii1 speed: 00=10Mbps 01=100Mbps 10=1000Mbps 11=reserved" "0: 10Mbps,1: 100Mbps,?,?" newline bitfld.byte 0x0 0. "LINK,Rgmii1 link indicator: 0=Link is down 1=Link is up" "0: Link is down,1: Link is up" rgroup.byte 0x34++0x0 line.byte 0x0 "CPSW0_RGMII2_STATUS_REG" bitfld.byte 0x0 3. "FULLDUPLEX,Rgmii2 full dulex: 0=Half-duplex 1=Full-duplex" "0: Half-duplex,1: Full-duplex" bitfld.byte 0x0 1.--2. "SPEED,Rgmii2 speed: 00=10Mbps 01=100Mbps 10=1000Mbps 11=reserved" "0: 10Mbps,1: 100Mbps,?,?" newline bitfld.byte 0x0 0. "LINK,Rgmii2 link indicator: 0=Link is down 1=Link is up" "0: Link is down,1: Link is up" tree.end tree "DCC" base ad:0x0 tree "DCC0" base ad:0x52B00000 group.long 0x0++0x3 line.long 0x0 "DCC0_DCCGCTRL" hexmask.long.byte 0x0 12.--15. 1. "DONENA,The DONEENA bit enables/disables the done signal. 0101 = disabled & 1010 = enabled" hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,Single/Continuous checking mode. 0101 = Continuous & 1010 = Single" hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. 0101 = disabled & 1010 = enabled" hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc 0101 = disabled & 1010 = enabled" rgroup.long 0x4++0x3 line.long 0x0 "DCC0_DCCREV" bitfld.long 0x0 28.--30. "SCHEME,SCHEME. - (RO )" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 14.--25. 1. "FUNC,Functional release number - (RO )" hexmask.long.byte 0x0 9.--13. 1. "RTL,Design Release Number - (RO )" bitfld.long 0x0 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "CUSTOM,Indicates a special version of the module. May not be supported by standard software - (RO )" "0,1" hexmask.long.byte 0x0 0.--4. 1. "MINOR,Minor revision number. - (RO )" group.long 0x8++0xF line.long 0x0 "DCC0_DCCCNTSEED0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0)" line.long 0x4 "DCC0_DCCVALIDSEED0" hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x8 "DCC0_DCCCNTSEED1" hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1" line.long 0xC "DCC0_DCCSTAT" bitfld.long 0xC 1. "DONE,Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag." "0,1" bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag." "0,1" rgroup.long 0x18++0xB line.long 0x0 "DCC0_DCCCNT0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. - (RO )" line.long 0x4 "DCC0_DCCVALID0" hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. - (RO )" line.long 0x8 "DCC0_DCCCNT1" hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. - (RO )" group.long 0x24++0x7 line.long 0x0 "DCC0_DCCCLKSSRC1" hexmask.long.byte 0x0 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)" hexmask.long.byte 0x0 0.--3. 1. "CLK_SRC1,Clock source selection for Source 0DCC-A Clock source-0 selection Program value and its respective clock selected 0x0 - REF_CLK0x1 - CPU_CLK0x2 - RC_CLK0x3 - RC_CLK0x4 - RC_CLK0x5 - RC_CLK0x6 - RC_CLK0x7 - RC_CLKDCC-B Clock source-0 selection.." line.long 0x4 "DCC0_DCCCLKSSRC0" hexmask.long.byte 0x4 0.--3. 1. "CLK_SRC0,Clock source selection for Source 0DCC-A Clock source-0 selection Program value and its respective clock selected 0 - REF_CLKA - PLL_6005 - PLL_240DCC-B Clock source-0 selection Program value and its respective clock selected 0 - PLL_600A -.." tree.end tree "DCC1" base ad:0x52B01000 group.long 0x0++0x3 line.long 0x0 "DCC1_DCCGCTRL" hexmask.long.byte 0x0 12.--15. 1. "DONENA,The DONEENA bit enables/disables the done signal. 0101 = disabled & 1010 = enabled" hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,Single/Continuous checking mode. 0101 = Continuous & 1010 = Single" hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. 0101 = disabled & 1010 = enabled" hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc 0101 = disabled & 1010 = enabled" rgroup.long 0x4++0x3 line.long 0x0 "DCC1_DCCREV" bitfld.long 0x0 28.--30. "SCHEME,SCHEME. - (RO )" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 14.--25. 1. "FUNC,Functional release number - (RO )" hexmask.long.byte 0x0 9.--13. 1. "RTL,Design Release Number - (RO )" bitfld.long 0x0 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "CUSTOM,Indicates a special version of the module. May not be supported by standard software - (RO )" "0,1" hexmask.long.byte 0x0 0.--4. 1. "MINOR,Minor revision number. - (RO )" group.long 0x8++0xF line.long 0x0 "DCC1_DCCCNTSEED0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0)" line.long 0x4 "DCC1_DCCVALIDSEED0" hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x8 "DCC1_DCCCNTSEED1" hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1" line.long 0xC "DCC1_DCCSTAT" bitfld.long 0xC 1. "DONE,Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag." "0,1" bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag." "0,1" rgroup.long 0x18++0xB line.long 0x0 "DCC1_DCCCNT0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. - (RO )" line.long 0x4 "DCC1_DCCVALID0" hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. - (RO )" line.long 0x8 "DCC1_DCCCNT1" hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. - (RO )" group.long 0x24++0x7 line.long 0x0 "DCC1_DCCCLKSSRC1" hexmask.long.byte 0x0 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)" hexmask.long.byte 0x0 0.--3. 1. "CLK_SRC1,Clock source selection for Source 0DCC-A Clock source-0 selection Program value and its respective clock selected 0x0 - REF_CLK0x1 - CPU_CLK0x2 - RC_CLK0x3 - RC_CLK0x4 - RC_CLK0x5 - RC_CLK0x6 - RC_CLK0x7 - RC_CLKDCC-B Clock source-0 selection.." line.long 0x4 "DCC1_DCCCLKSSRC0" hexmask.long.byte 0x4 0.--3. 1. "CLK_SRC0,Clock source selection for Source 0DCC-A Clock source-0 selection Program value and its respective clock selected 0 - REF_CLKA - PLL_6005 - PLL_240DCC-B Clock source-0 selection Program value and its respective clock selected 0 - PLL_600A -.." tree.end tree "DCC2" base ad:0x52B02000 group.long 0x0++0x3 line.long 0x0 "DCC2_DCCGCTRL" hexmask.long.byte 0x0 12.--15. 1. "DONENA,The DONEENA bit enables/disables the done signal. 0101 = disabled & 1010 = enabled" hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,Single/Continuous checking mode. 0101 = Continuous & 1010 = Single" hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. 0101 = disabled & 1010 = enabled" hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc 0101 = disabled & 1010 = enabled" rgroup.long 0x4++0x3 line.long 0x0 "DCC2_DCCREV" bitfld.long 0x0 28.--30. "SCHEME,SCHEME. - (RO )" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 14.--25. 1. "FUNC,Functional release number - (RO )" hexmask.long.byte 0x0 9.--13. 1. "RTL,Design Release Number - (RO )" bitfld.long 0x0 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "CUSTOM,Indicates a special version of the module. May not be supported by standard software - (RO )" "0,1" hexmask.long.byte 0x0 0.--4. 1. "MINOR,Minor revision number. - (RO )" group.long 0x8++0xF line.long 0x0 "DCC2_DCCCNTSEED0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0)" line.long 0x4 "DCC2_DCCVALIDSEED0" hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x8 "DCC2_DCCCNTSEED1" hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1" line.long 0xC "DCC2_DCCSTAT" bitfld.long 0xC 1. "DONE,Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag." "0,1" bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag." "0,1" rgroup.long 0x18++0xB line.long 0x0 "DCC2_DCCCNT0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. - (RO )" line.long 0x4 "DCC2_DCCVALID0" hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. - (RO )" line.long 0x8 "DCC2_DCCCNT1" hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. - (RO )" group.long 0x24++0x7 line.long 0x0 "DCC2_DCCCLKSSRC1" hexmask.long.byte 0x0 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)" hexmask.long.byte 0x0 0.--3. 1. "CLK_SRC1,Clock source selection for Source 0DCC-A Clock source-0 selection Program value and its respective clock selected 0x0 - REF_CLK0x1 - CPU_CLK0x2 - RC_CLK0x3 - RC_CLK0x4 - RC_CLK0x5 - RC_CLK0x6 - RC_CLK0x7 - RC_CLKDCC-B Clock source-0 selection.." line.long 0x4 "DCC2_DCCCLKSSRC0" hexmask.long.byte 0x4 0.--3. 1. "CLK_SRC0,Clock source selection for Source 0DCC-A Clock source-0 selection Program value and its respective clock selected 0 - REF_CLKA - PLL_6005 - PLL_240DCC-B Clock source-0 selection Program value and its respective clock selected 0 - PLL_600A -.." tree.end tree "DCC3" base ad:0x52B03000 group.long 0x0++0x3 line.long 0x0 "DCC3_DCCGCTRL" hexmask.long.byte 0x0 12.--15. 1. "DONENA,The DONEENA bit enables/disables the done signal. 0101 = disabled & 1010 = enabled" hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,Single/Continuous checking mode. 0101 = Continuous & 1010 = Single" hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. 0101 = disabled & 1010 = enabled" hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc 0101 = disabled & 1010 = enabled" rgroup.long 0x4++0x3 line.long 0x0 "DCC3_DCCREV" bitfld.long 0x0 28.--30. "SCHEME,SCHEME. - (RO )" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 14.--25. 1. "FUNC,Functional release number - (RO )" hexmask.long.byte 0x0 9.--13. 1. "RTL,Design Release Number - (RO )" bitfld.long 0x0 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "CUSTOM,Indicates a special version of the module. May not be supported by standard software - (RO )" "0,1" hexmask.long.byte 0x0 0.--4. 1. "MINOR,Minor revision number. - (RO )" group.long 0x8++0xF line.long 0x0 "DCC3_DCCCNTSEED0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0)" line.long 0x4 "DCC3_DCCVALIDSEED0" hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x8 "DCC3_DCCCNTSEED1" hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1" line.long 0xC "DCC3_DCCSTAT" bitfld.long 0xC 1. "DONE,Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag." "0,1" bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag." "0,1" rgroup.long 0x18++0xB line.long 0x0 "DCC3_DCCCNT0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. - (RO )" line.long 0x4 "DCC3_DCCVALID0" hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. - (RO )" line.long 0x8 "DCC3_DCCCNT1" hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. - (RO )" group.long 0x24++0x7 line.long 0x0 "DCC3_DCCCLKSSRC1" hexmask.long.byte 0x0 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)" hexmask.long.byte 0x0 0.--3. 1. "CLK_SRC1,Clock source selection for Source 0DCC-A Clock source-0 selection Program value and its respective clock selected 0x0 - REF_CLK0x1 - CPU_CLK0x2 - RC_CLK0x3 - RC_CLK0x4 - RC_CLK0x5 - RC_CLK0x6 - RC_CLK0x7 - RC_CLKDCC-B Clock source-0 selection.." line.long 0x4 "DCC3_DCCCLKSSRC0" hexmask.long.byte 0x4 0.--3. 1. "CLK_SRC0,Clock source selection for Source 0DCC-A Clock source-0 selection Program value and its respective clock selected 0 - REF_CLKA - PLL_6005 - PLL_240DCC-B Clock source-0 selection Program value and its respective clock selected 0 - PLL_600A -.." tree.end tree.end tree "DEBUGSS" base ad:0x50800000 rgroup.long 0x0++0x3 line.long 0x0 "DEBUGSS_ONEMCU_APB_BASE" hexmask.long 0x0 0.--31. 1. "ONEMCU_APB_BASE,OneMCU APB Space : Start Address of ROM Table" rgroup.long 0xFFC++0x3 line.long 0x0 "DEBUGSS_ONEMCU_APB_BASE_END" hexmask.long 0x0 0.--31. 1. "ONEMCU_APB_BASE_END,OneMCU APB Space : Endt Address of ROM Table" group.long 0x1000++0x3 line.long 0x0 "DEBUGSS_ONEMCU_CTI_CONTROL" hexmask.long 0x0 0.--31. 1. "ONEMCU_CTI_CONTROL,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.htmlhttp://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html" wgroup.long 0x1010++0x3 line.long 0x0 "DEBUGSS_ONEMCU_CTI_INTACK" hexmask.long 0x0 0.--31. 1. "ONEMCU_CTI_INTACK,Not Defined" group.long 0x1014++0x3 line.long 0x0 "DEBUGSS_ONEMCU_CTI_APPSET" hexmask.long 0x0 0.--31. 1. "ONEMCU_CTI_APPSET,Not Defined" wgroup.long 0x1018++0x7 line.long 0x0 "DEBUGSS_ONEMCU_CTI_APPCLEAR" hexmask.long 0x0 0.--31. 1. "ONEMCU_CTI_APPCLEAR,Not Defined" line.long 0x4 "DEBUGSS_ONEMCU_CTI_APPPULSE" hexmask.long 0x4 0.--31. 1. "ONEMCU_CTI_APPPULSE,Not Defined" group.long 0x1020++0x1F line.long 0x0 "DEBUGSS_ONEMCU_CTI_INEN0" hexmask.long 0x0 0.--31. 1. "ONEMCU_CTI_INEN0,Not Defined" line.long 0x4 "DEBUGSS_ONEMCU_CTI_INEN1" hexmask.long 0x4 0.--31. 1. "ONEMCU_CTI_INEN1,Not Defined" line.long 0x8 "DEBUGSS_ONEMCU_CTI_INEN2" hexmask.long 0x8 0.--31. 1. "ONEMCU_CTI_INEN2,Not Defined" line.long 0xC "DEBUGSS_ONEMCU_CTI_INEN3" hexmask.long 0xC 0.--31. 1. "ONEMCU_CTI_INEN3,Not Defined" line.long 0x10 "DEBUGSS_ONEMCU_CTI_INEN4" hexmask.long 0x10 0.--31. 1. "ONEMCU_CTI_INEN4,Not Defined" line.long 0x14 "DEBUGSS_ONEMCU_CTI_INEN5" hexmask.long 0x14 0.--31. 1. "ONEMCU_CTI_INEN5,Not Defined" line.long 0x18 "DEBUGSS_ONEMCU_CTI_INEN6" hexmask.long 0x18 0.--31. 1. "ONEMCU_CTI_INEN6,Not Defined" line.long 0x1C "DEBUGSS_ONEMCU_CTI_INEN7" hexmask.long 0x1C 0.--31. 1. "ONEMCU_CTI_INEN7,Not Defined" group.long 0x10A0++0x1F line.long 0x0 "DEBUGSS_ONEMCU_CTI_OUTEN0" hexmask.long 0x0 0.--31. 1. "ONEMCU_CTI_OUTEN0,Not Defined" line.long 0x4 "DEBUGSS_ONEMCU_CTI_OUTEN1" hexmask.long 0x4 0.--31. 1. "ONEMCU_CTI_OUTEN1,Not Defined" line.long 0x8 "DEBUGSS_ONEMCU_CTI_OUTEN2" hexmask.long 0x8 0.--31. 1. "ONEMCU_CTI_OUTEN2,Not Defined" line.long 0xC "DEBUGSS_ONEMCU_CTI_OUTEN3" hexmask.long 0xC 0.--31. 1. "ONEMCU_CTI_OUTEN3,Not Defined" line.long 0x10 "DEBUGSS_ONEMCU_CTI_OUTEN4" hexmask.long 0x10 0.--31. 1. "ONEMCU_CTI_OUTEN4,Not Defined" line.long 0x14 "DEBUGSS_ONEMCU_CTI_OUTEN5" hexmask.long 0x14 0.--31. 1. "ONEMCU_CTI_OUTEN5,Not Defined" line.long 0x18 "DEBUGSS_ONEMCU_CTI_OUTEN6" hexmask.long 0x18 0.--31. 1. "ONEMCU_CTI_OUTEN6,Not Defined" line.long 0x1C "DEBUGSS_ONEMCU_CTI_OUTEN7" hexmask.long 0x1C 0.--31. 1. "ONEMCU_CTI_OUTEN7,Not Defined" rgroup.long 0x1130++0xF line.long 0x0 "DEBUGSS_ONEMCU_CTI_TRIGINSTATUS" hexmask.long 0x0 0.--31. 1. "ONEMCU_CTI_TRIGINSTATUS,Not Defined" line.long 0x4 "DEBUGSS_ONEMCU_CTI_TRIGOUTSTATUS" hexmask.long 0x4 0.--31. 1. "ONEMCU_CTI_TRIGOUTSTATUS,Not Defined" line.long 0x8 "DEBUGSS_ONEMCU_CTI_CHINSTATUS" hexmask.long 0x8 0.--31. 1. "ONEMCU_CTI_CHINSTATUS,Not Defined" line.long 0xC "DEBUGSS_ONEMCU_CTI_CHOUTSTATUS" hexmask.long 0xC 0.--31. 1. "ONEMCU_CTI_CHOUTSTATUS,Not Defined" group.long 0x1140++0x7 line.long 0x0 "DEBUGSS_ONEMCU_CTI_GATE" hexmask.long 0x0 0.--31. 1. "ONEMCU_CTI_GATE,Not Defined" line.long 0x4 "DEBUGSS_ONEMCU_CTI_ASICCTL" hexmask.long 0x4 0.--31. 1. "ONEMCU_CTI_ASICCTL,Not Defined" wgroup.long 0x1EDC++0xF line.long 0x0 "DEBUGSS_ONEMCU_CTI_ITCHINACK" hexmask.long 0x0 0.--31. 1. "ONEMCU_CTI_ITCHINACK,Not Defined" line.long 0x4 "DEBUGSS_ONEMCU_CTI_ITTRIGINACK" hexmask.long 0x4 0.--31. 1. "ONEMCU_CTI_ITTRIGINACK,Not Defined" line.long 0x8 "DEBUGSS_ONEMCU_CTI_ITCHOUT" hexmask.long 0x8 0.--31. 1. "ONEMCU_CTI_ITCHOUT,Not Defined" line.long 0xC "DEBUGSS_ONEMCU_CTI_ITTRIGOUT" hexmask.long 0xC 0.--31. 1. "ONEMCU_CTI_ITTRIGOUT,Not Defined" rgroup.long 0x1EEC++0xF line.long 0x0 "DEBUGSS_ONEMCU_CTI_ITCHOUTACK" hexmask.long 0x0 0.--31. 1. "ONEMCU_CTI_ITCHOUTACK,Not Defined" line.long 0x4 "DEBUGSS_ONEMCU_CTI_ITTRIGOUTACK" hexmask.long 0x4 0.--31. 1. "ONEMCU_CTI_ITTRIGOUTACK,Not Defined" line.long 0x8 "DEBUGSS_ONEMCU_CTI_ITCHIN" hexmask.long 0x8 0.--31. 1. "ONEMCU_CTI_ITCHIN,Not Defined" line.long 0xC "DEBUGSS_ONEMCU_CTI_ITTRIGIN" hexmask.long 0xC 0.--31. 1. "ONEMCU_CTI_ITTRIGIN,Not Defined" group.long 0x1F00++0x3 line.long 0x0 "DEBUGSS_ONEMCU_CTI_ITCTRL" hexmask.long 0x0 0.--31. 1. "ONEMCU_CTI_ITCTRL,Not Defined" group.long 0x1FA0++0x7 line.long 0x0 "DEBUGSS_ONEMCU_CTI_CLAIM_TAG_SET" hexmask.long 0x0 0.--31. 1. "ONEMCU_CTI_CLAIM_TAG_SET,Not Defined" line.long 0x4 "DEBUGSS_ONEMCU_CTI_CLAIM_TAG_CLEAR" hexmask.long 0x4 0.--31. 1. "ONEMCU_CTI_CLAIM_TAG_CLEAR,Not Defined" wgroup.long 0x1FB0++0x3 line.long 0x0 "DEBUGSS_ONEMCU_CTI_LOCK_ACCESS_REGISTER" hexmask.long 0x0 0.--31. 1. "ONEMCU_CTI_LOCK_ACCESS_REGISTER,Not Defined" rgroup.long 0x1FB4++0x7 line.long 0x0 "DEBUGSS_ONEMCU_CTI_LOCK_STATUS_REGISTER" hexmask.long 0x0 0.--31. 1. "ONEMCU_CTI_LOCK_STATUS_REGISTER,Not Defined" line.long 0x4 "DEBUGSS_ONEMCU_CTI_AUTHENTICATION_STATUS" hexmask.long 0x4 0.--31. 1. "ONEMCU_CTI_AUTHENTICATION_STATUS,Not Defined" rgroup.long 0x1FC8++0x3B line.long 0x0 "DEBUGSS_ONEMCU_CTI_DEVICE_ID" hexmask.long 0x0 0.--31. 1. "ONEMCU_CTI_DEVICE_ID,Not Defined" line.long 0x4 "DEBUGSS_ONEMCU_CTI_DEVICE_TYPE_IDENTIFIER" hexmask.long 0x4 0.--31. 1. "ONEMCU_CTI_DEVICE_TYPE_IDENTIFIER,Not Defined" line.long 0x8 "DEBUGSS_ONEMCU_CTI_PERIPHERALID4" hexmask.long 0x8 0.--31. 1. "ONEMCU_CTI_PERIPHERALID4,Not Defined" line.long 0xC "DEBUGSS_ONEMCU_CTI_PERIPHERALID5" hexmask.long 0xC 0.--31. 1. "ONEMCU_CTI_PERIPHERALID5,Not Defined" line.long 0x10 "DEBUGSS_ONEMCU_CTI_PERIPHERALID6" hexmask.long 0x10 0.--31. 1. "ONEMCU_CTI_PERIPHERALID6,Not Defined" line.long 0x14 "DEBUGSS_ONEMCU_CTI_PERIPHERALID7" hexmask.long 0x14 0.--31. 1. "ONEMCU_CTI_PERIPHERALID7,Not Defined" line.long 0x18 "DEBUGSS_ONEMCU_CTI_PERIPHERALID0" hexmask.long 0x18 0.--31. 1. "ONEMCU_CTI_PERIPHERALID0,Not Defined" line.long 0x1C "DEBUGSS_ONEMCU_CTI_PERIPHERALID1" hexmask.long 0x1C 0.--31. 1. "ONEMCU_CTI_PERIPHERALID1,Not Defined" line.long 0x20 "DEBUGSS_ONEMCU_CTI_PERIPHERALID2" hexmask.long 0x20 0.--31. 1. "ONEMCU_CTI_PERIPHERALID2,Not Defined" line.long 0x24 "DEBUGSS_ONEMCU_CTI_PERIPHERALID3" hexmask.long 0x24 0.--31. 1. "ONEMCU_CTI_PERIPHERALID3,Not Defined" line.long 0x28 "DEBUGSS_ONEMCU_CTI_COMPONENT_ID0" hexmask.long 0x28 0.--31. 1. "ONEMCU_CTI_COMPONENT_ID0,Not Defined" line.long 0x2C "DEBUGSS_ONEMCU_CTI_COMPONENT_ID1" hexmask.long 0x2C 0.--31. 1. "ONEMCU_CTI_COMPONENT_ID1,Not Defined" line.long 0x30 "DEBUGSS_ONEMCU_CTI_COMPONENT_ID2" hexmask.long 0x30 0.--31. 1. "ONEMCU_CTI_COMPONENT_ID2,Not Defined" line.long 0x34 "DEBUGSS_ONEMCU_CTI_COMPONENT_ID3" hexmask.long 0x34 0.--31. 1. "ONEMCU_CTI_COMPONENT_ID3,Not Defined" line.long 0x38 "DEBUGSS_ONEMCU_TPIU_SPORTSZ" hexmask.long 0x38 0.--31. 1. "ONEMCU_TPIU_SPORTSZ,Supported port sizes" group.long 0x2004++0x3 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_CPORTSZ" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_CPORTSZ,Current port size" rgroup.long 0x2100++0x3 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_STRIGM" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_STRIGM,Supported trigger modes" group.long 0x2104++0x7 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_TRIGCNT" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_TRIGCNT,Trigger counter value" line.long 0x4 "DEBUGSS_ONEMCU_TPIU_TRIGMUL" hexmask.long 0x4 0.--31. 1. "ONEMCU_TPIU_TRIGMUL,Trigger multiplier" rgroup.long 0x2200++0x3 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_STSTPTRN" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_STSTPTRN,Supported test pattern/modes" group.long 0x2204++0x7 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_CTSTPTRN" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_CTSTPTRN,Current test pattern/mode" line.long 0x4 "DEBUGSS_ONEMCU_TPIU_TPRCNTR" hexmask.long 0x4 0.--31. 1. "ONEMCU_TPIU_TPRCNTR,Test pattern repeat counter" rgroup.long 0x2300++0x3 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_FFSTS" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_FFSTS,Formatter and flush status" group.long 0x2304++0x7 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_FFCTRL" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_FFCTRL,Formatter and flush control" line.long 0x4 "DEBUGSS_ONEMCU_TPIU_FSCNTR" hexmask.long 0x4 0.--31. 1. "ONEMCU_TPIU_FSCNTR,Formatter synchronization counter" rgroup.long 0x2400++0x3 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_EXCTLIN" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_EXCTLIN,EXTCTL In Port" group.long 0x2404++0x3 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_EXCTLOUT" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_EXCTLOUT,EXTCTL Out Port" wgroup.long 0x2EE4++0x3 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_ITTRFLINACK" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_ITTRFLINACK,Integration Register ITTRFLINACK" rgroup.long 0x2EE8++0x7 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_ITTRFLIN" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_ITTRFLIN,Integration Register ITTRFLIN" line.long 0x4 "DEBUGSS_ONEMCU_TPIU_ITATBDATA0" hexmask.long 0x4 0.--31. 1. "ONEMCU_TPIU_ITATBDATA0,Integration Register ITATBDATA0" wgroup.long 0x2EF0++0x3 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_ITATBCTR2" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_ITATBCTR2,Integration Register ITATBCTR2" rgroup.long 0x2EF4++0x7 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_ITATBCTR1" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_ITATBCTR1,Integration Register ITATBCTR1" line.long 0x4 "DEBUGSS_ONEMCU_TPIU_ITATBCTR0" hexmask.long 0x4 0.--31. 1. "ONEMCU_TPIU_ITATBCTR0,Integration Register ITATBCTR0" group.long 0x2F00++0x3 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_ITCTRL" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_ITCTRL,Integration Mode Control Register" group.long 0x2FA0++0x7 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_CLAIMSET" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_CLAIMSET,Claim Tag Set" line.long 0x4 "DEBUGSS_ONEMCU_TPIU_CLAIMCLR" hexmask.long 0x4 0.--31. 1. "ONEMCU_TPIU_CLAIMCLR,Claim Tag Clear" rgroup.long 0x2FB0++0x3 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_LAR" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_LAR,Lock status" wgroup.long 0x2FB4++0x3 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_LSR" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_LSR,Lock Access" rgroup.long 0x2FB8++0x3 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_AUTHSTATUS" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_AUTHSTATUS,Authentication status" rgroup.long 0x2FC8++0x37 line.long 0x0 "DEBUGSS_ONEMCU_TPIU_DEVID" hexmask.long 0x0 0.--31. 1. "ONEMCU_TPIU_DEVID,Device ID" line.long 0x4 "DEBUGSS_ONEMCU_TPIU_DEVTYPE" hexmask.long 0x4 0.--31. 1. "ONEMCU_TPIU_DEVTYPE,Device type identifier" line.long 0x8 "DEBUGSS_ONEMCU_TPIU_PIDR4" hexmask.long 0x8 0.--31. 1. "ONEMCU_TPIU_PIDR4,Peripheral ID4" line.long 0xC "DEBUGSS_ONEMCU_TPIU_PIDR5" hexmask.long 0xC 0.--31. 1. "ONEMCU_TPIU_PIDR5,Peripheral ID5" line.long 0x10 "DEBUGSS_ONEMCU_TPIU_PIDR6" hexmask.long 0x10 0.--31. 1. "ONEMCU_TPIU_PIDR6,Peripheral ID6" line.long 0x14 "DEBUGSS_ONEMCU_TPIU_PIDR7" hexmask.long 0x14 0.--31. 1. "ONEMCU_TPIU_PIDR7,Peripheral ID7" line.long 0x18 "DEBUGSS_ONEMCU_TPIU_PIDR0" hexmask.long 0x18 0.--31. 1. "ONEMCU_TPIU_PIDR0,Peripheral ID0" line.long 0x1C "DEBUGSS_ONEMCU_TPIU_PIDR1" hexmask.long 0x1C 0.--31. 1. "ONEMCU_TPIU_PIDR1,Peripheral ID1" line.long 0x20 "DEBUGSS_ONEMCU_TPIU_PIDR2" hexmask.long 0x20 0.--31. 1. "ONEMCU_TPIU_PIDR2,Peripheral ID2" line.long 0x24 "DEBUGSS_ONEMCU_TPIU_PIDR3" hexmask.long 0x24 0.--31. 1. "ONEMCU_TPIU_PIDR3,Peripheral ID3" line.long 0x28 "DEBUGSS_ONEMCU_TPIU_CIDR0" hexmask.long 0x28 0.--31. 1. "ONEMCU_TPIU_CIDR0,Component ID0" line.long 0x2C "DEBUGSS_ONEMCU_TPIU_CIDR1" hexmask.long 0x2C 0.--31. 1. "ONEMCU_TPIU_CIDR1,Component ID1" line.long 0x30 "DEBUGSS_ONEMCU_TPIU_CIDR2" hexmask.long 0x30 0.--31. 1. "ONEMCU_TPIU_CIDR2,Component ID2" line.long 0x34 "DEBUGSS_ONEMCU_TPIU_CIDR3" hexmask.long 0x34 0.--31. 1. "ONEMCU_TPIU_CIDR3,Component ID3" group.long 0x10000++0x3 line.long 0x0 "DEBUGSS_APB_EXT_PORT0_ROM" hexmask.long 0x0 0.--31. 1. "ATB_REPLICATOR_IDFILTER0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDFGIED.htmlhttp://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDBDCII.html" group.long 0x11000++0x3 line.long 0x0 "DEBUGSS_ATB_REPLICATOR_IDFILTER0" hexmask.long 0x0 0.--31. 1. "ATB_REPLICATOR_IDFILTER1,Not Defined" rgroup.long 0x11004++0x3 line.long 0x0 "DEBUGSS_ATB_REPLICATOR_IDFILTER1" hexmask.long 0x0 0.--31. 1. "ATB_REPLICATOR_ITATBCTR1,Not Defined" wgroup.long 0x11EF8++0x3 line.long 0x0 "DEBUGSS_ATB_REPLICATOR_ITATBCTR1" hexmask.long 0x0 0.--31. 1. "ATB_REPLICATOR_ITATBCTR0,Not Defined" group.long 0x11EFC++0x7 line.long 0x0 "DEBUGSS_ATB_REPLICATOR_ITATBCTR0" hexmask.long 0x0 0.--31. 1. "ATB_REPLICATOR_ITCTRL,Not Defined" line.long 0x4 "DEBUGSS_ATB_REPLICATOR_ITCTRL" hexmask.long 0x4 0.--31. 1. "ATB_REPLICATOR_CLAIMSET,Not Defined" group.long 0x11FA0++0x3 line.long 0x0 "DEBUGSS_ATB_REPLICATOR_CLAIMSET" hexmask.long 0x0 0.--31. 1. "ATB_REPLICATOR_CLAIMCLR,Not Defined" wgroup.long 0x11FA4++0x3 line.long 0x0 "DEBUGSS_ATB_REPLICATOR_CLAIMCLR" hexmask.long 0x0 0.--31. 1. "ATB_REPLICATOR_LAR,Not Defined" rgroup.long 0x11FB0++0xB line.long 0x0 "DEBUGSS_ATB_REPLICATOR_LAR" hexmask.long 0x0 0.--31. 1. "ATB_REPLICATOR_LSR,Not Defined" line.long 0x4 "DEBUGSS_ATB_REPLICATOR_LSR" hexmask.long 0x4 0.--31. 1. "ATB_REPLICATOR_AUTHSTATUS,Not Defined" line.long 0x8 "DEBUGSS_ATB_REPLICATOR_AUTHSTATUS" hexmask.long 0x8 0.--31. 1. "ATB_REPLICATOR_DEVID,Not Defined" rgroup.long 0x11FC8++0x37 line.long 0x0 "DEBUGSS_ATB_REPLICATOR_DEVID" hexmask.long 0x0 0.--31. 1. "ATB_REPLICATOR_DEVTYPE,Not Defined" line.long 0x4 "DEBUGSS_ATB_REPLICATOR_DEVTYPE" hexmask.long 0x4 0.--31. 1. "ATB_REPLICATOR_PIDR4,Not Defined" line.long 0x8 "DEBUGSS_ATB_REPLICATOR_PIDR4" hexmask.long 0x8 0.--31. 1. "ATB_REPLICATOR_RESERVED1,Not Defined" line.long 0xC "DEBUGSS_ATB_REPLICATOR_RESERVED1" hexmask.long 0xC 0.--31. 1. "ATB_REPLICATOR_RESERVED2,Not Defined" line.long 0x10 "DEBUGSS_ATB_REPLICATOR_RESERVED2" hexmask.long 0x10 0.--31. 1. "ATB_REPLICATOR_RESERVED3,Not Defined" line.long 0x14 "DEBUGSS_ATB_REPLICATOR_RESERVED3" hexmask.long 0x14 0.--31. 1. "ATB_REPLICATOR_PIDR0,Not Defined" line.long 0x18 "DEBUGSS_ATB_REPLICATOR_PIDR0" hexmask.long 0x18 0.--31. 1. "ATB_REPLICATOR_PIDR1,Not Defined" line.long 0x1C "DEBUGSS_ATB_REPLICATOR_PIDR1" hexmask.long 0x1C 0.--31. 1. "ATB_REPLICATOR_PIDR2,Not Defined" line.long 0x20 "DEBUGSS_ATB_REPLICATOR_PIDR2" hexmask.long 0x20 0.--31. 1. "ATB_REPLICATOR_PIDR3,Not Defined" line.long 0x24 "DEBUGSS_ATB_REPLICATOR_PIDR3" hexmask.long 0x24 0.--31. 1. "ATB_REPLICATOR_CIDR0,Not Defined" line.long 0x28 "DEBUGSS_ATB_REPLICATOR_CIDR0" hexmask.long 0x28 0.--31. 1. "ATB_REPLICATOR_CIDR1,Not Defined" line.long 0x2C "DEBUGSS_ATB_REPLICATOR_CIDR1" hexmask.long 0x2C 0.--31. 1. "ATB_REPLICATOR_CIDR2,Not Defined" line.long 0x30 "DEBUGSS_ATB_REPLICATOR_CIDR2" hexmask.long 0x30 0.--31. 1. "ATB_REPLICATOR_CIDR3,Not Defined" line.long 0x34 "DEBUGSS_ATB_REPLICATOR_CIDR3" hexmask.long 0x34 0.--31. 1. "ETB_RDP,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDIEIAJ.htmlhttp://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDDBEHG.html" rgroup.long 0x12004++0x3 line.long 0x0 "DEBUGSS_ETB_RDP" hexmask.long 0x0 0.--31. 1. "ETB_STS,Not Defined" rgroup.long 0x1200C++0x3 line.long 0x0 "DEBUGSS_ETB_STS" hexmask.long 0x0 0.--31. 1. "ETB_RRD,Not Defined" group.long 0x12010++0xF line.long 0x0 "DEBUGSS_ETB_RRD" hexmask.long 0x0 0.--31. 1. "ETB_RRP,Not Defined" line.long 0x4 "DEBUGSS_ETB_RRP" hexmask.long 0x4 0.--31. 1. "ETB_RWP,Not Defined" line.long 0x8 "DEBUGSS_ETB_RWP" hexmask.long 0x8 0.--31. 1. "ETB_TRG,Not Defined" line.long 0xC "DEBUGSS_ETB_TRG" hexmask.long 0xC 0.--31. 1. "ETB_CTL,Not Defined" wgroup.long 0x12020++0x3 line.long 0x0 "DEBUGSS_ETB_CTL" hexmask.long 0x0 0.--31. 1. "ETB_RWD,Not Defined" rgroup.long 0x12024++0x3 line.long 0x0 "DEBUGSS_ETB_RWD" hexmask.long 0x0 0.--31. 1. "ETB_FFSR,Not Defined" group.long 0x12300++0x3 line.long 0x0 "DEBUGSS_ETB_FFSR" hexmask.long 0x0 0.--31. 1. "ETB_FFCR,Not Defined" wgroup.long 0x12304++0x3 line.long 0x0 "DEBUGSS_ETB_FFCR" hexmask.long 0x0 0.--31. 1. "ETB_ITMISCOP0,Not Defined" wgroup.long 0x12EE0++0x3 line.long 0x0 "DEBUGSS_ETB_ITMISCOP0" hexmask.long 0x0 0.--31. 1. "ETB_ITTRFLINACK,Not Defined" rgroup.long 0x12EE4++0x7 line.long 0x0 "DEBUGSS_ETB_ITTRFLINACK" hexmask.long 0x0 0.--31. 1. "ETB_ITTRFLIN,Not Defined" line.long 0x4 "DEBUGSS_ETB_ITTRFLIN" hexmask.long 0x4 0.--31. 1. "ETB_ITATBDATA0,Not Defined" wgroup.long 0x12EEC++0x3 line.long 0x0 "DEBUGSS_ETB_ITATBDATA0" hexmask.long 0x0 0.--31. 1. "ETB_ITATBCTR2,Not Defined" rgroup.long 0x12EF0++0x7 line.long 0x0 "DEBUGSS_ETB_ITATBCTR2" hexmask.long 0x0 0.--31. 1. "ETB_ITATBCTR1,Not Defined" line.long 0x4 "DEBUGSS_ETB_ITATBCTR1" hexmask.long 0x4 0.--31. 1. "ETB_ITATBCTR0,Not Defined" group.long 0x12EF8++0x3 line.long 0x0 "DEBUGSS_ETB_ITATBCTR0" hexmask.long 0x0 0.--31. 1. "ETB_ITCTRL,Not Defined" group.long 0x12F00++0x3 line.long 0x0 "DEBUGSS_ETB_ITCTRL" hexmask.long 0x0 0.--31. 1. "ETB_CLAIMSET,Not Defined" group.long 0x12FA0++0x3 line.long 0x0 "DEBUGSS_ETB_CLAIMSET" hexmask.long 0x0 0.--31. 1. "ETB_CLAIMCLR,Not Defined" wgroup.long 0x12FA4++0x3 line.long 0x0 "DEBUGSS_ETB_CLAIMCLR" hexmask.long 0x0 0.--31. 1. "ETB_LAR,Not Defined" rgroup.long 0x12FB0++0xB line.long 0x0 "DEBUGSS_ETB_LAR" hexmask.long 0x0 0.--31. 1. "ETB_LSR,Not Defined" line.long 0x4 "DEBUGSS_ETB_LSR" hexmask.long 0x4 0.--31. 1. "ETB_AUTHSTATUS,Not Defined" line.long 0x8 "DEBUGSS_ETB_AUTHSTATUS" hexmask.long 0x8 0.--31. 1. "ETB_DEVID,Not Defined" rgroup.long 0x12FC8++0x33 line.long 0x0 "DEBUGSS_ETB_DEVID" hexmask.long 0x0 0.--31. 1. "ETB_DEVTYPE,Not Defined" line.long 0x4 "DEBUGSS_ETB_DEVTYPE" hexmask.long 0x4 0.--31. 1. "ETB_PIDR4,Not Defined" line.long 0x8 "DEBUGSS_ETB_PIDR4" hexmask.long 0x8 0.--31. 1. "ETB_RESERVED4,Not Defined" line.long 0xC "DEBUGSS_ETB_RESERVED4" hexmask.long 0xC 0.--31. 1. "ETB_RESERVED5,Not Defined" line.long 0x10 "DEBUGSS_ETB_RESERVED5" hexmask.long 0x10 0.--31. 1. "ETB_RESERVED6,Not Defined" line.long 0x14 "DEBUGSS_ETB_RESERVED6" hexmask.long 0x14 0.--31. 1. "ETB_PIDR0,Not Defined" line.long 0x18 "DEBUGSS_ETB_PIDR0" hexmask.long 0x18 0.--31. 1. "ETB_PIDR1,Not Defined" line.long 0x1C "DEBUGSS_ETB_PIDR1" hexmask.long 0x1C 0.--31. 1. "ETB_PIDR2,Not Defined" line.long 0x20 "DEBUGSS_ETB_PIDR2" hexmask.long 0x20 0.--31. 1. "ETB_PIDR3,Not Defined" line.long 0x24 "DEBUGSS_ETB_PIDR3" hexmask.long 0x24 0.--31. 1. "ETB_CIDR0,Not Defined" line.long 0x28 "DEBUGSS_ETB_CIDR0" hexmask.long 0x28 0.--31. 1. "ETB_CIDR1,Not Defined" line.long 0x2C "DEBUGSS_ETB_CIDR1" hexmask.long 0x2C 0.--31. 1. "ETB_CIDR2,Not Defined" line.long 0x30 "DEBUGSS_ETB_CIDR2" hexmask.long 0x30 0.--31. 1. "ETB_CIDR3,Not Defined" wgroup.long 0x12FFC++0x3 line.long 0x0 "DEBUGSS_ETB_CIDR3" hexmask.long 0x0 0.--31. 1. "STMDMASTARTR,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" wgroup.long 0x13C04++0x3 line.long 0x0 "DEBUGSS_STMDMASTARTR" hexmask.long 0x0 0.--31. 1. "STMDMASTOPR,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" rgroup.long 0x13C08++0x3 line.long 0x0 "DEBUGSS_STMDMASTOPR" hexmask.long 0x0 0.--31. 1. "STMDMASTATR,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" group.byte 0x13C0C++0x0 line.byte 0x0 "DEBUGSS_STMDMASTATR" bitfld.byte 0x0 2.--3. "SENS,Determines the sensitivity of the DMA request to the current buffer level in the STM:0b00 Buffer is <25% full.0b01 Buffer is <50% full.0b10 Buffer is <75% full.0b11 Buffer is <100% full." "0,1,2,3" rgroup.long 0x13C10++0x3 line.long 0x0 "DEBUGSS_STMDMACTLR" hexmask.long 0x0 0.--31. 1. "STMDMAIDR,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" group.long 0x13CFC++0x7 line.long 0x0 "DEBUGSS_STMDMAIDR" hexmask.long 0x0 0.--31. 1. "STMHEER,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" line.long 0x4 "DEBUGSS_STMHEER" hexmask.long 0x4 0.--31. 1. "STMHETER,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" group.long 0x13D20++0x3 line.long 0x0 "DEBUGSS_STMHETER" hexmask.long 0x0 0.--31. 1. "STMHEBSR,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" group.long 0x13D60++0x3 line.long 0x0 "DEBUGSS_STMHEBSR" hexmask.long 0x0 0.--31. 1. "STMHEMCR,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" group.byte 0x13D64++0x0 line.byte 0x0 "DEBUGSS_STMHEMCR" hexmask.byte 0x0 0.--7. 1. "EXTMUX,Specifies the value that the optional external multiplexing logic uses to select the hardware events to connectto the STM.The value of this register is output from the STM on the HEEXTMUX[7:0] signals. The behavior of themultiplexing logic is.." rgroup.word 0x13D68++0x1 line.word 0x0 "DEBUGSS_STMHEEXTMUXR" hexmask.word 0x0 0.--15. 1. "MASTER,The STPv2 master number for the hardware event trace:0x80 Hardware events are associated with master ID 0x80." rgroup.long 0x13DF4++0x3 line.long 0x0 "DEBUGSS_STMHEMASTR" bitfld.long 0x0 28.--30. "HEEXTMUXSIZE,The size of the STMHEEXTMUXR.EXTMUX bit field:0b011 8 bits wide." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 15.--23. 1. "NUMHE,The number of hardware events supported by the STM:0b001000000 64 hardware events." newline bitfld.long 0x0 4.--5. "HECOMP,Data compression on hardware event tracing support:0b11 Programmable data compression support. The STM implements theSTMHEMCR.COMPEN bit." "0,1,2,3" bitfld.long 0x0 3. "HEMASTR,Specifies the STMHEMASTR support:0b0 The STMHEMASTR is read-only." "0,1" newline bitfld.long 0x0 2. "HEERR,Hardware event error detection support:0b1 Implemented. The STM implements the STMHEMCR.ERRDETECT bit." "0,1" bitfld.long 0x0 0. "HETER,Specifies the STMHETER support:0b1 Implemented." "0,1" rgroup.word 0x13DF8++0x1 line.word 0x0 "DEBUGSS_STMHEFEAT1R" hexmask.word.byte 0x0 8.--11. 1. "VENDSPEC,Identifies vendor-specific modifications or mappings:0b0000 Vendor-specific information." hexmask.word.byte 0x0 4.--7. 1. "CLASSREV,Identifies the revision of the programmers model:0b0001 Revision." newline hexmask.word.byte 0x0 0.--3. 1. "CLASS,Identifies the programmers model:0b0001 Hardware event control." group.long 0x13DFC++0x7 line.long 0x0 "DEBUGSS_STMHEIDR" hexmask.long 0x0 0.--31. 1. "STMSPER,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" line.long 0x4 "DEBUGSS_STMSPER" hexmask.long 0x4 0.--31. 1. "STMSPTER,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" group.long 0x13E20++0x3 line.long 0x0 "DEBUGSS_STMSPTER" hexmask.long 0x0 0.--31. 1. "STMSPSCR,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" group.long 0x13E60++0xF line.long 0x0 "DEBUGSS_STMSPSCR" hexmask.long 0x0 0.--31. 1. "STMSPMSCR,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" line.long 0x4 "DEBUGSS_STMSPMSCR" hexmask.long 0x4 0.--31. 1. "STMSPOVERRIDER,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" line.long 0x8 "DEBUGSS_STMSPOVERRIDER" hexmask.long 0x8 0.--31. 1. "STMSPMOVERRIDER,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" line.long 0xC "DEBUGSS_STMSPMOVERRIDER" hexmask.long 0xC 0.--31. 1. "STMSPTRIGCSR,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" group.tbyte 0x13E70++0x2 line.tbyte 0x0 "DEBUGSS_STMSPTRIGCSR" bitfld.tbyte 0x0 23. "BUSY,Indicates whether the STM is busy for example the STM trace FIFO is not empty:0b0 Not busy.0b1 Busy." "0,1" hexmask.tbyte.byte 0x0 16.--22. 1. "TRACEID,ATB trace ID. Setting this value to all zeroes or to a value greater than 0x6F might result in UNPREDICTABLEtracing. Reset value of this bit field is UNKNOWN." newline bitfld.tbyte 0x0 5. "COMPEN,Compression enable for stimulus ports:0b0 Disabled the STM transmits data transfers based on the size of the transaction.0b1 Enabled the STM compresses data transfers to save bandwidth." "0,1" bitfld.tbyte 0x0 2. "SYNCEN,The STM implements the STMSYNCR so this bit is Read As One.0b1 The STM implements the STMSYNCR." "0,1" newline bitfld.tbyte 0x0 1. "TSEN,Determines whether to ignore timestamp requests:0b0 Disable timestamping. The STM ignores requests for timestamp generation and treatsstimulus port writes that select timestamping as if timestamping were not selected.0b1 Enable timestamping. If.." "0,1" bitfld.tbyte 0x0 0. "EN,Global STM enable:0b0 Disabled0b1 Enabled." "0,1" wgroup.long 0x13E80++0x3 line.long 0x0 "DEBUGSS_STMTCSR" hexmask.long 0x0 0.--31. 1. "STMTSSTIMR,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" group.long 0x13E84++0x3 line.long 0x0 "DEBUGSS_STMTSSTIMR" hexmask.long 0x0 0.--31. 1. "STMTSFREQR,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" group.long 0x13E8C++0x3 line.long 0x0 "DEBUGSS_STMTSFREQR" hexmask.long 0x0 0.--31. 1. "STMSYNCR,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" group.byte 0x13E90++0x0 line.byte 0x0 "DEBUGSS_STMSYNCR" bitfld.byte 0x0 7. "QHWEVOVERRIDE,Low-power interface override when hardware event tracing is enabled:0b0 The STM can accept a quiescence request on the STM low-power interface whenthe STMHEMCR.EN bit is set to 0b1.0b1 If the STMHEMCR.EN bit is set to 0b1 all quiescence.." "0,1" bitfld.byte 0x0 2. "PRIORINVDIS,Controls arbitration between the AXI interface and the hardware event observation interface duringflush:0b0 Priority inversion. When the AXI flush completes the hardware event observationinterface gets priority until the hardware event.." "0,1" newline bitfld.byte 0x0 1. "ASYNCPE,ASYNC priority:0b0 Always lower than trace.0b1 Escalates on second synchronization request.Reset value is 0b0." "0,1" bitfld.byte 0x0 0. "FIFOAF,Auto-flush:0b0 Disabled.0b1 Enabled. The STM automatically drains all data even if the ATB interface is notfully utilized.Reset value is 0b0." "0,1" rgroup.tbyte 0x13E94++0x2 line.tbyte 0x0 "DEBUGSS_STMAUXCR" bitfld.tbyte 0x0 22.--23. "SWOEN,Specifies the STMTCSR.SWOEN bit support:0b01 Not implemented." "0,1,2,3" bitfld.tbyte 0x0 20.--21. "SYNCEN,Specifies the STMTCSR.SYNCEN bit support:0b10 Implemented but always reads as 0b1." "0,1,2,3" newline bitfld.tbyte 0x0 18.--19. "HWTEN,Specifies the STMTCSR.HWTEN bit support:0b01 Not implemented." "0,1,2,3" bitfld.tbyte 0x0 16.--17. "TSPRESCALE,Timestamp prescale support:0b01 Not implemented." "0,1,2,3" newline bitfld.tbyte 0x0 14.--15. "TRIGCTL,Trigger control support:0b10 Multi-shot and single-shot triggers supported the STM implements the STMTRIGCSR." "0,1,2,3" hexmask.tbyte.byte 0x0 10.--13. 1. "TRACEBUS,Trace bus support:0b0001 CoreSight ATB plus ATB trigger support implemented the STM implements theSTMTCSR.TRACEID and STMTRIGCSR.ATBTRIGEN bit fields." newline bitfld.tbyte 0x0 8.--9. "SYNC,Specifies the STMSYNCR support:0b11 Implemented with MODE control." "0,1,2,3" bitfld.tbyte 0x0 7. "FORCETS,Specifies the STMTSSTIMR support:0b1 The STM implements the STMTSSTIMR.FORCETS bit." "0,1" newline bitfld.tbyte 0x0 6. "TSFREQ,Timestamp frequency indication configuration:0b1 The STMTSFREQR is read-write." "0,1" bitfld.tbyte 0x0 4.--5. "TS,Timestamp support:0b01 Absolute timestamps implemented." "0,1,2,3" newline hexmask.tbyte.byte 0x0 0.--3. 1. "PROT,Protocol:0b0001 STPv2 protocol." rgroup.tbyte 0x13EA0++0x2 line.tbyte 0x0 "DEBUGSS_STMFEAT1R" bitfld.tbyte 0x0 16.--17. "SPTYPE,Stimulus port type support:0b01 Only extended stimulus ports." "0,1,2,3" hexmask.tbyte.byte 0x0 12.--15. 1. "DSIZE,Fundamental data size:0b0001 64-bit data." newline bitfld.tbyte 0x0 9.--10. "SPTRTYPE,Stimulus port transaction type support:0b10 Both invariant timing and guaranteed transactions." "0,1,2,3" bitfld.tbyte 0x0 7.--8. "PRIVMASK,Specifies the STMPRIVMASKR support:0b01 Not implemented." "0,1,2,3" newline bitfld.tbyte 0x0 6. "SPOVERRIDE,Specifies the STMSPOVERRIDER support:0b1 STMSPOVERRIDER and STMSPMOVERRIDER implemented." "0,1" bitfld.tbyte 0x0 4.--5. "SPCOMP,Data compression on stimulus ports support:0b11 Data compression support is programmable the STM implements theSTMTCSR.COMPEN bit." "0,1,2,3" newline bitfld.tbyte 0x0 2. "SPER,Specifies the STMSPER presence:0b0 Implemented." "0,1" bitfld.tbyte 0x0 0.--1. "SPTER,Specifies the STMSPTER support:0b10 Implemented." "0,1,2,3" rgroup.byte 0x13EA4++0x0 line.byte 0x0 "DEBUGSS_STMFEAT2R" hexmask.byte 0x0 0.--6. 1. "NUMMAST,The number of stimulus port masters implemented minus 1:0b1111111 128 ports." wgroup.byte 0x13EA8++0x0 line.byte 0x0 "DEBUGSS_STMFEAT3R" bitfld.byte 0x0 3. "ASYNCOUT_W,Sets the value of the ASYNCOUT output signal in integration mode:0b1 Drive logic 0b1.0b0 Drive logic 0b0." "0,1" bitfld.byte 0x0 2. "TRIGOUTHETE_W,Sets the value of the TRIGOUTHETE output signal in integration mode:0b1 Drive logic 0b1.0b0 Drive logic 0b0." "0,1" newline bitfld.byte 0x0 1. "TRIGOUTSW_W,Sets the value of the TRIGOUTSW output signal in integration mode:0b1 Drive logic 0b1.0b0 Drive logic 0b0." "0,1" bitfld.byte 0x0 0. "TRIGOUTSPTE_W,Sets the value of the TRIGOUTSPTE output signal in integration mode:0b1 Drive logic 0b1.0b0 Drive logic 0b0." "0,1" wgroup.word 0x13EE8++0x1 line.word 0x0 "DEBUGSS_STMITTRIGGER" bitfld.word 0x0 8. "ATDATAM63_W,Sets the value of the ATDATAM[63] output signal:0b1 Drive logic 0b1.0b0 Drive logic 0b0." "0,1" bitfld.word 0x0 7. "ATDATAM55_W,Sets the value of the ATDATAM[55] output signal:0b1 Drive logic 0b1.0b0 Drive logic 0b0." "0,1" newline bitfld.word 0x0 6. "ATDATAM47_W,Sets the value of the ATDATAM[47] output signal:0b1 Drive logic 0b1.0b0 Drive logic 0b0." "0,1" bitfld.word 0x0 5. "ATDATAM39_W,Sets the value of the ATDATAM[39] output signal:0b1 Drive logic 0b1.0b0 Drive logic 0b0." "0,1" newline bitfld.word 0x0 4. "ATDATAM31_W,Sets the value of the ATDATAM[31] output signal:0b1 Drive logic 0b1.0b0 Drive logic 0b0." "0,1" bitfld.word 0x0 3. "ATDATAM23_W,Sets the value of the ATDATAM[23] output signal:0b1 Drive logic 0b1.0b0 Drive logic 0b0." "0,1" newline bitfld.word 0x0 2. "ATDATAM15_W,Sets the value of the ATDATAM[15] output signal:0b1 Drive logic 0b1.0b0 Drive logic 0b0." "0,1" bitfld.word 0x0 1. "ATDATAM7_W,Sets the value of the ATDATAM[7] output signal:0b1 Drive logic 0b1.0b0 Drive logic 0b0." "0,1" newline bitfld.word 0x0 0. "ATDATAM0_W,Sets the value of the ATDATAM[0] output signal:0b1 Drive logic 0b1.0b0 Drive logic 0b0." "0,1" rgroup.byte 0x13EEC++0x0 line.byte 0x0 "DEBUGSS_STMITATBDATA0" bitfld.byte 0x0 1. "AFVALIDM_R,Reads the value of the AFVALIDM input signal:0b1 The signal is at logic 0b1.0b0 The signal is at logic 0b0." "0,1" bitfld.byte 0x0 0. "ATREADYM_R,Reads the value of the ATREADYM input signal:0b1 The signal is at logic 0b1.0b0 The signal is at logic 0b0." "0,1" wgroup.byte 0x13EF0++0x0 line.byte 0x0 "DEBUGSS_STMITATBCTR2" hexmask.byte 0x0 0.--6. 1. "ATIDM_W,Sets the value of the ATIDM output signal." wgroup.word 0x13EF4++0x1 line.word 0x0 "DEBUGSS_STMITATBID" bitfld.word 0x0 8.--10. "ATBYTESM_W,Sets the value of the ATBYTESM output signal:0b111 Drive logic 0b111.0b110 Drive logic 0b110.0b101 Drive logic 0b101.0b100 Drive logic 0b100.0b011 Drive logic 0b011.0b010 Drive logic 0b010.0b001 Drive logic 0b001.0b000 Drive logic 0b000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 1. "AFREADYM_W,Sets the value of the AFREADYM output signal:0b1 Drive logic 0b1.0b0 Drive logic 0b0." "0,1" newline bitfld.word 0x0 0. "ATVALIDM_W,Sets the value of the ATVALIDM output signal:0b1 Drive logic 0b1.0b0 Drive logic 0b0." "0,1" group.byte 0x13EF8++0x0 line.byte 0x0 "DEBUGSS_STMITATBCTR0" bitfld.byte 0x0 0. "IME,Enables the component to switch between functional and integration mode.0b1 Enable integration mode.0b0 Disable integration mode." "0,1" group.long 0x13F00++0x3 line.long 0x0 "DEBUGSS_STMITCTRL" hexmask.long 0x0 0.--31. 1. "STMCLAIMSET,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" group.long 0x13FA0++0x3 line.long 0x0 "DEBUGSS_STMCLAIMSET" hexmask.long 0x0 0.--31. 1. "STMCLAIMCLR,ARM? System Trace Macrocell Programmers? ModelArchitecture Specification" wgroup.long 0x13FA4++0x3 line.long 0x0 "DEBUGSS_STMCLAIMCLR" hexmask.long 0x0 0.--31. 1. "KEY,Ignores writes when the PADDRDBG31 signal is HIGH.When the PADDRDBG31 signal is LOW a write of 0xC5ACCE55 unlocks the lock control mechanism enablingfurther writes with the PADDRDBG31 signal LOW.Other values lock the lock control mechanism .." wgroup.byte 0x13FB0++0x0 line.byte 0x0 "DEBUGSS_STMLAR" bitfld.byte 0x0 2. "NTT,Indicates whether the component implements the STMLAR as 8 bit or 32 bit.0b0 32 bit." "0,1" bitfld.byte 0x0 1. "SLK,Returns the current status of the lock.0b0 Enables write access to the STM. For read accesses to the STMLSR when the PADDRDBG31signal is HIGH this bit is always 0b0.0b1 Blocks write access to the STM. The STM ignores all write accesses to the.." "0,1" newline bitfld.byte 0x0 0. "SLI,Indicates that a lock control mechanism exists for the device.0b0 No lock control mechanism exists. The STM ignores writes to the STMLAR. For read accessesto the STMLSR when the PADDRDBG31 signal is HIGH this bit is always 0b0.0b1 Lock control.." "0,1" rgroup.byte 0x13FB4++0x0 line.byte 0x0 "DEBUGSS_STMLSR" bitfld.byte 0x0 6.--7. "SNID,Indicates the security level for Secure non-invasive debug:0b10 Disabled.0b11 Enabled." "0,1,2,3" bitfld.byte 0x0 4.--5. "SID,Indicates the security level for Secure invasive debug:0b10 Disabled.0b11 Enabled." "0,1,2,3" newline bitfld.byte 0x0 2.--3. "NSNID,Indicates the security level for Non-secure non-invasive debug:0b10 Disabled.0b11 Enabled." "0,1,2,3" bitfld.byte 0x0 0.--1. "NSID,Indicates the security level for Non-secure invasive debug:0b10 Disabled.0b11 Enabled." "0,1,2,3" rgroup.long 0x13FB8++0x7 line.long 0x0 "DEBUGSS_STMAUTHSTATUS" hexmask.long.word 0x0 21.--31. 1. "ARCHITECT,Defines the architect of the component:Bits[31:28] Indicates the JEP106 continuation code.Bits[27:21] Indicates the JEP106 identification code.See the Standard Manufacturer?s Identification Code for information about JEP106. For the STM-500 ARM.." bitfld.long 0x0 20. "PRESENT,Indicates the presence of the STMDEVARCH register:0b1 The STMDEVARCH register is present." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "REVISION,Architecture revision. Returns the revision of the architecture that the ARCHID field specifies. For theSTM this value is 0x1 indicating the STMv1.1 architecture." hexmask.long.word 0x0 0.--15. 1. "ARCHID,Architecture ID. Returns a value that identifies the architecture of the component. For the STM this valueis 0x0A63 indicating the STMv1.1 architecture." line.long 0x4 "DEBUGSS_STMDEVARCH" hexmask.long.tbyte 0x4 0.--16. 1. "NUMSP,Indicates the number of stimulus ports implemented.0x10000 65536" rgroup.byte 0x13FC8++0x0 line.byte 0x0 "DEBUGSS_STMDEVID" hexmask.byte 0x0 4.--7. 1. "SUB,Sub-classification within the major category:0b0110 The component generates trace based on software and hardware stimulus" hexmask.byte 0x0 0.--3. 1. "MAJOR,Major classification grouping for the debug or trace component:0b0011 The component is a trace source." rgroup.byte 0x13FCC++0x0 line.byte 0x0 "DEBUGSS_STMDEVTYPE" hexmask.byte 0x0 4.--7. 1. "SIZE,This 4-bit value indicates the total contiguous size of the memory window used by the component in powers oftwo from the standard 4KB. If a component only requires the standard 4KB this bit field must read as 0x0 4KBonly. For 8KB set to 0x1 for.." hexmask.byte 0x0 0.--3. 1. "DES_2,JEDEC continuation code indicating the designer of the component together with the identity code.0x4 ARM JEDEC identity code is on the fifth bank." rgroup.byte 0x13FD0++0x0 line.byte 0x0 "DEBUGSS_STMPIDR4" hexmask.byte 0x0 0.--7. 1. "PART_0,Bits [7:0] of the component part number specified by the designer of the component.0b01100011 Lowest eight bits of the part number 0x963." rgroup.byte 0x13FE0++0x0 line.byte 0x0 "DEBUGSS_STMPIDR0" hexmask.byte 0x0 4.--7. 1. "DES_0,Bits [3:0] of the JEDEC identity code indicating the designer of the component together with the continuationcode.0b1011 Lowest four bits of the JEP106 identity code." hexmask.byte 0x0 0.--3. 1. "PART_1,Bits [11:8] of the component part number specified by the designer of the component.0b1001 Upper four bits of the part number 0x963." rgroup.byte 0x13FE4++0x0 line.byte 0x0 "DEBUGSS_STMPIDR1" hexmask.byte 0x0 4.--7. 1. "REVISION,An incremental value starting at 0x0 for the first design of this component. The value increases by one for bothmajor and minor revisions and is used as a look-up to establish the exact major and minor revision.0b0000 The device is at r0p0" bitfld.byte 0x0 3. "JEDEC,Indicates the use of a JEDEC assigned value. This bit is always set.0b1 The designer ID is specified by JEDEC (http://www.jedec.org)." "0,1" newline bitfld.byte 0x0 0.--2. "DES_1,Bits [6:4] of the JEDEC identity code indicating the designer of the component together with the continuationcode.0b011 Upper three bits of the JEP106 identity code" "0,1,2,3,4,5,6,7" rgroup.byte 0x13FE8++0x0 line.byte 0x0 "DEBUGSS_STMPIDR2" hexmask.byte 0x0 4.--7. 1. "REVAND,Indicates minor errata fixes specific to the design for example metal fixes after implementation. In most casesthis field is zero. ARM recommends that the component designers ensure that the bit field can be changed by ametal fix if required for.." hexmask.byte 0x0 0.--3. 1. "CMOD,Where the component is reusable IP this value indicates whether the customer has modified the behavior of thecomponent. In most cases this field is zero.0x0 No modifications made." rgroup.byte 0x13FEC++0x0 line.byte 0x0 "DEBUGSS_STMPIDR3" hexmask.byte 0x0 0.--7. 1. "PRMBL_0,Contains bits [31:21] of the component identification.0x0D Identification value." rgroup.byte 0x13FF0++0x0 line.byte 0x0 "DEBUGSS_STMCIDR0" hexmask.byte 0x0 4.--7. 1. "CLASS,Class of the component for example the ROM table or CoreSight component.0x9 Indicates the component is a CoreSight component." hexmask.byte 0x0 0.--3. 1. "PRMBL_1,Contains bits [19:16] of the component identification.0x0 Identification value." rgroup.byte 0x13FF4++0x0 line.byte 0x0 "DEBUGSS_STMCIDR1" hexmask.byte 0x0 0.--7. 1. "PRMBL_2,Contains bits [15:8] of the component identification.0x05 Identification value." rgroup.byte 0x13FF8++0x0 line.byte 0x0 "DEBUGSS_STMCIDR2" hexmask.byte 0x0 0.--7. 1. "PRMBL_3,Contains bits [7:0] of the component identification.0xB1 Identification value." group.long 0x13FFC++0x3 line.long 0x0 "DEBUGSS_STMCIDR3" hexmask.long 0x0 0.--31. 1. "STM_CTI_CONTROL,Not Defined" wgroup.long 0x14000++0x3 line.long 0x0 "DEBUGSS_STM_CTI_CONTROL" hexmask.long 0x0 0.--31. 1. "STM_CTI_INTACK,Not Defined" group.long 0x14010++0x3 line.long 0x0 "DEBUGSS_STM_CTI_INTACK" hexmask.long 0x0 0.--31. 1. "STM_CTI_APPSET,Not Defined" wgroup.long 0x14014++0x7 line.long 0x0 "DEBUGSS_STM_CTI_APPSET" hexmask.long 0x0 0.--31. 1. "STM_CTI_APPCLEAR,Not Defined" line.long 0x4 "DEBUGSS_STM_CTI_APPCLEAR" hexmask.long 0x4 0.--31. 1. "STM_CTI_APPPULSE,Not Defined" group.long 0x1401C++0x23 line.long 0x0 "DEBUGSS_STM_CTI_APPPULSE" hexmask.long 0x0 0.--31. 1. "STM_CTI_INEN0,Not Defined" line.long 0x4 "DEBUGSS_STM_CTI_INEN0" hexmask.long 0x4 0.--31. 1. "STM_CTI_INEN1,Not Defined" line.long 0x8 "DEBUGSS_STM_CTI_INEN1" hexmask.long 0x8 0.--31. 1. "STM_CTI_INEN2,Not Defined" line.long 0xC "DEBUGSS_STM_CTI_INEN2" hexmask.long 0xC 0.--31. 1. "STM_CTI_INEN3,Not Defined" line.long 0x10 "DEBUGSS_STM_CTI_INEN3" hexmask.long 0x10 0.--31. 1. "STM_CTI_INEN4,Not Defined" line.long 0x14 "DEBUGSS_STM_CTI_INEN4" hexmask.long 0x14 0.--31. 1. "STM_CTI_INEN5,Not Defined" line.long 0x18 "DEBUGSS_STM_CTI_INEN5" hexmask.long 0x18 0.--31. 1. "STM_CTI_INEN6,Not Defined" line.long 0x1C "DEBUGSS_STM_CTI_INEN6" hexmask.long 0x1C 0.--31. 1. "STM_CTI_INEN7,Not Defined" line.long 0x20 "DEBUGSS_STM_CTI_INEN7" hexmask.long 0x20 0.--31. 1. "STM_CTI_OUTEN0,Not Defined" group.long 0x140A0++0x1B line.long 0x0 "DEBUGSS_STM_CTI_OUTEN0" hexmask.long 0x0 0.--31. 1. "STM_CTI_OUTEN1,Not Defined" line.long 0x4 "DEBUGSS_STM_CTI_OUTEN1" hexmask.long 0x4 0.--31. 1. "STM_CTI_OUTEN2,Not Defined" line.long 0x8 "DEBUGSS_STM_CTI_OUTEN2" hexmask.long 0x8 0.--31. 1. "STM_CTI_OUTEN3,Not Defined" line.long 0xC "DEBUGSS_STM_CTI_OUTEN3" hexmask.long 0xC 0.--31. 1. "STM_CTI_OUTEN4,Not Defined" line.long 0x10 "DEBUGSS_STM_CTI_OUTEN4" hexmask.long 0x10 0.--31. 1. "STM_CTI_OUTEN5,Not Defined" line.long 0x14 "DEBUGSS_STM_CTI_OUTEN5" hexmask.long 0x14 0.--31. 1. "STM_CTI_OUTEN6,Not Defined" line.long 0x18 "DEBUGSS_STM_CTI_OUTEN6" hexmask.long 0x18 0.--31. 1. "STM_CTI_OUTEN7,Not Defined" rgroup.long 0x140BC++0x3 line.long 0x0 "DEBUGSS_STM_CTI_OUTEN7" hexmask.long 0x0 0.--31. 1. "STM_CTI_TRIGINSTATUS,Not Defined" rgroup.long 0x14130++0xB line.long 0x0 "DEBUGSS_STM_CTI_TRIGINSTATUS" hexmask.long 0x0 0.--31. 1. "STM_CTI_TRIGOUTSTATUS,Not Defined" line.long 0x4 "DEBUGSS_STM_CTI_TRIGOUTSTATUS" hexmask.long 0x4 0.--31. 1. "STM_CTI_CHINSTATUS,Not Defined" line.long 0x8 "DEBUGSS_STM_CTI_CHINSTATUS" hexmask.long 0x8 0.--31. 1. "STM_CTI_CHOUTSTATUS,Not Defined" group.long 0x1413C++0x7 line.long 0x0 "DEBUGSS_STM_CTI_CHOUTSTATUS" hexmask.long 0x0 0.--31. 1. "STM_CTI_GATE,Not Defined" line.long 0x4 "DEBUGSS_STM_CTI_GATE" hexmask.long 0x4 0.--31. 1. "STM_CTI_ASICCTL,Not Defined" wgroup.long 0x14144++0x3 line.long 0x0 "DEBUGSS_STM_CTI_ASICCTL" hexmask.long 0x0 0.--31. 1. "STM_CTI_ITCHINACK,Not Defined" wgroup.long 0x14EDC++0xB line.long 0x0 "DEBUGSS_STM_CTI_ITCHINACK" hexmask.long 0x0 0.--31. 1. "STM_CTI_ITTRIGINACK,Not Defined" line.long 0x4 "DEBUGSS_STM_CTI_ITTRIGINACK" hexmask.long 0x4 0.--31. 1. "STM_CTI_ITCHOUT,Not Defined" line.long 0x8 "DEBUGSS_STM_CTI_ITCHOUT" hexmask.long 0x8 0.--31. 1. "STM_CTI_ITTRIGOUT,Not Defined" rgroup.long 0x14EE8++0xF line.long 0x0 "DEBUGSS_STM_CTI_ITTRIGOUT" hexmask.long 0x0 0.--31. 1. "STM_CTI_ITCHOUTACK,Not Defined" line.long 0x4 "DEBUGSS_STM_CTI_ITCHOUTACK" hexmask.long 0x4 0.--31. 1. "STM_CTI_ITTRIGOUTACK,Not Defined" line.long 0x8 "DEBUGSS_STM_CTI_ITTRIGOUTACK" hexmask.long 0x8 0.--31. 1. "STM_CTI_ITCHIN,Not Defined" line.long 0xC "DEBUGSS_STM_CTI_ITCHIN" hexmask.long 0xC 0.--31. 1. "STM_CTI_ITTRIGIN,Not Defined" group.long 0x14EF8++0x3 line.long 0x0 "DEBUGSS_STM_CTI_ITTRIGIN" hexmask.long 0x0 0.--31. 1. "STM_CTI_ITCTRL,Not Defined" group.long 0x14F00++0x3 line.long 0x0 "DEBUGSS_STM_CTI_ITCTRL" hexmask.long 0x0 0.--31. 1. "STM_CTI_CLAIM_TAG_SET,Not Defined" group.long 0x14FA0++0x3 line.long 0x0 "DEBUGSS_STM_CTI_CLAIM_TAG_SET" hexmask.long 0x0 0.--31. 1. "STM_CTI_CLAIM_TAG_CLEAR,Not Defined" wgroup.long 0x14FA4++0x3 line.long 0x0 "DEBUGSS_STM_CTI_CLAIM_TAG_CLEAR" hexmask.long 0x0 0.--31. 1. "STM_CTI_LOCK_ACCESS_REGISTER,Not Defined" rgroup.long 0x14FB0++0xB line.long 0x0 "DEBUGSS_STM_CTI_LOCK_ACCESS_REGISTER" hexmask.long 0x0 0.--31. 1. "STM_CTI_LOCK_STATUS_REGISTER,Not Defined" line.long 0x4 "DEBUGSS_STM_CTI_LOCK_STATUS_REGISTER" hexmask.long 0x4 0.--31. 1. "STM_CTI_AUTHENTICATION_STATUS,Not Defined" line.long 0x8 "DEBUGSS_STM_CTI_AUTHENTICATION_STATUS" hexmask.long 0x8 0.--31. 1. "STM_CTI_DEVICE_ID,Not Defined" rgroup.long 0x14FC8++0x33 line.long 0x0 "DEBUGSS_STM_CTI_DEVICE_ID" hexmask.long 0x0 0.--31. 1. "STM_CTI_DEVICE_TYPE_IDENTIFIER,Not Defined" line.long 0x4 "DEBUGSS_STM_CTI_DEVICE_TYPE_IDENTIFIER" hexmask.long 0x4 0.--31. 1. "STM_CTI_PERIPHERALID4,Not Defined" line.long 0x8 "DEBUGSS_STM_CTI_PERIPHERALID4" hexmask.long 0x8 0.--31. 1. "STM_CTI_PERIPHERALID5,Not Defined" line.long 0xC "DEBUGSS_STM_CTI_PERIPHERALID5" hexmask.long 0xC 0.--31. 1. "STM_CTI_PERIPHERALID6,Not Defined" line.long 0x10 "DEBUGSS_STM_CTI_PERIPHERALID6" hexmask.long 0x10 0.--31. 1. "STM_CTI_PERIPHERALID7,Not Defined" line.long 0x14 "DEBUGSS_STM_CTI_PERIPHERALID7" hexmask.long 0x14 0.--31. 1. "STM_CTI_PERIPHERALID0,Not Defined" line.long 0x18 "DEBUGSS_STM_CTI_PERIPHERALID0" hexmask.long 0x18 0.--31. 1. "STM_CTI_PERIPHERALID1,Not Defined" line.long 0x1C "DEBUGSS_STM_CTI_PERIPHERALID1" hexmask.long 0x1C 0.--31. 1. "STM_CTI_PERIPHERALID2,Not Defined" line.long 0x20 "DEBUGSS_STM_CTI_PERIPHERALID2" hexmask.long 0x20 0.--31. 1. "STM_CTI_PERIPHERALID3,Not Defined" line.long 0x24 "DEBUGSS_STM_CTI_PERIPHERALID3" hexmask.long 0x24 0.--31. 1. "STM_CTI_COMPONENT_ID0,Not Defined" line.long 0x28 "DEBUGSS_STM_CTI_COMPONENT_ID0" hexmask.long 0x28 0.--31. 1. "STM_CTI_COMPONENT_ID1,Not Defined" line.long 0x2C "DEBUGSS_STM_CTI_COMPONENT_ID1" hexmask.long 0x2C 0.--31. 1. "STM_CTI_COMPONENT_ID2,Not Defined" line.long 0x30 "DEBUGSS_STM_CTI_COMPONENT_ID2" hexmask.long 0x30 0.--31. 1. "STM_CTI_COMPONENT_ID3,Not Defined" group.long 0x14FFC++0x3 line.long 0x0 "DEBUGSS_STM_CTI_COMPONENT_ID3" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_CONTROL,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.htmlhttp://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html" wgroup.long 0x15000++0x3 line.long 0x0 "DEBUGSS_HSM_CM4_CTI_CONTROL" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_INTACK,Not Defined" group.long 0x15010++0x3 line.long 0x0 "DEBUGSS_HSM_CM4_CTI_INTACK" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_APPSET,Not Defined" wgroup.long 0x15014++0x7 line.long 0x0 "DEBUGSS_HSM_CM4_CTI_APPSET" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_APPCLEAR,Not Defined" line.long 0x4 "DEBUGSS_HSM_CM4_CTI_APPCLEAR" hexmask.long 0x4 0.--31. 1. "HSM_CM4_CTI_APPPULSE,Not Defined" group.long 0x1501C++0x23 line.long 0x0 "DEBUGSS_HSM_CM4_CTI_APPPULSE" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_INEN0,Not Defined" line.long 0x4 "DEBUGSS_HSM_CM4_CTI_INEN0" hexmask.long 0x4 0.--31. 1. "HSM_CM4_CTI_INEN1,Not Defined" line.long 0x8 "DEBUGSS_HSM_CM4_CTI_INEN1" hexmask.long 0x8 0.--31. 1. "HSM_CM4_CTI_INEN2,Not Defined" line.long 0xC "DEBUGSS_HSM_CM4_CTI_INEN2" hexmask.long 0xC 0.--31. 1. "HSM_CM4_CTI_INEN3,Not Defined" line.long 0x10 "DEBUGSS_HSM_CM4_CTI_INEN3" hexmask.long 0x10 0.--31. 1. "HSM_CM4_CTI_INEN4,Not Defined" line.long 0x14 "DEBUGSS_HSM_CM4_CTI_INEN4" hexmask.long 0x14 0.--31. 1. "HSM_CM4_CTI_INEN5,Not Defined" line.long 0x18 "DEBUGSS_HSM_CM4_CTI_INEN5" hexmask.long 0x18 0.--31. 1. "HSM_CM4_CTI_INEN6,Not Defined" line.long 0x1C "DEBUGSS_HSM_CM4_CTI_INEN6" hexmask.long 0x1C 0.--31. 1. "HSM_CM4_CTI_INEN7,Not Defined" line.long 0x20 "DEBUGSS_HSM_CM4_CTI_INEN7" hexmask.long 0x20 0.--31. 1. "HSM_CM4_CTI_OUTEN0,Not Defined" group.long 0x150A0++0x1B line.long 0x0 "DEBUGSS_HSM_CM4_CTI_OUTEN0" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_OUTEN1,Not Defined" line.long 0x4 "DEBUGSS_HSM_CM4_CTI_OUTEN1" hexmask.long 0x4 0.--31. 1. "HSM_CM4_CTI_OUTEN2,Not Defined" line.long 0x8 "DEBUGSS_HSM_CM4_CTI_OUTEN2" hexmask.long 0x8 0.--31. 1. "HSM_CM4_CTI_OUTEN3,Not Defined" line.long 0xC "DEBUGSS_HSM_CM4_CTI_OUTEN3" hexmask.long 0xC 0.--31. 1. "HSM_CM4_CTI_OUTEN4,Not Defined" line.long 0x10 "DEBUGSS_HSM_CM4_CTI_OUTEN4" hexmask.long 0x10 0.--31. 1. "HSM_CM4_CTI_OUTEN5,Not Defined" line.long 0x14 "DEBUGSS_HSM_CM4_CTI_OUTEN5" hexmask.long 0x14 0.--31. 1. "HSM_CM4_CTI_OUTEN6,Not Defined" line.long 0x18 "DEBUGSS_HSM_CM4_CTI_OUTEN6" hexmask.long 0x18 0.--31. 1. "HSM_CM4_CTI_OUTEN7,Not Defined" rgroup.long 0x150BC++0x3 line.long 0x0 "DEBUGSS_HSM_CM4_CTI_OUTEN7" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_TRIGINSTATUS,Not Defined" rgroup.long 0x15130++0xB line.long 0x0 "DEBUGSS_HSM_CM4_CTI_TRIGINSTATUS" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_TRIGOUTSTATUS,Not Defined" line.long 0x4 "DEBUGSS_HSM_CM4_CTI_TRIGOUTSTATUS" hexmask.long 0x4 0.--31. 1. "HSM_CM4_CTI_CHINSTATUS,Not Defined" line.long 0x8 "DEBUGSS_HSM_CM4_CTI_CHINSTATUS" hexmask.long 0x8 0.--31. 1. "HSM_CM4_CTI_CHOUTSTATUS,Not Defined" group.long 0x1513C++0x7 line.long 0x0 "DEBUGSS_HSM_CM4_CTI_CHOUTSTATUS" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_GATE,Not Defined" line.long 0x4 "DEBUGSS_HSM_CM4_CTI_GATE" hexmask.long 0x4 0.--31. 1. "HSM_CM4_CTI_ASICCTL,Not Defined" wgroup.long 0x15144++0x3 line.long 0x0 "DEBUGSS_HSM_CM4_CTI_ASICCTL" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_ITCHINACK,Not Defined" wgroup.long 0x15EDC++0xB line.long 0x0 "DEBUGSS_HSM_CM4_CTI_ITCHINACK" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_ITTRIGINACK,Not Defined" line.long 0x4 "DEBUGSS_HSM_CM4_CTI_ITTRIGINACK" hexmask.long 0x4 0.--31. 1. "HSM_CM4_CTI_ITCHOUT,Not Defined" line.long 0x8 "DEBUGSS_HSM_CM4_CTI_ITCHOUT" hexmask.long 0x8 0.--31. 1. "HSM_CM4_CTI_ITTRIGOUT,Not Defined" rgroup.long 0x15EE8++0xF line.long 0x0 "DEBUGSS_HSM_CM4_CTI_ITTRIGOUT" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_ITCHOUTACK,Not Defined" line.long 0x4 "DEBUGSS_HSM_CM4_CTI_ITCHOUTACK" hexmask.long 0x4 0.--31. 1. "HSM_CM4_CTI_ITTRIGOUTACK,Not Defined" line.long 0x8 "DEBUGSS_HSM_CM4_CTI_ITTRIGOUTACK" hexmask.long 0x8 0.--31. 1. "HSM_CM4_CTI_ITCHIN,Not Defined" line.long 0xC "DEBUGSS_HSM_CM4_CTI_ITCHIN" hexmask.long 0xC 0.--31. 1. "HSM_CM4_CTI_ITTRIGIN,Not Defined" group.long 0x15EF8++0x3 line.long 0x0 "DEBUGSS_HSM_CM4_CTI_ITTRIGIN" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_ITCTRL,Not Defined" group.long 0x15F00++0x3 line.long 0x0 "DEBUGSS_HSM_CM4_CTI_ITCTRL" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_CLAIM_TAG_SET,Not Defined" group.long 0x15FA0++0x3 line.long 0x0 "DEBUGSS_HSM_CM4_CTI_CLAIM_TAG_SET" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_CLAIM_TAG_CLEAR,Not Defined" wgroup.long 0x15FA4++0x3 line.long 0x0 "DEBUGSS_HSM_CM4_CTI_CLAIM_TAG_CLEAR" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_LOCK_ACCESS_REGISTER,Not Defined" rgroup.long 0x15FB0++0xB line.long 0x0 "DEBUGSS_HSM_CM4_CTI_LOCK_ACCESS_REGISTER" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_LOCK_STATUS_REGISTER,Not Defined" line.long 0x4 "DEBUGSS_HSM_CM4_CTI_LOCK_STATUS_REGISTER" hexmask.long 0x4 0.--31. 1. "HSM_CM4_CTI_AUTHENTICATION_STATUS,Not Defined" line.long 0x8 "DEBUGSS_HSM_CM4_CTI_AUTHENTICATION_STATUS" hexmask.long 0x8 0.--31. 1. "HSM_CM4_CTI_DEVICE_ID,Not Defined" rgroup.long 0x15FC8++0x33 line.long 0x0 "DEBUGSS_HSM_CM4_CTI_DEVICE_ID" hexmask.long 0x0 0.--31. 1. "HSM_CM4_CTI_DEVICE_TYPE_IDENTIFIER,Not Defined" line.long 0x4 "DEBUGSS_HSM_CM4_CTI_DEVICE_TYPE_IDENTIFIER" hexmask.long 0x4 0.--31. 1. "HSM_CM4_CTI_PERIPHERALID4,Not Defined" line.long 0x8 "DEBUGSS_HSM_CM4_CTI_PERIPHERALID4" hexmask.long 0x8 0.--31. 1. "HSM_CM4_CTI_PERIPHERALID5,Not Defined" line.long 0xC "DEBUGSS_HSM_CM4_CTI_PERIPHERALID5" hexmask.long 0xC 0.--31. 1. "HSM_CM4_CTI_PERIPHERALID6,Not Defined" line.long 0x10 "DEBUGSS_HSM_CM4_CTI_PERIPHERALID6" hexmask.long 0x10 0.--31. 1. "HSM_CM4_CTI_PERIPHERALID7,Not Defined" line.long 0x14 "DEBUGSS_HSM_CM4_CTI_PERIPHERALID7" hexmask.long 0x14 0.--31. 1. "HSM_CM4_CTI_PERIPHERALID0,Not Defined" line.long 0x18 "DEBUGSS_HSM_CM4_CTI_PERIPHERALID0" hexmask.long 0x18 0.--31. 1. "HSM_CM4_CTI_PERIPHERALID1,Not Defined" line.long 0x1C "DEBUGSS_HSM_CM4_CTI_PERIPHERALID1" hexmask.long 0x1C 0.--31. 1. "HSM_CM4_CTI_PERIPHERALID2,Not Defined" line.long 0x20 "DEBUGSS_HSM_CM4_CTI_PERIPHERALID2" hexmask.long 0x20 0.--31. 1. "HSM_CM4_CTI_PERIPHERALID3,Not Defined" line.long 0x24 "DEBUGSS_HSM_CM4_CTI_PERIPHERALID3" hexmask.long 0x24 0.--31. 1. "HSM_CM4_CTI_COMPONENT_ID0,Not Defined" line.long 0x28 "DEBUGSS_HSM_CM4_CTI_COMPONENT_ID0" hexmask.long 0x28 0.--31. 1. "HSM_CM4_CTI_COMPONENT_ID1,Not Defined" line.long 0x2C "DEBUGSS_HSM_CM4_CTI_COMPONENT_ID1" hexmask.long 0x2C 0.--31. 1. "HSM_CM4_CTI_COMPONENT_ID2,Not Defined" line.long 0x30 "DEBUGSS_HSM_CM4_CTI_COMPONENT_ID2" hexmask.long 0x30 0.--31. 1. "HSM_CM4_CTI_COMPONENT_ID3,Not Defined" group.long 0x15FFC++0x3 line.long 0x0 "DEBUGSS_HSM_CM4_CTI_COMPONENT_ID3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGDIDR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0363e/Cegejeeb.htmlDebug Identification Register" group.long 0x20000++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_ROM" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGWFAR,Watchpoint Fault Address Register" group.long 0x30000++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_DBGDIDR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGVCR,Vector Catch Register" group.long 0x30018++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_DBGWFAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGECR,Not Implemented" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_DBGVCR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGDSCCR,Debug State Cache Control Register" group.long 0x30024++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_DBGECR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGDTRRX,Host to Target Data Transfer Register" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_DBGDSCCR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGITR,Instruction Transfer Register" group.long 0x30080++0x13 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_DBGDTRRX" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGDSCR,Debug Status and Control Register" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_DBGITR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGDTRTX,Target to Host Data Transfer Register" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_APB_DBGDSCR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_DBGDRCR,Debug Run Control Register" line.long 0xC "DEBUGSS_MSS_R5SS0_A_APB_DBGDTRTX" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_APB_DBGBVR0,Break Point Value Register 0" line.long 0x10 "DEBUGSS_MSS_R5SS0_A_APB_DBGDRCR" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_APB_DBGBVR1,Break Point Value Register 1" group.long 0x30100++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_DBGBVR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGBVR2,Break Point Value Register 2" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_DBGBVR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGBVR3,Break Point Value Register 3" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_APB_DBGBVR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_DBGBVR4,Break Point Value Register 4" line.long 0xC "DEBUGSS_MSS_R5SS0_A_APB_DBGBVR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_APB_DBGBVR5,Break Point Value Register 5" line.long 0x10 "DEBUGSS_MSS_R5SS0_A_APB_DBGBVR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_APB_DBGBVR6,Break Point Value Register 6" line.long 0x14 "DEBUGSS_MSS_R5SS0_A_APB_DBGBVR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_APB_DBGBVR7,Break Point Value Register 7" line.long 0x18 "DEBUGSS_MSS_R5SS0_A_APB_DBGBVR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_APB_DBGBCR0,Break Point Control Register 0" line.long 0x1C "DEBUGSS_MSS_R5SS0_A_APB_DBGBVR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_APB_DBGBCR1,Break Point Control Register 1" group.long 0x30140++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_DBGBCR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGBCR2,Break Point Control Register 2" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_DBGBCR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGBCR3,Break Point Control Register 3" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_APB_DBGBCR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_DBGBCR4,Break Point Control Register 4" line.long 0xC "DEBUGSS_MSS_R5SS0_A_APB_DBGBCR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_APB_DBGBCR5,Break Point Control Register 5" line.long 0x10 "DEBUGSS_MSS_R5SS0_A_APB_DBGBCR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_APB_DBGBCR6,Break Point Control Register 6" line.long 0x14 "DEBUGSS_MSS_R5SS0_A_APB_DBGBCR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_APB_DBGBCR7,Break Point Control Register 7" line.long 0x18 "DEBUGSS_MSS_R5SS0_A_APB_DBGBCR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_APB_DBGWVR0,Watch Point Value Register 0" line.long 0x1C "DEBUGSS_MSS_R5SS0_A_APB_DBGBCR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_APB_DBGWVR1,Watch Point Value Register 1" group.long 0x30180++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_DBGWVR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGWVR2,Watch Point Value Register 2" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_DBGWVR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGWVR3,Watch Point Value Register 3" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_APB_DBGWVR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_DBGWVR4,Watch Point Value Register 4" line.long 0xC "DEBUGSS_MSS_R5SS0_A_APB_DBGWVR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_APB_DBGWVR5,Watch Point Value Register 5" line.long 0x10 "DEBUGSS_MSS_R5SS0_A_APB_DBGWVR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_APB_DBGWVR6,Watch Point Value Register 6" line.long 0x14 "DEBUGSS_MSS_R5SS0_A_APB_DBGWVR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_APB_DBGWVR7,Watch Point Value Register 7" line.long 0x18 "DEBUGSS_MSS_R5SS0_A_APB_DBGWVR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_APB_DBGWCR0,Watch Point Control Register 0" line.long 0x1C "DEBUGSS_MSS_R5SS0_A_APB_DBGWVR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_APB_DBGWCR1,Watch Point Control Register 1" group.long 0x301C0++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_DBGWCR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGWCR2,Watch Point Control Register 2" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_DBGWCR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGWCR3,Watch Point Control Register 3" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_APB_DBGWCR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_DBGWCR4,Watch Point Control Register 4" line.long 0xC "DEBUGSS_MSS_R5SS0_A_APB_DBGWCR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_APB_DBGWCR5,Watch Point Control Register 5" line.long 0x10 "DEBUGSS_MSS_R5SS0_A_APB_DBGWCR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_APB_DBGWCR6,Watch Point Control Register 6" line.long 0x14 "DEBUGSS_MSS_R5SS0_A_APB_DBGWCR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_APB_DBGWCR7,Watch Point Control Register 7" line.long 0x18 "DEBUGSS_MSS_R5SS0_A_APB_DBGWCR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_APB_DBGOSLAR,Not Implemented" line.long 0x1C "DEBUGSS_MSS_R5SS0_A_APB_DBGWCR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_APB_DBGOSLSR,Operating System Lock Status Register" group.long 0x30300++0xB line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_DBGOSLAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGOSSRR,Not Implemented" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_DBGOSLSR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGPRCR,Device Power Down and Reset Control Regsiter" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_APB_DBGOSSRR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_DBGPRSR,Device Power Down and Reset Status Register" group.long 0x30310++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_DBGPRCR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_PROCID_MIDR,Main ID Register" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_DBGPRSR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_PROCID_CTR,Cache Type Register" group.long 0x30D00++0xB line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_MIDR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_PROCID_TCMTR,TCM Type Register" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_CTR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_PROCID_MPUIR,MPU Type Register" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_TCMTR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_PROCID_MPIDR,Multiprocessor Affinity Register" group.long 0x30D10++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_MPUIR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_PROCID_PFR0,Processor Feature Register 0" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_MPIDR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_PROCID_PFR1,Processor Feature Register 1" group.long 0x30D20++0x37 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_PFR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_PROCID_DFR0,Debug Feature Register 0" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_PFR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_PROCID_AFR0,Auxiliary Feature Register 0" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_DFR0" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_PROCID_MMFR0,Processor Feature Register 0" line.long 0xC "DEBUGSS_MSS_R5SS0_A_APB_PROCID_AFR0" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_APB_PROCID_MMFR1,Memory Model Feature Register 1" line.long 0x10 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_MMFR0" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_APB_PROCID_MMFR2,Memory Model Feature Register 2" line.long 0x14 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_MMFR1" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_APB_PROCID_MMFR3,Memory Model Feature Register 3" line.long 0x18 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_MMFR2" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_APB_PROCID_ISAR0,ISA Feature Register 0" line.long 0x1C "DEBUGSS_MSS_R5SS0_A_APB_PROCID_MMFR3" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_APB_PROCID_ISAR1,ISA Feature Register 1" line.long 0x20 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_ISAR0" hexmask.long 0x20 0.--31. 1. "MSS_R5SS0_APB_PROCID_ISAR2,ISA Feature Register 2" line.long 0x24 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_ISAR1" hexmask.long 0x24 0.--31. 1. "MSS_R5SS0_APB_PROCID_ISAR3,ISA Feature Register 3" line.long 0x28 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_ISAR2" hexmask.long 0x28 0.--31. 1. "MSS_R5SS0_APB_PROCID_ISAR4,ISA Feature Register 4" line.long 0x2C "DEBUGSS_MSS_R5SS0_A_APB_PROCID_ISAR3" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS0_APB_PROCID_ISAR5,ISA Feature Register 5" line.long 0x30 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_ISAR4" hexmask.long 0x30 0.--31. 1. "MSS_R5SS0_APB_MR_ITCTRL,Integration Mode Control Registers" line.long 0x34 "DEBUGSS_MSS_R5SS0_A_APB_PROCID_ISAR5" hexmask.long 0x34 0.--31. 1. "MSS_R5SS0_APB_MR_CLAIMSET,Claim Tag Set Register" group.long 0x30F00++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_MR_ITCTRL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_MR_CLAIMCLR,Claim Tag Clear Register" group.long 0x30FA0++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_MR_CLAIMSET" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_MR_LOCKACCESS,Lock Access Register" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_MR_CLAIMCLR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_MR_LOCKSTATUS,Lock Status Register" group.long 0x30FB0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_MR_LOCKACCESS" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_MR_AUTHSTATUS,Authentication Status Register" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_MR_LOCKSTATUS" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_MR_DEVID,Device Identifier" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_APB_MR_AUTHSTATUS" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_MR_DEVTYPE,Device Type Register" group.long 0x30FC8++0xB line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_MR_DEVID" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_PERIP_ID4,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_MR_DEVTYPE" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_PERIP_ID0,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_APB_PERIP_ID4" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_PERIP_ID1,Not Defined" group.long 0x30FE0++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS0_A_APB_PERIP_ID0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_PERIP_ID2,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_APB_PERIP_ID1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_PERIP_ID3,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_APB_PERIP_ID2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_COMP_ID0,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_A_APB_PERIP_ID3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_APB_COMP_ID1,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_A_APB_COMP_ID0" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_APB_COMP_ID2,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_A_APB_COMP_ID1" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_APB_COMP_ID3,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS0_A_APB_COMP_ID2" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_APB_DBGDIDR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0363e/Cegejeeb.htmlDebug Identification Register" line.long 0x1C "DEBUGSS_MSS_R5SS0_A_APB_COMP_ID3" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_APB_DBGWFAR,Watchpoint Fault Address Register" group.long 0x32000++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_DBGDIDR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGVCR,Vector Catch Register" group.long 0x32018++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_DBGWFAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGECR,Not Implemented" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_DBGVCR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGDSCCR,Debug State Cache Control Register" group.long 0x32024++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_DBGECR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGDTRRX,Host to Target Data Transfer Register" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_DBGDSCCR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGITR,Instruction Transfer Register" group.long 0x32080++0x13 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_DBGDTRRX" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGDSCR,Debug Status and Control Register" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_DBGITR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGDTRTX,Target to Host Data Transfer Register" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_APB_DBGDSCR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_DBGDRCR,Debug Run Control Register" line.long 0xC "DEBUGSS_MSS_R5SS0_B_APB_DBGDTRTX" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_APB_DBGBVR0,Break Point Value Register 0" line.long 0x10 "DEBUGSS_MSS_R5SS0_B_APB_DBGDRCR" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_APB_DBGBVR1,Break Point Value Register 1" group.long 0x32100++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_DBGBVR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGBVR2,Break Point Value Register 2" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_DBGBVR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGBVR3,Break Point Value Register 3" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_APB_DBGBVR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_DBGBVR4,Break Point Value Register 4" line.long 0xC "DEBUGSS_MSS_R5SS0_B_APB_DBGBVR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_APB_DBGBVR5,Break Point Value Register 5" line.long 0x10 "DEBUGSS_MSS_R5SS0_B_APB_DBGBVR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_APB_DBGBVR6,Break Point Value Register 6" line.long 0x14 "DEBUGSS_MSS_R5SS0_B_APB_DBGBVR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_APB_DBGBVR7,Break Point Value Register 7" line.long 0x18 "DEBUGSS_MSS_R5SS0_B_APB_DBGBVR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_APB_DBGBCR0,Break Point Control Register 0" line.long 0x1C "DEBUGSS_MSS_R5SS0_B_APB_DBGBVR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_APB_DBGBCR1,Break Point Control Register 1" group.long 0x32140++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_DBGBCR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGBCR2,Break Point Control Register 2" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_DBGBCR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGBCR3,Break Point Control Register 3" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_APB_DBGBCR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_DBGBCR4,Break Point Control Register 4" line.long 0xC "DEBUGSS_MSS_R5SS0_B_APB_DBGBCR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_APB_DBGBCR5,Break Point Control Register 5" line.long 0x10 "DEBUGSS_MSS_R5SS0_B_APB_DBGBCR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_APB_DBGBCR6,Break Point Control Register 6" line.long 0x14 "DEBUGSS_MSS_R5SS0_B_APB_DBGBCR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_APB_DBGBCR7,Break Point Control Register 7" line.long 0x18 "DEBUGSS_MSS_R5SS0_B_APB_DBGBCR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_APB_DBGWVR0,Watch Point Value Register 0" line.long 0x1C "DEBUGSS_MSS_R5SS0_B_APB_DBGBCR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_APB_DBGWVR1,Watch Point Value Register 1" group.long 0x32180++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_DBGWVR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGWVR2,Watch Point Value Register 2" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_DBGWVR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGWVR3,Watch Point Value Register 3" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_APB_DBGWVR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_DBGWVR4,Watch Point Value Register 4" line.long 0xC "DEBUGSS_MSS_R5SS0_B_APB_DBGWVR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_APB_DBGWVR5,Watch Point Value Register 5" line.long 0x10 "DEBUGSS_MSS_R5SS0_B_APB_DBGWVR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_APB_DBGWVR6,Watch Point Value Register 6" line.long 0x14 "DEBUGSS_MSS_R5SS0_B_APB_DBGWVR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_APB_DBGWVR7,Watch Point Value Register 7" line.long 0x18 "DEBUGSS_MSS_R5SS0_B_APB_DBGWVR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_APB_DBGWCR0,Watch Point Control Register 0" line.long 0x1C "DEBUGSS_MSS_R5SS0_B_APB_DBGWVR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_APB_DBGWCR1,Watch Point Control Register 1" group.long 0x321C0++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_DBGWCR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGWCR2,Watch Point Control Register 2" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_DBGWCR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGWCR3,Watch Point Control Register 3" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_APB_DBGWCR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_DBGWCR4,Watch Point Control Register 4" line.long 0xC "DEBUGSS_MSS_R5SS0_B_APB_DBGWCR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_APB_DBGWCR5,Watch Point Control Register 5" line.long 0x10 "DEBUGSS_MSS_R5SS0_B_APB_DBGWCR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_APB_DBGWCR6,Watch Point Control Register 6" line.long 0x14 "DEBUGSS_MSS_R5SS0_B_APB_DBGWCR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_APB_DBGWCR7,Watch Point Control Register 7" line.long 0x18 "DEBUGSS_MSS_R5SS0_B_APB_DBGWCR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_APB_DBGOSLAR,Not Implemented" line.long 0x1C "DEBUGSS_MSS_R5SS0_B_APB_DBGWCR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_APB_DBGOSLSR,Operating System Lock Status Register" group.long 0x32300++0xB line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_DBGOSLAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_DBGOSSRR,Not Implemented" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_DBGOSLSR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_DBGPRCR,Device Power Down and Reset Control Regsiter" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_APB_DBGOSSRR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_DBGPRSR,Device Power Down and Reset Status Register" group.long 0x32310++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_DBGPRCR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_PROCID_MIDR,Main ID Register" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_DBGPRSR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_PROCID_CTR,Cache Type Register" group.long 0x32D00++0xB line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_MIDR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_PROCID_TCMTR,TCM Type Register" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_CTR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_PROCID_MPUIR,MPU Type Register" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_TCMTR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_PROCID_MPIDR,Multiprocessor Affinity Register" group.long 0x32D10++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_MPUIR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_PROCID_PFR0,Processor Feature Register 0" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_MPIDR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_PROCID_PFR1,Processor Feature Register 1" group.long 0x32D20++0x37 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_PFR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_PROCID_DFR0,Debug Feature Register 0" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_PFR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_PROCID_AFR0,Auxiliary Feature Register 0" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_DFR0" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_PROCID_MMFR0,Processor Feature Register 0" line.long 0xC "DEBUGSS_MSS_R5SS0_B_APB_PROCID_AFR0" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_APB_PROCID_MMFR1,Memory Model Feature Register 1" line.long 0x10 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_MMFR0" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_APB_PROCID_MMFR2,Memory Model Feature Register 2" line.long 0x14 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_MMFR1" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_APB_PROCID_MMFR3,Memory Model Feature Register 3" line.long 0x18 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_MMFR2" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_APB_PROCID_ISAR0,ISA Feature Register 0" line.long 0x1C "DEBUGSS_MSS_R5SS0_B_APB_PROCID_MMFR3" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_APB_PROCID_ISAR1,ISA Feature Register 1" line.long 0x20 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_ISAR0" hexmask.long 0x20 0.--31. 1. "MSS_R5SS0_APB_PROCID_ISAR2,ISA Feature Register 2" line.long 0x24 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_ISAR1" hexmask.long 0x24 0.--31. 1. "MSS_R5SS0_APB_PROCID_ISAR3,ISA Feature Register 3" line.long 0x28 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_ISAR2" hexmask.long 0x28 0.--31. 1. "MSS_R5SS0_APB_PROCID_ISAR4,ISA Feature Register 4" line.long 0x2C "DEBUGSS_MSS_R5SS0_B_APB_PROCID_ISAR3" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS0_APB_PROCID_ISAR5,ISA Feature Register 5" line.long 0x30 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_ISAR4" hexmask.long 0x30 0.--31. 1. "MSS_R5SS0_APB_MR_ITCTRL,Integration Mode Control Registers" line.long 0x34 "DEBUGSS_MSS_R5SS0_B_APB_PROCID_ISAR5" hexmask.long 0x34 0.--31. 1. "MSS_R5SS0_APB_MR_CLAIMSET,Claim Tag Set Register" group.long 0x32F00++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_MR_ITCTRL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_MR_CLAIMCLR,Claim Tag Clear Register" group.long 0x32FA0++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_MR_CLAIMSET" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_MR_LOCKACCESS,Lock Access Register" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_MR_CLAIMCLR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_MR_LOCKSTATUS,Lock Status Register" group.long 0x32FB0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_MR_LOCKACCESS" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_MR_AUTHSTATUS,Authentication Status Register" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_MR_LOCKSTATUS" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_MR_DEVID,Device Identifier" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_APB_MR_AUTHSTATUS" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_MR_DEVTYPE,Device Type Register" group.long 0x32FC8++0xB line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_MR_DEVID" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_PERIP_ID4,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_MR_DEVTYPE" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_PERIP_ID0,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_APB_PERIP_ID4" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_PERIP_ID1,Not Defined" group.long 0x32FE0++0x1B line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_PERIP_ID0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_APB_PERIP_ID2,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_APB_PERIP_ID1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_APB_PERIP_ID3,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_APB_PERIP_ID2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_APB_COMP_ID0,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_B_APB_PERIP_ID3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_APB_COMP_ID1,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_B_APB_COMP_ID0" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_APB_COMP_ID2,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_B_APB_COMP_ID1" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_APB_COMP_ID3,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS0_B_APB_COMP_ID2" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_CTI_CONTROL,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.htmlhttp://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html" wgroup.long 0x32FFC++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_APB_COMP_ID3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_INTACK,Not Defined" group.long 0x38000++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_CONTROL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_APPSET,Not Defined" wgroup.long 0x38010++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_INTACK" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_APPCLEAR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_CTI_APPSET" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_APPPULSE,Not Defined" group.long 0x38018++0x27 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_APPCLEAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_INEN0,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_CTI_APPPULSE" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_INEN1,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_CTI_INEN0" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_CTI_INEN2,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_A_CTI_INEN1" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_CTI_INEN3,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_A_CTI_INEN2" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_CTI_INEN4,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_A_CTI_INEN3" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_CTI_INEN5,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS0_A_CTI_INEN4" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_CTI_INEN6,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS0_A_CTI_INEN5" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_CTI_INEN7,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS0_A_CTI_INEN6" hexmask.long 0x20 0.--31. 1. "MSS_R5SS0_CTI_OUTEN0,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS0_A_CTI_INEN7" hexmask.long 0x24 0.--31. 1. "MSS_R5SS0_CTI_OUTEN1,Not Defined" group.long 0x380A0++0x17 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_OUTEN0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_OUTEN2,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_CTI_OUTEN1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_OUTEN3,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_CTI_OUTEN2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_CTI_OUTEN4,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_A_CTI_OUTEN3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_CTI_OUTEN5,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_A_CTI_OUTEN4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_CTI_OUTEN6,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_A_CTI_OUTEN5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_CTI_OUTEN7,Not Defined" rgroup.long 0x380B8++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_OUTEN6" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_TRIGINSTATUS,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_CTI_OUTEN7" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_TRIGOUTSTATUS,Not Defined" rgroup.long 0x38130++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_TRIGINSTATUS" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_CHINSTATUS,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_CTI_TRIGOUTSTATUS" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_CHOUTSTATUS,Not Defined" group.long 0x38138++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_CHINSTATUS" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_GATE,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_CTI_CHOUTSTATUS" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_ASICCTL,Not Defined" wgroup.long 0x38140++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_GATE" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_ITCHINACK,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_CTI_ASICCTL" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_ITTRIGINACK,Not Defined" wgroup.long 0x38EDC++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_ITCHINACK" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_ITCHOUT,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_CTI_ITTRIGINACK" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_ITTRIGOUT,Not Defined" rgroup.long 0x38EE4++0xF line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_ITCHOUT" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_ITCHOUTACK,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_CTI_ITTRIGOUT" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_ITTRIGOUTACK,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_CTI_ITCHOUTACK" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_CTI_ITCHIN,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_A_CTI_ITTRIGOUTACK" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_CTI_ITTRIGIN,Not Defined" group.long 0x38EF4++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_ITCHIN" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_ITCTRL,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_CTI_ITTRIGIN" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_CLAIM_TAG_SET,Not Defined" group.long 0x38F00++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_ITCTRL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_CLAIM_TAG_CLEAR,Not Defined" wgroup.long 0x38FA0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_CLAIM_TAG_SET" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_LOCK_ACCESS_REGISTER,Not Defined" rgroup.long 0x38FA4++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_CLAIM_TAG_CLEAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_LOCK_STATUS_REGISTER,Not Defined" rgroup.long 0x38FB0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_LOCK_ACCESS_REGISTER" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_AUTHENTICATION_STATUS,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_CTI_LOCK_STATUS_REGISTER" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_DEVICE_ID,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_CTI_AUTHENTICATION_STATUS" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_CTI_DEVICE_TYPE_IDENTIFIER,Not Defined" rgroup.long 0x38FC8++0x2F line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_DEVICE_ID" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID4,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_CTI_DEVICE_TYPE_IDENTIFIER" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID5,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_CTI_PERIPHERALID4" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID6,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_A_CTI_PERIPHERALID5" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID7,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_A_CTI_PERIPHERALID6" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID0,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_A_CTI_PERIPHERALID7" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID1,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS0_A_CTI_PERIPHERALID0" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID2,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS0_A_CTI_PERIPHERALID1" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID3,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS0_A_CTI_PERIPHERALID2" hexmask.long 0x20 0.--31. 1. "MSS_R5SS0_CTI_COMPONENT_ID0,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS0_A_CTI_PERIPHERALID3" hexmask.long 0x24 0.--31. 1. "MSS_R5SS0_CTI_COMPONENT_ID1,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS0_A_CTI_COMPONENT_ID0" hexmask.long 0x28 0.--31. 1. "MSS_R5SS0_CTI_COMPONENT_ID2,Not Defined" line.long 0x2C "DEBUGSS_MSS_R5SS0_A_CTI_COMPONENT_ID1" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS0_CTI_COMPONENT_ID3,Not Defined" group.long 0x38FF8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_COMPONENT_ID2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_CONTROL,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.htmlhttp://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html" wgroup.long 0x38FFC++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_CTI_COMPONENT_ID3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_INTACK,Not Defined" group.long 0x39000++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_CONTROL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_APPSET,Not Defined" wgroup.long 0x39010++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_INTACK" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_APPCLEAR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_CTI_APPSET" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_APPPULSE,Not Defined" group.long 0x39018++0x27 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_APPCLEAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_INEN0,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_CTI_APPPULSE" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_INEN1,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_CTI_INEN0" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_CTI_INEN2,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_B_CTI_INEN1" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_CTI_INEN3,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_B_CTI_INEN2" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_CTI_INEN4,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_B_CTI_INEN3" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_CTI_INEN5,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS0_B_CTI_INEN4" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_CTI_INEN6,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS0_B_CTI_INEN5" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_CTI_INEN7,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS0_B_CTI_INEN6" hexmask.long 0x20 0.--31. 1. "MSS_R5SS0_CTI_OUTEN0,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS0_B_CTI_INEN7" hexmask.long 0x24 0.--31. 1. "MSS_R5SS0_CTI_OUTEN1,Not Defined" group.long 0x390A0++0x17 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_OUTEN0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_OUTEN2,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_CTI_OUTEN1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_OUTEN3,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_CTI_OUTEN2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_CTI_OUTEN4,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_B_CTI_OUTEN3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_CTI_OUTEN5,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_B_CTI_OUTEN4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_CTI_OUTEN6,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_B_CTI_OUTEN5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_CTI_OUTEN7,Not Defined" rgroup.long 0x390B8++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_OUTEN6" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_TRIGINSTATUS,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_CTI_OUTEN7" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_TRIGOUTSTATUS,Not Defined" rgroup.long 0x39130++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_TRIGINSTATUS" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_CHINSTATUS,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_CTI_TRIGOUTSTATUS" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_CHOUTSTATUS,Not Defined" group.long 0x39138++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_CHINSTATUS" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_GATE,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_CTI_CHOUTSTATUS" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_ASICCTL,Not Defined" wgroup.long 0x39140++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_GATE" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_ITCHINACK,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_CTI_ASICCTL" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_ITTRIGINACK,Not Defined" wgroup.long 0x39EDC++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_ITCHINACK" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_ITCHOUT,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_CTI_ITTRIGINACK" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_ITTRIGOUT,Not Defined" rgroup.long 0x39EE4++0xF line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_ITCHOUT" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_ITCHOUTACK,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_CTI_ITTRIGOUT" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_ITTRIGOUTACK,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_CTI_ITCHOUTACK" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_CTI_ITCHIN,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_B_CTI_ITTRIGOUTACK" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_CTI_ITTRIGIN,Not Defined" group.long 0x39EF4++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_ITCHIN" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_ITCTRL,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_CTI_ITTRIGIN" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_CLAIM_TAG_SET,Not Defined" group.long 0x39F00++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_ITCTRL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_CLAIM_TAG_CLEAR,Not Defined" wgroup.long 0x39FA0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_CLAIM_TAG_SET" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_LOCK_ACCESS_REGISTER,Not Defined" rgroup.long 0x39FA4++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_CLAIM_TAG_CLEAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_LOCK_STATUS_REGISTER,Not Defined" rgroup.long 0x39FB0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_LOCK_ACCESS_REGISTER" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_AUTHENTICATION_STATUS,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_CTI_LOCK_STATUS_REGISTER" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_DEVICE_ID,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_CTI_AUTHENTICATION_STATUS" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_CTI_DEVICE_TYPE_IDENTIFIER,Not Defined" rgroup.long 0x39FC8++0x2F line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_DEVICE_ID" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID4,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_CTI_DEVICE_TYPE_IDENTIFIER" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID5,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_CTI_PERIPHERALID4" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID6,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_B_CTI_PERIPHERALID5" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID7,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_B_CTI_PERIPHERALID6" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID0,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_B_CTI_PERIPHERALID7" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID1,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS0_B_CTI_PERIPHERALID0" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID2,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS0_B_CTI_PERIPHERALID1" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_CTI_PERIPHERALID3,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS0_B_CTI_PERIPHERALID2" hexmask.long 0x20 0.--31. 1. "MSS_R5SS0_CTI_COMPONENT_ID0,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS0_B_CTI_PERIPHERALID3" hexmask.long 0x24 0.--31. 1. "MSS_R5SS0_CTI_COMPONENT_ID1,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS0_B_CTI_COMPONENT_ID0" hexmask.long 0x28 0.--31. 1. "MSS_R5SS0_CTI_COMPONENT_ID2,Not Defined" line.long 0x2C "DEBUGSS_MSS_R5SS0_B_CTI_COMPONENT_ID1" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS0_CTI_COMPONENT_ID3,Not Defined" group.long 0x39FF8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_COMPONENT_ID2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_CR,http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0014q/Chdfiagc.htmlhttp://infocenter.arm.com/help/topic/com.arm.doc.ihi0014q/I84249.html" rgroup.long 0x39FFC++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_CTI_COMPONENT_ID3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_CCR,Not Defined" group.long 0x3C000++0xB line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_CR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_TRIGGER,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_ETM_CCR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_ASICCTLR,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_ETM_TRIGGER" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_ETM_SR,Not Defined" rgroup.long 0x3C00C++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_ASICCTLR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_SCR,Not Defined" group.long 0x3C010++0xB3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_SR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_TSSCR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_ETM_SCR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_TECR2,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_ETM_TSSCR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_ETM_TEEVR,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_A_ETM_TECR2" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_ETM_TECR1,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_A_ETM_TEEVR" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_ETM_FFRR,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_A_ETM_TECR1" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_ETM_FFLR,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS0_A_ETM_FFRR" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_ETM_VDEVR,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS0_A_ETM_FFLR" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_ETM_VDCR1,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS0_A_ETM_VDEVR" hexmask.long 0x20 0.--31. 1. "MSS_R5SS0_ETM_VDCR2,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS0_A_ETM_VDCR1" hexmask.long 0x24 0.--31. 1. "MSS_R5SS0_ETM_VDCR3,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS0_A_ETM_VDCR2" hexmask.long 0x28 0.--31. 1. "MSS_R5SS0_ETM_ACVR1,Not Defined" line.long 0x2C "DEBUGSS_MSS_R5SS0_A_ETM_VDCR3" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS0_ETM_ACVR2,Not Defined" line.long 0x30 "DEBUGSS_MSS_R5SS0_A_ETM_ACVR1" hexmask.long 0x30 0.--31. 1. "MSS_R5SS0_ETM_ACVR3,Not Defined" line.long 0x34 "DEBUGSS_MSS_R5SS0_A_ETM_ACVR2" hexmask.long 0x34 0.--31. 1. "MSS_R5SS0_ETM_ACVR4,Not Defined" line.long 0x38 "DEBUGSS_MSS_R5SS0_A_ETM_ACVR3" hexmask.long 0x38 0.--31. 1. "MSS_R5SS0_ETM_ACVR5,Not Defined" line.long 0x3C "DEBUGSS_MSS_R5SS0_A_ETM_ACVR4" hexmask.long 0x3C 0.--31. 1. "MSS_R5SS0_ETM_ACVR6,Not Defined" line.long 0x40 "DEBUGSS_MSS_R5SS0_A_ETM_ACVR5" hexmask.long 0x40 0.--31. 1. "MSS_R5SS0_ETM_ACVR7,Not Defined" line.long 0x44 "DEBUGSS_MSS_R5SS0_A_ETM_ACVR6" hexmask.long 0x44 0.--31. 1. "MSS_R5SS0_ETM_ACVR8,Not Defined" line.long 0x48 "DEBUGSS_MSS_R5SS0_A_ETM_ACVR7" hexmask.long 0x48 0.--31. 1. "MSS_R5SS0_ETM_ACVR9,Not Defined" line.long 0x4C "DEBUGSS_MSS_R5SS0_A_ETM_ACVR8" hexmask.long 0x4C 0.--31. 1. "MSS_R5SS0_ETM_ACVR10,Not Defined" line.long 0x50 "DEBUGSS_MSS_R5SS0_A_ETM_ACVR9" hexmask.long 0x50 0.--31. 1. "MSS_R5SS0_ETM_ACVR11,Not Defined" line.long 0x54 "DEBUGSS_MSS_R5SS0_A_ETM_ACVR10" hexmask.long 0x54 0.--31. 1. "MSS_R5SS0_ETM_ACVR12,Not Defined" line.long 0x58 "DEBUGSS_MSS_R5SS0_A_ETM_ACVR11" hexmask.long 0x58 0.--31. 1. "MSS_R5SS0_ETM_ACVR13,Not Defined" line.long 0x5C "DEBUGSS_MSS_R5SS0_A_ETM_ACVR12" hexmask.long 0x5C 0.--31. 1. "MSS_R5SS0_ETM_ACVR14,Not Defined" line.long 0x60 "DEBUGSS_MSS_R5SS0_A_ETM_ACVR13" hexmask.long 0x60 0.--31. 1. "MSS_R5SS0_ETM_ACVR15,Not Defined" line.long 0x64 "DEBUGSS_MSS_R5SS0_A_ETM_ACVR14" hexmask.long 0x64 0.--31. 1. "MSS_R5SS0_ETM_ACVR16,Not Defined" line.long 0x68 "DEBUGSS_MSS_R5SS0_A_ETM_ACVR15" hexmask.long 0x68 0.--31. 1. "MSS_R5SS0_ETM_ACTR1,Not Defined" line.long 0x6C "DEBUGSS_MSS_R5SS0_A_ETM_ACVR16" hexmask.long 0x6C 0.--31. 1. "MSS_R5SS0_ETM_ACTR2,Not Defined" line.long 0x70 "DEBUGSS_MSS_R5SS0_A_ETM_ACTR1" hexmask.long 0x70 0.--31. 1. "MSS_R5SS0_ETM_ACTR3,Not Defined" line.long 0x74 "DEBUGSS_MSS_R5SS0_A_ETM_ACTR2" hexmask.long 0x74 0.--31. 1. "MSS_R5SS0_ETM_ACTR4,Not Defined" line.long 0x78 "DEBUGSS_MSS_R5SS0_A_ETM_ACTR3" hexmask.long 0x78 0.--31. 1. "MSS_R5SS0_ETM_ACTR5,Not Defined" line.long 0x7C "DEBUGSS_MSS_R5SS0_A_ETM_ACTR4" hexmask.long 0x7C 0.--31. 1. "MSS_R5SS0_ETM_ACTR6,Not Defined" line.long 0x80 "DEBUGSS_MSS_R5SS0_A_ETM_ACTR5" hexmask.long 0x80 0.--31. 1. "MSS_R5SS0_ETM_ACTR7,Not Defined" line.long 0x84 "DEBUGSS_MSS_R5SS0_A_ETM_ACTR6" hexmask.long 0x84 0.--31. 1. "MSS_R5SS0_ETM_ACTR8,Not Defined" line.long 0x88 "DEBUGSS_MSS_R5SS0_A_ETM_ACTR7" hexmask.long 0x88 0.--31. 1. "MSS_R5SS0_ETM_ACTR9,Not Defined" line.long 0x8C "DEBUGSS_MSS_R5SS0_A_ETM_ACTR8" hexmask.long 0x8C 0.--31. 1. "MSS_R5SS0_ETM_ACTR10,Not Defined" line.long 0x90 "DEBUGSS_MSS_R5SS0_A_ETM_ACTR9" hexmask.long 0x90 0.--31. 1. "MSS_R5SS0_ETM_ACTR11,Not Defined" line.long 0x94 "DEBUGSS_MSS_R5SS0_A_ETM_ACTR10" hexmask.long 0x94 0.--31. 1. "MSS_R5SS0_ETM_ACTR12,Not Defined" line.long 0x98 "DEBUGSS_MSS_R5SS0_A_ETM_ACTR11" hexmask.long 0x98 0.--31. 1. "MSS_R5SS0_ETM_ACTR13,Not Defined" line.long 0x9C "DEBUGSS_MSS_R5SS0_A_ETM_ACTR12" hexmask.long 0x9C 0.--31. 1. "MSS_R5SS0_ETM_ACTR14,Not Defined" line.long 0xA0 "DEBUGSS_MSS_R5SS0_A_ETM_ACTR13" hexmask.long 0xA0 0.--31. 1. "MSS_R5SS0_ETM_ACTR15,Not Defined" line.long 0xA4 "DEBUGSS_MSS_R5SS0_A_ETM_ACTR14" hexmask.long 0xA4 0.--31. 1. "MSS_R5SS0_ETM_ACTR16,Not Defined" line.long 0xA8 "DEBUGSS_MSS_R5SS0_A_ETM_ACTR15" hexmask.long 0xA8 0.--31. 1. "MSS_R5SS0_ETM_DCVR1,Not Defined" line.long 0xAC "DEBUGSS_MSS_R5SS0_A_ETM_ACTR16" hexmask.long 0xAC 0.--31. 1. "MSS_R5SS0_ETM_DCVR2,Not Defined" line.long 0xB0 "DEBUGSS_MSS_R5SS0_A_ETM_DCVR1" hexmask.long 0xB0 0.--31. 1. "MSS_R5SS0_ETM_DCVR3,Not Defined" group.long 0x3C0C8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DCVR2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCVR4,Not Defined" group.long 0x3C0D0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DCVR3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCVR5,Not Defined" group.long 0x3C0D8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DCVR4" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCVR6,Not Defined" group.long 0x3C0E0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DCVR5" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCVR7,Not Defined" group.long 0x3C0E8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DCVR6" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCVR8,Not Defined" group.long 0x3C0F0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DCVR7" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR1,Not Defined" group.long 0x3C0F8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DCVR8" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR2,Not Defined" group.long 0x3C100++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DCMR1" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR3,Not Defined" group.long 0x3C108++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DCMR2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR4,Not Defined" group.long 0x3C110++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DCMR3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR5,Not Defined" group.long 0x3C118++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DCMR4" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR6,Not Defined" group.long 0x3C120++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DCMR5" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR7,Not Defined" group.long 0x3C128++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DCMR6" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR8,Not Defined" group.long 0x3C130++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DCMR7" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDVR1,Not Defined" group.long 0x3C138++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DCMR8" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDVR2,Not Defined" group.long 0x3C140++0x57 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_CNTRLDVR1" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDVR3,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_ETM_CNTRLDVR2" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDVR4,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_ETM_CNTRLDVR3" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_ETM_CNTENR1,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_A_ETM_CNTRLDVR4" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_ETM_CNTENR2,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_A_ETM_CNTENR1" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_ETM_CNTENR3,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_A_ETM_CNTENR2" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_ETM_CNTENR4,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS0_A_ETM_CNTENR3" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDEVR1,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS0_A_ETM_CNTENR4" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDEVR2,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS0_A_ETM_CNTRLDEVR1" hexmask.long 0x20 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDEVR3,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS0_A_ETM_CNTRLDEVR2" hexmask.long 0x24 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDEVR4,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS0_A_ETM_CNTRLDEVR3" hexmask.long 0x28 0.--31. 1. "MSS_R5SS0_ETM_CNTVR1,Not Defined" line.long 0x2C "DEBUGSS_MSS_R5SS0_A_ETM_CNTRLDEVR4" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS0_ETM_CNTVR2,Not Defined" line.long 0x30 "DEBUGSS_MSS_R5SS0_A_ETM_CNTVR1" hexmask.long 0x30 0.--31. 1. "MSS_R5SS0_ETM_CNTVR3,Not Defined" line.long 0x34 "DEBUGSS_MSS_R5SS0_A_ETM_CNTVR2" hexmask.long 0x34 0.--31. 1. "MSS_R5SS0_ETM_CNTVR4,Not Defined" line.long 0x38 "DEBUGSS_MSS_R5SS0_A_ETM_CNTVR3" hexmask.long 0x38 0.--31. 1. "MSS_R5SS0_ETM_SQ12EVR,Not Defined" line.long 0x3C "DEBUGSS_MSS_R5SS0_A_ETM_CNTVR4" hexmask.long 0x3C 0.--31. 1. "MSS_R5SS0_ETM_SQ21EVR,Not Defined" line.long 0x40 "DEBUGSS_MSS_R5SS0_A_ETM_SQ12EVR" hexmask.long 0x40 0.--31. 1. "MSS_R5SS0_ETM_SQ23EVR,Not Defined" line.long 0x44 "DEBUGSS_MSS_R5SS0_A_ETM_SQ21EVR" hexmask.long 0x44 0.--31. 1. "MSS_R5SS0_ETM_SQ31EVR,Not Defined" line.long 0x48 "DEBUGSS_MSS_R5SS0_A_ETM_SQ23EVR" hexmask.long 0x48 0.--31. 1. "MSS_R5SS0_ETM_SQ32EVR,Not Defined" line.long 0x4C "DEBUGSS_MSS_R5SS0_A_ETM_SQ31EVR" hexmask.long 0x4C 0.--31. 1. "MSS_R5SS0_ETM_SQ13EVR,Not Defined" line.long 0x50 "DEBUGSS_MSS_R5SS0_A_ETM_SQ32EVR" hexmask.long 0x50 0.--31. 1. "MSS_R5SS0_ETM_SQR,Not Defined" line.long 0x54 "DEBUGSS_MSS_R5SS0_A_ETM_SQ13EVR" hexmask.long 0x54 0.--31. 1. "MSS_R5SS0_ETM_EXTOUTEVR1,Not Defined" group.long 0x3C19C++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_SQR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_EXTOUTEVR2,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_ETM_EXTOUTEVR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_EXTOUTEVR3,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_ETM_EXTOUTEVR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_ETM_EXTOUTEVR4,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_A_ETM_EXTOUTEVR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_ETM_CIDCVR1,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_A_ETM_EXTOUTEVR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_ETM_CIDCVR2,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_A_ETM_CIDCVR1" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_ETM_CIDCVR3,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS0_A_ETM_CIDCVR2" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_ETM_CIDCMR,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS0_A_ETM_CIDCVR3" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_ETM_SYNCFR,Not Defined" rgroup.long 0x3C1BC++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_CIDCMR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_IDR,Not Defined" rgroup.long 0x3C1E0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_SYNCFR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_CCER,Not Defined" group.long 0x3C1E4++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_IDR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_EXTINSELR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_ETM_CCER" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_TRACEIDR,Not Defined" rgroup.long 0x3C1EC++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_EXTINSELR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_PDSR,Not Defined" rgroup.long 0x3C200++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_TRACEIDR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_ITETMIF,Not Defined" wgroup.long 0x3C314++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_PDSR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_ITMISCOUT,Not Defined" rgroup.long 0x3CED8++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_ITETMIF" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_ITMISCIN,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_ETM_ITMISCOUT" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_ITTRIGGERACK,Not Defined" wgroup.long 0x3CEE0++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_ITMISCIN" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_ITTRIGGERREQ,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_ETM_ITTRIGGERACK" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_ITATBDATA0,Not Defined" rgroup.long 0x3CEE8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_ITTRIGGERREQ" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_ITATBCTR2,Not Defined" wgroup.long 0x3CEEC++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_ITATBDATA0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_ITATBCTR1,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_ETM_ITATBCTR2" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_ITATBCTR0,Not Defined" group.long 0x3CEF4++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_ITATBCTR1" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_ITCTRL,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_ETM_ITATBCTR0" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_CLAIMSET,Not Defined" group.long 0x3CF00++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_ITCTRL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_CLAIMCLR,Not Defined" wgroup.long 0x3CFA0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_CLAIMSET" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_LAR,Not Defined" rgroup.long 0x3CFA4++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_CLAIMCLR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_LSR,Not Defined" rgroup.long 0x3CFB0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_LAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_AUTHSTATUS,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_ETM_LSR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_DEVID,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_ETM_AUTHSTATUS" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_ETM_DEVTYPE,Not Defined" rgroup.long 0x3CFC8++0x2F line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_DEVID" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_PIDR4,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_A_ETM_DEVTYPE" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_PIDR5,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_A_ETM_PIDR4" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_ETM_PIDR6,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_A_ETM_PIDR5" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_ETM_PIDR7,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_A_ETM_PIDR6" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_ETM_PIDR0,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_A_ETM_PIDR7" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_ETM_PIDR1,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS0_A_ETM_PIDR0" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_ETM_PIDR2,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS0_A_ETM_PIDR1" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_ETM_PIDR3,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS0_A_ETM_PIDR2" hexmask.long 0x20 0.--31. 1. "MSS_R5SS0_ETM_CIDR0,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS0_A_ETM_PIDR3" hexmask.long 0x24 0.--31. 1. "MSS_R5SS0_ETM_CIDR1,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS0_A_ETM_CIDR0" hexmask.long 0x28 0.--31. 1. "MSS_R5SS0_ETM_CIDR2,Not Defined" line.long 0x2C "DEBUGSS_MSS_R5SS0_A_ETM_CIDR1" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS0_ETM_CIDR3,Not Defined" group.long 0x3CFF8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_CIDR2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_CR,http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0014q/Chdfiagc.htmlhttp://infocenter.arm.com/help/topic/com.arm.doc.ihi0014q/I84249.html" rgroup.long 0x3CFFC++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_A_ETM_CIDR3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_CCR,Not Defined" group.long 0x3D000++0xB line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_CR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_TRIGGER,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_ETM_CCR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_ASICCTLR,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_ETM_TRIGGER" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_ETM_SR,Not Defined" rgroup.long 0x3D00C++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_ASICCTLR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_SCR,Not Defined" group.long 0x3D010++0xB3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_SR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_TSSCR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_ETM_SCR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_TECR2,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_ETM_TSSCR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_ETM_TEEVR,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_B_ETM_TECR2" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_ETM_TECR1,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_B_ETM_TEEVR" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_ETM_FFRR,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_B_ETM_TECR1" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_ETM_FFLR,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS0_B_ETM_FFRR" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_ETM_VDEVR,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS0_B_ETM_FFLR" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_ETM_VDCR1,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS0_B_ETM_VDEVR" hexmask.long 0x20 0.--31. 1. "MSS_R5SS0_ETM_VDCR2,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS0_B_ETM_VDCR1" hexmask.long 0x24 0.--31. 1. "MSS_R5SS0_ETM_VDCR3,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS0_B_ETM_VDCR2" hexmask.long 0x28 0.--31. 1. "MSS_R5SS0_ETM_ACVR1,Not Defined" line.long 0x2C "DEBUGSS_MSS_R5SS0_B_ETM_VDCR3" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS0_ETM_ACVR2,Not Defined" line.long 0x30 "DEBUGSS_MSS_R5SS0_B_ETM_ACVR1" hexmask.long 0x30 0.--31. 1. "MSS_R5SS0_ETM_ACVR3,Not Defined" line.long 0x34 "DEBUGSS_MSS_R5SS0_B_ETM_ACVR2" hexmask.long 0x34 0.--31. 1. "MSS_R5SS0_ETM_ACVR4,Not Defined" line.long 0x38 "DEBUGSS_MSS_R5SS0_B_ETM_ACVR3" hexmask.long 0x38 0.--31. 1. "MSS_R5SS0_ETM_ACVR5,Not Defined" line.long 0x3C "DEBUGSS_MSS_R5SS0_B_ETM_ACVR4" hexmask.long 0x3C 0.--31. 1. "MSS_R5SS0_ETM_ACVR6,Not Defined" line.long 0x40 "DEBUGSS_MSS_R5SS0_B_ETM_ACVR5" hexmask.long 0x40 0.--31. 1. "MSS_R5SS0_ETM_ACVR7,Not Defined" line.long 0x44 "DEBUGSS_MSS_R5SS0_B_ETM_ACVR6" hexmask.long 0x44 0.--31. 1. "MSS_R5SS0_ETM_ACVR8,Not Defined" line.long 0x48 "DEBUGSS_MSS_R5SS0_B_ETM_ACVR7" hexmask.long 0x48 0.--31. 1. "MSS_R5SS0_ETM_ACVR9,Not Defined" line.long 0x4C "DEBUGSS_MSS_R5SS0_B_ETM_ACVR8" hexmask.long 0x4C 0.--31. 1. "MSS_R5SS0_ETM_ACVR10,Not Defined" line.long 0x50 "DEBUGSS_MSS_R5SS0_B_ETM_ACVR9" hexmask.long 0x50 0.--31. 1. "MSS_R5SS0_ETM_ACVR11,Not Defined" line.long 0x54 "DEBUGSS_MSS_R5SS0_B_ETM_ACVR10" hexmask.long 0x54 0.--31. 1. "MSS_R5SS0_ETM_ACVR12,Not Defined" line.long 0x58 "DEBUGSS_MSS_R5SS0_B_ETM_ACVR11" hexmask.long 0x58 0.--31. 1. "MSS_R5SS0_ETM_ACVR13,Not Defined" line.long 0x5C "DEBUGSS_MSS_R5SS0_B_ETM_ACVR12" hexmask.long 0x5C 0.--31. 1. "MSS_R5SS0_ETM_ACVR14,Not Defined" line.long 0x60 "DEBUGSS_MSS_R5SS0_B_ETM_ACVR13" hexmask.long 0x60 0.--31. 1. "MSS_R5SS0_ETM_ACVR15,Not Defined" line.long 0x64 "DEBUGSS_MSS_R5SS0_B_ETM_ACVR14" hexmask.long 0x64 0.--31. 1. "MSS_R5SS0_ETM_ACVR16,Not Defined" line.long 0x68 "DEBUGSS_MSS_R5SS0_B_ETM_ACVR15" hexmask.long 0x68 0.--31. 1. "MSS_R5SS0_ETM_ACTR1,Not Defined" line.long 0x6C "DEBUGSS_MSS_R5SS0_B_ETM_ACVR16" hexmask.long 0x6C 0.--31. 1. "MSS_R5SS0_ETM_ACTR2,Not Defined" line.long 0x70 "DEBUGSS_MSS_R5SS0_B_ETM_ACTR1" hexmask.long 0x70 0.--31. 1. "MSS_R5SS0_ETM_ACTR3,Not Defined" line.long 0x74 "DEBUGSS_MSS_R5SS0_B_ETM_ACTR2" hexmask.long 0x74 0.--31. 1. "MSS_R5SS0_ETM_ACTR4,Not Defined" line.long 0x78 "DEBUGSS_MSS_R5SS0_B_ETM_ACTR3" hexmask.long 0x78 0.--31. 1. "MSS_R5SS0_ETM_ACTR5,Not Defined" line.long 0x7C "DEBUGSS_MSS_R5SS0_B_ETM_ACTR4" hexmask.long 0x7C 0.--31. 1. "MSS_R5SS0_ETM_ACTR6,Not Defined" line.long 0x80 "DEBUGSS_MSS_R5SS0_B_ETM_ACTR5" hexmask.long 0x80 0.--31. 1. "MSS_R5SS0_ETM_ACTR7,Not Defined" line.long 0x84 "DEBUGSS_MSS_R5SS0_B_ETM_ACTR6" hexmask.long 0x84 0.--31. 1. "MSS_R5SS0_ETM_ACTR8,Not Defined" line.long 0x88 "DEBUGSS_MSS_R5SS0_B_ETM_ACTR7" hexmask.long 0x88 0.--31. 1. "MSS_R5SS0_ETM_ACTR9,Not Defined" line.long 0x8C "DEBUGSS_MSS_R5SS0_B_ETM_ACTR8" hexmask.long 0x8C 0.--31. 1. "MSS_R5SS0_ETM_ACTR10,Not Defined" line.long 0x90 "DEBUGSS_MSS_R5SS0_B_ETM_ACTR9" hexmask.long 0x90 0.--31. 1. "MSS_R5SS0_ETM_ACTR11,Not Defined" line.long 0x94 "DEBUGSS_MSS_R5SS0_B_ETM_ACTR10" hexmask.long 0x94 0.--31. 1. "MSS_R5SS0_ETM_ACTR12,Not Defined" line.long 0x98 "DEBUGSS_MSS_R5SS0_B_ETM_ACTR11" hexmask.long 0x98 0.--31. 1. "MSS_R5SS0_ETM_ACTR13,Not Defined" line.long 0x9C "DEBUGSS_MSS_R5SS0_B_ETM_ACTR12" hexmask.long 0x9C 0.--31. 1. "MSS_R5SS0_ETM_ACTR14,Not Defined" line.long 0xA0 "DEBUGSS_MSS_R5SS0_B_ETM_ACTR13" hexmask.long 0xA0 0.--31. 1. "MSS_R5SS0_ETM_ACTR15,Not Defined" line.long 0xA4 "DEBUGSS_MSS_R5SS0_B_ETM_ACTR14" hexmask.long 0xA4 0.--31. 1. "MSS_R5SS0_ETM_ACTR16,Not Defined" line.long 0xA8 "DEBUGSS_MSS_R5SS0_B_ETM_ACTR15" hexmask.long 0xA8 0.--31. 1. "MSS_R5SS0_ETM_DCVR1,Not Defined" line.long 0xAC "DEBUGSS_MSS_R5SS0_B_ETM_ACTR16" hexmask.long 0xAC 0.--31. 1. "MSS_R5SS0_ETM_DCVR2,Not Defined" line.long 0xB0 "DEBUGSS_MSS_R5SS0_B_ETM_DCVR1" hexmask.long 0xB0 0.--31. 1. "MSS_R5SS0_ETM_DCVR3,Not Defined" group.long 0x3D0C8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DCVR2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCVR4,Not Defined" group.long 0x3D0D0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DCVR3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCVR5,Not Defined" group.long 0x3D0D8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DCVR4" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCVR6,Not Defined" group.long 0x3D0E0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DCVR5" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCVR7,Not Defined" group.long 0x3D0E8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DCVR6" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCVR8,Not Defined" group.long 0x3D0F0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DCVR7" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR1,Not Defined" group.long 0x3D0F8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DCVR8" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR2,Not Defined" group.long 0x3D100++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DCMR1" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR3,Not Defined" group.long 0x3D108++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DCMR2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR4,Not Defined" group.long 0x3D110++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DCMR3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR5,Not Defined" group.long 0x3D118++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DCMR4" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR6,Not Defined" group.long 0x3D120++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DCMR5" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR7,Not Defined" group.long 0x3D128++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DCMR6" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_DCMR8,Not Defined" group.long 0x3D130++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DCMR7" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDVR1,Not Defined" group.long 0x3D138++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DCMR8" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDVR2,Not Defined" group.long 0x3D140++0x57 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_CNTRLDVR1" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDVR3,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_ETM_CNTRLDVR2" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDVR4,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_ETM_CNTRLDVR3" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_ETM_CNTENR1,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_B_ETM_CNTRLDVR4" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_ETM_CNTENR2,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_B_ETM_CNTENR1" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_ETM_CNTENR3,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_B_ETM_CNTENR2" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_ETM_CNTENR4,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS0_B_ETM_CNTENR3" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDEVR1,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS0_B_ETM_CNTENR4" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDEVR2,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS0_B_ETM_CNTRLDEVR1" hexmask.long 0x20 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDEVR3,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS0_B_ETM_CNTRLDEVR2" hexmask.long 0x24 0.--31. 1. "MSS_R5SS0_ETM_CNTRLDEVR4,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS0_B_ETM_CNTRLDEVR3" hexmask.long 0x28 0.--31. 1. "MSS_R5SS0_ETM_CNTVR1,Not Defined" line.long 0x2C "DEBUGSS_MSS_R5SS0_B_ETM_CNTRLDEVR4" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS0_ETM_CNTVR2,Not Defined" line.long 0x30 "DEBUGSS_MSS_R5SS0_B_ETM_CNTVR1" hexmask.long 0x30 0.--31. 1. "MSS_R5SS0_ETM_CNTVR3,Not Defined" line.long 0x34 "DEBUGSS_MSS_R5SS0_B_ETM_CNTVR2" hexmask.long 0x34 0.--31. 1. "MSS_R5SS0_ETM_CNTVR4,Not Defined" line.long 0x38 "DEBUGSS_MSS_R5SS0_B_ETM_CNTVR3" hexmask.long 0x38 0.--31. 1. "MSS_R5SS0_ETM_SQ12EVR,Not Defined" line.long 0x3C "DEBUGSS_MSS_R5SS0_B_ETM_CNTVR4" hexmask.long 0x3C 0.--31. 1. "MSS_R5SS0_ETM_SQ21EVR,Not Defined" line.long 0x40 "DEBUGSS_MSS_R5SS0_B_ETM_SQ12EVR" hexmask.long 0x40 0.--31. 1. "MSS_R5SS0_ETM_SQ23EVR,Not Defined" line.long 0x44 "DEBUGSS_MSS_R5SS0_B_ETM_SQ21EVR" hexmask.long 0x44 0.--31. 1. "MSS_R5SS0_ETM_SQ31EVR,Not Defined" line.long 0x48 "DEBUGSS_MSS_R5SS0_B_ETM_SQ23EVR" hexmask.long 0x48 0.--31. 1. "MSS_R5SS0_ETM_SQ32EVR,Not Defined" line.long 0x4C "DEBUGSS_MSS_R5SS0_B_ETM_SQ31EVR" hexmask.long 0x4C 0.--31. 1. "MSS_R5SS0_ETM_SQ13EVR,Not Defined" line.long 0x50 "DEBUGSS_MSS_R5SS0_B_ETM_SQ32EVR" hexmask.long 0x50 0.--31. 1. "MSS_R5SS0_ETM_SQR,Not Defined" line.long 0x54 "DEBUGSS_MSS_R5SS0_B_ETM_SQ13EVR" hexmask.long 0x54 0.--31. 1. "MSS_R5SS0_ETM_EXTOUTEVR1,Not Defined" group.long 0x3D19C++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_SQR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_EXTOUTEVR2,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_ETM_EXTOUTEVR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_EXTOUTEVR3,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_ETM_EXTOUTEVR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_ETM_EXTOUTEVR4,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_B_ETM_EXTOUTEVR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_ETM_CIDCVR1,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_B_ETM_EXTOUTEVR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_ETM_CIDCVR2,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_B_ETM_CIDCVR1" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_ETM_CIDCVR3,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS0_B_ETM_CIDCVR2" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_ETM_CIDCMR,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS0_B_ETM_CIDCVR3" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_ETM_SYNCFR,Not Defined" rgroup.long 0x3D1BC++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_CIDCMR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_IDR,Not Defined" rgroup.long 0x3D1E0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_SYNCFR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_CCER,Not Defined" group.long 0x3D1E4++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_IDR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_EXTINSELR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_ETM_CCER" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_TRACEIDR,Not Defined" rgroup.long 0x3D1EC++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_EXTINSELR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_PDSR,Not Defined" rgroup.long 0x3D200++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_TRACEIDR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_ITETMIF,Not Defined" wgroup.long 0x3D314++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_PDSR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_ITMISCOUT,Not Defined" rgroup.long 0x3DED8++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_ITETMIF" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_ITMISCIN,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_ETM_ITMISCOUT" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_ITTRIGGERACK,Not Defined" wgroup.long 0x3DEE0++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_ITMISCIN" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_ITTRIGGERREQ,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_ETM_ITTRIGGERACK" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_ITATBDATA0,Not Defined" rgroup.long 0x3DEE8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_ITTRIGGERREQ" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_ITATBCTR2,Not Defined" wgroup.long 0x3DEEC++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_ITATBDATA0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_ITATBCTR1,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_ETM_ITATBCTR2" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_ITATBCTR0,Not Defined" group.long 0x3DEF4++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_ITATBCTR1" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_ITCTRL,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_ETM_ITATBCTR0" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_CLAIMSET,Not Defined" group.long 0x3DF00++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_ITCTRL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_CLAIMCLR,Not Defined" wgroup.long 0x3DFA0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_CLAIMSET" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_LAR,Not Defined" rgroup.long 0x3DFA4++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_CLAIMCLR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_LSR,Not Defined" rgroup.long 0x3DFB0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_LAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_AUTHSTATUS,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_ETM_LSR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_DEVID,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_ETM_AUTHSTATUS" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_ETM_DEVTYPE,Not Defined" rgroup.long 0x3DFC8++0x2F line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_DEVID" hexmask.long 0x0 0.--31. 1. "MSS_R5SS0_ETM_PIDR4,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_ETM_DEVTYPE" hexmask.long 0x4 0.--31. 1. "MSS_R5SS0_ETM_PIDR5,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS0_B_ETM_PIDR4" hexmask.long 0x8 0.--31. 1. "MSS_R5SS0_ETM_PIDR6,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS0_B_ETM_PIDR5" hexmask.long 0xC 0.--31. 1. "MSS_R5SS0_ETM_PIDR7,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS0_B_ETM_PIDR6" hexmask.long 0x10 0.--31. 1. "MSS_R5SS0_ETM_PIDR0,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS0_B_ETM_PIDR7" hexmask.long 0x14 0.--31. 1. "MSS_R5SS0_ETM_PIDR1,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS0_B_ETM_PIDR0" hexmask.long 0x18 0.--31. 1. "MSS_R5SS0_ETM_PIDR2,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS0_B_ETM_PIDR1" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS0_ETM_PIDR3,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS0_B_ETM_PIDR2" hexmask.long 0x20 0.--31. 1. "MSS_R5SS0_ETM_CIDR0,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS0_B_ETM_PIDR3" hexmask.long 0x24 0.--31. 1. "MSS_R5SS0_ETM_CIDR1,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS0_B_ETM_CIDR0" hexmask.long 0x28 0.--31. 1. "MSS_R5SS0_ETM_CIDR2,Not Defined" line.long 0x2C "DEBUGSS_MSS_R5SS0_B_ETM_CIDR1" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS0_ETM_CIDR3,Not Defined" group.long 0x3DFF8++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS0_B_ETM_CIDR2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGDIDR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0363e/Cegejeeb.htmlDebug Identification Register" line.long 0x4 "DEBUGSS_MSS_R5SS0_B_ETM_CIDR3" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGWFAR,Watchpoint Fault Address Register" group.long 0x40000++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_ROM" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGVCR,Vector Catch Register" group.long 0x50000++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_DBGDIDR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGECR,Not Implemented" group.long 0x50018++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_DBGWFAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGDSCCR,Debug State Cache Control Register" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_DBGVCR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGDTRRX,Host to Target Data Transfer Register" group.long 0x50024++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_DBGECR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGITR,Instruction Transfer Register" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_DBGDSCCR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGDSCR,Debug Status and Control Register" group.long 0x50080++0x13 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_DBGDTRRX" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGDTRTX,Target to Host Data Transfer Register" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_DBGITR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGDRCR,Debug Run Control Register" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_APB_DBGDSCR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_DBGBVR0,Break Point Value Register 0" line.long 0xC "DEBUGSS_MSS_R5SS1_A_APB_DBGDTRTX" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_APB_DBGBVR1,Break Point Value Register 1" line.long 0x10 "DEBUGSS_MSS_R5SS1_A_APB_DBGDRCR" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_APB_DBGBVR2,Break Point Value Register 2" group.long 0x50100++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_DBGBVR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGBVR3,Break Point Value Register 3" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_DBGBVR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGBVR4,Break Point Value Register 4" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_APB_DBGBVR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_DBGBVR5,Break Point Value Register 5" line.long 0xC "DEBUGSS_MSS_R5SS1_A_APB_DBGBVR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_APB_DBGBVR6,Break Point Value Register 6" line.long 0x10 "DEBUGSS_MSS_R5SS1_A_APB_DBGBVR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_APB_DBGBVR7,Break Point Value Register 7" line.long 0x14 "DEBUGSS_MSS_R5SS1_A_APB_DBGBVR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_APB_DBGBCR0,Break Point Control Register 0" line.long 0x18 "DEBUGSS_MSS_R5SS1_A_APB_DBGBVR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_APB_DBGBCR1,Break Point Control Register 1" line.long 0x1C "DEBUGSS_MSS_R5SS1_A_APB_DBGBVR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_APB_DBGBCR2,Break Point Control Register 2" group.long 0x50140++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_DBGBCR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGBCR3,Break Point Control Register 3" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_DBGBCR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGBCR4,Break Point Control Register 4" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_APB_DBGBCR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_DBGBCR5,Break Point Control Register 5" line.long 0xC "DEBUGSS_MSS_R5SS1_A_APB_DBGBCR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_APB_DBGBCR6,Break Point Control Register 6" line.long 0x10 "DEBUGSS_MSS_R5SS1_A_APB_DBGBCR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_APB_DBGBCR7,Break Point Control Register 7" line.long 0x14 "DEBUGSS_MSS_R5SS1_A_APB_DBGBCR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_APB_DBGWVR0,Watch Point Value Register 0" line.long 0x18 "DEBUGSS_MSS_R5SS1_A_APB_DBGBCR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_APB_DBGWVR1,Watch Point Value Register 1" line.long 0x1C "DEBUGSS_MSS_R5SS1_A_APB_DBGBCR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_APB_DBGWVR2,Watch Point Value Register 2" group.long 0x50180++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_DBGWVR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGWVR3,Watch Point Value Register 3" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_DBGWVR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGWVR4,Watch Point Value Register 4" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_APB_DBGWVR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_DBGWVR5,Watch Point Value Register 5" line.long 0xC "DEBUGSS_MSS_R5SS1_A_APB_DBGWVR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_APB_DBGWVR6,Watch Point Value Register 6" line.long 0x10 "DEBUGSS_MSS_R5SS1_A_APB_DBGWVR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_APB_DBGWVR7,Watch Point Value Register 7" line.long 0x14 "DEBUGSS_MSS_R5SS1_A_APB_DBGWVR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_APB_DBGWCR0,Watch Point Control Register 0" line.long 0x18 "DEBUGSS_MSS_R5SS1_A_APB_DBGWVR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_APB_DBGWCR1,Watch Point Control Register 1" line.long 0x1C "DEBUGSS_MSS_R5SS1_A_APB_DBGWVR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_APB_DBGWCR2,Watch Point Control Register 2" group.long 0x501C0++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_DBGWCR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGWCR3,Watch Point Control Register 3" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_DBGWCR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGWCR4,Watch Point Control Register 4" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_APB_DBGWCR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_DBGWCR5,Watch Point Control Register 5" line.long 0xC "DEBUGSS_MSS_R5SS1_A_APB_DBGWCR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_APB_DBGWCR6,Watch Point Control Register 6" line.long 0x10 "DEBUGSS_MSS_R5SS1_A_APB_DBGWCR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_APB_DBGWCR7,Watch Point Control Register 7" line.long 0x14 "DEBUGSS_MSS_R5SS1_A_APB_DBGWCR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_APB_DBGOSLAR,Not Implemented" line.long 0x18 "DEBUGSS_MSS_R5SS1_A_APB_DBGWCR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_APB_DBGOSLSR,Operating System Lock Status Register" line.long 0x1C "DEBUGSS_MSS_R5SS1_A_APB_DBGWCR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_APB_DBGOSSRR,Not Implemented" group.long 0x50300++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_DBGOSLAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGPRCR,Device Power Down and Reset Control Regsiter" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_DBGOSLSR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGPRSR,Device Power Down and Reset Status Register" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_APB_DBGOSSRR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_PROCID_MIDR,Main ID Register" group.long 0x50310++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_DBGPRCR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_PROCID_CTR,Cache Type Register" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_DBGPRSR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_PROCID_TCMTR,TCM Type Register" group.long 0x50D00++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_MIDR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_PROCID_MPUIR,MPU Type Register" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_CTR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_PROCID_MPIDR,Multiprocessor Affinity Register" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_TCMTR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_PROCID_PFR0,Processor Feature Register 0" group.long 0x50D10++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_MPUIR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_PROCID_PFR1,Processor Feature Register 1" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_MPIDR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_PROCID_DFR0,Debug Feature Register 0" group.long 0x50D20++0x37 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_PFR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_PROCID_AFR0,Auxiliary Feature Register 0" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_PFR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_PROCID_MMFR0,Processor Feature Register 0" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_DFR0" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_PROCID_MMFR1,Memory Model Feature Register 1" line.long 0xC "DEBUGSS_MSS_R5SS1_A_APB_PROCID_AFR0" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_APB_PROCID_MMFR2,Memory Model Feature Register 2" line.long 0x10 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_MMFR0" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_APB_PROCID_MMFR3,Memory Model Feature Register 3" line.long 0x14 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_MMFR1" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_APB_PROCID_ISAR0,ISA Feature Register 0" line.long 0x18 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_MMFR2" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_APB_PROCID_ISAR1,ISA Feature Register 1" line.long 0x1C "DEBUGSS_MSS_R5SS1_A_APB_PROCID_MMFR3" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_APB_PROCID_ISAR2,ISA Feature Register 2" line.long 0x20 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_ISAR0" hexmask.long 0x20 0.--31. 1. "MSS_R5SS1_APB_PROCID_ISAR3,ISA Feature Register 3" line.long 0x24 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_ISAR1" hexmask.long 0x24 0.--31. 1. "MSS_R5SS1_APB_PROCID_ISAR4,ISA Feature Register 4" line.long 0x28 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_ISAR2" hexmask.long 0x28 0.--31. 1. "MSS_R5SS1_APB_PROCID_ISAR5,ISA Feature Register 5" line.long 0x2C "DEBUGSS_MSS_R5SS1_A_APB_PROCID_ISAR3" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS1_APB_MR_ITCTRL,Integration Mode Control Registers" line.long 0x30 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_ISAR4" hexmask.long 0x30 0.--31. 1. "MSS_R5SS1_APB_MR_CLAIMSET,Claim Tag Set Register" line.long 0x34 "DEBUGSS_MSS_R5SS1_A_APB_PROCID_ISAR5" hexmask.long 0x34 0.--31. 1. "MSS_R5SS1_APB_MR_CLAIMCLR,Claim Tag Clear Register" group.long 0x50F00++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_MR_ITCTRL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_MR_LOCKACCESS,Lock Access Register" group.long 0x50FA0++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_MR_CLAIMSET" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_MR_LOCKSTATUS,Lock Status Register" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_MR_CLAIMCLR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_MR_AUTHSTATUS,Authentication Status Register" group.long 0x50FB0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_MR_LOCKACCESS" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_MR_DEVID,Device Identifier" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_MR_LOCKSTATUS" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_MR_DEVTYPE,Device Type Register" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_APB_MR_AUTHSTATUS" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_PERIP_ID4,Not Defined" group.long 0x50FC8++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_MR_DEVID" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_PERIP_ID0,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_MR_DEVTYPE" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_PERIP_ID1,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_APB_PERIP_ID4" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_PERIP_ID2,Not Defined" group.long 0x50FE0++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS1_A_APB_PERIP_ID0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_PERIP_ID3,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_APB_PERIP_ID1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_COMP_ID0,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_APB_PERIP_ID2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_COMP_ID1,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_A_APB_PERIP_ID3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_APB_COMP_ID2,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_A_APB_COMP_ID0" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_APB_COMP_ID3,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS1_A_APB_COMP_ID1" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_APB_DBGDIDR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0363e/Cegejeeb.htmlDebug Identification Register" line.long 0x18 "DEBUGSS_MSS_R5SS1_A_APB_COMP_ID2" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_APB_DBGWFAR,Watchpoint Fault Address Register" line.long 0x1C "DEBUGSS_MSS_R5SS1_A_APB_COMP_ID3" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_APB_DBGVCR,Vector Catch Register" group.long 0x52000++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_DBGDIDR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGECR,Not Implemented" group.long 0x52018++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_DBGWFAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGDSCCR,Debug State Cache Control Register" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_DBGVCR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGDTRRX,Host to Target Data Transfer Register" group.long 0x52024++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_DBGECR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGITR,Instruction Transfer Register" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_DBGDSCCR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGDSCR,Debug Status and Control Register" group.long 0x52080++0x13 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_DBGDTRRX" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGDTRTX,Target to Host Data Transfer Register" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_DBGITR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGDRCR,Debug Run Control Register" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_APB_DBGDSCR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_DBGBVR0,Break Point Value Register 0" line.long 0xC "DEBUGSS_MSS_R5SS1_B_APB_DBGDTRTX" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_APB_DBGBVR1,Break Point Value Register 1" line.long 0x10 "DEBUGSS_MSS_R5SS1_B_APB_DBGDRCR" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_APB_DBGBVR2,Break Point Value Register 2" group.long 0x52100++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_DBGBVR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGBVR3,Break Point Value Register 3" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_DBGBVR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGBVR4,Break Point Value Register 4" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_APB_DBGBVR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_DBGBVR5,Break Point Value Register 5" line.long 0xC "DEBUGSS_MSS_R5SS1_B_APB_DBGBVR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_APB_DBGBVR6,Break Point Value Register 6" line.long 0x10 "DEBUGSS_MSS_R5SS1_B_APB_DBGBVR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_APB_DBGBVR7,Break Point Value Register 7" line.long 0x14 "DEBUGSS_MSS_R5SS1_B_APB_DBGBVR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_APB_DBGBCR0,Break Point Control Register 0" line.long 0x18 "DEBUGSS_MSS_R5SS1_B_APB_DBGBVR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_APB_DBGBCR1,Break Point Control Register 1" line.long 0x1C "DEBUGSS_MSS_R5SS1_B_APB_DBGBVR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_APB_DBGBCR2,Break Point Control Register 2" group.long 0x52140++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_DBGBCR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGBCR3,Break Point Control Register 3" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_DBGBCR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGBCR4,Break Point Control Register 4" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_APB_DBGBCR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_DBGBCR5,Break Point Control Register 5" line.long 0xC "DEBUGSS_MSS_R5SS1_B_APB_DBGBCR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_APB_DBGBCR6,Break Point Control Register 6" line.long 0x10 "DEBUGSS_MSS_R5SS1_B_APB_DBGBCR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_APB_DBGBCR7,Break Point Control Register 7" line.long 0x14 "DEBUGSS_MSS_R5SS1_B_APB_DBGBCR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_APB_DBGWVR0,Watch Point Value Register 0" line.long 0x18 "DEBUGSS_MSS_R5SS1_B_APB_DBGBCR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_APB_DBGWVR1,Watch Point Value Register 1" line.long 0x1C "DEBUGSS_MSS_R5SS1_B_APB_DBGBCR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_APB_DBGWVR2,Watch Point Value Register 2" group.long 0x52180++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_DBGWVR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGWVR3,Watch Point Value Register 3" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_DBGWVR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGWVR4,Watch Point Value Register 4" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_APB_DBGWVR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_DBGWVR5,Watch Point Value Register 5" line.long 0xC "DEBUGSS_MSS_R5SS1_B_APB_DBGWVR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_APB_DBGWVR6,Watch Point Value Register 6" line.long 0x10 "DEBUGSS_MSS_R5SS1_B_APB_DBGWVR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_APB_DBGWVR7,Watch Point Value Register 7" line.long 0x14 "DEBUGSS_MSS_R5SS1_B_APB_DBGWVR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_APB_DBGWCR0,Watch Point Control Register 0" line.long 0x18 "DEBUGSS_MSS_R5SS1_B_APB_DBGWVR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_APB_DBGWCR1,Watch Point Control Register 1" line.long 0x1C "DEBUGSS_MSS_R5SS1_B_APB_DBGWVR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_APB_DBGWCR2,Watch Point Control Register 2" group.long 0x521C0++0x1F line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_DBGWCR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGWCR3,Watch Point Control Register 3" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_DBGWCR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGWCR4,Watch Point Control Register 4" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_APB_DBGWCR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_DBGWCR5,Watch Point Control Register 5" line.long 0xC "DEBUGSS_MSS_R5SS1_B_APB_DBGWCR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_APB_DBGWCR6,Watch Point Control Register 6" line.long 0x10 "DEBUGSS_MSS_R5SS1_B_APB_DBGWCR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_APB_DBGWCR7,Watch Point Control Register 7" line.long 0x14 "DEBUGSS_MSS_R5SS1_B_APB_DBGWCR5" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_APB_DBGOSLAR,Not Implemented" line.long 0x18 "DEBUGSS_MSS_R5SS1_B_APB_DBGWCR6" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_APB_DBGOSLSR,Operating System Lock Status Register" line.long 0x1C "DEBUGSS_MSS_R5SS1_B_APB_DBGWCR7" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_APB_DBGOSSRR,Not Implemented" group.long 0x52300++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_DBGOSLAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_DBGPRCR,Device Power Down and Reset Control Regsiter" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_DBGOSLSR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_DBGPRSR,Device Power Down and Reset Status Register" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_APB_DBGOSSRR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_PROCID_MIDR,Main ID Register" group.long 0x52310++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_DBGPRCR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_PROCID_CTR,Cache Type Register" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_DBGPRSR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_PROCID_TCMTR,TCM Type Register" group.long 0x52D00++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_MIDR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_PROCID_MPUIR,MPU Type Register" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_CTR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_PROCID_MPIDR,Multiprocessor Affinity Register" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_TCMTR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_PROCID_PFR0,Processor Feature Register 0" group.long 0x52D10++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_MPUIR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_PROCID_PFR1,Processor Feature Register 1" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_MPIDR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_PROCID_DFR0,Debug Feature Register 0" group.long 0x52D20++0x37 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_PFR0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_PROCID_AFR0,Auxiliary Feature Register 0" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_PFR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_PROCID_MMFR0,Processor Feature Register 0" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_DFR0" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_PROCID_MMFR1,Memory Model Feature Register 1" line.long 0xC "DEBUGSS_MSS_R5SS1_B_APB_PROCID_AFR0" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_APB_PROCID_MMFR2,Memory Model Feature Register 2" line.long 0x10 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_MMFR0" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_APB_PROCID_MMFR3,Memory Model Feature Register 3" line.long 0x14 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_MMFR1" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_APB_PROCID_ISAR0,ISA Feature Register 0" line.long 0x18 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_MMFR2" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_APB_PROCID_ISAR1,ISA Feature Register 1" line.long 0x1C "DEBUGSS_MSS_R5SS1_B_APB_PROCID_MMFR3" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_APB_PROCID_ISAR2,ISA Feature Register 2" line.long 0x20 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_ISAR0" hexmask.long 0x20 0.--31. 1. "MSS_R5SS1_APB_PROCID_ISAR3,ISA Feature Register 3" line.long 0x24 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_ISAR1" hexmask.long 0x24 0.--31. 1. "MSS_R5SS1_APB_PROCID_ISAR4,ISA Feature Register 4" line.long 0x28 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_ISAR2" hexmask.long 0x28 0.--31. 1. "MSS_R5SS1_APB_PROCID_ISAR5,ISA Feature Register 5" line.long 0x2C "DEBUGSS_MSS_R5SS1_B_APB_PROCID_ISAR3" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS1_APB_MR_ITCTRL,Integration Mode Control Registers" line.long 0x30 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_ISAR4" hexmask.long 0x30 0.--31. 1. "MSS_R5SS1_APB_MR_CLAIMSET,Claim Tag Set Register" line.long 0x34 "DEBUGSS_MSS_R5SS1_B_APB_PROCID_ISAR5" hexmask.long 0x34 0.--31. 1. "MSS_R5SS1_APB_MR_CLAIMCLR,Claim Tag Clear Register" group.long 0x52F00++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_MR_ITCTRL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_MR_LOCKACCESS,Lock Access Register" group.long 0x52FA0++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_MR_CLAIMSET" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_MR_LOCKSTATUS,Lock Status Register" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_MR_CLAIMCLR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_MR_AUTHSTATUS,Authentication Status Register" group.long 0x52FB0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_MR_LOCKACCESS" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_MR_DEVID,Device Identifier" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_MR_LOCKSTATUS" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_MR_DEVTYPE,Device Type Register" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_APB_MR_AUTHSTATUS" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_PERIP_ID4,Not Defined" group.long 0x52FC8++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_MR_DEVID" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_PERIP_ID0,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_MR_DEVTYPE" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_PERIP_ID1,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_APB_PERIP_ID4" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_PERIP_ID2,Not Defined" group.long 0x52FE0++0x17 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_PERIP_ID0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_APB_PERIP_ID3,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_APB_PERIP_ID1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_APB_COMP_ID0,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_APB_PERIP_ID2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_APB_COMP_ID1,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_B_APB_PERIP_ID3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_APB_COMP_ID2,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_B_APB_COMP_ID0" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_APB_COMP_ID3,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS1_B_APB_COMP_ID1" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_CTI_CONTROL,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.htmlhttp://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html" wgroup.long 0x52FF8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_COMP_ID2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_INTACK,Not Defined" group.long 0x52FFC++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_APB_COMP_ID3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_APPSET,Not Defined" wgroup.long 0x58000++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_CONTROL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_APPCLEAR,Not Defined" wgroup.long 0x58010++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_INTACK" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_APPPULSE,Not Defined" group.long 0x58014++0x2B line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_APPSET" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_INEN0,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_CTI_APPCLEAR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_INEN1,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_CTI_APPPULSE" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_INEN2,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_A_CTI_INEN0" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_CTI_INEN3,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_A_CTI_INEN1" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_CTI_INEN4,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS1_A_CTI_INEN2" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_CTI_INEN5,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS1_A_CTI_INEN3" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_CTI_INEN6,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS1_A_CTI_INEN4" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_CTI_INEN7,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS1_A_CTI_INEN5" hexmask.long 0x20 0.--31. 1. "MSS_R5SS1_CTI_OUTEN0,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS1_A_CTI_INEN6" hexmask.long 0x24 0.--31. 1. "MSS_R5SS1_CTI_OUTEN1,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS1_A_CTI_INEN7" hexmask.long 0x28 0.--31. 1. "MSS_R5SS1_CTI_OUTEN2,Not Defined" group.long 0x580A0++0x13 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_OUTEN0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_OUTEN3,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_CTI_OUTEN1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_OUTEN4,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_CTI_OUTEN2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_OUTEN5,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_A_CTI_OUTEN3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_CTI_OUTEN6,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_A_CTI_OUTEN4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_CTI_OUTEN7,Not Defined" rgroup.long 0x580B4++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_OUTEN5" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_TRIGINSTATUS,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_CTI_OUTEN6" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_TRIGOUTSTATUS,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_CTI_OUTEN7" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_CHINSTATUS,Not Defined" rgroup.long 0x58130++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_TRIGINSTATUS" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_CHOUTSTATUS,Not Defined" group.long 0x58134++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_TRIGOUTSTATUS" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_GATE,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_CTI_CHINSTATUS" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_ASICCTL,Not Defined" wgroup.long 0x5813C++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_CHOUTSTATUS" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_ITCHINACK,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_CTI_GATE" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_ITTRIGINACK,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_CTI_ASICCTL" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_ITCHOUT,Not Defined" wgroup.long 0x58EDC++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_ITCHINACK" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_ITTRIGOUT,Not Defined" rgroup.long 0x58EE0++0xF line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_ITTRIGINACK" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_ITCHOUTACK,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_CTI_ITCHOUT" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_ITTRIGOUTACK,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_CTI_ITTRIGOUT" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_ITCHIN,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_A_CTI_ITCHOUTACK" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_CTI_ITTRIGIN,Not Defined" group.long 0x58EF0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_ITTRIGOUTACK" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_ITCTRL,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_CTI_ITCHIN" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_CLAIM_TAG_SET,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_CTI_ITTRIGIN" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_CLAIM_TAG_CLEAR,Not Defined" wgroup.long 0x58F00++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_ITCTRL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_LOCK_ACCESS_REGISTER,Not Defined" rgroup.long 0x58FA0++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_CLAIM_TAG_SET" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_LOCK_STATUS_REGISTER,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_CTI_CLAIM_TAG_CLEAR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_AUTHENTICATION_STATUS,Not Defined" rgroup.long 0x58FB0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_LOCK_ACCESS_REGISTER" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_DEVICE_ID,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_CTI_LOCK_STATUS_REGISTER" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_DEVICE_TYPE_IDENTIFIER,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_CTI_AUTHENTICATION_STATUS" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID4,Not Defined" rgroup.long 0x58FC8++0x2B line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_DEVICE_ID" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID5,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_CTI_DEVICE_TYPE_IDENTIFIER" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID6,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_CTI_PERIPHERALID4" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID7,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_A_CTI_PERIPHERALID5" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID0,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_A_CTI_PERIPHERALID6" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID1,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS1_A_CTI_PERIPHERALID7" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID2,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS1_A_CTI_PERIPHERALID0" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID3,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS1_A_CTI_PERIPHERALID1" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_CTI_COMPONENT_ID0,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS1_A_CTI_PERIPHERALID2" hexmask.long 0x20 0.--31. 1. "MSS_R5SS1_CTI_COMPONENT_ID1,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS1_A_CTI_PERIPHERALID3" hexmask.long 0x24 0.--31. 1. "MSS_R5SS1_CTI_COMPONENT_ID2,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS1_A_CTI_COMPONENT_ID0" hexmask.long 0x28 0.--31. 1. "MSS_R5SS1_CTI_COMPONENT_ID3,Not Defined" group.long 0x58FF4++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_COMPONENT_ID1" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_CONTROL,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.htmlhttp://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html" wgroup.long 0x58FF8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_COMPONENT_ID2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_INTACK,Not Defined" group.long 0x58FFC++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_CTI_COMPONENT_ID3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_APPSET,Not Defined" wgroup.long 0x59000++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_CONTROL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_APPCLEAR,Not Defined" wgroup.long 0x59010++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_INTACK" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_APPPULSE,Not Defined" group.long 0x59014++0x2B line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_APPSET" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_INEN0,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_CTI_APPCLEAR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_INEN1,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_CTI_APPPULSE" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_INEN2,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_B_CTI_INEN0" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_CTI_INEN3,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_B_CTI_INEN1" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_CTI_INEN4,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS1_B_CTI_INEN2" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_CTI_INEN5,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS1_B_CTI_INEN3" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_CTI_INEN6,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS1_B_CTI_INEN4" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_CTI_INEN7,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS1_B_CTI_INEN5" hexmask.long 0x20 0.--31. 1. "MSS_R5SS1_CTI_OUTEN0,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS1_B_CTI_INEN6" hexmask.long 0x24 0.--31. 1. "MSS_R5SS1_CTI_OUTEN1,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS1_B_CTI_INEN7" hexmask.long 0x28 0.--31. 1. "MSS_R5SS1_CTI_OUTEN2,Not Defined" group.long 0x590A0++0x13 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_OUTEN0" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_OUTEN3,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_CTI_OUTEN1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_OUTEN4,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_CTI_OUTEN2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_OUTEN5,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_B_CTI_OUTEN3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_CTI_OUTEN6,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_B_CTI_OUTEN4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_CTI_OUTEN7,Not Defined" rgroup.long 0x590B4++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_OUTEN5" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_TRIGINSTATUS,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_CTI_OUTEN6" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_TRIGOUTSTATUS,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_CTI_OUTEN7" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_CHINSTATUS,Not Defined" rgroup.long 0x59130++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_TRIGINSTATUS" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_CHOUTSTATUS,Not Defined" group.long 0x59134++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_TRIGOUTSTATUS" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_GATE,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_CTI_CHINSTATUS" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_ASICCTL,Not Defined" wgroup.long 0x5913C++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_CHOUTSTATUS" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_ITCHINACK,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_CTI_GATE" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_ITTRIGINACK,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_CTI_ASICCTL" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_ITCHOUT,Not Defined" wgroup.long 0x59EDC++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_ITCHINACK" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_ITTRIGOUT,Not Defined" rgroup.long 0x59EE0++0xF line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_ITTRIGINACK" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_ITCHOUTACK,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_CTI_ITCHOUT" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_ITTRIGOUTACK,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_CTI_ITTRIGOUT" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_ITCHIN,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_B_CTI_ITCHOUTACK" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_CTI_ITTRIGIN,Not Defined" group.long 0x59EF0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_ITTRIGOUTACK" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_ITCTRL,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_CTI_ITCHIN" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_CLAIM_TAG_SET,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_CTI_ITTRIGIN" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_CLAIM_TAG_CLEAR,Not Defined" wgroup.long 0x59F00++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_ITCTRL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_LOCK_ACCESS_REGISTER,Not Defined" rgroup.long 0x59FA0++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_CLAIM_TAG_SET" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_LOCK_STATUS_REGISTER,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_CTI_CLAIM_TAG_CLEAR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_AUTHENTICATION_STATUS,Not Defined" rgroup.long 0x59FB0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_LOCK_ACCESS_REGISTER" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_DEVICE_ID,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_CTI_LOCK_STATUS_REGISTER" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_DEVICE_TYPE_IDENTIFIER,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_CTI_AUTHENTICATION_STATUS" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID4,Not Defined" rgroup.long 0x59FC8++0x2B line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_DEVICE_ID" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID5,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_CTI_DEVICE_TYPE_IDENTIFIER" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID6,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_CTI_PERIPHERALID4" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID7,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_B_CTI_PERIPHERALID5" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID0,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_B_CTI_PERIPHERALID6" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID1,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS1_B_CTI_PERIPHERALID7" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID2,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS1_B_CTI_PERIPHERALID0" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_CTI_PERIPHERALID3,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS1_B_CTI_PERIPHERALID1" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_CTI_COMPONENT_ID0,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS1_B_CTI_PERIPHERALID2" hexmask.long 0x20 0.--31. 1. "MSS_R5SS1_CTI_COMPONENT_ID1,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS1_B_CTI_PERIPHERALID3" hexmask.long 0x24 0.--31. 1. "MSS_R5SS1_CTI_COMPONENT_ID2,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS1_B_CTI_COMPONENT_ID0" hexmask.long 0x28 0.--31. 1. "MSS_R5SS1_CTI_COMPONENT_ID3,Not Defined" group.long 0x59FF4++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_COMPONENT_ID1" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_CR,http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0014q/Chdfiagc.htmlhttp://infocenter.arm.com/help/topic/com.arm.doc.ihi0014q/I84249.html" rgroup.long 0x59FF8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_COMPONENT_ID2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_CCR,Not Defined" group.long 0x59FFC++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_CTI_COMPONENT_ID3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_TRIGGER,Not Defined" group.long 0x5C000++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_CR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_ASICCTLR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_ETM_CCR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_SR,Not Defined" rgroup.long 0x5C008++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_TRIGGER" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_SCR,Not Defined" group.long 0x5C00C++0xB7 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_ASICCTLR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_TSSCR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_ETM_SR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_TECR2,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_ETM_SCR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_ETM_TEEVR,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_A_ETM_TSSCR" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_ETM_TECR1,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_A_ETM_TECR2" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_ETM_FFRR,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS1_A_ETM_TEEVR" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_ETM_FFLR,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS1_A_ETM_TECR1" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_ETM_VDEVR,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS1_A_ETM_FFRR" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_ETM_VDCR1,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS1_A_ETM_FFLR" hexmask.long 0x20 0.--31. 1. "MSS_R5SS1_ETM_VDCR2,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS1_A_ETM_VDEVR" hexmask.long 0x24 0.--31. 1. "MSS_R5SS1_ETM_VDCR3,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS1_A_ETM_VDCR1" hexmask.long 0x28 0.--31. 1. "MSS_R5SS1_ETM_ACVR1,Not Defined" line.long 0x2C "DEBUGSS_MSS_R5SS1_A_ETM_VDCR2" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS1_ETM_ACVR2,Not Defined" line.long 0x30 "DEBUGSS_MSS_R5SS1_A_ETM_VDCR3" hexmask.long 0x30 0.--31. 1. "MSS_R5SS1_ETM_ACVR3,Not Defined" line.long 0x34 "DEBUGSS_MSS_R5SS1_A_ETM_ACVR1" hexmask.long 0x34 0.--31. 1. "MSS_R5SS1_ETM_ACVR4,Not Defined" line.long 0x38 "DEBUGSS_MSS_R5SS1_A_ETM_ACVR2" hexmask.long 0x38 0.--31. 1. "MSS_R5SS1_ETM_ACVR5,Not Defined" line.long 0x3C "DEBUGSS_MSS_R5SS1_A_ETM_ACVR3" hexmask.long 0x3C 0.--31. 1. "MSS_R5SS1_ETM_ACVR6,Not Defined" line.long 0x40 "DEBUGSS_MSS_R5SS1_A_ETM_ACVR4" hexmask.long 0x40 0.--31. 1. "MSS_R5SS1_ETM_ACVR7,Not Defined" line.long 0x44 "DEBUGSS_MSS_R5SS1_A_ETM_ACVR5" hexmask.long 0x44 0.--31. 1. "MSS_R5SS1_ETM_ACVR8,Not Defined" line.long 0x48 "DEBUGSS_MSS_R5SS1_A_ETM_ACVR6" hexmask.long 0x48 0.--31. 1. "MSS_R5SS1_ETM_ACVR9,Not Defined" line.long 0x4C "DEBUGSS_MSS_R5SS1_A_ETM_ACVR7" hexmask.long 0x4C 0.--31. 1. "MSS_R5SS1_ETM_ACVR10,Not Defined" line.long 0x50 "DEBUGSS_MSS_R5SS1_A_ETM_ACVR8" hexmask.long 0x50 0.--31. 1. "MSS_R5SS1_ETM_ACVR11,Not Defined" line.long 0x54 "DEBUGSS_MSS_R5SS1_A_ETM_ACVR9" hexmask.long 0x54 0.--31. 1. "MSS_R5SS1_ETM_ACVR12,Not Defined" line.long 0x58 "DEBUGSS_MSS_R5SS1_A_ETM_ACVR10" hexmask.long 0x58 0.--31. 1. "MSS_R5SS1_ETM_ACVR13,Not Defined" line.long 0x5C "DEBUGSS_MSS_R5SS1_A_ETM_ACVR11" hexmask.long 0x5C 0.--31. 1. "MSS_R5SS1_ETM_ACVR14,Not Defined" line.long 0x60 "DEBUGSS_MSS_R5SS1_A_ETM_ACVR12" hexmask.long 0x60 0.--31. 1. "MSS_R5SS1_ETM_ACVR15,Not Defined" line.long 0x64 "DEBUGSS_MSS_R5SS1_A_ETM_ACVR13" hexmask.long 0x64 0.--31. 1. "MSS_R5SS1_ETM_ACVR16,Not Defined" line.long 0x68 "DEBUGSS_MSS_R5SS1_A_ETM_ACVR14" hexmask.long 0x68 0.--31. 1. "MSS_R5SS1_ETM_ACTR1,Not Defined" line.long 0x6C "DEBUGSS_MSS_R5SS1_A_ETM_ACVR15" hexmask.long 0x6C 0.--31. 1. "MSS_R5SS1_ETM_ACTR2,Not Defined" line.long 0x70 "DEBUGSS_MSS_R5SS1_A_ETM_ACVR16" hexmask.long 0x70 0.--31. 1. "MSS_R5SS1_ETM_ACTR3,Not Defined" line.long 0x74 "DEBUGSS_MSS_R5SS1_A_ETM_ACTR1" hexmask.long 0x74 0.--31. 1. "MSS_R5SS1_ETM_ACTR4,Not Defined" line.long 0x78 "DEBUGSS_MSS_R5SS1_A_ETM_ACTR2" hexmask.long 0x78 0.--31. 1. "MSS_R5SS1_ETM_ACTR5,Not Defined" line.long 0x7C "DEBUGSS_MSS_R5SS1_A_ETM_ACTR3" hexmask.long 0x7C 0.--31. 1. "MSS_R5SS1_ETM_ACTR6,Not Defined" line.long 0x80 "DEBUGSS_MSS_R5SS1_A_ETM_ACTR4" hexmask.long 0x80 0.--31. 1. "MSS_R5SS1_ETM_ACTR7,Not Defined" line.long 0x84 "DEBUGSS_MSS_R5SS1_A_ETM_ACTR5" hexmask.long 0x84 0.--31. 1. "MSS_R5SS1_ETM_ACTR8,Not Defined" line.long 0x88 "DEBUGSS_MSS_R5SS1_A_ETM_ACTR6" hexmask.long 0x88 0.--31. 1. "MSS_R5SS1_ETM_ACTR9,Not Defined" line.long 0x8C "DEBUGSS_MSS_R5SS1_A_ETM_ACTR7" hexmask.long 0x8C 0.--31. 1. "MSS_R5SS1_ETM_ACTR10,Not Defined" line.long 0x90 "DEBUGSS_MSS_R5SS1_A_ETM_ACTR8" hexmask.long 0x90 0.--31. 1. "MSS_R5SS1_ETM_ACTR11,Not Defined" line.long 0x94 "DEBUGSS_MSS_R5SS1_A_ETM_ACTR9" hexmask.long 0x94 0.--31. 1. "MSS_R5SS1_ETM_ACTR12,Not Defined" line.long 0x98 "DEBUGSS_MSS_R5SS1_A_ETM_ACTR10" hexmask.long 0x98 0.--31. 1. "MSS_R5SS1_ETM_ACTR13,Not Defined" line.long 0x9C "DEBUGSS_MSS_R5SS1_A_ETM_ACTR11" hexmask.long 0x9C 0.--31. 1. "MSS_R5SS1_ETM_ACTR14,Not Defined" line.long 0xA0 "DEBUGSS_MSS_R5SS1_A_ETM_ACTR12" hexmask.long 0xA0 0.--31. 1. "MSS_R5SS1_ETM_ACTR15,Not Defined" line.long 0xA4 "DEBUGSS_MSS_R5SS1_A_ETM_ACTR13" hexmask.long 0xA4 0.--31. 1. "MSS_R5SS1_ETM_ACTR16,Not Defined" line.long 0xA8 "DEBUGSS_MSS_R5SS1_A_ETM_ACTR14" hexmask.long 0xA8 0.--31. 1. "MSS_R5SS1_ETM_DCVR1,Not Defined" line.long 0xAC "DEBUGSS_MSS_R5SS1_A_ETM_ACTR15" hexmask.long 0xAC 0.--31. 1. "MSS_R5SS1_ETM_DCVR2,Not Defined" line.long 0xB0 "DEBUGSS_MSS_R5SS1_A_ETM_ACTR16" hexmask.long 0xB0 0.--31. 1. "MSS_R5SS1_ETM_DCVR3,Not Defined" line.long 0xB4 "DEBUGSS_MSS_R5SS1_A_ETM_DCVR1" hexmask.long 0xB4 0.--31. 1. "MSS_R5SS1_ETM_DCVR4,Not Defined" group.long 0x5C0C8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DCVR2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCVR5,Not Defined" group.long 0x5C0D0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DCVR3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCVR6,Not Defined" group.long 0x5C0D8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DCVR4" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCVR7,Not Defined" group.long 0x5C0E0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DCVR5" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCVR8,Not Defined" group.long 0x5C0E8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DCVR6" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR1,Not Defined" group.long 0x5C0F0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DCVR7" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR2,Not Defined" group.long 0x5C0F8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DCVR8" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR3,Not Defined" group.long 0x5C100++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DCMR1" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR4,Not Defined" group.long 0x5C108++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DCMR2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR5,Not Defined" group.long 0x5C110++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DCMR3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR6,Not Defined" group.long 0x5C118++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DCMR4" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR7,Not Defined" group.long 0x5C120++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DCMR5" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR8,Not Defined" group.long 0x5C128++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DCMR6" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDVR1,Not Defined" group.long 0x5C130++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DCMR7" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDVR2,Not Defined" group.long 0x5C138++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DCMR8" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDVR3,Not Defined" group.long 0x5C140++0x57 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_CNTRLDVR1" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDVR4,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_ETM_CNTRLDVR2" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_CNTENR1,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_ETM_CNTRLDVR3" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_ETM_CNTENR2,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_A_ETM_CNTRLDVR4" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_ETM_CNTENR3,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_A_ETM_CNTENR1" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_ETM_CNTENR4,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS1_A_ETM_CNTENR2" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDEVR1,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS1_A_ETM_CNTENR3" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDEVR2,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS1_A_ETM_CNTENR4" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDEVR3,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS1_A_ETM_CNTRLDEVR1" hexmask.long 0x20 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDEVR4,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS1_A_ETM_CNTRLDEVR2" hexmask.long 0x24 0.--31. 1. "MSS_R5SS1_ETM_CNTVR1,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS1_A_ETM_CNTRLDEVR3" hexmask.long 0x28 0.--31. 1. "MSS_R5SS1_ETM_CNTVR2,Not Defined" line.long 0x2C "DEBUGSS_MSS_R5SS1_A_ETM_CNTRLDEVR4" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS1_ETM_CNTVR3,Not Defined" line.long 0x30 "DEBUGSS_MSS_R5SS1_A_ETM_CNTVR1" hexmask.long 0x30 0.--31. 1. "MSS_R5SS1_ETM_CNTVR4,Not Defined" line.long 0x34 "DEBUGSS_MSS_R5SS1_A_ETM_CNTVR2" hexmask.long 0x34 0.--31. 1. "MSS_R5SS1_ETM_SQ12EVR,Not Defined" line.long 0x38 "DEBUGSS_MSS_R5SS1_A_ETM_CNTVR3" hexmask.long 0x38 0.--31. 1. "MSS_R5SS1_ETM_SQ21EVR,Not Defined" line.long 0x3C "DEBUGSS_MSS_R5SS1_A_ETM_CNTVR4" hexmask.long 0x3C 0.--31. 1. "MSS_R5SS1_ETM_SQ23EVR,Not Defined" line.long 0x40 "DEBUGSS_MSS_R5SS1_A_ETM_SQ12EVR" hexmask.long 0x40 0.--31. 1. "MSS_R5SS1_ETM_SQ31EVR,Not Defined" line.long 0x44 "DEBUGSS_MSS_R5SS1_A_ETM_SQ21EVR" hexmask.long 0x44 0.--31. 1. "MSS_R5SS1_ETM_SQ32EVR,Not Defined" line.long 0x48 "DEBUGSS_MSS_R5SS1_A_ETM_SQ23EVR" hexmask.long 0x48 0.--31. 1. "MSS_R5SS1_ETM_SQ13EVR,Not Defined" line.long 0x4C "DEBUGSS_MSS_R5SS1_A_ETM_SQ31EVR" hexmask.long 0x4C 0.--31. 1. "MSS_R5SS1_ETM_SQR,Not Defined" line.long 0x50 "DEBUGSS_MSS_R5SS1_A_ETM_SQ32EVR" hexmask.long 0x50 0.--31. 1. "MSS_R5SS1_ETM_EXTOUTEVR1,Not Defined" line.long 0x54 "DEBUGSS_MSS_R5SS1_A_ETM_SQ13EVR" hexmask.long 0x54 0.--31. 1. "MSS_R5SS1_ETM_EXTOUTEVR2,Not Defined" group.long 0x5C19C++0x1B line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_SQR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_EXTOUTEVR3,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_ETM_EXTOUTEVR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_EXTOUTEVR4,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_ETM_EXTOUTEVR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_ETM_CIDCVR1,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_A_ETM_EXTOUTEVR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_ETM_CIDCVR2,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_A_ETM_EXTOUTEVR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_ETM_CIDCVR3,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS1_A_ETM_CIDCVR1" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_ETM_CIDCMR,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS1_A_ETM_CIDCVR2" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_ETM_SYNCFR,Not Defined" rgroup.long 0x5C1B8++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_CIDCVR3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_IDR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_ETM_CIDCMR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_CCER,Not Defined" group.long 0x5C1E0++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_SYNCFR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_EXTINSELR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_ETM_IDR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_TRACEIDR,Not Defined" rgroup.long 0x5C1E8++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_CCER" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_PDSR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_ETM_EXTINSELR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_ITETMIF,Not Defined" wgroup.long 0x5C200++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_TRACEIDR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_ITMISCOUT,Not Defined" rgroup.long 0x5C314++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_PDSR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_ITMISCIN,Not Defined" rgroup.long 0x5CED8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_ITETMIF" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_ITTRIGGERACK,Not Defined" wgroup.long 0x5CEDC++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_ITMISCOUT" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_ITTRIGGERREQ,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_ETM_ITMISCIN" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_ITATBDATA0,Not Defined" rgroup.long 0x5CEE4++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_ITTRIGGERACK" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_ITATBCTR2,Not Defined" wgroup.long 0x5CEE8++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_ITTRIGGERREQ" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_ITATBCTR1,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_ETM_ITATBDATA0" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_ITATBCTR0,Not Defined" group.long 0x5CEF0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_ITATBCTR2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_ITCTRL,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_ETM_ITATBCTR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_CLAIMSET,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_ETM_ITATBCTR0" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_ETM_CLAIMCLR,Not Defined" wgroup.long 0x5CF00++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_ITCTRL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_LAR,Not Defined" rgroup.long 0x5CFA0++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_CLAIMSET" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_LSR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_ETM_CLAIMCLR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_AUTHSTATUS,Not Defined" rgroup.long 0x5CFB0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_LAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DEVID,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_ETM_LSR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_DEVTYPE,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_ETM_AUTHSTATUS" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_ETM_PIDR4,Not Defined" rgroup.long 0x5CFC8++0x2B line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_DEVID" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_PIDR5,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_A_ETM_DEVTYPE" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_PIDR6,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_A_ETM_PIDR4" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_ETM_PIDR7,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_A_ETM_PIDR5" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_ETM_PIDR0,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_A_ETM_PIDR6" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_ETM_PIDR1,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS1_A_ETM_PIDR7" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_ETM_PIDR2,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS1_A_ETM_PIDR0" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_ETM_PIDR3,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS1_A_ETM_PIDR1" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_ETM_CIDR0,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS1_A_ETM_PIDR2" hexmask.long 0x20 0.--31. 1. "MSS_R5SS1_ETM_CIDR1,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS1_A_ETM_PIDR3" hexmask.long 0x24 0.--31. 1. "MSS_R5SS1_ETM_CIDR2,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS1_A_ETM_CIDR0" hexmask.long 0x28 0.--31. 1. "MSS_R5SS1_ETM_CIDR3,Not Defined" group.long 0x5CFF4++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_CIDR1" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_CR,http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0014q/Chdfiagc.htmlhttp://infocenter.arm.com/help/topic/com.arm.doc.ihi0014q/I84249.html" rgroup.long 0x5CFF8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_CIDR2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_CCR,Not Defined" group.long 0x5CFFC++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_A_ETM_CIDR3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_TRIGGER,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_ETM_CR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_ASICCTLR,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_ETM_CCR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_ETM_SR,Not Defined" rgroup.long 0x5D008++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_TRIGGER" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_SCR,Not Defined" group.long 0x5D00C++0xB7 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_ASICCTLR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_TSSCR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_ETM_SR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_TECR2,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_ETM_SCR" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_ETM_TEEVR,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_B_ETM_TSSCR" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_ETM_TECR1,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_B_ETM_TECR2" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_ETM_FFRR,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS1_B_ETM_TEEVR" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_ETM_FFLR,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS1_B_ETM_TECR1" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_ETM_VDEVR,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS1_B_ETM_FFRR" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_ETM_VDCR1,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS1_B_ETM_FFLR" hexmask.long 0x20 0.--31. 1. "MSS_R5SS1_ETM_VDCR2,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS1_B_ETM_VDEVR" hexmask.long 0x24 0.--31. 1. "MSS_R5SS1_ETM_VDCR3,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS1_B_ETM_VDCR1" hexmask.long 0x28 0.--31. 1. "MSS_R5SS1_ETM_ACVR1,Not Defined" line.long 0x2C "DEBUGSS_MSS_R5SS1_B_ETM_VDCR2" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS1_ETM_ACVR2,Not Defined" line.long 0x30 "DEBUGSS_MSS_R5SS1_B_ETM_VDCR3" hexmask.long 0x30 0.--31. 1. "MSS_R5SS1_ETM_ACVR3,Not Defined" line.long 0x34 "DEBUGSS_MSS_R5SS1_B_ETM_ACVR1" hexmask.long 0x34 0.--31. 1. "MSS_R5SS1_ETM_ACVR4,Not Defined" line.long 0x38 "DEBUGSS_MSS_R5SS1_B_ETM_ACVR2" hexmask.long 0x38 0.--31. 1. "MSS_R5SS1_ETM_ACVR5,Not Defined" line.long 0x3C "DEBUGSS_MSS_R5SS1_B_ETM_ACVR3" hexmask.long 0x3C 0.--31. 1. "MSS_R5SS1_ETM_ACVR6,Not Defined" line.long 0x40 "DEBUGSS_MSS_R5SS1_B_ETM_ACVR4" hexmask.long 0x40 0.--31. 1. "MSS_R5SS1_ETM_ACVR7,Not Defined" line.long 0x44 "DEBUGSS_MSS_R5SS1_B_ETM_ACVR5" hexmask.long 0x44 0.--31. 1. "MSS_R5SS1_ETM_ACVR8,Not Defined" line.long 0x48 "DEBUGSS_MSS_R5SS1_B_ETM_ACVR6" hexmask.long 0x48 0.--31. 1. "MSS_R5SS1_ETM_ACVR9,Not Defined" line.long 0x4C "DEBUGSS_MSS_R5SS1_B_ETM_ACVR7" hexmask.long 0x4C 0.--31. 1. "MSS_R5SS1_ETM_ACVR10,Not Defined" line.long 0x50 "DEBUGSS_MSS_R5SS1_B_ETM_ACVR8" hexmask.long 0x50 0.--31. 1. "MSS_R5SS1_ETM_ACVR11,Not Defined" line.long 0x54 "DEBUGSS_MSS_R5SS1_B_ETM_ACVR9" hexmask.long 0x54 0.--31. 1. "MSS_R5SS1_ETM_ACVR12,Not Defined" line.long 0x58 "DEBUGSS_MSS_R5SS1_B_ETM_ACVR10" hexmask.long 0x58 0.--31. 1. "MSS_R5SS1_ETM_ACVR13,Not Defined" line.long 0x5C "DEBUGSS_MSS_R5SS1_B_ETM_ACVR11" hexmask.long 0x5C 0.--31. 1. "MSS_R5SS1_ETM_ACVR14,Not Defined" line.long 0x60 "DEBUGSS_MSS_R5SS1_B_ETM_ACVR12" hexmask.long 0x60 0.--31. 1. "MSS_R5SS1_ETM_ACVR15,Not Defined" line.long 0x64 "DEBUGSS_MSS_R5SS1_B_ETM_ACVR13" hexmask.long 0x64 0.--31. 1. "MSS_R5SS1_ETM_ACVR16,Not Defined" line.long 0x68 "DEBUGSS_MSS_R5SS1_B_ETM_ACVR14" hexmask.long 0x68 0.--31. 1. "MSS_R5SS1_ETM_ACTR1,Not Defined" line.long 0x6C "DEBUGSS_MSS_R5SS1_B_ETM_ACVR15" hexmask.long 0x6C 0.--31. 1. "MSS_R5SS1_ETM_ACTR2,Not Defined" line.long 0x70 "DEBUGSS_MSS_R5SS1_B_ETM_ACVR16" hexmask.long 0x70 0.--31. 1. "MSS_R5SS1_ETM_ACTR3,Not Defined" line.long 0x74 "DEBUGSS_MSS_R5SS1_B_ETM_ACTR1" hexmask.long 0x74 0.--31. 1. "MSS_R5SS1_ETM_ACTR4,Not Defined" line.long 0x78 "DEBUGSS_MSS_R5SS1_B_ETM_ACTR2" hexmask.long 0x78 0.--31. 1. "MSS_R5SS1_ETM_ACTR5,Not Defined" line.long 0x7C "DEBUGSS_MSS_R5SS1_B_ETM_ACTR3" hexmask.long 0x7C 0.--31. 1. "MSS_R5SS1_ETM_ACTR6,Not Defined" line.long 0x80 "DEBUGSS_MSS_R5SS1_B_ETM_ACTR4" hexmask.long 0x80 0.--31. 1. "MSS_R5SS1_ETM_ACTR7,Not Defined" line.long 0x84 "DEBUGSS_MSS_R5SS1_B_ETM_ACTR5" hexmask.long 0x84 0.--31. 1. "MSS_R5SS1_ETM_ACTR8,Not Defined" line.long 0x88 "DEBUGSS_MSS_R5SS1_B_ETM_ACTR6" hexmask.long 0x88 0.--31. 1. "MSS_R5SS1_ETM_ACTR9,Not Defined" line.long 0x8C "DEBUGSS_MSS_R5SS1_B_ETM_ACTR7" hexmask.long 0x8C 0.--31. 1. "MSS_R5SS1_ETM_ACTR10,Not Defined" line.long 0x90 "DEBUGSS_MSS_R5SS1_B_ETM_ACTR8" hexmask.long 0x90 0.--31. 1. "MSS_R5SS1_ETM_ACTR11,Not Defined" line.long 0x94 "DEBUGSS_MSS_R5SS1_B_ETM_ACTR9" hexmask.long 0x94 0.--31. 1. "MSS_R5SS1_ETM_ACTR12,Not Defined" line.long 0x98 "DEBUGSS_MSS_R5SS1_B_ETM_ACTR10" hexmask.long 0x98 0.--31. 1. "MSS_R5SS1_ETM_ACTR13,Not Defined" line.long 0x9C "DEBUGSS_MSS_R5SS1_B_ETM_ACTR11" hexmask.long 0x9C 0.--31. 1. "MSS_R5SS1_ETM_ACTR14,Not Defined" line.long 0xA0 "DEBUGSS_MSS_R5SS1_B_ETM_ACTR12" hexmask.long 0xA0 0.--31. 1. "MSS_R5SS1_ETM_ACTR15,Not Defined" line.long 0xA4 "DEBUGSS_MSS_R5SS1_B_ETM_ACTR13" hexmask.long 0xA4 0.--31. 1. "MSS_R5SS1_ETM_ACTR16,Not Defined" line.long 0xA8 "DEBUGSS_MSS_R5SS1_B_ETM_ACTR14" hexmask.long 0xA8 0.--31. 1. "MSS_R5SS1_ETM_DCVR1,Not Defined" line.long 0xAC "DEBUGSS_MSS_R5SS1_B_ETM_ACTR15" hexmask.long 0xAC 0.--31. 1. "MSS_R5SS1_ETM_DCVR2,Not Defined" line.long 0xB0 "DEBUGSS_MSS_R5SS1_B_ETM_ACTR16" hexmask.long 0xB0 0.--31. 1. "MSS_R5SS1_ETM_DCVR3,Not Defined" line.long 0xB4 "DEBUGSS_MSS_R5SS1_B_ETM_DCVR1" hexmask.long 0xB4 0.--31. 1. "MSS_R5SS1_ETM_DCVR4,Not Defined" group.long 0x5D0C8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DCVR2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCVR5,Not Defined" group.long 0x5D0D0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DCVR3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCVR6,Not Defined" group.long 0x5D0D8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DCVR4" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCVR7,Not Defined" group.long 0x5D0E0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DCVR5" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCVR8,Not Defined" group.long 0x5D0E8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DCVR6" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR1,Not Defined" group.long 0x5D0F0++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DCVR7" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR2,Not Defined" group.long 0x5D0F8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DCVR8" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR3,Not Defined" group.long 0x5D100++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DCMR1" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR4,Not Defined" group.long 0x5D108++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DCMR2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR5,Not Defined" group.long 0x5D110++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DCMR3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR6,Not Defined" group.long 0x5D118++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DCMR4" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR7,Not Defined" group.long 0x5D120++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DCMR5" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DCMR8,Not Defined" group.long 0x5D128++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DCMR6" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDVR1,Not Defined" group.long 0x5D130++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DCMR7" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDVR2,Not Defined" group.long 0x5D138++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DCMR8" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDVR3,Not Defined" group.long 0x5D140++0x57 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_CNTRLDVR1" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDVR4,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_ETM_CNTRLDVR2" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_CNTENR1,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_ETM_CNTRLDVR3" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_ETM_CNTENR2,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_B_ETM_CNTRLDVR4" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_ETM_CNTENR3,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_B_ETM_CNTENR1" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_ETM_CNTENR4,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS1_B_ETM_CNTENR2" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDEVR1,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS1_B_ETM_CNTENR3" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDEVR2,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS1_B_ETM_CNTENR4" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDEVR3,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS1_B_ETM_CNTRLDEVR1" hexmask.long 0x20 0.--31. 1. "MSS_R5SS1_ETM_CNTRLDEVR4,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS1_B_ETM_CNTRLDEVR2" hexmask.long 0x24 0.--31. 1. "MSS_R5SS1_ETM_CNTVR1,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS1_B_ETM_CNTRLDEVR3" hexmask.long 0x28 0.--31. 1. "MSS_R5SS1_ETM_CNTVR2,Not Defined" line.long 0x2C "DEBUGSS_MSS_R5SS1_B_ETM_CNTRLDEVR4" hexmask.long 0x2C 0.--31. 1. "MSS_R5SS1_ETM_CNTVR3,Not Defined" line.long 0x30 "DEBUGSS_MSS_R5SS1_B_ETM_CNTVR1" hexmask.long 0x30 0.--31. 1. "MSS_R5SS1_ETM_CNTVR4,Not Defined" line.long 0x34 "DEBUGSS_MSS_R5SS1_B_ETM_CNTVR2" hexmask.long 0x34 0.--31. 1. "MSS_R5SS1_ETM_SQ12EVR,Not Defined" line.long 0x38 "DEBUGSS_MSS_R5SS1_B_ETM_CNTVR3" hexmask.long 0x38 0.--31. 1. "MSS_R5SS1_ETM_SQ21EVR,Not Defined" line.long 0x3C "DEBUGSS_MSS_R5SS1_B_ETM_CNTVR4" hexmask.long 0x3C 0.--31. 1. "MSS_R5SS1_ETM_SQ23EVR,Not Defined" line.long 0x40 "DEBUGSS_MSS_R5SS1_B_ETM_SQ12EVR" hexmask.long 0x40 0.--31. 1. "MSS_R5SS1_ETM_SQ31EVR,Not Defined" line.long 0x44 "DEBUGSS_MSS_R5SS1_B_ETM_SQ21EVR" hexmask.long 0x44 0.--31. 1. "MSS_R5SS1_ETM_SQ32EVR,Not Defined" line.long 0x48 "DEBUGSS_MSS_R5SS1_B_ETM_SQ23EVR" hexmask.long 0x48 0.--31. 1. "MSS_R5SS1_ETM_SQ13EVR,Not Defined" line.long 0x4C "DEBUGSS_MSS_R5SS1_B_ETM_SQ31EVR" hexmask.long 0x4C 0.--31. 1. "MSS_R5SS1_ETM_SQR,Not Defined" line.long 0x50 "DEBUGSS_MSS_R5SS1_B_ETM_SQ32EVR" hexmask.long 0x50 0.--31. 1. "MSS_R5SS1_ETM_EXTOUTEVR1,Not Defined" line.long 0x54 "DEBUGSS_MSS_R5SS1_B_ETM_SQ13EVR" hexmask.long 0x54 0.--31. 1. "MSS_R5SS1_ETM_EXTOUTEVR2,Not Defined" group.long 0x5D19C++0x1B line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_SQR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_EXTOUTEVR3,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_ETM_EXTOUTEVR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_EXTOUTEVR4,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_ETM_EXTOUTEVR2" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_ETM_CIDCVR1,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_B_ETM_EXTOUTEVR3" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_ETM_CIDCVR2,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_B_ETM_EXTOUTEVR4" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_ETM_CIDCVR3,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS1_B_ETM_CIDCVR1" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_ETM_CIDCMR,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS1_B_ETM_CIDCVR2" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_ETM_SYNCFR,Not Defined" rgroup.long 0x5D1B8++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_CIDCVR3" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_IDR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_ETM_CIDCMR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_CCER,Not Defined" group.long 0x5D1E0++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_SYNCFR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_EXTINSELR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_ETM_IDR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_TRACEIDR,Not Defined" rgroup.long 0x5D1E8++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_CCER" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_PDSR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_ETM_EXTINSELR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_ITETMIF,Not Defined" wgroup.long 0x5D200++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_TRACEIDR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_ITMISCOUT,Not Defined" rgroup.long 0x5D314++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_PDSR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_ITMISCIN,Not Defined" rgroup.long 0x5DED8++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_ITETMIF" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_ITTRIGGERACK,Not Defined" wgroup.long 0x5DEDC++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_ITMISCOUT" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_ITTRIGGERREQ,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_ETM_ITMISCIN" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_ITATBDATA0,Not Defined" rgroup.long 0x5DEE4++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_ITTRIGGERACK" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_ITATBCTR2,Not Defined" wgroup.long 0x5DEE8++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_ITTRIGGERREQ" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_ITATBCTR1,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_ETM_ITATBDATA0" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_ITATBCTR0,Not Defined" group.long 0x5DEF0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_ITATBCTR2" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_ITCTRL,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_ETM_ITATBCTR1" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_CLAIMSET,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_ETM_ITATBCTR0" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_ETM_CLAIMCLR,Not Defined" wgroup.long 0x5DF00++0x3 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_ITCTRL" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_LAR,Not Defined" rgroup.long 0x5DFA0++0x7 line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_CLAIMSET" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_LSR,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_ETM_CLAIMCLR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_AUTHSTATUS,Not Defined" rgroup.long 0x5DFB0++0xB line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_LAR" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_DEVID,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_ETM_LSR" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_DEVTYPE,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_ETM_AUTHSTATUS" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_ETM_PIDR4,Not Defined" rgroup.long 0x5DFC8++0x2B line.long 0x0 "DEBUGSS_MSS_R5SS1_B_ETM_DEVID" hexmask.long 0x0 0.--31. 1. "MSS_R5SS1_ETM_PIDR5,Not Defined" line.long 0x4 "DEBUGSS_MSS_R5SS1_B_ETM_DEVTYPE" hexmask.long 0x4 0.--31. 1. "MSS_R5SS1_ETM_PIDR6,Not Defined" line.long 0x8 "DEBUGSS_MSS_R5SS1_B_ETM_PIDR4" hexmask.long 0x8 0.--31. 1. "MSS_R5SS1_ETM_PIDR7,Not Defined" line.long 0xC "DEBUGSS_MSS_R5SS1_B_ETM_PIDR5" hexmask.long 0xC 0.--31. 1. "MSS_R5SS1_ETM_PIDR0,Not Defined" line.long 0x10 "DEBUGSS_MSS_R5SS1_B_ETM_PIDR6" hexmask.long 0x10 0.--31. 1. "MSS_R5SS1_ETM_PIDR1,Not Defined" line.long 0x14 "DEBUGSS_MSS_R5SS1_B_ETM_PIDR7" hexmask.long 0x14 0.--31. 1. "MSS_R5SS1_ETM_PIDR2,Not Defined" line.long 0x18 "DEBUGSS_MSS_R5SS1_B_ETM_PIDR0" hexmask.long 0x18 0.--31. 1. "MSS_R5SS1_ETM_PIDR3,Not Defined" line.long 0x1C "DEBUGSS_MSS_R5SS1_B_ETM_PIDR1" hexmask.long 0x1C 0.--31. 1. "MSS_R5SS1_ETM_CIDR0,Not Defined" line.long 0x20 "DEBUGSS_MSS_R5SS1_B_ETM_PIDR2" hexmask.long 0x20 0.--31. 1. "MSS_R5SS1_ETM_CIDR1,Not Defined" line.long 0x24 "DEBUGSS_MSS_R5SS1_B_ETM_PIDR3" hexmask.long 0x24 0.--31. 1. "MSS_R5SS1_ETM_CIDR2,Not Defined" line.long 0x28 "DEBUGSS_MSS_R5SS1_B_ETM_CIDR0" hexmask.long 0x28 0.--31. 1. "MSS_R5SS1_ETM_CIDR3,Not Defined" tree.end tree "ECC_AGG" base ad:0x0 tree "ECC_AGG_R5SS0_CORE0" base ad:0x53000000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE0_REV" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE0_VECTOR" rbitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.word 0xC++0x1 line.word 0x0 "ECC_AGG_R5SS0_CORE0_STAT" hexmask.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE0_WRAP_REV" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.word 0x14++0x1 line.word 0x0 "ECC_AGG_R5SS0_CORE0_CTRL" bitfld.word 0x0 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1" bitfld.word 0x0 7. "CHECK_PARITY,check for parity errors" "0,1" newline bitfld.word 0x0 6. "ERROR_ONCE,Force Error only once" "0,1" bitfld.word 0x0 5. "FORCE_N_ROW,Force Error on any RAM read" "0,1" newline bitfld.word 0x0 4. "FORCE_DED,Force Double Bit Error" "0,1" bitfld.word 0x0 3. "FORCE_SEC,Force Single Bit Error" "0,1" newline bitfld.word 0x0 2. "ENABLE_RMW,Enable rmw" "0,1" bitfld.word 0x0 1. "ECC_CHECK,Enable ECC check" "0,1" newline bitfld.word 0x0 0. "ECC_ENABLE,Enable ECC" "0,1" group.long 0x18++0xB line.long 0x0 "ECC_AGG_R5SS0_CORE0_ERR_CTRL1" hexmask.long 0x0 0.--31. 1. "ECC_ROW,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x4 "ECC_AGG_R5SS0_CORE0_ERR_CTRL2" hexmask.long.word 0x4 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x4 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set" line.long 0x8 "ECC_AGG_R5SS0_CORE0_ERR_STAT1" hexmask.long.word 0x8 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error" bitfld.long 0x8 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1" newline bitfld.long 0x8 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3" bitfld.long 0x8 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1" newline bitfld.long 0x8 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3" bitfld.long 0x8 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3" newline bitfld.long 0x8 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1" bitfld.long 0x8 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3" newline bitfld.long 0x8 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1" bitfld.long 0x8 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3" newline bitfld.long 0x8 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE0_ERR_STAT2" hexmask.long 0x0 0.--31. 1. "ECC_ROW,Row address where the single or double-bit error has occurred" group.word 0x28++0x1 line.word 0x0 "ECC_AGG_R5SS0_CORE0_ERR_STAT3" bitfld.word 0x0 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1" bitfld.word 0x0 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1" newline rbitfld.word 0x0 0. "WB_PEND,delayed write back pending Status" "0,1" group.long 0x3C++0x7 line.long 0x0 "ECC_AGG_R5SS0_CORE0_SEC_EOI_REG" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGG_R5SS0_CORE0_SEC_STATUS_REG0" bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE0_SEC_ENABLE_SET_REG0" bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE0_SEC_ENABLE_CLR_REG0" bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGG_R5SS0_CORE0_DED_EOI_REG" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGG_R5SS0_CORE0_DED_STATUS_REG0" bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE0_DED_ENABLE_SET_REG0" bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE0_DED_ENABLE_CLR_REG0" bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1" group.byte 0x200++0x0 line.byte 0x0 "ECC_AGG_R5SS0_CORE0_AGGR_ENABLE_SET" bitfld.byte 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.byte 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" group.byte 0x204++0x0 line.byte 0x0 "ECC_AGG_R5SS0_CORE0_AGGR_ENABLE_CLR" bitfld.byte 0x0 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.byte 0x0 0. "PARITY,interrupt enable clear for parity errors" "0,1" group.byte 0x208++0x0 line.byte 0x0 "ECC_AGG_R5SS0_CORE0_AGGR_STATUS_SET" bitfld.byte 0x0 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.byte 0x0 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" group.byte 0x20C++0x0 line.byte 0x0 "ECC_AGG_R5SS0_CORE0_AGGR_STATUS_CLR" bitfld.byte 0x0 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.byte 0x0 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "ECC_AGG_R5SS0_CORE1" base ad:0x53003000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE1_REV" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE1_VECTOR" rbitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.word 0xC++0x1 line.word 0x0 "ECC_AGG_R5SS0_CORE1_STAT" hexmask.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE1_WRAP_REV" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.word 0x14++0x1 line.word 0x0 "ECC_AGG_R5SS0_CORE1_CTRL" bitfld.word 0x0 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1" bitfld.word 0x0 7. "CHECK_PARITY,check for parity errors" "0,1" newline bitfld.word 0x0 6. "ERROR_ONCE,Force Error only once" "0,1" bitfld.word 0x0 5. "FORCE_N_ROW,Force Error on any RAM read" "0,1" newline bitfld.word 0x0 4. "FORCE_DED,Force Double Bit Error" "0,1" bitfld.word 0x0 3. "FORCE_SEC,Force Single Bit Error" "0,1" newline bitfld.word 0x0 2. "ENABLE_RMW,Enable rmw" "0,1" bitfld.word 0x0 1. "ECC_CHECK,Enable ECC check" "0,1" newline bitfld.word 0x0 0. "ECC_ENABLE,Enable ECC" "0,1" group.long 0x18++0xB line.long 0x0 "ECC_AGG_R5SS0_CORE1_ERR_CTRL1" hexmask.long 0x0 0.--31. 1. "ECC_ROW,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x4 "ECC_AGG_R5SS0_CORE1_ERR_CTRL2" hexmask.long.word 0x4 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x4 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set" line.long 0x8 "ECC_AGG_R5SS0_CORE1_ERR_STAT1" hexmask.long.word 0x8 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error" bitfld.long 0x8 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1" newline bitfld.long 0x8 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3" bitfld.long 0x8 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1" newline bitfld.long 0x8 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3" bitfld.long 0x8 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3" newline bitfld.long 0x8 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1" bitfld.long 0x8 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3" newline bitfld.long 0x8 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1" bitfld.long 0x8 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3" newline bitfld.long 0x8 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE1_ERR_STAT2" hexmask.long 0x0 0.--31. 1. "ECC_ROW,Row address where the single or double-bit error has occurred" group.word 0x28++0x1 line.word 0x0 "ECC_AGG_R5SS0_CORE1_ERR_STAT3" bitfld.word 0x0 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1" bitfld.word 0x0 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1" newline rbitfld.word 0x0 0. "WB_PEND,delayed write back pending Status" "0,1" group.long 0x3C++0x7 line.long 0x0 "ECC_AGG_R5SS0_CORE1_SEC_EOI_REG" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGG_R5SS0_CORE1_SEC_STATUS_REG0" bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE1_SEC_ENABLE_SET_REG0" bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE1_SEC_ENABLE_CLR_REG0" bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGG_R5SS0_CORE1_DED_EOI_REG" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGG_R5SS0_CORE1_DED_STATUS_REG0" bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE1_DED_ENABLE_SET_REG0" bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGG_R5SS0_CORE1_DED_ENABLE_CLR_REG0" bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1" group.byte 0x200++0x0 line.byte 0x0 "ECC_AGG_R5SS0_CORE1_AGGR_ENABLE_SET" bitfld.byte 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.byte 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" group.byte 0x204++0x0 line.byte 0x0 "ECC_AGG_R5SS0_CORE1_AGGR_ENABLE_CLR" bitfld.byte 0x0 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.byte 0x0 0. "PARITY,interrupt enable clear for parity errors" "0,1" group.byte 0x208++0x0 line.byte 0x0 "ECC_AGG_R5SS0_CORE1_AGGR_STATUS_SET" bitfld.byte 0x0 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.byte 0x0 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" group.byte 0x20C++0x0 line.byte 0x0 "ECC_AGG_R5SS0_CORE1_AGGR_STATUS_CLR" bitfld.byte 0x0 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.byte 0x0 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "ECC_AGG_R5SS1_CORE0" base ad:0x53004000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE0_REV" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE0_VECTOR" rbitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.word 0xC++0x1 line.word 0x0 "ECC_AGG_R5SS1_CORE0_STAT" hexmask.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE0_WRAP_REV" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.word 0x14++0x1 line.word 0x0 "ECC_AGG_R5SS1_CORE0_CTRL" bitfld.word 0x0 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1" bitfld.word 0x0 7. "CHECK_PARITY,check for parity errors" "0,1" newline bitfld.word 0x0 6. "ERROR_ONCE,Force Error only once" "0,1" bitfld.word 0x0 5. "FORCE_N_ROW,Force Error on any RAM read" "0,1" newline bitfld.word 0x0 4. "FORCE_DED,Force Double Bit Error" "0,1" bitfld.word 0x0 3. "FORCE_SEC,Force Single Bit Error" "0,1" newline bitfld.word 0x0 2. "ENABLE_RMW,Enable rmw" "0,1" bitfld.word 0x0 1. "ECC_CHECK,Enable ECC check" "0,1" newline bitfld.word 0x0 0. "ECC_ENABLE,Enable ECC" "0,1" group.long 0x18++0xB line.long 0x0 "ECC_AGG_R5SS1_CORE0_ERR_CTRL1" hexmask.long 0x0 0.--31. 1. "ECC_ROW,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x4 "ECC_AGG_R5SS1_CORE0_ERR_CTRL2" hexmask.long.word 0x4 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x4 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set" line.long 0x8 "ECC_AGG_R5SS1_CORE0_ERR_STAT1" hexmask.long.word 0x8 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error" bitfld.long 0x8 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1" newline bitfld.long 0x8 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3" bitfld.long 0x8 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1" newline bitfld.long 0x8 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3" bitfld.long 0x8 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3" newline bitfld.long 0x8 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1" bitfld.long 0x8 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3" newline bitfld.long 0x8 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1" bitfld.long 0x8 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3" newline bitfld.long 0x8 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE0_ERR_STAT2" hexmask.long 0x0 0.--31. 1. "ECC_ROW,Row address where the single or double-bit error has occurred" group.word 0x28++0x1 line.word 0x0 "ECC_AGG_R5SS1_CORE0_ERR_STAT3" bitfld.word 0x0 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1" bitfld.word 0x0 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1" newline rbitfld.word 0x0 0. "WB_PEND,delayed write back pending Status" "0,1" group.long 0x3C++0x7 line.long 0x0 "ECC_AGG_R5SS1_CORE0_SEC_EOI_REG" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGG_R5SS1_CORE0_SEC_STATUS_REG0" bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE0_SEC_ENABLE_SET_REG0" bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE0_SEC_ENABLE_CLR_REG0" bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGG_R5SS1_CORE0_DED_EOI_REG" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGG_R5SS1_CORE0_DED_STATUS_REG0" bitfld.long 0x4 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE0_DED_ENABLE_SET_REG0" bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE0_DED_ENABLE_CLR_REG0" bitfld.long 0x0 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1" group.byte 0x200++0x0 line.byte 0x0 "ECC_AGG_R5SS1_CORE0_AGGR_ENABLE_SET" bitfld.byte 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.byte 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" group.byte 0x204++0x0 line.byte 0x0 "ECC_AGG_R5SS1_CORE0_AGGR_ENABLE_CLR" bitfld.byte 0x0 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.byte 0x0 0. "PARITY,interrupt enable clear for parity errors" "0,1" group.byte 0x208++0x0 line.byte 0x0 "ECC_AGG_R5SS1_CORE0_AGGR_STATUS_SET" bitfld.byte 0x0 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.byte 0x0 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" group.byte 0x20C++0x0 line.byte 0x0 "ECC_AGG_R5SS1_CORE0_AGGR_STATUS_CLR" bitfld.byte 0x0 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.byte 0x0 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "ECC_AGG_R5SS1_CORE1" base ad:0x53007000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE1_REV" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE1_VECTOR" rbitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" newline bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.word 0xC++0x1 line.word 0x0 "ECC_AGG_R5SS1_CORE1_STAT" hexmask.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" rgroup.long 0x10++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE1_WRAP_REV" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" newline bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.word 0x14++0x1 line.word 0x0 "ECC_AGG_R5SS1_CORE1_CTRL" bitfld.word 0x0 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1" bitfld.word 0x0 7. "CHECK_PARITY,check for parity errors" "0,1" newline bitfld.word 0x0 6. "ERROR_ONCE,Force Error only once" "0,1" bitfld.word 0x0 5. "FORCE_N_ROW,Force Error on any RAM read" "0,1" newline bitfld.word 0x0 4. "FORCE_DED,Force Double Bit Error" "0,1" bitfld.word 0x0 3. "FORCE_SEC,Force Single Bit Error" "0,1" newline bitfld.word 0x0 2. "ENABLE_RMW,Enable rmw" "0,1" bitfld.word 0x0 1. "ECC_CHECK,Enable ECC check" "0,1" newline bitfld.word 0x0 0. "ECC_ENABLE,Enable ECC" "0,1" group.long 0x18++0xB line.long 0x0 "ECC_AGG_R5SS1_CORE1_ERR_CTRL1" hexmask.long 0x0 0.--31. 1. "ECC_ROW,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x4 "ECC_AGG_R5SS1_CORE1_ERR_CTRL2" hexmask.long.word 0x4 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x4 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set" line.long 0x8 "ECC_AGG_R5SS1_CORE1_ERR_STAT1" hexmask.long.word 0x8 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error" bitfld.long 0x8 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1" newline bitfld.long 0x8 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3" bitfld.long 0x8 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1" newline bitfld.long 0x8 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3" bitfld.long 0x8 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3" newline bitfld.long 0x8 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1" bitfld.long 0x8 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3" newline bitfld.long 0x8 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1" bitfld.long 0x8 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3" newline bitfld.long 0x8 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE1_ERR_STAT2" hexmask.long 0x0 0.--31. 1. "ECC_ROW,Row address where the single or double-bit error has occurred" group.word 0x28++0x1 line.word 0x0 "ECC_AGG_R5SS1_CORE1_ERR_STAT3" bitfld.word 0x0 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1" bitfld.word 0x0 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1" newline rbitfld.word 0x0 0. "WB_PEND,delayed write back pending Status" "0,1" group.long 0x3C++0x7 line.long 0x0 "ECC_AGG_R5SS1_CORE1_SEC_EOI_REG" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGG_R5SS1_CORE1_SEC_STATUS_REG0" bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1" group.long 0x80++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE1_SEC_ENABLE_SET_REG0" bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1" group.long 0xC0++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE1_SEC_ENABLE_CLR_REG0" bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1" group.long 0x13C++0x7 line.long 0x0 "ECC_AGG_R5SS1_CORE1_DED_EOI_REG" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" line.long 0x4 "ECC_AGG_R5SS1_CORE1_DED_STATUS_REG0" bitfld.long 0x4 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x4 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1" bitfld.long 0x4 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x4 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1" bitfld.long 0x4 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1" newline bitfld.long 0x4 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1" bitfld.long 0x4 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x4 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x4 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x4 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x4 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x4 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x4 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x4 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x4 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x4 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x4 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x4 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x4 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x4 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x4 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x4 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x4 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x4 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x4 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x4 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x4 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1" group.long 0x180++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE1_DED_ENABLE_SET_REG0" bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1" group.long 0x1C0++0x3 line.long 0x0 "ECC_AGG_R5SS1_CORE1_DED_ENABLE_CLR_REG0" bitfld.long 0x0 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1" bitfld.long 0x0 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1" bitfld.long 0x0 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1" newline bitfld.long 0x0 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1" bitfld.long 0x0 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1" newline bitfld.long 0x0 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1" bitfld.long 0x0 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1" newline bitfld.long 0x0 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1" bitfld.long 0x0 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1" newline bitfld.long 0x0 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1" bitfld.long 0x0 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1" newline bitfld.long 0x0 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1" bitfld.long 0x0 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1" newline bitfld.long 0x0 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1" bitfld.long 0x0 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1" newline bitfld.long 0x0 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1" bitfld.long 0x0 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1" newline bitfld.long 0x0 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1" bitfld.long 0x0 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1" newline bitfld.long 0x0 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1" bitfld.long 0x0 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1" newline bitfld.long 0x0 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1" bitfld.long 0x0 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1" newline bitfld.long 0x0 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1" bitfld.long 0x0 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1" newline bitfld.long 0x0 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1" bitfld.long 0x0 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1" group.byte 0x200++0x0 line.byte 0x0 "ECC_AGG_R5SS1_CORE1_AGGR_ENABLE_SET" bitfld.byte 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.byte 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" group.byte 0x204++0x0 line.byte 0x0 "ECC_AGG_R5SS1_CORE1_AGGR_ENABLE_CLR" bitfld.byte 0x0 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.byte 0x0 0. "PARITY,interrupt enable clear for parity errors" "0,1" group.byte 0x208++0x0 line.byte 0x0 "ECC_AGG_R5SS1_CORE1_AGGR_STATUS_SET" bitfld.byte 0x0 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.byte 0x0 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" group.byte 0x20C++0x0 line.byte 0x0 "ECC_AGG_R5SS1_CORE1_AGGR_STATUS_CLR" bitfld.byte 0x0 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.byte 0x0 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree "ECC_AGG_TOP" base ad:0x53010000 rgroup.long 0x0++0x3 line.long 0x0 "ECC_AGG_TOP_REV" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "ECC_AGG_TOP_VECTOR" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDRESS,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status" rgroup.word 0xC++0x1 line.word 0x0 "ECC_AGG_TOP_STAT" hexmask.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.word 0x14++0x1 line.word 0x0 "ECC_AGG_TOP_CTRL" bitfld.word 0x0 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1" bitfld.word 0x0 7. "CHECK_PARITY,check for parity errors" "0,1" bitfld.word 0x0 6. "ERROR_ONCE,Force Error only once" "0,1" newline bitfld.word 0x0 5. "FORCE_N_ROW,Force Error on any RAM read" "0,1" bitfld.word 0x0 4. "FORCE_DED,Force Double Bit Error" "0,1" bitfld.word 0x0 3. "FORCE_SEC,Force Single Bit Error" "0,1" newline bitfld.word 0x0 2. "ENABLE_RMW,Enable rmw" "0,1" bitfld.word 0x0 1. "ECC_CHECK,Enable ECC check" "0,1" bitfld.word 0x0 0. "ECC_ENABLE,Enable ECC" "0,1" group.long 0x18++0xB line.long 0x0 "ECC_AGG_TOP_ERR_CTRL1" hexmask.long 0x0 0.--31. 1. "ECC_ROW,Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x4 "ECC_AGG_TOP_ERR_CTRL2" hexmask.long.word 0x4 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x4 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set" line.long 0x8 "ECC_AGG_TOP_ERR_STAT1" hexmask.long.word 0x8 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error" bitfld.long 0x8 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1" bitfld.long 0x8 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3" newline bitfld.long 0x8 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1" bitfld.long 0x8 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3" bitfld.long 0x8 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3" newline bitfld.long 0x8 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1" bitfld.long 0x8 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3" bitfld.long 0x8 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1" newline bitfld.long 0x8 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3" bitfld.long 0x8 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "ECC_AGG_TOP_ERR_STAT2" hexmask.long 0x0 0.--31. 1. "ECC_ROW,Row address where the single or double-bit error has occurred" group.word 0x28++0x1 line.word 0x0 "ECC_AGG_TOP_ERR_STAT3" bitfld.word 0x0 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1" bitfld.word 0x0 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1" rbitfld.word 0x0 0. "WB_PEND,delayed write back pending Status" "0,1" group.long 0x3C++0x3 line.long 0x0 "ECC_AGG_TOP_SEC_EOI_REG" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" group.byte 0x40++0x0 line.byte 0x0 "ECC_AGG_TOP_SEC_STATUS_REG0" bitfld.byte 0x0 6. "TPTC_A1_PEND,Interrupt Pending Status for tptc_a1_pend" "0,1" bitfld.byte 0x0 5. "TPTC_A0_PEND,Interrupt Pending Status for tptc_a0_pend" "0,1" bitfld.byte 0x0 4. "MSS_MBOX_PEND,Interrupt Pending Status for mss_mbox_pend" "0,1" newline bitfld.byte 0x0 3. "MSS_L2SLV3_PEND,Interrupt Pending Status for mss_l2slv3_pend" "0,1" bitfld.byte 0x0 2. "MSS_L2SLV2_PEND,Interrupt Pending Status for mss_l2slv2_pend" "0,1" bitfld.byte 0x0 1. "MSS_L2SLV1_PEND,Interrupt Pending Status for mss_l2slv1_pend" "0,1" newline bitfld.byte 0x0 0. "MSS_L2SLV0_PEND,Interrupt Pending Status for mss_l2slv0_pend" "0,1" group.byte 0x80++0x0 line.byte 0x0 "ECC_AGG_TOP_SEC_ENABLE_SET_REG0" bitfld.byte 0x0 6. "TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for tptc_a1_pend" "0,1" bitfld.byte 0x0 5. "TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for tptc_a0_pend" "0,1" bitfld.byte 0x0 4. "MSS_MBOX_ENABLE_SET,Interrupt Enable Set Register for mss_mbox_pend" "0,1" newline bitfld.byte 0x0 3. "MSS_L2SLV3_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv3_pend" "0,1" bitfld.byte 0x0 2. "MSS_L2SLV2_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv2_pend" "0,1" bitfld.byte 0x0 1. "MSS_L2SLV1_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv1_pend" "0,1" newline bitfld.byte 0x0 0. "MSS_L2SLV0_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv0_pend" "0,1" group.byte 0xC0++0x0 line.byte 0x0 "ECC_AGG_TOP_SEC_ENABLE_CLR_REG0" bitfld.byte 0x0 6. "TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a1_pend" "0,1" bitfld.byte 0x0 5. "TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a0_pend" "0,1" bitfld.byte 0x0 4. "MSS_MBOX_ENABLE_CLR,Interrupt Enable Clear Register for mss_mbox_pend" "0,1" newline bitfld.byte 0x0 3. "MSS_L2SLV3_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv3_pend" "0,1" bitfld.byte 0x0 2. "MSS_L2SLV2_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv2_pend" "0,1" bitfld.byte 0x0 1. "MSS_L2SLV1_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv1_pend" "0,1" newline bitfld.byte 0x0 0. "MSS_L2SLV0_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv0_pend" "0,1" group.long 0x13C++0x3 line.long 0x0 "ECC_AGG_TOP_DED_EOI_REG" bitfld.long 0x0 0. "EOI_WR,EOI Register" "0,1" group.byte 0x140++0x0 line.byte 0x0 "ECC_AGG_TOP_DED_STATUS_REG0" bitfld.byte 0x0 6. "TPTC_A1_PEND,Interrupt Pending Status for tptc_a1_pend" "0,1" bitfld.byte 0x0 5. "TPTC_A0_PEND,Interrupt Pending Status for tptc_a0_pend" "0,1" bitfld.byte 0x0 4. "MSS_MBOX_PEND,Interrupt Pending Status for mss_mbox_pend" "0,1" newline bitfld.byte 0x0 3. "MSS_L2SLV3_PEND,Interrupt Pending Status for mss_l2slv3_pend" "0,1" bitfld.byte 0x0 2. "MSS_L2SLV2_PEND,Interrupt Pending Status for mss_l2slv2_pend" "0,1" bitfld.byte 0x0 1. "MSS_L2SLV1_PEND,Interrupt Pending Status for mss_l2slv1_pend" "0,1" newline bitfld.byte 0x0 0. "MSS_L2SLV0_PEND,Interrupt Pending Status for mss_l2slv0_pend" "0,1" group.byte 0x180++0x0 line.byte 0x0 "ECC_AGG_TOP_DED_ENABLE_SET_REG0" bitfld.byte 0x0 6. "TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for tptc_a1_pend" "0,1" bitfld.byte 0x0 5. "TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for tptc_a0_pend" "0,1" bitfld.byte 0x0 4. "MSS_MBOX_ENABLE_SET,Interrupt Enable Set Register for mss_mbox_pend" "0,1" newline bitfld.byte 0x0 3. "MSS_L2SLV3_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv3_pend" "0,1" bitfld.byte 0x0 2. "MSS_L2SLV2_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv2_pend" "0,1" bitfld.byte 0x0 1. "MSS_L2SLV1_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv1_pend" "0,1" newline bitfld.byte 0x0 0. "MSS_L2SLV0_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv0_pend" "0,1" group.byte 0x1C0++0x0 line.byte 0x0 "ECC_AGG_TOP_DED_ENABLE_CLR_REG0" bitfld.byte 0x0 6. "TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a1_pend" "0,1" bitfld.byte 0x0 5. "TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a0_pend" "0,1" bitfld.byte 0x0 4. "MSS_MBOX_ENABLE_CLR,Interrupt Enable Clear Register for mss_mbox_pend" "0,1" newline bitfld.byte 0x0 3. "MSS_L2SLV3_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv3_pend" "0,1" bitfld.byte 0x0 2. "MSS_L2SLV2_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv2_pend" "0,1" bitfld.byte 0x0 1. "MSS_L2SLV1_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv1_pend" "0,1" newline bitfld.byte 0x0 0. "MSS_L2SLV0_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv0_pend" "0,1" group.byte 0x200++0x0 line.byte 0x0 "ECC_AGG_TOP_AGGR_ENABLE_SET" bitfld.byte 0x0 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1" bitfld.byte 0x0 0. "PARITY,interrupt enable set for parity errors" "0,1" group.byte 0x204++0x0 line.byte 0x0 "ECC_AGG_TOP_AGGR_ENABLE_CLR" bitfld.byte 0x0 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1" bitfld.byte 0x0 0. "PARITY,interrupt enable clear for parity errors" "0,1" group.byte 0x208++0x0 line.byte 0x0 "ECC_AGG_TOP_AGGR_STATUS_SET" bitfld.byte 0x0 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3" bitfld.byte 0x0 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3" group.byte 0x20C++0x0 line.byte 0x0 "ECC_AGG_TOP_AGGR_STATUS_CLR" bitfld.byte 0x0 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3" bitfld.byte 0x0 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3" tree.end tree.end tree "EDMA_TRIG_XBAR" base ad:0x52E01000 rgroup.long 0x0++0x3 line.long 0x0 "EDMA_TRIG_XBAR_PID" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "EDMA_TRIG_XBAR_MUXCNTL" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENABLE,Mux control for interrupt N" tree.end tree "EXT_FLASH" base ad:0x0 tree "EXT_FLASH0" base ad:0x60000000 group.long 0x0++0x3 line.long 0x0 "EXT_FLASH0_EXT_FLASH_START" hexmask.long 0x0 0.--31. 1. "MEM_START,External flash start Address" group.long 0x1FFFFFC++0x3 line.long 0x0 "EXT_FLASH0_EXT_FLASH_END" hexmask.long 0x0 0.--31. 1. "MEM_END,External flash end address" tree.end tree "EXT_FLASH1" base ad:0x62000000 group.long 0x0++0x3 line.long 0x0 "EXT_FLASH0_EXT_FLASH_START" hexmask.long 0x0 0.--31. 1. "MEM_START,External flash start Address" group.long 0x1FFFFFC++0x3 line.long 0x0 "EXT_FLASH0_EXT_FLASH_END" hexmask.long 0x0 0.--31. 1. "MEM_END,External flash end address" tree.end tree.end tree "GPIO" base ad:0x0 tree "GPIO0" base ad:0x52000000 rgroup.long 0x0++0x3 line.long 0x0 "GPIO0_PID" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" rgroup.byte 0x4++0x0 line.byte 0x0 "GPIO0_PCR" bitfld.byte 0x0 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.byte 0x0 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" group.long 0x8++0x3 line.long 0x0 "GPIO0_BINTEN" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." group.long 0x10++0xF line.long 0x0 "GPIO0_DIR01" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "GPIO0_OUT_DATA01" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "GPIO0_SET_DATA01" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "GPIO0_CLR_DATA01" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "GPIO0_IN_DATA01" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." group.long 0x24++0x23 line.long 0x0 "GPIO0_SET_RIS_TRIG01" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "GPIO0_CLR_RIS_TRIG01" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "GPIO0_SET_FAL_TRIG01" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "GPIO0_CLR_FAL_TRIG01" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "GPIO0_INTSTAT01" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO0_DIR23" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "GPIO0_OUT_DATA23" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO0_SET_DATA23" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "GPIO0_CLR_DATA23" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "GPIO0_IN_DATA23" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." group.long 0x4C++0x23 line.long 0x0 "GPIO0_SET_RIS_TRIG23" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "GPIO0_CLR_RIS_TRIG23" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "GPIO0_SET_FAL_TRIG23" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "GPIO0_CLR_FAL_TRIG23" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "GPIO0_INTSTAT23" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO0_DIR45" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "GPIO0_OUT_DATA45" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO0_SET_DATA45" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "GPIO0_CLR_DATA45" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "GPIO0_IN_DATA45" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." group.long 0x74++0x23 line.long 0x0 "GPIO0_SET_RIS_TRIG45" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "GPIO0_CLR_RIS_TRIG45" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "GPIO0_SET_FAL_TRIG45" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "GPIO0_CLR_FAL_TRIG45" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "GPIO0_INTSTAT45" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO0_DIR67" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "GPIO0_OUT_DATA67" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO0_SET_DATA67" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "GPIO0_CLR_DATA67" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "GPIO0_IN_DATA67" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." group.long 0x9C++0x23 line.long 0x0 "GPIO0_SET_RIS_TRIG67" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "GPIO0_CLR_RIS_TRIG67" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "GPIO0_SET_FAL_TRIG67" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "GPIO0_CLR_FAL_TRIG67" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "GPIO0_INTSTAT67" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO0_DIR8" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "GPIO0_OUT_DATA8" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO0_SET_DATA8" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "GPIO0_CLR_DATA8" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "GPIO0_IN_DATA8" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." group.word 0xC4++0x1 line.word 0x0 "GPIO0_SET_RIS_TRIG8" hexmask.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." group.word 0xC8++0x1 line.word 0x0 "GPIO0_CLR_RIS_TRIG8" hexmask.word 0x0 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." group.word 0xCC++0x1 line.word 0x0 "GPIO0_SET_FAL_TRIG8" hexmask.word 0x0 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." group.word 0xD0++0x1 line.word 0x0 "GPIO0_CLR_FAL_TRIG8" hexmask.word 0x0 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." group.long 0xD4++0x3 line.long 0x0 "GPIO0_INTSTAT8" hexmask.long.word 0x0 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree "GPIO1" base ad:0x52001000 rgroup.long 0x0++0x3 line.long 0x0 "GPIO1_PID" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" rgroup.byte 0x4++0x0 line.byte 0x0 "GPIO1_PCR" bitfld.byte 0x0 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.byte 0x0 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" group.long 0x8++0x3 line.long 0x0 "GPIO1_BINTEN" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." group.long 0x10++0xF line.long 0x0 "GPIO1_DIR01" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "GPIO1_OUT_DATA01" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "GPIO1_SET_DATA01" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "GPIO1_CLR_DATA01" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "GPIO1_IN_DATA01" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." group.long 0x24++0x23 line.long 0x0 "GPIO1_SET_RIS_TRIG01" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "GPIO1_CLR_RIS_TRIG01" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "GPIO1_SET_FAL_TRIG01" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "GPIO1_CLR_FAL_TRIG01" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "GPIO1_INTSTAT01" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO1_DIR23" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "GPIO1_OUT_DATA23" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO1_SET_DATA23" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "GPIO1_CLR_DATA23" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "GPIO1_IN_DATA23" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." group.long 0x4C++0x23 line.long 0x0 "GPIO1_SET_RIS_TRIG23" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "GPIO1_CLR_RIS_TRIG23" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "GPIO1_SET_FAL_TRIG23" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "GPIO1_CLR_FAL_TRIG23" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "GPIO1_INTSTAT23" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO1_DIR45" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "GPIO1_OUT_DATA45" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO1_SET_DATA45" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "GPIO1_CLR_DATA45" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "GPIO1_IN_DATA45" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." group.long 0x74++0x23 line.long 0x0 "GPIO1_SET_RIS_TRIG45" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "GPIO1_CLR_RIS_TRIG45" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "GPIO1_SET_FAL_TRIG45" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "GPIO1_CLR_FAL_TRIG45" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "GPIO1_INTSTAT45" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO1_DIR67" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "GPIO1_OUT_DATA67" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO1_SET_DATA67" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "GPIO1_CLR_DATA67" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "GPIO1_IN_DATA67" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." group.long 0x9C++0x23 line.long 0x0 "GPIO1_SET_RIS_TRIG67" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "GPIO1_CLR_RIS_TRIG67" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "GPIO1_SET_FAL_TRIG67" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "GPIO1_CLR_FAL_TRIG67" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "GPIO1_INTSTAT67" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO1_DIR8" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "GPIO1_OUT_DATA8" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO1_SET_DATA8" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "GPIO1_CLR_DATA8" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "GPIO1_IN_DATA8" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." group.word 0xC4++0x1 line.word 0x0 "GPIO1_SET_RIS_TRIG8" hexmask.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." group.word 0xC8++0x1 line.word 0x0 "GPIO1_CLR_RIS_TRIG8" hexmask.word 0x0 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." group.word 0xCC++0x1 line.word 0x0 "GPIO1_SET_FAL_TRIG8" hexmask.word 0x0 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." group.word 0xD0++0x1 line.word 0x0 "GPIO1_CLR_FAL_TRIG8" hexmask.word 0x0 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." group.long 0xD4++0x3 line.long 0x0 "GPIO1_INTSTAT8" hexmask.long.word 0x0 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree "GPIO2" base ad:0x52002000 rgroup.long 0x0++0x3 line.long 0x0 "GPIO2_PID" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" rgroup.byte 0x4++0x0 line.byte 0x0 "GPIO2_PCR" bitfld.byte 0x0 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.byte 0x0 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" group.long 0x8++0x3 line.long 0x0 "GPIO2_BINTEN" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." group.long 0x10++0xF line.long 0x0 "GPIO2_DIR01" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "GPIO2_OUT_DATA01" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "GPIO2_SET_DATA01" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "GPIO2_CLR_DATA01" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "GPIO2_IN_DATA01" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." group.long 0x24++0x23 line.long 0x0 "GPIO2_SET_RIS_TRIG01" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "GPIO2_CLR_RIS_TRIG01" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "GPIO2_SET_FAL_TRIG01" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "GPIO2_CLR_FAL_TRIG01" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "GPIO2_INTSTAT01" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO2_DIR23" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "GPIO2_OUT_DATA23" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO2_SET_DATA23" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "GPIO2_CLR_DATA23" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "GPIO2_IN_DATA23" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." group.long 0x4C++0x23 line.long 0x0 "GPIO2_SET_RIS_TRIG23" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "GPIO2_CLR_RIS_TRIG23" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "GPIO2_SET_FAL_TRIG23" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "GPIO2_CLR_FAL_TRIG23" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "GPIO2_INTSTAT23" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO2_DIR45" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "GPIO2_OUT_DATA45" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO2_SET_DATA45" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "GPIO2_CLR_DATA45" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "GPIO2_IN_DATA45" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." group.long 0x74++0x23 line.long 0x0 "GPIO2_SET_RIS_TRIG45" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "GPIO2_CLR_RIS_TRIG45" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "GPIO2_SET_FAL_TRIG45" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "GPIO2_CLR_FAL_TRIG45" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "GPIO2_INTSTAT45" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO2_DIR67" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "GPIO2_OUT_DATA67" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO2_SET_DATA67" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "GPIO2_CLR_DATA67" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "GPIO2_IN_DATA67" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." group.long 0x9C++0x23 line.long 0x0 "GPIO2_SET_RIS_TRIG67" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "GPIO2_CLR_RIS_TRIG67" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "GPIO2_SET_FAL_TRIG67" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "GPIO2_CLR_FAL_TRIG67" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "GPIO2_INTSTAT67" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO2_DIR8" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "GPIO2_OUT_DATA8" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO2_SET_DATA8" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "GPIO2_CLR_DATA8" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "GPIO2_IN_DATA8" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." group.word 0xC4++0x1 line.word 0x0 "GPIO2_SET_RIS_TRIG8" hexmask.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." group.word 0xC8++0x1 line.word 0x0 "GPIO2_CLR_RIS_TRIG8" hexmask.word 0x0 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." group.word 0xCC++0x1 line.word 0x0 "GPIO2_SET_FAL_TRIG8" hexmask.word 0x0 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." group.word 0xD0++0x1 line.word 0x0 "GPIO2_CLR_FAL_TRIG8" hexmask.word 0x0 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." group.long 0xD4++0x3 line.long 0x0 "GPIO2_INTSTAT8" hexmask.long.word 0x0 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree "GPIO3" base ad:0x52003000 rgroup.long 0x0++0x3 line.long 0x0 "GPIO3_PID" bitfld.long 0x0 30.--31. "SCHEME,Current scheme" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function code assigned to TCP3" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version R code" bitfld.long 0x0 8.--10. "MAJOR,Major revision X code" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version code" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision Y code" rgroup.byte 0x4++0x0 line.byte 0x0 "GPIO3_PCR" bitfld.byte 0x0 1. "SOFT,Used in conjunction with FREE bit to determine the emulation suspend mode." "0,1" bitfld.byte 0x0 0. "FREE,For GPIO the FREE bit is fixed at 1 which means GPIO runs free in emulation suspend." "0,1" group.long 0x8++0x3 line.long 0x0 "GPIO3_BINTEN" hexmask.long.word 0x0 0.--15. 1. "EN,Per bank interrupt enable. 0 = disable 1 = enable." group.long 0x10++0xF line.long 0x0 "GPIO3_DIR01" hexmask.long.word 0x0 16.--31. 1. "DIR1,Direction of GPIO bank 1 bits 0 = output 1 = input." hexmask.long.word 0x0 0.--15. 1. "DIR0,Direction of GPIO bank 0 bits 0 = output 1 = input." line.long 0x4 "GPIO3_OUT_DATA01" hexmask.long.word 0x4 16.--31. 1. "OUT1,Output drive state of GPIO bank 1 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x4 0.--15. 1. "OUT0,Output drive state of GPIO bank 0 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x8 "GPIO3_SET_DATA01" hexmask.long.word 0x8 16.--31. 1. "SET1,Writing 1 sets the output drive state of GPIO bank 1 bits. Reading it returns the output drive state." hexmask.long.word 0x8 0.--15. 1. "SET0,Writing 1 sets the output drive state of GPIO bank 0 bits. Reading it returns the output drive state." line.long 0xC "GPIO3_CLR_DATA01" hexmask.long.word 0xC 16.--31. 1. "CLR1,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0xC 0.--15. 1. "CLR0,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x20++0x3 line.long 0x0 "GPIO3_IN_DATA01" hexmask.long.word 0x0 16.--31. 1. "IN1,Status of GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "IN0,Status of GPIO bank 0 bits." group.long 0x24++0x23 line.long 0x0 "GPIO3_SET_RIS_TRIG01" hexmask.long.word 0x0 16.--31. 1. "SETRIS1,Writing 1 enables rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS0,Writing 1 enables rising edge detection for GPIO bank 0 bits." line.long 0x4 "GPIO3_CLR_RIS_TRIG01" hexmask.long.word 0x4 16.--31. 1. "CLRRIS1,Writing 1 clears rising edge detection for GPIO bank 1 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS0,Writing 1 clears rising edge detection for GPIO bank 0 bits." line.long 0x8 "GPIO3_SET_FAL_TRIG01" hexmask.long.word 0x8 16.--31. 1. "SETFAL1,Writing 1 enables falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL0,Writing 1 enables falling edge detection for for GPIO bank 0 bits." line.long 0xC "GPIO3_CLR_FAL_TRIG01" hexmask.long.word 0xC 16.--31. 1. "CLRFAL1,Writing 1 clears falling edge detection for for GPIO bank 1 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL0,Writing 1 clears falling edge detection for for GPIO bank 0 bits." line.long 0x10 "GPIO3_INTSTAT01" hexmask.long.word 0x10 16.--31. 1. "STAT1,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT0,Status of GPIO bank 0 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO3_DIR23" hexmask.long.word 0x14 16.--31. 1. "DIR3,Direction of GPIO bank 3 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR2,Direction of GPIO bank 2 bits 0 = output 1 = input." line.long 0x18 "GPIO3_OUT_DATA23" hexmask.long.word 0x18 16.--31. 1. "OUT3,Output drive state of GPIO bank 3 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT2,Output drive state of GPIO bank 2 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO3_SET_DATA23" hexmask.long.word 0x1C 16.--31. 1. "SET3,Writing 1 sets the output drive state of GPIO bank 3 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET2,Writing 1 sets the output drive state of GPIO bank 2 bits. Reading it returns the output drive state." line.long 0x20 "GPIO3_CLR_DATA23" hexmask.long.word 0x20 16.--31. 1. "CLR3,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR2,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x48++0x3 line.long 0x0 "GPIO3_IN_DATA23" hexmask.long.word 0x0 16.--31. 1. "IN3,Status of GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "IN2,Status of GPIO bank 2 bits." group.long 0x4C++0x23 line.long 0x0 "GPIO3_SET_RIS_TRIG23" hexmask.long.word 0x0 16.--31. 1. "SETRIS3,Writing 1 enables rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS2,Writing 1 enables rising edge detection for GPIO bank 2 bits." line.long 0x4 "GPIO3_CLR_RIS_TRIG23" hexmask.long.word 0x4 16.--31. 1. "CLRRIS3,Writing 1 clears rising edge detection for GPIO bank 3 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS2,Writing 1 clears rising edge detection for GPIO bank 2 bits." line.long 0x8 "GPIO3_SET_FAL_TRIG23" hexmask.long.word 0x8 16.--31. 1. "SETFAL3,Writing 1 enables falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL2,Writing 1 enables falling edge detection for for GPIO bank 2 bits." line.long 0xC "GPIO3_CLR_FAL_TRIG23" hexmask.long.word 0xC 16.--31. 1. "CLRFAL3,Writing 1 clears falling edge detection for for GPIO bank 3 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL2,Writing 1 clears falling edge detection for for GPIO bank 2 bits." line.long 0x10 "GPIO3_INTSTAT23" hexmask.long.word 0x10 16.--31. 1. "STAT3,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT2,Status of GPIO bank 2 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO3_DIR45" hexmask.long.word 0x14 16.--31. 1. "DIR5,Direction of GPIO bank 5 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR4,Direction of GPIO bank 4 bits 0 = output 1 = input." line.long 0x18 "GPIO3_OUT_DATA45" hexmask.long.word 0x18 16.--31. 1. "OUT5,Output drive state of GPIO bank 5 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT4,Output drive state of GPIO bank 4 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO3_SET_DATA45" hexmask.long.word 0x1C 16.--31. 1. "SET5,Writing 1 sets the output drive state of GPIO bank 5 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET4,Writing 1 sets the output drive state of GPIO bank 4 bits. Reading it returns the output drive state." line.long 0x20 "GPIO3_CLR_DATA45" hexmask.long.word 0x20 16.--31. 1. "CLR5,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR4,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x70++0x3 line.long 0x0 "GPIO3_IN_DATA45" hexmask.long.word 0x0 16.--31. 1. "IN5,Status of GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "IN4,Status of GPIO bank 4 bits." group.long 0x74++0x23 line.long 0x0 "GPIO3_SET_RIS_TRIG45" hexmask.long.word 0x0 16.--31. 1. "SETRIS5,Writing 1 enables rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS4,Writing 1 enables rising edge detection for GPIO bank 4 bits." line.long 0x4 "GPIO3_CLR_RIS_TRIG45" hexmask.long.word 0x4 16.--31. 1. "CLRRIS5,Writing 1 clears rising edge detection for GPIO bank 5 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS4,Writing 1 clears rising edge detection for GPIO bank 4 bits." line.long 0x8 "GPIO3_SET_FAL_TRIG45" hexmask.long.word 0x8 16.--31. 1. "SETFAL5,Writing 1 enables falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL4,Writing 1 enables falling edge detection for for GPIO bank 4 bits." line.long 0xC "GPIO3_CLR_FAL_TRIG45" hexmask.long.word 0xC 16.--31. 1. "CLRFAL5,Writing 1 clears falling edge detection for for GPIO bank 5 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL4,Writing 1 clears falling edge detection for for GPIO bank 4 bits." line.long 0x10 "GPIO3_INTSTAT45" hexmask.long.word 0x10 16.--31. 1. "STAT5,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT4,Status of GPIO bank 4 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO3_DIR67" hexmask.long.word 0x14 16.--31. 1. "DIR7,Direction of GPIO bank 7 bits 0 = output 1 = input." hexmask.long.word 0x14 0.--15. 1. "DIR6,Direction of GPIO bank 6 bits 0 = output 1 = input." line.long 0x18 "GPIO3_OUT_DATA67" hexmask.long.word 0x18 16.--31. 1. "OUT7,Output drive state of GPIO bank 7 bits does not affect operation when it is configured as input. Reading it returns the output drive state." hexmask.long.word 0x18 0.--15. 1. "OUT6,Output drive state of GPIO bank 6 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO3_SET_DATA67" hexmask.long.word 0x1C 16.--31. 1. "SET7,Writing 1 sets the output drive state of GPIO bank 7 bits. Reading it returns the output drive state." hexmask.long.word 0x1C 0.--15. 1. "SET6,Writing 1 sets the output drive state of GPIO bank 6 bits. Reading it returns the output drive state." line.long 0x20 "GPIO3_CLR_DATA67" hexmask.long.word 0x20 16.--31. 1. "CLR7,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." hexmask.long.word 0x20 0.--15. 1. "CLR6,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0x98++0x3 line.long 0x0 "GPIO3_IN_DATA67" hexmask.long.word 0x0 16.--31. 1. "IN7,Status of GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "IN6,Status of GPIO bank 6 bits." group.long 0x9C++0x23 line.long 0x0 "GPIO3_SET_RIS_TRIG67" hexmask.long.word 0x0 16.--31. 1. "SETRIS7,Writing 1 enables rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x0 0.--15. 1. "SETRIS6,Writing 1 enables rising edge detection for GPIO bank 6 bits." line.long 0x4 "GPIO3_CLR_RIS_TRIG67" hexmask.long.word 0x4 16.--31. 1. "CLRRIS7,Writing 1 clears rising edge detection for GPIO bank 7 bits." hexmask.long.word 0x4 0.--15. 1. "CLRRIS6,Writing 1 clears rising edge detection for GPIO bank 6 bits." line.long 0x8 "GPIO3_SET_FAL_TRIG67" hexmask.long.word 0x8 16.--31. 1. "SETFAL7,Writing 1 enables falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0x8 0.--15. 1. "SETFAL6,Writing 1 enables falling edge detection for for GPIO bank 6 bits." line.long 0xC "GPIO3_CLR_FAL_TRIG67" hexmask.long.word 0xC 16.--31. 1. "CLRFAL7,Writing 1 clears falling edge detection for for GPIO bank 7 bits." hexmask.long.word 0xC 0.--15. 1. "CLRFAL6,Writing 1 clears falling edge detection for for GPIO bank 6 bits." line.long 0x10 "GPIO3_INTSTAT67" hexmask.long.word 0x10 16.--31. 1. "STAT7,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." hexmask.long.word 0x10 0.--15. 1. "STAT6,Status of GPIO bank 6 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." line.long 0x14 "GPIO3_DIR8" hexmask.long.word 0x14 0.--15. 1. "DIR8,Direction of GPIO bank 8 bits 0 = output 1 = input." line.long 0x18 "GPIO3_OUT_DATA8" hexmask.long.word 0x18 0.--15. 1. "OUT8,Output drive state of GPIO bank 8 bits does not affect operation when it is configured as input. Reading it returns the output drive state." line.long 0x1C "GPIO3_SET_DATA8" hexmask.long.word 0x1C 0.--15. 1. "SET8,Writing 1 sets the output drive state of GPIO bank 8 bits. Reading it returns the output drive state." line.long 0x20 "GPIO3_CLR_DATA8" hexmask.long.word 0x20 0.--15. 1. "CLR8,Writing 1 clears the output drive state of GPIO. Reading it returns the output drive state." rgroup.long 0xC0++0x3 line.long 0x0 "GPIO3_IN_DATA8" hexmask.long.word 0x0 0.--15. 1. "IN8,Status of GPIO bank 8 bits." group.word 0xC4++0x1 line.word 0x0 "GPIO3_SET_RIS_TRIG8" hexmask.word 0x0 0.--15. 1. "SETRIS8,Writing 1 enables rising edge detection for GPIO bank 8 bits." group.word 0xC8++0x1 line.word 0x0 "GPIO3_CLR_RIS_TRIG8" hexmask.word 0x0 0.--15. 1. "CLRRIS8,Writing 1 clears rising edge detection for GPIO bank 8 bits." group.word 0xCC++0x1 line.word 0x0 "GPIO3_SET_FAL_TRIG8" hexmask.word 0x0 0.--15. 1. "SETFAL8,Writing 1 enables falling edge detection for for GPIO bank 8 bits." group.word 0xD0++0x1 line.word 0x0 "GPIO3_CLR_FAL_TRIG8" hexmask.word 0x0 0.--15. 1. "CLRFAL8,Writing 1 clears falling edge detection for for GPIO bank 8 bits." group.long 0xD4++0x3 line.long 0x0 "GPIO3_INTSTAT8" hexmask.long.word 0x0 0.--15. 1. "STAT8,Status of GPIO bank 8 bits interrupt. Reading back 1 = interrupt occurred. 0 = interrupt hasnt occurred since last cleared. Writing 1 clears the corresponding interrupt status." tree.end tree "GPIO_INTR_XBAR" base ad:0x52E02000 rgroup.long 0x0++0x3 line.long 0x0 "GPIO_INTR_XBAR_PID" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "GPIO_INTR_XBAR_MUXCNTL" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.byte 0x0 0.--7. 1. "ENABLE,Mux control for interrupt N" tree.end tree.end tree "HSM_DCC" base ad:0x47F79000 group.long 0x0++0x3 line.long 0x0 "HSM_DCC0_DCCGCTRL" hexmask.long.byte 0x0 12.--15. 1. "DONENA,The DONEENA bit enables/disables the done signal. 0101 = disabled & 1010 = enabled" hexmask.long.byte 0x0 8.--11. 1. "SINGLESHOT,Single/Continuous checking mode. 0101 = Continuous & 1010 = Single" hexmask.long.byte 0x0 4.--7. 1. "ERRENA,The ERRENA bit enables/disables the error signal. 0101 = disabled & 1010 = enabled" hexmask.long.byte 0x0 0.--3. 1. "DCCENA,The DCCENA bit starts and stops the operation of the dcc 0101 = disabled & 1010 = enabled" rgroup.long 0x4++0x3 line.long 0x0 "HSM_DCC0_DCCREV" bitfld.long 0x0 28.--30. "SCHEME,SCHEME. - (RO )" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 14.--25. 1. "FUNC,Functional release number - (RO )" hexmask.long.byte 0x0 9.--13. 1. "RTL,Design Release Number - (RO )" bitfld.long 0x0 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. "CUSTOM,Indicates a special version of the module. May not be supported by standard software - (RO )" "0,1" hexmask.long.byte 0x0 0.--4. 1. "MINOR,Minor revision number. - (RO )" group.long 0x8++0xF line.long 0x0 "HSM_DCC0_DCCCNTSEED0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNTSEED0,The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0)" line.long 0x4 "HSM_DCC0_DCCVALIDSEED0" hexmask.long.word 0x4 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0" line.long 0x8 "HSM_DCC0_DCCCNTSEED1" hexmask.long.tbyte 0x8 0.--19. 1. "COUNTSEED1,The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1" line.long 0xC "HSM_DCC0_DCCSTAT" bitfld.long 0xC 1. "DONE,Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag." "0,1" bitfld.long 0xC 0. "ERR,Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag." "0,1" rgroup.long 0x18++0xB line.long 0x0 "HSM_DCC0_DCCCNT0" hexmask.long.tbyte 0x0 0.--19. 1. "COUNT0,This field contains the current value of counter 0. - (RO )" line.long 0x4 "HSM_DCC0_DCCVALID0" hexmask.long.word 0x4 0.--15. 1. "VALID0,This field contains the current value of valid counter 0. - (RO )" line.long 0x8 "HSM_DCC0_DCCCNT1" hexmask.long.tbyte 0x8 0.--19. 1. "COUNT1,This field contains the current value of counter 1. - (RO )" group.long 0x24++0x7 line.long 0x0 "HSM_DCC0_DCCCLKSSRC1" hexmask.long.byte 0x0 12.--15. 1. "KEY_B4,Key Programing (1010 is the KEY Value)" hexmask.long.byte 0x0 0.--3. 1. "CLK_SRC1,Clock source selection for Source 0DCC-A Clock source-0 selection Program value and its respective clock selected 0x0 - REF_CLK0x1 - CPU_CLK0x2 - RC_CLK0x3 - RC_CLK0x4 - RC_CLK0x5 - RC_CLK0x6 - RC_CLK0x7 - RC_CLKDCC-B Clock source-0 selection.." line.long 0x4 "HSM_DCC0_DCCCLKSSRC0" hexmask.long.byte 0x4 0.--3. 1. "CLK_SRC0,Clock source selection for Source 0DCC-A Clock source-0 selection Program value and its respective clock selected 0 - REF_CLKA - PLL_6005 - PLL_240DCC-B Clock source-0 selection Program value and its respective clock selected 0 - PLL_600A -.." tree.end tree "I2C" base ad:0x0 tree "I2C0" base ad:0x52500000 group.long 0x0++0x63 line.long 0x0 "I2C0_ICOAR" hexmask.long.word 0x0 0.--9. 1. "A9_A0,Own address. Use in both 7- and 10-bit address mode. Note that usercan program the I2C own address to any value as long as it does notconflict with other components in the system." line.long 0x4 "I2C0_ICIMR" bitfld.long 0x4 6. "AAS,Address As Slave interrupt mask bit. Setting a'1' to this bit unmasks the Address As Slave interrupt. Setting a'0' to this bit masks the Address As Slave interrupt." "0,1" newline bitfld.long 0x4 5. "SCD,Stop Condition Detection mask bit. Setting a'1' to this bit unmasks the Stop Condition Detection interrupt. Setting a '0' to this bit masks the Stop Condition Detection interrupt." "0,1" newline bitfld.long 0x4 4. "ICXRDY,Transmit Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Transmit Data Ready interrupt. Setting a'0' to this bit masks the Transmit Data Ready interrupt." "0,1" newline bitfld.long 0x4 3. "ICRRDY,Receive Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Receive Data Ready interrupt. Setting a'0' to this bit masks the Receive Data Ready interrupt." "0,1" newline bitfld.long 0x4 2. "ARDY,Register access ready interrupt mask bit. Setting a'1' to this bit unmasks the Register access ready interrupt. Setting a'0' to this bit masks the Register access ready interrupt." "0,1" newline bitfld.long 0x4 1. "NACK,No Acknowledgement interrupt mask bit. Setting a'1' to this bit unmasks the No Acknowledgement interrupt. Setting a'0' to this bit masks the No Acknowledgement interrupt." "0,1" newline bitfld.long 0x4 0. "AL,Arbitration Lost interrupt mask bit. Setting a'1' to this bit unmasks the Arbitration Lost interrupt. Setting a'0' to this bit masks the Arbitration Lost interrupt." "0,1" line.long 0x8 "I2C0_ICSTR" bitfld.long 0x8 14. "SDIR,Slave Direction. This bit is clear to '0' indicating the I2C is a master transmitter/receiver or a slave receiver. This bit is also clear by STOP condition or START condition. It is set to '1' when the I2C slave is a transmitter. In DLB mode.." "0,1" newline bitfld.long 0x8 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'. NACKSNT =0: A No Acknowledge is not sent. NACKSNT =1: A No Acknowledge is sent. Writing a'1' to this bit to clear it." "0: A No Acknowledge is not sent,1: A No Acknowledge is sent" newline bitfld.long 0x8 12. "BB,Bus Busy. This bit indicates the state of the serial bus. BB=0: The bus is free. BB=1: The bus is occupied. On reception of a'start' condition the device sets BB to 1. This bit is also set if the I2C detects SCL low state. BB is clear to 0 after.." "0: The bus is free,1: The bus is occupied" newline bitfld.long 0x8 11. "RSFULL,Receive shift full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when the receive shift register (ICRSR) is full and ICDRR has not been read since the ICRSR-to-ICDRR transfer. The FSM is holding for ICDRR.." "0,1" newline bitfld.long 0x8 10. "XSMT,Transmit shift empty not. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when the transmit shift register (ICXSR) is empty and ICDXR has not been loaded. The FSM is holding for ICDXR write access. XSMT_.." "0,1" newline bitfld.long 0x8 9. "AAS,Address As Slave. This bit is set to 1 by the device when it has recognized its own slave address or an address of all (8) zeros. The AAS bit is reset by stop condition or detection of any address byte that does not match ICOAR. - (RW )" "0,1" newline bitfld.long 0x8 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call). The AD0 bit is reset to 0 (default value) when a'start' or'stop' condition is detected. - (RW )" "0,1" newline bitfld.long 0x8 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition. This bit is cleared by reading ICIVR (as 110) or writing '1' to itself." "0,1" newline bitfld.long 0x8 4. "ICXRDY,Transmit Data Ready interrupt flag bit. ICXRDY is set to'1' is generated when the transmitted data has been copied from ICDXR to the transmit-shift register (ICXSR). ICRXDY is clear to'0' when the ICDXR is written. This bit can also be.." "0,1" newline bitfld.long 0x8 3. "ICRRDY,Receive Data Ready interrupt flag bit. ICRRDY is set to'1' when the received data has been copied from ICRSR into the ICDRR. ICRRDY is cleared to'0' when the ICDRR is read. This bit can also be polled by the CPU to read the received data in.." "0,1" newline bitfld.long 0x8 2. "ARDY,Register-access-ready interrupt flag bit. ARDY is generated by the hardware if the I2C is in the master mode when the previously programmed data and command has been performed and status bit has been updated. This flag is used by the CPU to let.." "0,1" newline bitfld.long 0x8 1. "NACK,No-Acknowledgement interrupt flag bit. The No Acknowledge flag bit is set when the hardware in 'master' mode detects no acknowledge has been received. This bit is NOT set by no-acknowledgement after Start byte Write '1' or Read the ICIVR (as 010).." "0,1" newline bitfld.long 0x8 0. "AL,Arbitration-Lost interrupt flag bit. The Arbitration Lost flag bit is set to 1 when the device in the 'master' mode senses it has lost an arbitration when two or more transmitters start a transmission almost simultaneously or when the I2C.." "0,1" line.long 0xC "I2C0_ICCLKL" hexmask.long.word 0xC 0.--15. 1. "ICCL15_ICCL0,Low time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL low time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)." line.long 0x10 "I2C0_ICCLKH" hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL high time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)." line.long 0x14 "I2C0_ICCNT" hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count. This data count register is used to generate a Stop condition if a Stop condition is specified (STP=1). . ICCNT=1 data count is 1 :::::::::::::::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::::::::::::::.." line.long 0x18 "I2C0_ICDRR" hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data" line.long 0x1C "I2C0_ICSAR" hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Slave address. Use in both 7- and 10-bit address mode." line.long 0x20 "I2C0_ICDXR" hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data" line.long 0x24 "I2C0_ICMDR" bitfld.long 0x24 15. "NACKMOD,No Acknowledge (NACK) mode. This bit is used to send an Acknowledge (ACK) or a No Acknowledge (NACK) to the transmitter. This bit is only applicable when the I2C is in receiver mode. In master receiver mode when the internal data count.." "0,1" newline bitfld.long 0x24 14. "FREE,Free Running. This bit is used to determine the state of the I2C when a breakpoint is encountered in the HLL debugger. FREE=0: (default) Stops immediately if SCL is low and keep driving SCL low whether I2C is master transmitter/receiver. If.." "0: (default,1: The I2C runs free" newline bitfld.long 0x24 13. "STT,Start Condition (Master only mode). This bit can be set to a'1' by the CPU to generate a Start condition. In master mode when setting Start to'1' generates a Start condition. It is reset to '0' by the hardware after the Start condition has been.." "0,1" newline bitfld.long 0x24 12. "NU1,Reserved for IDLEEN (IDLE Enable on 5509). - (RW )" "0,1" newline bitfld.long 0x24 11. "STP,Stop Condition (Master mode only). This bit can be set to a'1' by the CPU to generate a Stop condition. It is reset to '0' by the hardware after the Stop condition has been generated. The Stop condition is generated when ICCNT passes 0 when.." "0,1" newline bitfld.long 0x24 10. "MST,Master. MST=0: The I 2 C peripheral is in the'slave' mode and clock is received from the'master' device. MST=1: The I 2 C peripheral is in the'master' mode and it generates the clock. This bit is clear when the transfer completed." "0: The I 2 C peripheral is in the'slave' mode and..,1: The I 2 C peripheral is in the'master' mode and.." newline bitfld.long 0x24 9. "TRX,Transmitter. TRX=0: The I 2 C is in the'receiver' mode and data on data line SDA is shifted into the data register ICDRR. TRX=1: The I 2 C is in the'transmitter' mode and the data in ICDXR is shifted out on data line SDA. The operating modes.." "0: The I 2 C is in the'receiver' mode and data on..,1: The I 2 C is in the'transmitter' mode and the.." newline bitfld.long 0x24 8. "XA,Expanded Address. XA=0: (default) 7-bit address mode (normal address mode). XA=1: 10-bit address mode (expanded address mode) Please note that XA needs to be configured even if the I2C is in slave mode." "0: (default,1: 10-bit address mode" newline bitfld.long 0x24 7. "RM,Repeat Mode. This bit is set to a'1' by the CPU to put the I2C in the repeat mode. In this mode data is continuously transmitted out of the ICDXR until the STP bit is set to'1' regardless of ICCNT value. This bit is don't care if the I2C is.." "0,1" newline bitfld.long 0x24 6. "DLB,Digital Loop Back (in master transmit mode only). This bit is set to a'1' by the CPU to put the I2C in the loop back mode. In this mode data transmitted out of the ICDXR will be received in the ICDRR after ((CPU freq/I2C freq)8) CPU cycles via.." "0,1" newline bitfld.long 0x24 5. "IRS,I2C Reset Not. This can be set to a'0' by the CPU to put the I2C in reset or to a'1' to take the I2C out of reset. When this bit is reset to 0 all status bits in ICSTR and ICIVR are set to default values. Note that if this bit is reset during.." "0,1" newline bitfld.long 0x24 4. "STB,Start Byte (Master only mode). The Start Byte mode bit is set to 1 by the CPU to configure the I2C in Start byte mode the I2C sends '00000001'? regardless ICSAR value. Refer to the Philip I2C spec for more details." "0,1" newline bitfld.long 0x24 3. "FDF,Free Data Format. This bit can be set to'1' by the CPU to configure the I2C in Free Data Format mode. ______________________________________________FDF___MST___TRX______Operating mode _0______0_____ x____Slave in non FDF mode.." "0,1" newline bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted." "0,1,2,3,4,5,6,7" line.long 0x28 "I2C0_ICIVR" hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved." newline hexmask.long.byte 0x28 8.--11. 1. "TESTMD,Reserved for internal testing." newline hexmask.long.byte 0x28 3.--7. 1. "NU1,Reserved." newline bitfld.long 0x28 0.--2. "INTCODE,Interrupt code. The binary-coded-interrupt vector indicates which interrupt has occurred. Reading the ICIVR clears the interrupt code except ARDY(011) RRDY(100) and XRDY(101). Interrupt code for ARDY RRDY and XRDY is cleared when ARDY ICRRDY.." "0,1,2,3,4,5,6,7" line.long 0x2C "I2C0_ICEMDR" hexmask.long 0x2C 2.--31. 1. "NU,Reserved. - (RW )" newline bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave. IGNACK=1 The master transmitter will ignore a NACK.." "0,1" newline bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode. This bit affects the I2C interrupt behavior. Refer to appendix A for details." "0,1" line.long 0x30 "I2C0_ICPSC" hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved." newline hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module. This register must be initialized while the I2C is still in reset (IRS_=0). The value takes effect on the rising edge of IRS_." line.long 0x34 "I2C0_ICPID1" hexmask.long.word 0x34 16.--31. 1. "NU,Reserved." newline hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral. This value should be 0x01 - (RW )" newline hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C. This value should be incremented each time the design is revised. - (RW )" line.long 0x38 "I2C0_ICPID2" hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved." newline hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral. This value should be 0x05 - (RW )" line.long 0x3C "I2C0_ICDMAC" hexmask.long 0x3C 2.--31. 1. "NU,Reserved. - (RW )" newline bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICTEVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICTEVT_POR pin is never.." "0: DMA transmit event is disabled,1: DMA transmit event is enabled" newline bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICREVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICREVT_POR pin is never.." "0: DMA receive event is disabled,1: DMA receive event is enabled" line.long 0x40 "I2C0_I2C_RESERVED1" hexmask.long 0x40 0.--31. 1. "NU,Reserved." line.long 0x44 "I2C0_I2C_RESERVED2" hexmask.long 0x44 0.--31. 1. "NU,Reserved." line.long 0x48 "I2C0_ICPFUNC" hexmask.long 0x48 1.--31. 1. "NU,Reserved." newline bitfld.long 0x48 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins. 0 = Pins function as SCL and SDA 1 = Pins functions as GPIO Note: No hardware protection is required to disable I2C function when the PFUNC[0] and IRS_ bits are both set to one. When PFUNC[0].." "0: Pins function as SCL and SDA,1: Pins functions as GPIO Note: No hardware.." line.long 0x4C "I2C0_ICPDIR" bitfld.long 0x4C 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO. 0 = SDA pin functions as input 1 = SDA pin functions as output" "0: SDA pin functions as input,1: SDA pin functions as output" newline bitfld.long 0x4C 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO. 0 = SCL pin functions as input 1 = SCL pin functions as output" "0: SCL pin functions as input,1: SCL pin functions as output" line.long 0x50 "I2C0_ICPDIN" bitfld.long 0x50 1. "PDIN1,Indicates the logic level present on the SDA pin. Reads: 0 = Logic low present at SDA pin regardless of PFUNC setting. 1 = Logic high present at SDA pin regardless of PFUNC setting. Writes: Writes have no effect. - (RW )" "0: Logic low present at SDA pin regardless of PFUNC..,1: Logic high present at SDA pin regardless of.." newline bitfld.long 0x50 0. "PDIN0,Indicates the logic level present on the SCL pin. Reads: 0 = Logic low present at SCL pin regardless of PFUNC setting. 1 = Logic high present at SCL pin regardless of PFUNC setting. Writes: Writes have no effect - (RW )" "0: Logic low present at SCL pin regardless of PFUNC..,1: Logic high present at SCL pin regardless of.." line.long 0x54 "I2C0_ICPDOUT" bitfld.long 0x54 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SDA pin driven low 1 = SDA pin driven high. Note: If SDA is connected to an open-drain buffer at.." "0: SDA pin driven low,1: SDA pin driven high" newline bitfld.long 0x54 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SCL pin driven low 1 = SCL pin driven high Note: If SCL is connected to an open-drain buffer at.." "0: SCL pin driven low,1: SCL pin driven high Note: If SCL is connected to.." line.long 0x58 "I2C0_ICPDSET" bitfld.long 0x58 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is set to logic high." "0: no effect,1: PDOUT[1] bit is set to logic high" newline bitfld.long 0x58 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is set to logic high." "0: no effect,1: PDOUT[0] bit is set to logic high" line.long 0x5C "I2C0_ICPDCLR" bitfld.long 0x5C 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is cleared to logic low." "0: no effect,1: PDOUT[1] bit is cleared to logic low" newline bitfld.long 0x5C 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is cleared to logic low." "0: no effect,1: PDOUT[0] bit is cleared to logic low" line.long 0x60 "I2C0_ICPDRV" bitfld.long 0x60 1. "PDRV1,Used to select driver mode of output buffer for SDA pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SDA_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" newline bitfld.long 0x60 0. "PDRV0,Used to select driver mode of output buffer for SCL pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SCL_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" tree.end tree "I2C1" base ad:0x52501000 group.long 0x0++0x63 line.long 0x0 "I2C1_ICOAR" hexmask.long.word 0x0 0.--9. 1. "A9_A0,Own address. Use in both 7- and 10-bit address mode. Note that usercan program the I2C own address to any value as long as it does notconflict with other components in the system." line.long 0x4 "I2C1_ICIMR" bitfld.long 0x4 6. "AAS,Address As Slave interrupt mask bit. Setting a'1' to this bit unmasks the Address As Slave interrupt. Setting a'0' to this bit masks the Address As Slave interrupt." "0,1" newline bitfld.long 0x4 5. "SCD,Stop Condition Detection mask bit. Setting a'1' to this bit unmasks the Stop Condition Detection interrupt. Setting a '0' to this bit masks the Stop Condition Detection interrupt." "0,1" newline bitfld.long 0x4 4. "ICXRDY,Transmit Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Transmit Data Ready interrupt. Setting a'0' to this bit masks the Transmit Data Ready interrupt." "0,1" newline bitfld.long 0x4 3. "ICRRDY,Receive Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Receive Data Ready interrupt. Setting a'0' to this bit masks the Receive Data Ready interrupt." "0,1" newline bitfld.long 0x4 2. "ARDY,Register access ready interrupt mask bit. Setting a'1' to this bit unmasks the Register access ready interrupt. Setting a'0' to this bit masks the Register access ready interrupt." "0,1" newline bitfld.long 0x4 1. "NACK,No Acknowledgement interrupt mask bit. Setting a'1' to this bit unmasks the No Acknowledgement interrupt. Setting a'0' to this bit masks the No Acknowledgement interrupt." "0,1" newline bitfld.long 0x4 0. "AL,Arbitration Lost interrupt mask bit. Setting a'1' to this bit unmasks the Arbitration Lost interrupt. Setting a'0' to this bit masks the Arbitration Lost interrupt." "0,1" line.long 0x8 "I2C1_ICSTR" bitfld.long 0x8 14. "SDIR,Slave Direction. This bit is clear to '0' indicating the I2C is a master transmitter/receiver or a slave receiver. This bit is also clear by STOP condition or START condition. It is set to '1' when the I2C slave is a transmitter. In DLB mode.." "0,1" newline bitfld.long 0x8 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'. NACKSNT =0: A No Acknowledge is not sent. NACKSNT =1: A No Acknowledge is sent. Writing a'1' to this bit to clear it." "0: A No Acknowledge is not sent,1: A No Acknowledge is sent" newline bitfld.long 0x8 12. "BB,Bus Busy. This bit indicates the state of the serial bus. BB=0: The bus is free. BB=1: The bus is occupied. On reception of a'start' condition the device sets BB to 1. This bit is also set if the I2C detects SCL low state. BB is clear to 0 after.." "0: The bus is free,1: The bus is occupied" newline bitfld.long 0x8 11. "RSFULL,Receive shift full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when the receive shift register (ICRSR) is full and ICDRR has not been read since the ICRSR-to-ICDRR transfer. The FSM is holding for ICDRR.." "0,1" newline bitfld.long 0x8 10. "XSMT,Transmit shift empty not. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when the transmit shift register (ICXSR) is empty and ICDXR has not been loaded. The FSM is holding for ICDXR write access. XSMT_.." "0,1" newline bitfld.long 0x8 9. "AAS,Address As Slave. This bit is set to 1 by the device when it has recognized its own slave address or an address of all (8) zeros. The AAS bit is reset by stop condition or detection of any address byte that does not match ICOAR. - (RW )" "0,1" newline bitfld.long 0x8 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call). The AD0 bit is reset to 0 (default value) when a'start' or'stop' condition is detected. - (RW )" "0,1" newline bitfld.long 0x8 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition. This bit is cleared by reading ICIVR (as 110) or writing '1' to itself." "0,1" newline bitfld.long 0x8 4. "ICXRDY,Transmit Data Ready interrupt flag bit. ICXRDY is set to'1' is generated when the transmitted data has been copied from ICDXR to the transmit-shift register (ICXSR). ICRXDY is clear to'0' when the ICDXR is written. This bit can also be.." "0,1" newline bitfld.long 0x8 3. "ICRRDY,Receive Data Ready interrupt flag bit. ICRRDY is set to'1' when the received data has been copied from ICRSR into the ICDRR. ICRRDY is cleared to'0' when the ICDRR is read. This bit can also be polled by the CPU to read the received data in.." "0,1" newline bitfld.long 0x8 2. "ARDY,Register-access-ready interrupt flag bit. ARDY is generated by the hardware if the I2C is in the master mode when the previously programmed data and command has been performed and status bit has been updated. This flag is used by the CPU to let.." "0,1" newline bitfld.long 0x8 1. "NACK,No-Acknowledgement interrupt flag bit. The No Acknowledge flag bit is set when the hardware in 'master' mode detects no acknowledge has been received. This bit is NOT set by no-acknowledgement after Start byte Write '1' or Read the ICIVR (as 010).." "0,1" newline bitfld.long 0x8 0. "AL,Arbitration-Lost interrupt flag bit. The Arbitration Lost flag bit is set to 1 when the device in the 'master' mode senses it has lost an arbitration when two or more transmitters start a transmission almost simultaneously or when the I2C.." "0,1" line.long 0xC "I2C1_ICCLKL" hexmask.long.word 0xC 0.--15. 1. "ICCL15_ICCL0,Low time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL low time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)." line.long 0x10 "I2C1_ICCLKH" hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL high time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)." line.long 0x14 "I2C1_ICCNT" hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count. This data count register is used to generate a Stop condition if a Stop condition is specified (STP=1). . ICCNT=1 data count is 1 :::::::::::::::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::::::::::::::.." line.long 0x18 "I2C1_ICDRR" hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data" line.long 0x1C "I2C1_ICSAR" hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Slave address. Use in both 7- and 10-bit address mode." line.long 0x20 "I2C1_ICDXR" hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data" line.long 0x24 "I2C1_ICMDR" bitfld.long 0x24 15. "NACKMOD,No Acknowledge (NACK) mode. This bit is used to send an Acknowledge (ACK) or a No Acknowledge (NACK) to the transmitter. This bit is only applicable when the I2C is in receiver mode. In master receiver mode when the internal data count.." "0,1" newline bitfld.long 0x24 14. "FREE,Free Running. This bit is used to determine the state of the I2C when a breakpoint is encountered in the HLL debugger. FREE=0: (default) Stops immediately if SCL is low and keep driving SCL low whether I2C is master transmitter/receiver. If.." "0: (default,1: The I2C runs free" newline bitfld.long 0x24 13. "STT,Start Condition (Master only mode). This bit can be set to a'1' by the CPU to generate a Start condition. In master mode when setting Start to'1' generates a Start condition. It is reset to '0' by the hardware after the Start condition has been.." "0,1" newline bitfld.long 0x24 12. "NU1,Reserved for IDLEEN (IDLE Enable on 5509). - (RW )" "0,1" newline bitfld.long 0x24 11. "STP,Stop Condition (Master mode only). This bit can be set to a'1' by the CPU to generate a Stop condition. It is reset to '0' by the hardware after the Stop condition has been generated. The Stop condition is generated when ICCNT passes 0 when.." "0,1" newline bitfld.long 0x24 10. "MST,Master. MST=0: The I 2 C peripheral is in the'slave' mode and clock is received from the'master' device. MST=1: The I 2 C peripheral is in the'master' mode and it generates the clock. This bit is clear when the transfer completed." "0: The I 2 C peripheral is in the'slave' mode and..,1: The I 2 C peripheral is in the'master' mode and.." newline bitfld.long 0x24 9. "TRX,Transmitter. TRX=0: The I 2 C is in the'receiver' mode and data on data line SDA is shifted into the data register ICDRR. TRX=1: The I 2 C is in the'transmitter' mode and the data in ICDXR is shifted out on data line SDA. The operating modes.." "0: The I 2 C is in the'receiver' mode and data on..,1: The I 2 C is in the'transmitter' mode and the.." newline bitfld.long 0x24 8. "XA,Expanded Address. XA=0: (default) 7-bit address mode (normal address mode). XA=1: 10-bit address mode (expanded address mode) Please note that XA needs to be configured even if the I2C is in slave mode." "0: (default,1: 10-bit address mode" newline bitfld.long 0x24 7. "RM,Repeat Mode. This bit is set to a'1' by the CPU to put the I2C in the repeat mode. In this mode data is continuously transmitted out of the ICDXR until the STP bit is set to'1' regardless of ICCNT value. This bit is don't care if the I2C is.." "0,1" newline bitfld.long 0x24 6. "DLB,Digital Loop Back (in master transmit mode only). This bit is set to a'1' by the CPU to put the I2C in the loop back mode. In this mode data transmitted out of the ICDXR will be received in the ICDRR after ((CPU freq/I2C freq)8) CPU cycles via.." "0,1" newline bitfld.long 0x24 5. "IRS,I2C Reset Not. This can be set to a'0' by the CPU to put the I2C in reset or to a'1' to take the I2C out of reset. When this bit is reset to 0 all status bits in ICSTR and ICIVR are set to default values. Note that if this bit is reset during.." "0,1" newline bitfld.long 0x24 4. "STB,Start Byte (Master only mode). The Start Byte mode bit is set to 1 by the CPU to configure the I2C in Start byte mode the I2C sends '00000001'? regardless ICSAR value. Refer to the Philip I2C spec for more details." "0,1" newline bitfld.long 0x24 3. "FDF,Free Data Format. This bit can be set to'1' by the CPU to configure the I2C in Free Data Format mode. ______________________________________________FDF___MST___TRX______Operating mode _0______0_____ x____Slave in non FDF mode.." "0,1" newline bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted." "0,1,2,3,4,5,6,7" line.long 0x28 "I2C1_ICIVR" hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved." newline hexmask.long.byte 0x28 8.--11. 1. "TESTMD,Reserved for internal testing." newline hexmask.long.byte 0x28 3.--7. 1. "NU1,Reserved." newline bitfld.long 0x28 0.--2. "INTCODE,Interrupt code. The binary-coded-interrupt vector indicates which interrupt has occurred. Reading the ICIVR clears the interrupt code except ARDY(011) RRDY(100) and XRDY(101). Interrupt code for ARDY RRDY and XRDY is cleared when ARDY ICRRDY.." "0,1,2,3,4,5,6,7" line.long 0x2C "I2C1_ICEMDR" hexmask.long 0x2C 2.--31. 1. "NU,Reserved. - (RW )" newline bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave. IGNACK=1 The master transmitter will ignore a NACK.." "0,1" newline bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode. This bit affects the I2C interrupt behavior. Refer to appendix A for details." "0,1" line.long 0x30 "I2C1_ICPSC" hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved." newline hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module. This register must be initialized while the I2C is still in reset (IRS_=0). The value takes effect on the rising edge of IRS_." line.long 0x34 "I2C1_ICPID1" hexmask.long.word 0x34 16.--31. 1. "NU,Reserved." newline hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral. This value should be 0x01 - (RW )" newline hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C. This value should be incremented each time the design is revised. - (RW )" line.long 0x38 "I2C1_ICPID2" hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved." newline hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral. This value should be 0x05 - (RW )" line.long 0x3C "I2C1_ICDMAC" hexmask.long 0x3C 2.--31. 1. "NU,Reserved. - (RW )" newline bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICTEVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICTEVT_POR pin is never.." "0: DMA transmit event is disabled,1: DMA transmit event is enabled" newline bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICREVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICREVT_POR pin is never.." "0: DMA receive event is disabled,1: DMA receive event is enabled" line.long 0x40 "I2C1_I2C_RESERVED1" hexmask.long 0x40 0.--31. 1. "NU,Reserved." line.long 0x44 "I2C1_I2C_RESERVED2" hexmask.long 0x44 0.--31. 1. "NU,Reserved." line.long 0x48 "I2C1_ICPFUNC" hexmask.long 0x48 1.--31. 1. "NU,Reserved." newline bitfld.long 0x48 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins. 0 = Pins function as SCL and SDA 1 = Pins functions as GPIO Note: No hardware protection is required to disable I2C function when the PFUNC[0] and IRS_ bits are both set to one. When PFUNC[0].." "0: Pins function as SCL and SDA,1: Pins functions as GPIO Note: No hardware.." line.long 0x4C "I2C1_ICPDIR" bitfld.long 0x4C 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO. 0 = SDA pin functions as input 1 = SDA pin functions as output" "0: SDA pin functions as input,1: SDA pin functions as output" newline bitfld.long 0x4C 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO. 0 = SCL pin functions as input 1 = SCL pin functions as output" "0: SCL pin functions as input,1: SCL pin functions as output" line.long 0x50 "I2C1_ICPDIN" bitfld.long 0x50 1. "PDIN1,Indicates the logic level present on the SDA pin. Reads: 0 = Logic low present at SDA pin regardless of PFUNC setting. 1 = Logic high present at SDA pin regardless of PFUNC setting. Writes: Writes have no effect. - (RW )" "0: Logic low present at SDA pin regardless of PFUNC..,1: Logic high present at SDA pin regardless of.." newline bitfld.long 0x50 0. "PDIN0,Indicates the logic level present on the SCL pin. Reads: 0 = Logic low present at SCL pin regardless of PFUNC setting. 1 = Logic high present at SCL pin regardless of PFUNC setting. Writes: Writes have no effect - (RW )" "0: Logic low present at SCL pin regardless of PFUNC..,1: Logic high present at SCL pin regardless of.." line.long 0x54 "I2C1_ICPDOUT" bitfld.long 0x54 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SDA pin driven low 1 = SDA pin driven high. Note: If SDA is connected to an open-drain buffer at.." "0: SDA pin driven low,1: SDA pin driven high" newline bitfld.long 0x54 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SCL pin driven low 1 = SCL pin driven high Note: If SCL is connected to an open-drain buffer at.." "0: SCL pin driven low,1: SCL pin driven high Note: If SCL is connected to.." line.long 0x58 "I2C1_ICPDSET" bitfld.long 0x58 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is set to logic high." "0: no effect,1: PDOUT[1] bit is set to logic high" newline bitfld.long 0x58 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is set to logic high." "0: no effect,1: PDOUT[0] bit is set to logic high" line.long 0x5C "I2C1_ICPDCLR" bitfld.long 0x5C 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is cleared to logic low." "0: no effect,1: PDOUT[1] bit is cleared to logic low" newline bitfld.long 0x5C 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is cleared to logic low." "0: no effect,1: PDOUT[0] bit is cleared to logic low" line.long 0x60 "I2C1_ICPDRV" bitfld.long 0x60 1. "PDRV1,Used to select driver mode of output buffer for SDA pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SDA_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" newline bitfld.long 0x60 0. "PDRV0,Used to select driver mode of output buffer for SCL pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SCL_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" tree.end tree "I2C2" base ad:0x52502000 group.long 0x0++0x63 line.long 0x0 "I2C2_ICOAR" hexmask.long.word 0x0 0.--9. 1. "A9_A0,Own address. Use in both 7- and 10-bit address mode. Note that usercan program the I2C own address to any value as long as it does notconflict with other components in the system." line.long 0x4 "I2C2_ICIMR" bitfld.long 0x4 6. "AAS,Address As Slave interrupt mask bit. Setting a'1' to this bit unmasks the Address As Slave interrupt. Setting a'0' to this bit masks the Address As Slave interrupt." "0,1" newline bitfld.long 0x4 5. "SCD,Stop Condition Detection mask bit. Setting a'1' to this bit unmasks the Stop Condition Detection interrupt. Setting a '0' to this bit masks the Stop Condition Detection interrupt." "0,1" newline bitfld.long 0x4 4. "ICXRDY,Transmit Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Transmit Data Ready interrupt. Setting a'0' to this bit masks the Transmit Data Ready interrupt." "0,1" newline bitfld.long 0x4 3. "ICRRDY,Receive Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Receive Data Ready interrupt. Setting a'0' to this bit masks the Receive Data Ready interrupt." "0,1" newline bitfld.long 0x4 2. "ARDY,Register access ready interrupt mask bit. Setting a'1' to this bit unmasks the Register access ready interrupt. Setting a'0' to this bit masks the Register access ready interrupt." "0,1" newline bitfld.long 0x4 1. "NACK,No Acknowledgement interrupt mask bit. Setting a'1' to this bit unmasks the No Acknowledgement interrupt. Setting a'0' to this bit masks the No Acknowledgement interrupt." "0,1" newline bitfld.long 0x4 0. "AL,Arbitration Lost interrupt mask bit. Setting a'1' to this bit unmasks the Arbitration Lost interrupt. Setting a'0' to this bit masks the Arbitration Lost interrupt." "0,1" line.long 0x8 "I2C2_ICSTR" bitfld.long 0x8 14. "SDIR,Slave Direction. This bit is clear to '0' indicating the I2C is a master transmitter/receiver or a slave receiver. This bit is also clear by STOP condition or START condition. It is set to '1' when the I2C slave is a transmitter. In DLB mode.." "0,1" newline bitfld.long 0x8 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'. NACKSNT =0: A No Acknowledge is not sent. NACKSNT =1: A No Acknowledge is sent. Writing a'1' to this bit to clear it." "0: A No Acknowledge is not sent,1: A No Acknowledge is sent" newline bitfld.long 0x8 12. "BB,Bus Busy. This bit indicates the state of the serial bus. BB=0: The bus is free. BB=1: The bus is occupied. On reception of a'start' condition the device sets BB to 1. This bit is also set if the I2C detects SCL low state. BB is clear to 0 after.." "0: The bus is free,1: The bus is occupied" newline bitfld.long 0x8 11. "RSFULL,Receive shift full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when the receive shift register (ICRSR) is full and ICDRR has not been read since the ICRSR-to-ICDRR transfer. The FSM is holding for ICDRR.." "0,1" newline bitfld.long 0x8 10. "XSMT,Transmit shift empty not. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when the transmit shift register (ICXSR) is empty and ICDXR has not been loaded. The FSM is holding for ICDXR write access. XSMT_.." "0,1" newline bitfld.long 0x8 9. "AAS,Address As Slave. This bit is set to 1 by the device when it has recognized its own slave address or an address of all (8) zeros. The AAS bit is reset by stop condition or detection of any address byte that does not match ICOAR. - (RW )" "0,1" newline bitfld.long 0x8 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call). The AD0 bit is reset to 0 (default value) when a'start' or'stop' condition is detected. - (RW )" "0,1" newline bitfld.long 0x8 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition. This bit is cleared by reading ICIVR (as 110) or writing '1' to itself." "0,1" newline bitfld.long 0x8 4. "ICXRDY,Transmit Data Ready interrupt flag bit. ICXRDY is set to'1' is generated when the transmitted data has been copied from ICDXR to the transmit-shift register (ICXSR). ICRXDY is clear to'0' when the ICDXR is written. This bit can also be.." "0,1" newline bitfld.long 0x8 3. "ICRRDY,Receive Data Ready interrupt flag bit. ICRRDY is set to'1' when the received data has been copied from ICRSR into the ICDRR. ICRRDY is cleared to'0' when the ICDRR is read. This bit can also be polled by the CPU to read the received data in.." "0,1" newline bitfld.long 0x8 2. "ARDY,Register-access-ready interrupt flag bit. ARDY is generated by the hardware if the I2C is in the master mode when the previously programmed data and command has been performed and status bit has been updated. This flag is used by the CPU to let.." "0,1" newline bitfld.long 0x8 1. "NACK,No-Acknowledgement interrupt flag bit. The No Acknowledge flag bit is set when the hardware in 'master' mode detects no acknowledge has been received. This bit is NOT set by no-acknowledgement after Start byte Write '1' or Read the ICIVR (as 010).." "0,1" newline bitfld.long 0x8 0. "AL,Arbitration-Lost interrupt flag bit. The Arbitration Lost flag bit is set to 1 when the device in the 'master' mode senses it has lost an arbitration when two or more transmitters start a transmission almost simultaneously or when the I2C.." "0,1" line.long 0xC "I2C2_ICCLKL" hexmask.long.word 0xC 0.--15. 1. "ICCL15_ICCL0,Low time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL low time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)." line.long 0x10 "I2C2_ICCLKH" hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL high time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)." line.long 0x14 "I2C2_ICCNT" hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count. This data count register is used to generate a Stop condition if a Stop condition is specified (STP=1). . ICCNT=1 data count is 1 :::::::::::::::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::::::::::::::.." line.long 0x18 "I2C2_ICDRR" hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data" line.long 0x1C "I2C2_ICSAR" hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Slave address. Use in both 7- and 10-bit address mode." line.long 0x20 "I2C2_ICDXR" hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data" line.long 0x24 "I2C2_ICMDR" bitfld.long 0x24 15. "NACKMOD,No Acknowledge (NACK) mode. This bit is used to send an Acknowledge (ACK) or a No Acknowledge (NACK) to the transmitter. This bit is only applicable when the I2C is in receiver mode. In master receiver mode when the internal data count.." "0,1" newline bitfld.long 0x24 14. "FREE,Free Running. This bit is used to determine the state of the I2C when a breakpoint is encountered in the HLL debugger. FREE=0: (default) Stops immediately if SCL is low and keep driving SCL low whether I2C is master transmitter/receiver. If.." "0: (default,1: The I2C runs free" newline bitfld.long 0x24 13. "STT,Start Condition (Master only mode). This bit can be set to a'1' by the CPU to generate a Start condition. In master mode when setting Start to'1' generates a Start condition. It is reset to '0' by the hardware after the Start condition has been.." "0,1" newline bitfld.long 0x24 12. "NU1,Reserved for IDLEEN (IDLE Enable on 5509). - (RW )" "0,1" newline bitfld.long 0x24 11. "STP,Stop Condition (Master mode only). This bit can be set to a'1' by the CPU to generate a Stop condition. It is reset to '0' by the hardware after the Stop condition has been generated. The Stop condition is generated when ICCNT passes 0 when.." "0,1" newline bitfld.long 0x24 10. "MST,Master. MST=0: The I 2 C peripheral is in the'slave' mode and clock is received from the'master' device. MST=1: The I 2 C peripheral is in the'master' mode and it generates the clock. This bit is clear when the transfer completed." "0: The I 2 C peripheral is in the'slave' mode and..,1: The I 2 C peripheral is in the'master' mode and.." newline bitfld.long 0x24 9. "TRX,Transmitter. TRX=0: The I 2 C is in the'receiver' mode and data on data line SDA is shifted into the data register ICDRR. TRX=1: The I 2 C is in the'transmitter' mode and the data in ICDXR is shifted out on data line SDA. The operating modes.." "0: The I 2 C is in the'receiver' mode and data on..,1: The I 2 C is in the'transmitter' mode and the.." newline bitfld.long 0x24 8. "XA,Expanded Address. XA=0: (default) 7-bit address mode (normal address mode). XA=1: 10-bit address mode (expanded address mode) Please note that XA needs to be configured even if the I2C is in slave mode." "0: (default,1: 10-bit address mode" newline bitfld.long 0x24 7. "RM,Repeat Mode. This bit is set to a'1' by the CPU to put the I2C in the repeat mode. In this mode data is continuously transmitted out of the ICDXR until the STP bit is set to'1' regardless of ICCNT value. This bit is don't care if the I2C is.." "0,1" newline bitfld.long 0x24 6. "DLB,Digital Loop Back (in master transmit mode only). This bit is set to a'1' by the CPU to put the I2C in the loop back mode. In this mode data transmitted out of the ICDXR will be received in the ICDRR after ((CPU freq/I2C freq)8) CPU cycles via.." "0,1" newline bitfld.long 0x24 5. "IRS,I2C Reset Not. This can be set to a'0' by the CPU to put the I2C in reset or to a'1' to take the I2C out of reset. When this bit is reset to 0 all status bits in ICSTR and ICIVR are set to default values. Note that if this bit is reset during.." "0,1" newline bitfld.long 0x24 4. "STB,Start Byte (Master only mode). The Start Byte mode bit is set to 1 by the CPU to configure the I2C in Start byte mode the I2C sends '00000001'? regardless ICSAR value. Refer to the Philip I2C spec for more details." "0,1" newline bitfld.long 0x24 3. "FDF,Free Data Format. This bit can be set to'1' by the CPU to configure the I2C in Free Data Format mode. ______________________________________________FDF___MST___TRX______Operating mode _0______0_____ x____Slave in non FDF mode.." "0,1" newline bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted." "0,1,2,3,4,5,6,7" line.long 0x28 "I2C2_ICIVR" hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved." newline hexmask.long.byte 0x28 8.--11. 1. "TESTMD,Reserved for internal testing." newline hexmask.long.byte 0x28 3.--7. 1. "NU1,Reserved." newline bitfld.long 0x28 0.--2. "INTCODE,Interrupt code. The binary-coded-interrupt vector indicates which interrupt has occurred. Reading the ICIVR clears the interrupt code except ARDY(011) RRDY(100) and XRDY(101). Interrupt code for ARDY RRDY and XRDY is cleared when ARDY ICRRDY.." "0,1,2,3,4,5,6,7" line.long 0x2C "I2C2_ICEMDR" hexmask.long 0x2C 2.--31. 1. "NU,Reserved. - (RW )" newline bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave. IGNACK=1 The master transmitter will ignore a NACK.." "0,1" newline bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode. This bit affects the I2C interrupt behavior. Refer to appendix A for details." "0,1" line.long 0x30 "I2C2_ICPSC" hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved." newline hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module. This register must be initialized while the I2C is still in reset (IRS_=0). The value takes effect on the rising edge of IRS_." line.long 0x34 "I2C2_ICPID1" hexmask.long.word 0x34 16.--31. 1. "NU,Reserved." newline hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral. This value should be 0x01 - (RW )" newline hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C. This value should be incremented each time the design is revised. - (RW )" line.long 0x38 "I2C2_ICPID2" hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved." newline hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral. This value should be 0x05 - (RW )" line.long 0x3C "I2C2_ICDMAC" hexmask.long 0x3C 2.--31. 1. "NU,Reserved. - (RW )" newline bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICTEVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICTEVT_POR pin is never.." "0: DMA transmit event is disabled,1: DMA transmit event is enabled" newline bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICREVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICREVT_POR pin is never.." "0: DMA receive event is disabled,1: DMA receive event is enabled" line.long 0x40 "I2C2_I2C_RESERVED1" hexmask.long 0x40 0.--31. 1. "NU,Reserved." line.long 0x44 "I2C2_I2C_RESERVED2" hexmask.long 0x44 0.--31. 1. "NU,Reserved." line.long 0x48 "I2C2_ICPFUNC" hexmask.long 0x48 1.--31. 1. "NU,Reserved." newline bitfld.long 0x48 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins. 0 = Pins function as SCL and SDA 1 = Pins functions as GPIO Note: No hardware protection is required to disable I2C function when the PFUNC[0] and IRS_ bits are both set to one. When PFUNC[0].." "0: Pins function as SCL and SDA,1: Pins functions as GPIO Note: No hardware.." line.long 0x4C "I2C2_ICPDIR" bitfld.long 0x4C 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO. 0 = SDA pin functions as input 1 = SDA pin functions as output" "0: SDA pin functions as input,1: SDA pin functions as output" newline bitfld.long 0x4C 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO. 0 = SCL pin functions as input 1 = SCL pin functions as output" "0: SCL pin functions as input,1: SCL pin functions as output" line.long 0x50 "I2C2_ICPDIN" bitfld.long 0x50 1. "PDIN1,Indicates the logic level present on the SDA pin. Reads: 0 = Logic low present at SDA pin regardless of PFUNC setting. 1 = Logic high present at SDA pin regardless of PFUNC setting. Writes: Writes have no effect. - (RW )" "0: Logic low present at SDA pin regardless of PFUNC..,1: Logic high present at SDA pin regardless of.." newline bitfld.long 0x50 0. "PDIN0,Indicates the logic level present on the SCL pin. Reads: 0 = Logic low present at SCL pin regardless of PFUNC setting. 1 = Logic high present at SCL pin regardless of PFUNC setting. Writes: Writes have no effect - (RW )" "0: Logic low present at SCL pin regardless of PFUNC..,1: Logic high present at SCL pin regardless of.." line.long 0x54 "I2C2_ICPDOUT" bitfld.long 0x54 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SDA pin driven low 1 = SDA pin driven high. Note: If SDA is connected to an open-drain buffer at.." "0: SDA pin driven low,1: SDA pin driven high" newline bitfld.long 0x54 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SCL pin driven low 1 = SCL pin driven high Note: If SCL is connected to an open-drain buffer at.." "0: SCL pin driven low,1: SCL pin driven high Note: If SCL is connected to.." line.long 0x58 "I2C2_ICPDSET" bitfld.long 0x58 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is set to logic high." "0: no effect,1: PDOUT[1] bit is set to logic high" newline bitfld.long 0x58 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is set to logic high." "0: no effect,1: PDOUT[0] bit is set to logic high" line.long 0x5C "I2C2_ICPDCLR" bitfld.long 0x5C 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is cleared to logic low." "0: no effect,1: PDOUT[1] bit is cleared to logic low" newline bitfld.long 0x5C 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is cleared to logic low." "0: no effect,1: PDOUT[0] bit is cleared to logic low" line.long 0x60 "I2C2_ICPDRV" bitfld.long 0x60 1. "PDRV1,Used to select driver mode of output buffer for SDA pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SDA_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" newline bitfld.long 0x60 0. "PDRV0,Used to select driver mode of output buffer for SCL pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SCL_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" tree.end tree "I2C3" base ad:0x52503000 group.long 0x0++0x63 line.long 0x0 "I2C3_ICOAR" hexmask.long.word 0x0 0.--9. 1. "A9_A0,Own address. Use in both 7- and 10-bit address mode. Note that usercan program the I2C own address to any value as long as it does notconflict with other components in the system." line.long 0x4 "I2C3_ICIMR" bitfld.long 0x4 6. "AAS,Address As Slave interrupt mask bit. Setting a'1' to this bit unmasks the Address As Slave interrupt. Setting a'0' to this bit masks the Address As Slave interrupt." "0,1" newline bitfld.long 0x4 5. "SCD,Stop Condition Detection mask bit. Setting a'1' to this bit unmasks the Stop Condition Detection interrupt. Setting a '0' to this bit masks the Stop Condition Detection interrupt." "0,1" newline bitfld.long 0x4 4. "ICXRDY,Transmit Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Transmit Data Ready interrupt. Setting a'0' to this bit masks the Transmit Data Ready interrupt." "0,1" newline bitfld.long 0x4 3. "ICRRDY,Receive Data Ready interrupt mask bit. Setting a'1' to this bit unmasks the Receive Data Ready interrupt. Setting a'0' to this bit masks the Receive Data Ready interrupt." "0,1" newline bitfld.long 0x4 2. "ARDY,Register access ready interrupt mask bit. Setting a'1' to this bit unmasks the Register access ready interrupt. Setting a'0' to this bit masks the Register access ready interrupt." "0,1" newline bitfld.long 0x4 1. "NACK,No Acknowledgement interrupt mask bit. Setting a'1' to this bit unmasks the No Acknowledgement interrupt. Setting a'0' to this bit masks the No Acknowledgement interrupt." "0,1" newline bitfld.long 0x4 0. "AL,Arbitration Lost interrupt mask bit. Setting a'1' to this bit unmasks the Arbitration Lost interrupt. Setting a'0' to this bit masks the Arbitration Lost interrupt." "0,1" line.long 0x8 "I2C3_ICSTR" bitfld.long 0x8 14. "SDIR,Slave Direction. This bit is clear to '0' indicating the I2C is a master transmitter/receiver or a slave receiver. This bit is also clear by STOP condition or START condition. It is set to '1' when the I2C slave is a transmitter. In DLB mode.." "0,1" newline bitfld.long 0x8 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'. NACKSNT =0: A No Acknowledge is not sent. NACKSNT =1: A No Acknowledge is sent. Writing a'1' to this bit to clear it." "0: A No Acknowledge is not sent,1: A No Acknowledge is sent" newline bitfld.long 0x8 12. "BB,Bus Busy. This bit indicates the state of the serial bus. BB=0: The bus is free. BB=1: The bus is occupied. On reception of a'start' condition the device sets BB to 1. This bit is also set if the I2C detects SCL low state. BB is clear to 0 after.." "0: The bus is free,1: The bus is occupied" newline bitfld.long 0x8 11. "RSFULL,Receive shift full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when the receive shift register (ICRSR) is full and ICDRR has not been read since the ICRSR-to-ICDRR transfer. The FSM is holding for ICDRR.." "0,1" newline bitfld.long 0x8 10. "XSMT,Transmit shift empty not. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when the transmit shift register (ICXSR) is empty and ICDXR has not been loaded. The FSM is holding for ICDXR write access. XSMT_.." "0,1" newline bitfld.long 0x8 9. "AAS,Address As Slave. This bit is set to 1 by the device when it has recognized its own slave address or an address of all (8) zeros. The AAS bit is reset by stop condition or detection of any address byte that does not match ICOAR. - (RW )" "0,1" newline bitfld.long 0x8 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call). The AD0 bit is reset to 0 (default value) when a'start' or'stop' condition is detected. - (RW )" "0,1" newline bitfld.long 0x8 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition. This bit is cleared by reading ICIVR (as 110) or writing '1' to itself." "0,1" newline bitfld.long 0x8 4. "ICXRDY,Transmit Data Ready interrupt flag bit. ICXRDY is set to'1' is generated when the transmitted data has been copied from ICDXR to the transmit-shift register (ICXSR). ICRXDY is clear to'0' when the ICDXR is written. This bit can also be.." "0,1" newline bitfld.long 0x8 3. "ICRRDY,Receive Data Ready interrupt flag bit. ICRRDY is set to'1' when the received data has been copied from ICRSR into the ICDRR. ICRRDY is cleared to'0' when the ICDRR is read. This bit can also be polled by the CPU to read the received data in.." "0,1" newline bitfld.long 0x8 2. "ARDY,Register-access-ready interrupt flag bit. ARDY is generated by the hardware if the I2C is in the master mode when the previously programmed data and command has been performed and status bit has been updated. This flag is used by the CPU to let.." "0,1" newline bitfld.long 0x8 1. "NACK,No-Acknowledgement interrupt flag bit. The No Acknowledge flag bit is set when the hardware in 'master' mode detects no acknowledge has been received. This bit is NOT set by no-acknowledgement after Start byte Write '1' or Read the ICIVR (as 010).." "0,1" newline bitfld.long 0x8 0. "AL,Arbitration-Lost interrupt flag bit. The Arbitration Lost flag bit is set to 1 when the device in the 'master' mode senses it has lost an arbitration when two or more transmitters start a transmission almost simultaneously or when the I2C.." "0,1" line.long 0xC "I2C3_ICCLKL" hexmask.long.word 0xC 0.--15. 1. "ICCL15_ICCL0,Low time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL low time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)." line.long 0x10 "I2C3_ICCLKH" hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL high time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0)." line.long 0x14 "I2C3_ICCNT" hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count. This data count register is used to generate a Stop condition if a Stop condition is specified (STP=1). . ICCNT=1 data count is 1 :::::::::::::::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::::::::::::::.." line.long 0x18 "I2C3_ICDRR" hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data" line.long 0x1C "I2C3_ICSAR" hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Slave address. Use in both 7- and 10-bit address mode." line.long 0x20 "I2C3_ICDXR" hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data" line.long 0x24 "I2C3_ICMDR" bitfld.long 0x24 15. "NACKMOD,No Acknowledge (NACK) mode. This bit is used to send an Acknowledge (ACK) or a No Acknowledge (NACK) to the transmitter. This bit is only applicable when the I2C is in receiver mode. In master receiver mode when the internal data count.." "0,1" newline bitfld.long 0x24 14. "FREE,Free Running. This bit is used to determine the state of the I2C when a breakpoint is encountered in the HLL debugger. FREE=0: (default) Stops immediately if SCL is low and keep driving SCL low whether I2C is master transmitter/receiver. If.." "0: (default,1: The I2C runs free" newline bitfld.long 0x24 13. "STT,Start Condition (Master only mode). This bit can be set to a'1' by the CPU to generate a Start condition. In master mode when setting Start to'1' generates a Start condition. It is reset to '0' by the hardware after the Start condition has been.." "0,1" newline bitfld.long 0x24 12. "NU1,Reserved for IDLEEN (IDLE Enable on 5509). - (RW )" "0,1" newline bitfld.long 0x24 11. "STP,Stop Condition (Master mode only). This bit can be set to a'1' by the CPU to generate a Stop condition. It is reset to '0' by the hardware after the Stop condition has been generated. The Stop condition is generated when ICCNT passes 0 when.." "0,1" newline bitfld.long 0x24 10. "MST,Master. MST=0: The I 2 C peripheral is in the'slave' mode and clock is received from the'master' device. MST=1: The I 2 C peripheral is in the'master' mode and it generates the clock. This bit is clear when the transfer completed." "0: The I 2 C peripheral is in the'slave' mode and..,1: The I 2 C peripheral is in the'master' mode and.." newline bitfld.long 0x24 9. "TRX,Transmitter. TRX=0: The I 2 C is in the'receiver' mode and data on data line SDA is shifted into the data register ICDRR. TRX=1: The I 2 C is in the'transmitter' mode and the data in ICDXR is shifted out on data line SDA. The operating modes.." "0: The I 2 C is in the'receiver' mode and data on..,1: The I 2 C is in the'transmitter' mode and the.." newline bitfld.long 0x24 8. "XA,Expanded Address. XA=0: (default) 7-bit address mode (normal address mode). XA=1: 10-bit address mode (expanded address mode) Please note that XA needs to be configured even if the I2C is in slave mode." "0: (default,1: 10-bit address mode" newline bitfld.long 0x24 7. "RM,Repeat Mode. This bit is set to a'1' by the CPU to put the I2C in the repeat mode. In this mode data is continuously transmitted out of the ICDXR until the STP bit is set to'1' regardless of ICCNT value. This bit is don't care if the I2C is.." "0,1" newline bitfld.long 0x24 6. "DLB,Digital Loop Back (in master transmit mode only). This bit is set to a'1' by the CPU to put the I2C in the loop back mode. In this mode data transmitted out of the ICDXR will be received in the ICDRR after ((CPU freq/I2C freq)8) CPU cycles via.." "0,1" newline bitfld.long 0x24 5. "IRS,I2C Reset Not. This can be set to a'0' by the CPU to put the I2C in reset or to a'1' to take the I2C out of reset. When this bit is reset to 0 all status bits in ICSTR and ICIVR are set to default values. Note that if this bit is reset during.." "0,1" newline bitfld.long 0x24 4. "STB,Start Byte (Master only mode). The Start Byte mode bit is set to 1 by the CPU to configure the I2C in Start byte mode the I2C sends '00000001'? regardless ICSAR value. Refer to the Philip I2C spec for more details." "0,1" newline bitfld.long 0x24 3. "FDF,Free Data Format. This bit can be set to'1' by the CPU to configure the I2C in Free Data Format mode. ______________________________________________FDF___MST___TRX______Operating mode _0______0_____ x____Slave in non FDF mode.." "0,1" newline bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted." "0,1,2,3,4,5,6,7" line.long 0x28 "I2C3_ICIVR" hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved." newline hexmask.long.byte 0x28 8.--11. 1. "TESTMD,Reserved for internal testing." newline hexmask.long.byte 0x28 3.--7. 1. "NU1,Reserved." newline bitfld.long 0x28 0.--2. "INTCODE,Interrupt code. The binary-coded-interrupt vector indicates which interrupt has occurred. Reading the ICIVR clears the interrupt code except ARDY(011) RRDY(100) and XRDY(101). Interrupt code for ARDY RRDY and XRDY is cleared when ARDY ICRRDY.." "0,1,2,3,4,5,6,7" line.long 0x2C "I2C3_ICEMDR" hexmask.long 0x2C 2.--31. 1. "NU,Reserved. - (RW )" newline bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave. IGNACK=1 The master transmitter will ignore a NACK.." "0,1" newline bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode. This bit affects the I2C interrupt behavior. Refer to appendix A for details." "0,1" line.long 0x30 "I2C3_ICPSC" hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved." newline hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module. This register must be initialized while the I2C is still in reset (IRS_=0). The value takes effect on the rising edge of IRS_." line.long 0x34 "I2C3_ICPID1" hexmask.long.word 0x34 16.--31. 1. "NU,Reserved." newline hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral. This value should be 0x01 - (RW )" newline hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C. This value should be incremented each time the design is revised. - (RW )" line.long 0x38 "I2C3_ICPID2" hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved." newline hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral. This value should be 0x05 - (RW )" line.long 0x3C "I2C3_ICDMAC" hexmask.long 0x3C 2.--31. 1. "NU,Reserved. - (RW )" newline bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICTEVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICTEVT_POR pin is never.." "0: DMA transmit event is disabled,1: DMA transmit event is enabled" newline bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICREVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICREVT_POR pin is never.." "0: DMA receive event is disabled,1: DMA receive event is enabled" line.long 0x40 "I2C3_I2C_RESERVED1" hexmask.long 0x40 0.--31. 1. "NU,Reserved." line.long 0x44 "I2C3_I2C_RESERVED2" hexmask.long 0x44 0.--31. 1. "NU,Reserved." line.long 0x48 "I2C3_ICPFUNC" hexmask.long 0x48 1.--31. 1. "NU,Reserved." newline bitfld.long 0x48 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins. 0 = Pins function as SCL and SDA 1 = Pins functions as GPIO Note: No hardware protection is required to disable I2C function when the PFUNC[0] and IRS_ bits are both set to one. When PFUNC[0].." "0: Pins function as SCL and SDA,1: Pins functions as GPIO Note: No hardware.." line.long 0x4C "I2C3_ICPDIR" bitfld.long 0x4C 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO. 0 = SDA pin functions as input 1 = SDA pin functions as output" "0: SDA pin functions as input,1: SDA pin functions as output" newline bitfld.long 0x4C 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO. 0 = SCL pin functions as input 1 = SCL pin functions as output" "0: SCL pin functions as input,1: SCL pin functions as output" line.long 0x50 "I2C3_ICPDIN" bitfld.long 0x50 1. "PDIN1,Indicates the logic level present on the SDA pin. Reads: 0 = Logic low present at SDA pin regardless of PFUNC setting. 1 = Logic high present at SDA pin regardless of PFUNC setting. Writes: Writes have no effect. - (RW )" "0: Logic low present at SDA pin regardless of PFUNC..,1: Logic high present at SDA pin regardless of.." newline bitfld.long 0x50 0. "PDIN0,Indicates the logic level present on the SCL pin. Reads: 0 = Logic low present at SCL pin regardless of PFUNC setting. 1 = Logic high present at SCL pin regardless of PFUNC setting. Writes: Writes have no effect - (RW )" "0: Logic low present at SCL pin regardless of PFUNC..,1: Logic high present at SCL pin regardless of.." line.long 0x54 "I2C3_ICPDOUT" bitfld.long 0x54 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SDA pin driven low 1 = SDA pin driven high. Note: If SDA is connected to an open-drain buffer at.." "0: SDA pin driven low,1: SDA pin driven high" newline bitfld.long 0x54 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SCL pin driven low 1 = SCL pin driven high Note: If SCL is connected to an open-drain buffer at.." "0: SCL pin driven low,1: SCL pin driven high Note: If SCL is connected to.." line.long 0x58 "I2C3_ICPDSET" bitfld.long 0x58 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is set to logic high." "0: no effect,1: PDOUT[1] bit is set to logic high" newline bitfld.long 0x58 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is set to logic high." "0: no effect,1: PDOUT[0] bit is set to logic high" line.long 0x5C "I2C3_ICPDCLR" bitfld.long 0x5C 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is cleared to logic low." "0: no effect,1: PDOUT[1] bit is cleared to logic low" newline bitfld.long 0x5C 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is cleared to logic low." "0: no effect,1: PDOUT[0] bit is cleared to logic low" line.long 0x60 "I2C3_ICPDRV" bitfld.long 0x60 1. "PDRV1,Used to select driver mode of output buffer for SDA pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SDA_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" newline bitfld.long 0x60 0. "PDRV0,Used to select driver mode of output buffer for SCL pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SCL_POR port. Actual function depends on I/O buffer and chip implementation." "0: I2C mode,1: GPIO mode" tree.end tree.end tree "ICSSM_INTR_XBAR" base ad:0x52E03000 rgroup.long 0x0++0x3 line.long 0x0 "ICSSM_INTR_XBAR_PID" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "ICSSM_INTR_XBAR_MUXCNTL" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.byte 0x0 0.--5. 1. "ENABLE,Mux control for interrupt N" tree.end tree "IOMUX" base ad:0x53100000 group.long 0x0++0x29F line.long 0x0 "IOMUX_QSPI0_CSN0_CFG_REG" bitfld.long 0x0 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x0 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x0 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x0 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x0 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x0 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x0 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x0 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x0 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "FUNC_SEL,Function select" line.long 0x4 "IOMUX_QSPI0_CSN1_CFG_REG" bitfld.long 0x4 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x4 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x4 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x4 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x4 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x4 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x4 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x4 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x4 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "FUNC_SEL,Function select" line.long 0x8 "IOMUX_QSPI0_CLK_CFG_REG" bitfld.long 0x8 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x8 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x8 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x8 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x8 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x8 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x8 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x8 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x8 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "FUNC_SEL,Function select" line.long 0xC "IOMUX_QSPI0_D0_CFG_REG" bitfld.long 0xC 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xC 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xC 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xC 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xC 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xC 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xC 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xC 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xC 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x10 "IOMUX_QSPI0_D1_CFG_REG" bitfld.long 0x10 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x10 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x10 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x10 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x10 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x10 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x10 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x10 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x10 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x10 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x10 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x10 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x10 0.--3. 1. "FUNC_SEL,Function select" line.long 0x14 "IOMUX_QSPI0_D2_CFG_REG" bitfld.long 0x14 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x14 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x14 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x14 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x14 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x14 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x14 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x14 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x14 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x14 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x14 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x14 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x14 0.--3. 1. "FUNC_SEL,Function select" line.long 0x18 "IOMUX_QSPI0_D3_CFG_REG" bitfld.long 0x18 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x18 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x18 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x18 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x18 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x18 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x18 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x18 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x18 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x18 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x18 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x18 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x18 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1C "IOMUX_MCAN0_RX_CFG_REG" bitfld.long 0x1C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x20 "IOMUX_MCAN0_TX_CFG_REG" bitfld.long 0x20 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x20 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x20 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x20 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x20 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x20 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x20 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x20 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x20 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x20 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x20 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x20 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x20 0.--3. 1. "FUNC_SEL,Function select" line.long 0x24 "IOMUX_MCAN1_RX_CFG_REG" bitfld.long 0x24 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x24 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x24 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x24 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x24 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x24 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x24 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x24 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x24 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x24 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x24 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x24 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x24 0.--3. 1. "FUNC_SEL,Function select" line.long 0x28 "IOMUX_MCAN1_TX_CFG_REG" bitfld.long 0x28 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x28 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x28 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x28 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x28 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x28 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x28 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x28 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x28 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x28 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x28 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x28 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "FUNC_SEL,Function select" line.long 0x2C "IOMUX_SPI0_CS0_CFG_REG" bitfld.long 0x2C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x2C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x2C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x2C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x2C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x2C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x2C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x2C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x2C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x2C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x2C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x2C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x2C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x30 "IOMUX_SPI0_CLK_CFG_REG" bitfld.long 0x30 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x30 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x30 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x30 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x30 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x30 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x30 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x30 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x30 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x30 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x30 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x30 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "FUNC_SEL,Function select" line.long 0x34 "IOMUX_SPI0_D0_CFG_REG" bitfld.long 0x34 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x34 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x34 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x34 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x34 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x34 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x34 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x34 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x34 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x34 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x34 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x34 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x34 0.--3. 1. "FUNC_SEL,Function select" line.long 0x38 "IOMUX_SPI0_D1_CFG_REG" bitfld.long 0x38 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x38 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x38 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x38 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x38 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x38 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x38 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x38 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x38 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x38 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x38 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x38 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x38 0.--3. 1. "FUNC_SEL,Function select" line.long 0x3C "IOMUX_SPI1_CS0_CFG_REG" bitfld.long 0x3C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x3C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x3C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x3C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x3C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x3C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x3C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x3C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x3C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x3C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x3C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x3C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x3C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x40 "IOMUX_SPI1_CLK_CFG_REG" bitfld.long 0x40 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x40 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x40 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x40 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x40 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x40 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x40 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x40 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x40 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x40 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x40 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x40 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x40 0.--3. 1. "FUNC_SEL,Function select" line.long 0x44 "IOMUX_SPI1_D0_CFG_REG" bitfld.long 0x44 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x44 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x44 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x44 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x44 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x44 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x44 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x44 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x44 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x44 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x44 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x44 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x44 0.--3. 1. "FUNC_SEL,Function select" line.long 0x48 "IOMUX_SPI1_D1_CFG_REG" bitfld.long 0x48 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x48 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x48 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x48 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x48 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x48 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x48 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x48 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x48 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x48 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x48 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x48 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x48 0.--3. 1. "FUNC_SEL,Function select" line.long 0x4C "IOMUX_LIN1_RXD_CFG_REG" bitfld.long 0x4C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x4C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x4C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x4C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x4C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x4C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x4C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x4C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x4C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x4C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x4C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x4C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x4C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x50 "IOMUX_LIN1_TXD_CFG_REG" bitfld.long 0x50 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x50 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x50 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x50 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x50 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x50 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x50 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x50 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x50 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x50 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x50 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x50 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x50 0.--3. 1. "FUNC_SEL,Function select" line.long 0x54 "IOMUX_LIN2_RXD_CFG_REG" bitfld.long 0x54 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x54 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x54 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x54 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x54 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x54 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x54 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x54 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x54 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x54 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x54 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x54 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x54 0.--3. 1. "FUNC_SEL,Function select" line.long 0x58 "IOMUX_LIN2_TXD_CFG_REG" bitfld.long 0x58 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x58 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x58 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x58 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x58 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x58 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x58 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x58 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x58 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x58 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x58 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x58 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x58 0.--3. 1. "FUNC_SEL,Function select" line.long 0x5C "IOMUX_I2C1_SCL_CFG_REG" bitfld.long 0x5C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x5C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x5C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x5C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x5C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x5C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x5C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x5C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x5C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x5C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x5C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x5C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x5C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x60 "IOMUX_I2C1_SDA_CFG_REG" bitfld.long 0x60 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x60 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x60 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x60 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x60 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x60 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x60 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x60 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x60 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x60 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x60 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x60 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x60 0.--3. 1. "FUNC_SEL,Function select" line.long 0x64 "IOMUX_UART0_RTSN_CFG_REG" bitfld.long 0x64 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x64 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x64 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x64 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x64 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x64 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x64 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x64 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x64 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x64 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x64 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x64 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x64 0.--3. 1. "FUNC_SEL,Function select" line.long 0x68 "IOMUX_UART0_CTSN_CFG_REG" bitfld.long 0x68 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x68 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x68 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x68 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x68 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x68 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x68 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x68 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x68 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x68 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x68 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x68 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x68 0.--3. 1. "FUNC_SEL,Function select" line.long 0x6C "IOMUX_UART0_RXD_CFG_REG" bitfld.long 0x6C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x6C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x6C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x6C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x6C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x6C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x6C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x6C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x6C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x6C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x6C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x6C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x6C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x70 "IOMUX_UART0_TXD_CFG_REG" bitfld.long 0x70 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x70 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x70 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x70 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x70 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x70 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x70 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x70 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x70 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x70 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x70 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x70 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x70 0.--3. 1. "FUNC_SEL,Function select" line.long 0x74 "IOMUX_RGMII1_RXC_CFG_REG" bitfld.long 0x74 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x74 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x74 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x74 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x74 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x74 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x74 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x74 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x74 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x74 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x74 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x74 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x74 0.--3. 1. "FUNC_SEL,Function select" line.long 0x78 "IOMUX_RGMII1_RX_CTL_CFG_REG" bitfld.long 0x78 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x78 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x78 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x78 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x78 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x78 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x78 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x78 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x78 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x78 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x78 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x78 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x78 0.--3. 1. "FUNC_SEL,Function select" line.long 0x7C "IOMUX_RGMII1_RD0_CFG_REG" bitfld.long 0x7C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x7C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x7C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x7C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x7C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x7C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x7C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x7C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x7C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x7C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x7C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x7C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x7C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x80 "IOMUX_RGMII1_RD1_CFG_REG" bitfld.long 0x80 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x80 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x80 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x80 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x80 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x80 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x80 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x80 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x80 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x80 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x80 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x80 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x80 0.--3. 1. "FUNC_SEL,Function select" line.long 0x84 "IOMUX_RGMII1_RD2_CFG_REG" bitfld.long 0x84 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x84 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x84 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x84 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x84 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x84 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x84 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x84 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x84 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x84 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x84 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x84 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x84 0.--3. 1. "FUNC_SEL,Function select" line.long 0x88 "IOMUX_RGMII1_RD3_CFG_REG" bitfld.long 0x88 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x88 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x88 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x88 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x88 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x88 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x88 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x88 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x88 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x88 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x88 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x88 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x88 0.--3. 1. "FUNC_SEL,Function select" line.long 0x8C "IOMUX_RGMII1_TXC_CFG_REG" bitfld.long 0x8C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x8C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x8C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x8C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x8C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x8C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x8C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x8C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x8C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x8C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x8C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x8C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x8C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x90 "IOMUX_RGMII1_TX_CTL_CFG_REG" bitfld.long 0x90 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x90 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x90 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x90 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x90 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x90 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x90 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x90 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x90 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x90 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x90 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x90 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x90 0.--3. 1. "FUNC_SEL,Function select" line.long 0x94 "IOMUX_RGMII1_TD0_CFG_REG" bitfld.long 0x94 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x94 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x94 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x94 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x94 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x94 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x94 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x94 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x94 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x94 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x94 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x94 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x94 0.--3. 1. "FUNC_SEL,Function select" line.long 0x98 "IOMUX_RGMII1_TD1_CFG_REG" bitfld.long 0x98 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x98 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x98 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x98 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x98 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x98 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x98 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x98 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x98 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x98 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x98 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x98 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x98 0.--3. 1. "FUNC_SEL,Function select" line.long 0x9C "IOMUX_RGMII1_TD2_CFG_REG" bitfld.long 0x9C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x9C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x9C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x9C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x9C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x9C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x9C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x9C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x9C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x9C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x9C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x9C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x9C 0.--3. 1. "FUNC_SEL,Function select" line.long 0xA0 "IOMUX_RGMII1_TD3_CFG_REG" bitfld.long 0xA0 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xA0 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xA0 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xA0 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xA0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xA0 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xA0 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xA0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xA0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xA0 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xA0 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xA0 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xA0 0.--3. 1. "FUNC_SEL,Function select" line.long 0xA4 "IOMUX_MDIO0_MDIO_CFG_REG" bitfld.long 0xA4 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xA4 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xA4 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xA4 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xA4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xA4 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xA4 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xA4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xA4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xA4 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xA4 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xA4 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xA4 0.--3. 1. "FUNC_SEL,Function select" line.long 0xA8 "IOMUX_MDIO0_MDC_CFG_REG" bitfld.long 0xA8 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xA8 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xA8 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xA8 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xA8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xA8 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xA8 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xA8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xA8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xA8 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xA8 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xA8 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xA8 0.--3. 1. "FUNC_SEL,Function select" line.long 0xAC "IOMUX_EPWM0_A_CFG_REG" bitfld.long 0xAC 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xAC 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xAC 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xAC 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xAC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xAC 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xAC 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xAC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xAC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xAC 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xAC 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xAC 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xAC 0.--3. 1. "FUNC_SEL,Function select" line.long 0xB0 "IOMUX_EPWM0_B_CFG_REG" bitfld.long 0xB0 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xB0 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xB0 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xB0 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xB0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xB0 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xB0 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xB0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xB0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xB0 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xB0 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xB0 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xB0 0.--3. 1. "FUNC_SEL,Function select" line.long 0xB4 "IOMUX_EPWM1_A_CFG_REG" bitfld.long 0xB4 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xB4 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xB4 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xB4 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xB4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xB4 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xB4 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xB4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xB4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xB4 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xB4 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xB4 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xB4 0.--3. 1. "FUNC_SEL,Function select" line.long 0xB8 "IOMUX_EPWM1_B_CFG_REG" bitfld.long 0xB8 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xB8 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xB8 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xB8 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xB8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xB8 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xB8 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xB8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xB8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xB8 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xB8 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xB8 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xB8 0.--3. 1. "FUNC_SEL,Function select" line.long 0xBC "IOMUX_EPWM2_A_CFG_REG" bitfld.long 0xBC 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xBC 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xBC 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xBC 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xBC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xBC 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xBC 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xBC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xBC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xBC 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xBC 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xBC 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xBC 0.--3. 1. "FUNC_SEL,Function select" line.long 0xC0 "IOMUX_EPWM2_B_CFG_REG" bitfld.long 0xC0 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xC0 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xC0 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xC0 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xC0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xC0 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xC0 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xC0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xC0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xC0 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xC0 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xC0 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xC0 0.--3. 1. "FUNC_SEL,Function select" line.long 0xC4 "IOMUX_EPWM3_A_CFG_REG" bitfld.long 0xC4 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xC4 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xC4 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xC4 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xC4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xC4 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xC4 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xC4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xC4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xC4 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xC4 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xC4 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xC4 0.--3. 1. "FUNC_SEL,Function select" line.long 0xC8 "IOMUX_EPWM3_B_CFG_REG" bitfld.long 0xC8 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xC8 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xC8 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xC8 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xC8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xC8 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xC8 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xC8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xC8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xC8 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xC8 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xC8 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xC8 0.--3. 1. "FUNC_SEL,Function select" line.long 0xCC "IOMUX_EPWM4_A_CFG_REG" bitfld.long 0xCC 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xCC 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xCC 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xCC 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xCC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xCC 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xCC 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xCC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xCC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xCC 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xCC 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xCC 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xCC 0.--3. 1. "FUNC_SEL,Function select" line.long 0xD0 "IOMUX_EPWM4_B_CFG_REG" bitfld.long 0xD0 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xD0 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xD0 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xD0 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xD0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xD0 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xD0 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xD0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xD0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xD0 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xD0 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xD0 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xD0 0.--3. 1. "FUNC_SEL,Function select" line.long 0xD4 "IOMUX_EPWM5_A_CFG_REG" bitfld.long 0xD4 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xD4 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xD4 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xD4 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xD4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xD4 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xD4 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xD4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xD4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xD4 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xD4 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xD4 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xD4 0.--3. 1. "FUNC_SEL,Function select" line.long 0xD8 "IOMUX_EPWM5_B_CFG_REG" bitfld.long 0xD8 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xD8 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xD8 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xD8 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xD8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xD8 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xD8 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xD8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xD8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xD8 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xD8 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xD8 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xD8 0.--3. 1. "FUNC_SEL,Function select" line.long 0xDC "IOMUX_EPWM6_A_CFG_REG" bitfld.long 0xDC 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xDC 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xDC 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xDC 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xDC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xDC 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xDC 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xDC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xDC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xDC 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xDC 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xDC 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xDC 0.--3. 1. "FUNC_SEL,Function select" line.long 0xE0 "IOMUX_EPWM6_B_CFG_REG" bitfld.long 0xE0 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xE0 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xE0 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xE0 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xE0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xE0 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xE0 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xE0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xE0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xE0 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xE0 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xE0 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xE0 0.--3. 1. "FUNC_SEL,Function select" line.long 0xE4 "IOMUX_EPWM7_A_CFG_REG" bitfld.long 0xE4 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xE4 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xE4 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xE4 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xE4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xE4 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xE4 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xE4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xE4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xE4 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xE4 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xE4 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xE4 0.--3. 1. "FUNC_SEL,Function select" line.long 0xE8 "IOMUX_EPWM7_B_CFG_REG" bitfld.long 0xE8 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xE8 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xE8 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xE8 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xE8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xE8 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xE8 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xE8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xE8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xE8 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xE8 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xE8 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xE8 0.--3. 1. "FUNC_SEL,Function select" line.long 0xEC "IOMUX_EPWM8_A_CFG_REG" bitfld.long 0xEC 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xEC 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xEC 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xEC 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xEC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xEC 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xEC 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xEC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xEC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xEC 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xEC 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xEC 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xEC 0.--3. 1. "FUNC_SEL,Function select" line.long 0xF0 "IOMUX_EPWM8_B_CFG_REG" bitfld.long 0xF0 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xF0 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xF0 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xF0 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xF0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xF0 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xF0 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xF0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xF0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xF0 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xF0 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xF0 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xF0 0.--3. 1. "FUNC_SEL,Function select" line.long 0xF4 "IOMUX_EPWM9_A_CFG_REG" bitfld.long 0xF4 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xF4 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xF4 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xF4 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xF4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xF4 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xF4 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xF4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xF4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xF4 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xF4 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xF4 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xF4 0.--3. 1. "FUNC_SEL,Function select" line.long 0xF8 "IOMUX_EPWM9_B_CFG_REG" bitfld.long 0xF8 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xF8 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xF8 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xF8 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xF8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xF8 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xF8 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xF8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xF8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xF8 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xF8 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xF8 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xF8 0.--3. 1. "FUNC_SEL,Function select" line.long 0xFC "IOMUX_EPWM10_A_CFG_REG" bitfld.long 0xFC 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0xFC 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0xFC 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0xFC 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0xFC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0xFC 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0xFC 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0xFC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0xFC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0xFC 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0xFC 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0xFC 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0xFC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x100 "IOMUX_EPWM10_B_CFG_REG" bitfld.long 0x100 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x100 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x100 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x100 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x100 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x100 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x100 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x100 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x100 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x100 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x100 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x100 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x100 0.--3. 1. "FUNC_SEL,Function select" line.long 0x104 "IOMUX_EPWM11_A_CFG_REG" bitfld.long 0x104 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x104 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x104 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x104 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x104 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x104 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x104 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x104 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x104 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x104 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x104 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x104 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x104 0.--3. 1. "FUNC_SEL,Function select" line.long 0x108 "IOMUX_EPWM11_B_CFG_REG" bitfld.long 0x108 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x108 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x108 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x108 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x108 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x108 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x108 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x108 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x108 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x108 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x108 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x108 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x108 0.--3. 1. "FUNC_SEL,Function select" line.long 0x10C "IOMUX_EPWM12_A_CFG_REG" bitfld.long 0x10C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x10C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x10C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x10C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x10C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x10C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x10C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x10C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x10C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x10C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x10C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x10C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x10C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x110 "IOMUX_EPWM12_B_CFG_REG" bitfld.long 0x110 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x110 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x110 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x110 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x110 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x110 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x110 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x110 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x110 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x110 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x110 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x110 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x110 0.--3. 1. "FUNC_SEL,Function select" line.long 0x114 "IOMUX_EPWM13_A_CFG_REG" bitfld.long 0x114 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x114 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x114 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x114 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x114 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x114 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x114 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x114 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x114 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x114 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x114 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x114 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x114 0.--3. 1. "FUNC_SEL,Function select" line.long 0x118 "IOMUX_EPWM13_B_CFG_REG" bitfld.long 0x118 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x118 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x118 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x118 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x118 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x118 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x118 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x118 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x118 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x118 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x118 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x118 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x118 0.--3. 1. "FUNC_SEL,Function select" line.long 0x11C "IOMUX_EPWM14_A_CFG_REG" bitfld.long 0x11C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x11C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x11C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x11C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x11C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x11C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x11C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x11C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x11C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x11C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x11C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x11C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x11C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x120 "IOMUX_EPWM14_B_CFG_REG" bitfld.long 0x120 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x120 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x120 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x120 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x120 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x120 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x120 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x120 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x120 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x120 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x120 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x120 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x120 0.--3. 1. "FUNC_SEL,Function select" line.long 0x124 "IOMUX_EPWM15_A_CFG_REG" bitfld.long 0x124 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x124 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x124 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x124 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x124 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x124 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x124 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x124 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x124 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x124 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x124 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x124 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x124 0.--3. 1. "FUNC_SEL,Function select" line.long 0x128 "IOMUX_EPWM15_B_CFG_REG" bitfld.long 0x128 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x128 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x128 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x128 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x128 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x128 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x128 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x128 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x128 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x128 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x128 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x128 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x128 0.--3. 1. "FUNC_SEL,Function select" line.long 0x12C "IOMUX_UART1_RXD_CFG_REG" bitfld.long 0x12C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x12C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x12C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x12C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x12C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x12C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x12C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x12C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x12C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x12C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x12C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x12C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x12C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x130 "IOMUX_UART1_TXD_CFG_REG" bitfld.long 0x130 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x130 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x130 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x130 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x130 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x130 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x130 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x130 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x130 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x130 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x130 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x130 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x130 0.--3. 1. "FUNC_SEL,Function select" line.long 0x134 "IOMUX_MMC0_CLK_CFG_REG" bitfld.long 0x134 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x134 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x134 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x134 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x134 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x134 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x134 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x134 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x134 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x134 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x134 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x134 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x134 0.--3. 1. "FUNC_SEL,Function select" line.long 0x138 "IOMUX_MMC0_CMD_CFG_REG" bitfld.long 0x138 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x138 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x138 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x138 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x138 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x138 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x138 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x138 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x138 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x138 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x138 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x138 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x138 0.--3. 1. "FUNC_SEL,Function select" line.long 0x13C "IOMUX_MMC0_D0_CFG_REG" bitfld.long 0x13C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x13C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x13C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x13C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x13C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x13C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x13C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x13C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x13C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x13C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x13C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x13C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x13C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x140 "IOMUX_MMC0_D1_CFG_REG" bitfld.long 0x140 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x140 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x140 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x140 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x140 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x140 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x140 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x140 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x140 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x140 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x140 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x140 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x140 0.--3. 1. "FUNC_SEL,Function select" line.long 0x144 "IOMUX_MMC0_D2_CFG_REG" bitfld.long 0x144 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x144 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x144 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x144 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x144 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x144 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x144 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x144 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x144 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x144 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x144 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x144 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x144 0.--3. 1. "FUNC_SEL,Function select" line.long 0x148 "IOMUX_MMC0_D3_CFG_REG" bitfld.long 0x148 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x148 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x148 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x148 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x148 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x148 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x148 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x148 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x148 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x148 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x148 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x148 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x148 0.--3. 1. "FUNC_SEL,Function select" line.long 0x14C "IOMUX_MMC0_WP_CFG_REG" bitfld.long 0x14C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x14C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x14C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x14C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x14C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x14C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x14C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x14C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x14C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x14C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x14C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x14C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x14C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x150 "IOMUX_MMC0_CD_CFG_REG" bitfld.long 0x150 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x150 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x150 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x150 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x150 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x150 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x150 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x150 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x150 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x150 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x150 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x150 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x150 0.--3. 1. "FUNC_SEL,Function select" line.long 0x154 "IOMUX_PR0_MDIO0_MDIO_CFG_REG" bitfld.long 0x154 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x154 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x154 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x154 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x154 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x154 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x154 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x154 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x154 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x154 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x154 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x154 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x154 0.--3. 1. "FUNC_SEL,Function select" line.long 0x158 "IOMUX_PR0_MDIO0_MDC_CFG_REG" bitfld.long 0x158 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x158 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x158 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x158 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x158 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x158 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x158 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x158 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x158 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x158 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x158 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x158 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x158 0.--3. 1. "FUNC_SEL,Function select" line.long 0x15C "IOMUX_PR0_PRU0_GPO5_CFG_REG" bitfld.long 0x15C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x15C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x15C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x15C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x15C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x15C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x15C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x15C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x15C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x15C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x15C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x15C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x15C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x160 "IOMUX_PR0_PRU0_GPO9_CFG_REG" bitfld.long 0x160 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x160 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x160 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x160 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x160 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x160 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x160 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x160 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x160 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x160 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x160 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x160 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x160 0.--3. 1. "FUNC_SEL,Function select" line.long 0x164 "IOMUX_PR0_PRU0_GPO10_CFG_REG" bitfld.long 0x164 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x164 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x164 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x164 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x164 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x164 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x164 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x164 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x164 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x164 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x164 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x164 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x164 0.--3. 1. "FUNC_SEL,Function select" line.long 0x168 "IOMUX_PR0_PRU0_GPO8_CFG_REG" bitfld.long 0x168 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x168 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x168 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x168 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x168 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x168 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x168 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x168 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x168 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x168 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x168 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x168 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x168 0.--3. 1. "FUNC_SEL,Function select" line.long 0x16C "IOMUX_PR0_PRU0_GPO6_CFG_REG" bitfld.long 0x16C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x16C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x16C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x16C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x16C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x16C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x16C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x16C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x16C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x16C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x16C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x16C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x16C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x170 "IOMUX_PR0_PRU0_GPO4_CFG_REG" bitfld.long 0x170 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x170 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x170 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x170 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x170 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x170 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x170 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x170 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x170 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x170 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x170 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x170 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x170 0.--3. 1. "FUNC_SEL,Function select" line.long 0x174 "IOMUX_PR0_PRU0_GPO0_CFG_REG" bitfld.long 0x174 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x174 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x174 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x174 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x174 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x174 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x174 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x174 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x174 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x174 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x174 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x174 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x174 0.--3. 1. "FUNC_SEL,Function select" line.long 0x178 "IOMUX_PR0_PRU0_GPO1_CFG_REG" bitfld.long 0x178 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x178 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x178 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x178 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x178 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x178 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x178 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x178 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x178 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x178 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x178 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x178 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x178 0.--3. 1. "FUNC_SEL,Function select" line.long 0x17C "IOMUX_PR0_PRU0_GPO2_CFG_REG" bitfld.long 0x17C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x17C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x17C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x17C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x17C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x17C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x17C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x17C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x17C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x17C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x17C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x17C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x17C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x180 "IOMUX_PR0_PRU0_GPO3_CFG_REG" bitfld.long 0x180 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x180 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x180 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x180 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x180 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x180 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x180 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x180 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x180 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x180 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x180 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x180 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x180 0.--3. 1. "FUNC_SEL,Function select" line.long 0x184 "IOMUX_PR0_PRU0_GPO16_CFG_REG" bitfld.long 0x184 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x184 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x184 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x184 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x184 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x184 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x184 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x184 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x184 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x184 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x184 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x184 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x184 0.--3. 1. "FUNC_SEL,Function select" line.long 0x188 "IOMUX_PR0_PRU0_GPO15_CFG_REG" bitfld.long 0x188 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x188 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x188 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x188 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x188 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x188 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x188 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x188 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x188 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x188 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x188 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x188 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x188 0.--3. 1. "FUNC_SEL,Function select" line.long 0x18C "IOMUX_PR0_PRU0_GPO11_CFG_REG" bitfld.long 0x18C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x18C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x18C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x18C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x18C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x18C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x18C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x18C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x18C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x18C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x18C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x18C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x18C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x190 "IOMUX_PR0_PRU0_GPO12_CFG_REG" bitfld.long 0x190 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x190 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x190 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x190 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x190 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x190 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x190 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x190 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x190 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x190 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x190 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x190 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x190 0.--3. 1. "FUNC_SEL,Function select" line.long 0x194 "IOMUX_PR0_PRU0_GPO13_CFG_REG" bitfld.long 0x194 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x194 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x194 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x194 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x194 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x194 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x194 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x194 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x194 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x194 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x194 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x194 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x194 0.--3. 1. "FUNC_SEL,Function select" line.long 0x198 "IOMUX_PR0_PRU0_GPO14_CFG_REG" bitfld.long 0x198 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x198 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x198 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x198 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x198 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x198 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x198 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x198 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x198 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x198 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x198 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x198 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x198 0.--3. 1. "FUNC_SEL,Function select" line.long 0x19C "IOMUX_PR0_PRU1_GPO5_CFG_REG" bitfld.long 0x19C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x19C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x19C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x19C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x19C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x19C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x19C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x19C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x19C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x19C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x19C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x19C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x19C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1A0 "IOMUX_PR0_PRU1_GPO9_CFG_REG" bitfld.long 0x1A0 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1A0 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1A0 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1A0 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1A0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1A0 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1A0 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1A0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1A0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1A0 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1A0 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1A0 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1A0 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1A4 "IOMUX_PR0_PRU1_GPO10_CFG_REG" bitfld.long 0x1A4 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1A4 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1A4 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1A4 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1A4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1A4 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1A4 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1A4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1A4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1A4 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1A4 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1A4 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1A4 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1A8 "IOMUX_PR0_PRU1_GPO8_CFG_REG" bitfld.long 0x1A8 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1A8 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1A8 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1A8 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1A8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1A8 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1A8 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1A8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1A8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1A8 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1A8 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1A8 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1A8 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1AC "IOMUX_PR0_PRU1_GPO6_CFG_REG" bitfld.long 0x1AC 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1AC 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1AC 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1AC 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1AC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1AC 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1AC 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1AC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1AC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1AC 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1AC 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1AC 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1AC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1B0 "IOMUX_PR0_PRU1_GPO4_CFG_REG" bitfld.long 0x1B0 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1B0 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1B0 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1B0 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1B0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1B0 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1B0 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1B0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1B0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1B0 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1B0 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1B0 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1B0 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1B4 "IOMUX_PR0_PRU1_GPO0_CFG_REG" bitfld.long 0x1B4 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1B4 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1B4 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1B4 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1B4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1B4 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1B4 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1B4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1B4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1B4 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1B4 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1B4 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1B4 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1B8 "IOMUX_PR0_PRU1_GPO1_CFG_REG" bitfld.long 0x1B8 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1B8 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1B8 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1B8 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1B8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1B8 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1B8 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1B8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1B8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1B8 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1B8 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1B8 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1B8 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1BC "IOMUX_PR0_PRU1_GPO2_CFG_REG" bitfld.long 0x1BC 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1BC 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1BC 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1BC 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1BC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1BC 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1BC 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1BC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1BC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1BC 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1BC 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1BC 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1BC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1C0 "IOMUX_PR0_PRU1_GPO3_CFG_REG" bitfld.long 0x1C0 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1C0 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1C0 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1C0 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1C0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1C0 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1C0 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1C0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1C0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1C0 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1C0 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1C0 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1C0 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1C4 "IOMUX_PR0_PRU1_GPO16_CFG_REG" bitfld.long 0x1C4 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1C4 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1C4 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1C4 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1C4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1C4 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1C4 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1C4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1C4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1C4 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1C4 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1C4 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1C4 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1C8 "IOMUX_PR0_PRU1_GPO15_CFG_REG" bitfld.long 0x1C8 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1C8 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1C8 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1C8 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1C8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1C8 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1C8 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1C8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1C8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1C8 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1C8 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1C8 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1C8 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1CC "IOMUX_PR0_PRU1_GPO11_CFG_REG" bitfld.long 0x1CC 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1CC 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1CC 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1CC 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1CC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1CC 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1CC 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1CC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1CC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1CC 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1CC 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1CC 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1CC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1D0 "IOMUX_PR0_PRU1_GPO12_CFG_REG" bitfld.long 0x1D0 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1D0 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1D0 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1D0 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1D0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1D0 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1D0 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1D0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1D0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1D0 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1D0 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1D0 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1D0 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1D4 "IOMUX_PR0_PRU1_GPO13_CFG_REG" bitfld.long 0x1D4 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1D4 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1D4 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1D4 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1D4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1D4 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1D4 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1D4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1D4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1D4 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1D4 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1D4 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1D4 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1D8 "IOMUX_PR0_PRU1_GPO14_CFG_REG" bitfld.long 0x1D8 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1D8 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1D8 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1D8 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1D8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1D8 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1D8 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1D8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1D8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1D8 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1D8 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1D8 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1D8 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1DC "IOMUX_PR0_PRU1_GPO19_CFG_REG" bitfld.long 0x1DC 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1DC 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1DC 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1DC 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1DC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1DC 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1DC 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1DC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1DC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1DC 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1DC 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1DC 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1DC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1E0 "IOMUX_PR0_PRU1_GPO18_CFG_REG" bitfld.long 0x1E0 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1E0 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1E0 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1E0 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1E0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1E0 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1E0 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1E0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1E0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1E0 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1E0 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1E0 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1E0 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1E4 "IOMUX_EXT_REFCLK0_CFG_REG" bitfld.long 0x1E4 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1E4 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1E4 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1E4 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1E4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1E4 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1E4 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1E4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1E4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1E4 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1E4 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1E4 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1E4 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1E8 "IOMUX_SDFM0_CLK0_CFG_REG" bitfld.long 0x1E8 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1E8 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1E8 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1E8 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1E8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1E8 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1E8 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1E8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1E8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1E8 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1E8 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1E8 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1E8 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1EC "IOMUX_SDFM0_D0_CFG_REG" bitfld.long 0x1EC 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1EC 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1EC 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1EC 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1EC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1EC 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1EC 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1EC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1EC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1EC 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1EC 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1EC 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1EC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1F0 "IOMUX_SDFM0_CLK1_CFG_REG" bitfld.long 0x1F0 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1F0 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1F0 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1F0 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1F0 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1F0 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1F0 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1F0 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1F0 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1F0 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1F0 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1F0 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1F0 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1F4 "IOMUX_SDFM0_D1_CFG_REG" bitfld.long 0x1F4 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1F4 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1F4 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1F4 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1F4 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1F4 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1F4 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1F4 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1F4 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1F4 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1F4 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1F4 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1F4 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1F8 "IOMUX_SDFM0_CLK2_CFG_REG" bitfld.long 0x1F8 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1F8 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1F8 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1F8 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1F8 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1F8 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1F8 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1F8 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1F8 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1F8 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1F8 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1F8 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1F8 0.--3. 1. "FUNC_SEL,Function select" line.long 0x1FC "IOMUX_SDFM0_D2_CFG_REG" bitfld.long 0x1FC 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x1FC 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x1FC 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x1FC 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x1FC 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x1FC 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x1FC 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x1FC 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x1FC 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x1FC 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x1FC 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x1FC 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x1FC 0.--3. 1. "FUNC_SEL,Function select" line.long 0x200 "IOMUX_SDFM0_CLK3_CFG_REG" bitfld.long 0x200 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x200 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x200 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x200 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x200 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x200 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x200 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x200 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x200 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x200 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x200 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x200 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x200 0.--3. 1. "FUNC_SEL,Function select" line.long 0x204 "IOMUX_SDFM0_D3_CFG_REG" bitfld.long 0x204 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x204 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x204 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x204 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x204 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x204 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x204 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x204 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x204 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x204 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x204 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x204 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x204 0.--3. 1. "FUNC_SEL,Function select" line.long 0x208 "IOMUX_EQEP0_A_CFG_REG" bitfld.long 0x208 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x208 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x208 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x208 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x208 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x208 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x208 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x208 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x208 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x208 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x208 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x208 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x208 0.--3. 1. "FUNC_SEL,Function select" line.long 0x20C "IOMUX_EQEP0_B_CFG_REG" bitfld.long 0x20C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x20C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x20C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x20C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x20C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x20C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x20C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x20C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x20C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x20C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x20C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x20C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x20C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x210 "IOMUX_EQEP0_STROBE_CFG_REG" bitfld.long 0x210 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x210 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x210 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x210 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x210 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x210 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x210 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x210 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x210 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x210 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x210 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x210 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x210 0.--3. 1. "FUNC_SEL,Function select" line.long 0x214 "IOMUX_EQEP0_INDEX_CFG_REG" bitfld.long 0x214 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x214 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x214 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x214 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x214 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x214 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x214 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x214 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x214 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x214 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x214 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x214 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x214 0.--3. 1. "FUNC_SEL,Function select" line.long 0x218 "IOMUX_I2C0_SDA_CFG_REG" bitfld.long 0x218 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x218 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x218 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x218 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x218 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x218 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x218 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x218 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x218 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x218 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x218 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x218 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x218 0.--3. 1. "FUNC_SEL,Function select" line.long 0x21C "IOMUX_I2C0_SCL_CFG_REG" bitfld.long 0x21C 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x21C 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x21C 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x21C 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x21C 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x21C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x21C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x21C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x21C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x21C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x21C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x21C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x21C 0.--3. 1. "FUNC_SEL,Function select" line.long 0x220 "IOMUX_MCAN2_TX_CFG_REG" bitfld.long 0x220 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x220 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x220 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x220 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x220 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x220 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x220 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x220 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x220 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x220 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x220 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x220 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x220 0.--3. 1. "FUNC_SEL,Function select" line.long 0x224 "IOMUX_MCAN2_RX_CFG_REG" bitfld.long 0x224 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x224 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x224 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x224 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x224 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x224 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x224 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x224 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x224 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x224 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x224 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x224 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x224 0.--3. 1. "FUNC_SEL,Function select" line.long 0x228 "IOMUX_CLKOUT0_CFG_REG" bitfld.long 0x228 31. "HSMASTER,MMR bits for HSMASTER pin incase of true I2C pads" "0,1" bitfld.long 0x228 30. "HSMODE,MMR bits for HSMODE pin incase of true I2C pads" "0,1" newline bitfld.long 0x228 20. "INP_INV_SEL,select value for chosing inverted version of PAD input for chip: 0 : Non Inverted 1 : Inverted" "0: Non Inverted,1: Inverted" bitfld.long 0x228 18.--19. "QUAL_SEL,select value for chosing input qualifer type for PAD. 00 : Sync 01 : 3 Sample qual 10 : 6 Samples qual 11 : Async" "0: Sync,1: 3 Sample qual,?,?" newline bitfld.long 0x228 16.--17. "GPIO_SEL,R5F CPU ownership select for GPIO. 0 : GPO0 1 :GPO1 2 : GPO2 3:GPO3" "0: GPO0,1: GPO1,2: GPO2,3: GPO3" bitfld.long 0x228 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" newline bitfld.long 0x228 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" bitfld.long 0x228 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" newline bitfld.long 0x228 7. "OE_OVERRIDE,Active Low Output Override" "0,1" bitfld.long 0x228 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" newline bitfld.long 0x228 5. "IE_OVERRIDE,Active Low Input Override" "0,1" bitfld.long 0x228 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" newline hexmask.long.byte 0x228 0.--3. 1. "FUNC_SEL,Function select" line.long 0x22C "IOMUX_WARMRSTN_CFG_REG" bitfld.long 0x22C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" bitfld.long 0x22C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" newline bitfld.long 0x22C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" bitfld.long 0x22C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x22C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" bitfld.long 0x22C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" newline bitfld.long 0x22C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" line.long 0x230 "IOMUX_SAFETY_ERRORN_CFG_REG" bitfld.long 0x230 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" bitfld.long 0x230 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" newline bitfld.long 0x230 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" bitfld.long 0x230 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x230 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" bitfld.long 0x230 5. "IE_OVERRIDE,Active Low Input Override" "0,1" newline bitfld.long 0x230 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" line.long 0x234 "IOMUX_TDI_CFG_REG" bitfld.long 0x234 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" bitfld.long 0x234 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" newline bitfld.long 0x234 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" bitfld.long 0x234 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x234 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" bitfld.long 0x234 5. "IE_OVERRIDE,Active Low Input Override" "0,1" newline bitfld.long 0x234 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" line.long 0x238 "IOMUX_TDO_CFG_REG" bitfld.long 0x238 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" bitfld.long 0x238 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" newline bitfld.long 0x238 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" bitfld.long 0x238 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x238 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" bitfld.long 0x238 5. "IE_OVERRIDE,Active Low Input Override" "0,1" newline bitfld.long 0x238 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" line.long 0x23C "IOMUX_TMS_CFG_REG" bitfld.long 0x23C 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" bitfld.long 0x23C 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" newline bitfld.long 0x23C 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" bitfld.long 0x23C 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x23C 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" bitfld.long 0x23C 5. "IE_OVERRIDE,Active Low Input Override" "0,1" newline bitfld.long 0x23C 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" line.long 0x240 "IOMUX_TCK_CFG_REG" bitfld.long 0x240 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" bitfld.long 0x240 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" newline bitfld.long 0x240 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" bitfld.long 0x240 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x240 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" bitfld.long 0x240 5. "IE_OVERRIDE,Active Low Input Override" "0,1" newline bitfld.long 0x240 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" line.long 0x244 "IOMUX_QSPI0_CLKLB_CFG_REG" bitfld.long 0x244 10. "SC1,IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate." "0: higher slew rate,1: Lower slew rate" bitfld.long 0x244 9. "PUPDSEL,Pullup/PullDown Selection 0 -- Pull Down 1 - Pull Up" "0,1" newline bitfld.long 0x244 8. "PI,Pull Inhibit/Pull Disable 0 -- Enable 1- Disable" "0,1" bitfld.long 0x244 7. "OE_OVERRIDE,Active Low Output Override" "0,1" newline bitfld.long 0x244 6. "OE_OVERRIDE_CTRL,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1" bitfld.long 0x244 5. "IE_OVERRIDE,Active Low Input Override" "0,1" newline bitfld.long 0x244 4. "IE_OVERRIDE_CTRL,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1" line.long 0x248 "IOMUX_QUAL_GRP_0_CFG_REG" hexmask.long.byte 0x248 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x24C "IOMUX_QUAL_GRP_1_CFG_REG" hexmask.long.byte 0x24C 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x250 "IOMUX_QUAL_GRP_2_CFG_REG" hexmask.long.byte 0x250 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x254 "IOMUX_QUAL_GRP_3_CFG_REG" hexmask.long.byte 0x254 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x258 "IOMUX_QUAL_GRP_4_CFG_REG" hexmask.long.byte 0x258 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x25C "IOMUX_QUAL_GRP_5_CFG_REG" hexmask.long.byte 0x25C 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x260 "IOMUX_QUAL_GRP_6_CFG_REG" hexmask.long.byte 0x260 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x264 "IOMUX_QUAL_GRP_7_CFG_REG" hexmask.long.byte 0x264 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x268 "IOMUX_QUAL_GRP_8_CFG_REG" hexmask.long.byte 0x268 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x26C "IOMUX_QUAL_GRP_9_CFG_REG" hexmask.long.byte 0x26C 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x270 "IOMUX_QUAL_GRP_10_CFG_REG" hexmask.long.byte 0x270 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x274 "IOMUX_QUAL_GRP_11_CFG_REG" hexmask.long.byte 0x274 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x278 "IOMUX_QUAL_GRP_12_CFG_REG" hexmask.long.byte 0x278 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x27C "IOMUX_QUAL_GRP_13_CFG_REG" hexmask.long.byte 0x27C 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x280 "IOMUX_QUAL_GRP_14_CFG_REG" hexmask.long.byte 0x280 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x284 "IOMUX_QUAL_GRP_15_CFG_REG" hexmask.long.byte 0x284 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x288 "IOMUX_QUAL_GRP_16_CFG_REG" hexmask.long.byte 0x288 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x28C "IOMUX_QUAL_GRP_17_CFG_REG" hexmask.long.byte 0x28C 0.--7. 1. "QUAL_PERIOD_PER_SAMPLE,MMR bits for programming the qualifier clock count per sample" line.long 0x290 "IOMUX_USER_MODE_EN" hexmask.long 0x290 0.--31. 1. "USER_MODE_EN,Write 0XADADADAD to enable user mode write access to IO CFG space" line.long 0x294 "IOMUX_PADGLBL_CFG_REG" hexmask.long 0x294 0.--31. 1. "PADGLBL_CFG_REG,2:0 : global_ie_n_ctl - Write 3'b111 to pass global_ie_n_val to IE_N/RXACTIVE_N pin of all the IOs.3 : global_ie_n_val - Active low10:8 : global_oe_n_ctl - Write 3'b111 to pass global_oe_n_val to OE_N/GZ pin of all the IOs.11 :.." line.long 0x298 "IOMUX_IO_CFG_KICK0" hexmask.long 0x298 0.--31. 1. "IO_CFG_KICK0,Kicker 0 Register. The value 83E7 0B13h must be written to KICK0 as part of the process to unlock the CPU.write access to the above PIN MUX registers (including IOCFGKICK1)" line.long 0x29C "IOMUX_IO_CFG_KICK1" hexmask.long 0x29C 0.--31. 1. "IO_CFG_KICK1,Kicker 1 Register. The value 95A4 F1E0h must be written to the KICK1 as part of the process to unlock the CPU write access to above PINMUX registers (excluding IOCFGKICK0). IOCFGKICK0 has to be written with 83E70B13h to enable access to.." tree.end tree "L2OCRAM" base ad:0x70000000 group.long 0x0++0x3 line.long 0x0 "L2OCRAM_START" hexmask.long 0x0 0.--31. 1. "START,L2 Memory start address" group.long 0x1FFFFC++0x3 line.long 0x0 "L2OCRAM_END" hexmask.long 0x0 0.--31. 1. "END,L2 Memory end address" tree.end tree "LIN" base ad:0x0 tree "LIN0" base ad:0x52400000 group.long 0x0++0x1F line.long 0x0 "LIN0_SCIGCR0,The SCIGCR0 register defines the module reset." bitfld.long 0x0 0. "RESET,This bit resets the SCI/LIN module. This bit is effective in LIN or SCI-compatible mode.. This bit affects the reset state of the SCI/LIN module." "0,1" line.long 0x4 "LIN0_SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI." bitfld.long 0x4 25. "TXENA,Transmit enable.This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy [with y=0 1 ...7] buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the.." "0,1" bitfld.long 0x4 24. "RXENA,Receive enable.This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the.." "0,1" bitfld.long 0x4 17. "CONT,Continue on suspend.This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set the counters are.." "0,1" newline bitfld.long 0x4 16. "LOOPBACK,Loopback bit.This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality then the LINTX pin is internally.." "0,1" bitfld.long 0x4 13. "STOPEXTFRAME,Stop extended frame communication.This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped this bit is cleared automatically." "0,1" bitfld.long 0x4 12. "HGENCTRL,HGEN control bit.This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison." "0,1" newline bitfld.long 0x4 11. "CTYPE,Checksum type.This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced." "0,1" bitfld.long 0x4 10. "MBUFMODE,Multibuffer mode.This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage that is whether the RX/TX multibuffers are used or a single register RD0/TD0 is used." "0,1" bitfld.long 0x4 9. "ADAPT,Adapt mode enable.This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file.." "0,1" newline bitfld.long 0x4 8. "SLEEP,SCI sleep.SCI compatibility mode only. In a multiprocessor configuration this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however RXRDY is.." "0,1" bitfld.long 0x4 7. "SWNRST,Software reset [active low].This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime [i.e. while SWnRESET = 1]:- STOP EXT Frame.." "0,1" bitfld.long 0x4 6. "LINMODE,LIN modeThis bit controls the mode of operation of the module." "0,1" newline bitfld.long 0x4 5. "CLK_MASTER,SCI internal clock enable or LIN Master/Slave configuration.In the SCI mode this bit enables the clock to the SCI module. In LIN mode this bit determines whether a LIN node is a slave or master." "0,1" bitfld.long 0x4 4. "STOP,SCI number of stop bits.This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode the receiver waits until the end of the second stop bit [if STOP = 1] to begin checking for an.." "0,1" bitfld.long 0x4 3. "PARITY,SCI parity odd/even selection.This bit is effective in SCI-compatible mode only. If the PARITY ENA bit [SCIGCR1.2] is set PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit.." "0,1" newline bitfld.long 0x4 2. "PARITYENA,Parity enable.Enables or disables the parity function." "0,1" bitfld.long 0x4 1. "TIMINGMODE,SCI timing mode bit.This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation." "0,1" bitfld.long 0x4 0. "COMMMODE,SCI/LIN communication mode bit.In compatibility mode it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5." "0,1" line.long 0x8 "LIN0_SCIGCR2,The SCIGCR2 register is used to send or compare a checksum byte during extended frames. to generate a wakeup and for low-power mode control of the LIN module." bitfld.long 0x8 17. "CC,Compare Checksum.This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by writing a one to this bit.In non multibuffer mode once the CC bit.." "0,1" bitfld.long 0x8 16. "SC,Send ChecksumThis mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the.." "0,1" bitfld.long 0x8 8. "GENWU,Generate wakeup signal.This bit controls the generation of a wakeup signal by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break." "0,1" newline bitfld.long 0x8 0. "POWERDOWN,Power down.This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup.." "0,1" line.long 0xC "LIN0_SCISETINT,The SCISETINT register is used to enable the various interrupts available in the LIN module." bitfld.long 0xC 31. "SETBEINT,Set bit error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 30. "SETPBEINT,Set physical bus error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 29. "SETCEINT,Set checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only." "0,1" newline bitfld.long 0xC 28. "SETISFEINT,Set inconsistent-sync-field-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 27. "SETNREINT,Set no-response-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 26. "SETFEINT,Set framing-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs." "0,1" newline bitfld.long 0xC 25. "SETOEINT,Set overrun-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs." "0,1" bitfld.long 0xC 24. "SETPEINT,Set parity interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs." "0,1" bitfld.long 0xC 18. "SET_RX_DMA_ALL,Set receiver DMA for Address & Data frames.This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared RX interrupt request is generated for address.." "0,1" newline bitfld.long 0xC 17. "SET_RX_DMA,Set receiver DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared interrupt requests are generated depending on SETRXINT." "0,1" bitfld.long 0xC 16. "SET_TX_DMA,Set transmit DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter this bit must be set. If it is cleared interrupt requests are generated depending on SETTXINT." "0,1" bitfld.long 0xC 13. "SETIDINT,Set Identification interrupt.This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received." "0,1" newline bitfld.long 0xC 9. "SETRXINT,Set Receiver interrupt.Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD." "0,1" bitfld.long 0xC 8. "SETTXINT,Set Transmitter interrupt.Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set." "0,1" bitfld.long 0xC 7. "SETTOA3WUSINT,Set Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN.." "0,1" newline bitfld.long 0xC 6. "SETTOAWUSINT,Set Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode.." "0,1" bitfld.long 0xC 4. "SETTIMEOUTINT,Set timeout interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity [bus idle] occurs for at least 4 seconds. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 1. "SETWAKEUPINT,Set wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up.." "0,1" newline bitfld.long 0xC 0. "SETBRKDTINT,Set break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only." "0,1" line.long 0x10 "LIN0_SCICLEARINT,The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register." bitfld.long 0x10 31. "CLRBEINT,Clear Bit Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 30. "CLRPBEINT,Clear Physical Bus Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 29. "CLRCEINT,Clear checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x10 28. "CLRISFEINT,Clear Inconsistent-Sync-Field-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 27. "CLRNREINT,Clear No-Reponse-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 26. "CLRFEINT,Clear Framing-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt." "0,1" newline bitfld.long 0x10 25. "CLROEINT,Clear Overrun-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt." "0,1" bitfld.long 0x10 24. "CLRPEINT,Clear Parity Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt." "0,1" bitfld.long 0x10 17. "SETRXDMA,Clear receiver DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request." "0,1" newline bitfld.long 0x10 16. "CLRTXDMA,Clear transmit DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request." "0,1" bitfld.long 0x10 13. "CLRIDINT,Clear Identifier interrupt.This bit is effective in LIN mode only. Setting this bit disables the ID interrupt." "0,1" bitfld.long 0x10 9. "CLRRXINT,Clear Receiver interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt." "0,1" newline bitfld.long 0x10 8. "CLRTXINT,Clear Transmitter interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt." "0,1" bitfld.long 0x10 7. "CLRTOA3WUSINT,Clear Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 6. "CLRTOAWUSINT,Clear Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x10 4. "CLRTIMEOUTINT,Clear Timeout interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout [LIN bus idle] interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 1. "CLRWAKEUPINT,Clear Wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt." "0,1" bitfld.long 0x10 0. "CLRBRKDTINT,Clear Break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only." "0,1" line.long 0x14 "LIN0_SCISETINTLVL,The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line." bitfld.long 0x14 31. "SETBEINTLVL,Set Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 30. "SETPBEINTLVL,Set Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 29. "SETCEINTLVL,Set Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x14 28. "SETISFEINTLVL,Set Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 27. "SETNREINTLVL,Set No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 26. "SETFEINTLVL,Set Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line." "0,1" newline bitfld.long 0x14 25. "SETOEINTLVL,Set Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line." "0,1" bitfld.long 0x14 24. "SETPEINTLVL,Set Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line." "0,1" bitfld.long 0x14 13. "SETIDINTLVL,Set ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x14 9. "SETRXINTOVO,Set Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line." "0,1" bitfld.long 0x14 8. "SETTXINTLVL,Set Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line." "0,1" bitfld.long 0x14 7. "SETTOA3WUSINTLVL,Set Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x14 6. "SETTOAWUSINTLVL,Set Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 4. "SETTIMEOUTINTLVL,Set Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 1. "SETWAKEUPINTLVL,Set Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line." "0,1" newline bitfld.long 0x14 0. "SETBRKDTINTLVL,Set Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only." "0,1" line.long 0x18 "LIN0_SCICLEARINTLVL,The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line." bitfld.long 0x18 31. "CLRBEINTLVL,Clear Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 30. "CLRPBEINTLVL,Clear Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 29. "CLRCEINTLVL,Clear Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x18 28. "CLRISFEINTLVL,Clear Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 27. "CLRNREINTLVL,Clear No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 26. "CLRFEINTLVL,Clear Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line." "0,1" newline bitfld.long 0x18 25. "CLROEINTLVL,Clear Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line." "0,1" bitfld.long 0x18 24. "CLRPEINTLVL,Clear Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line." "0,1" bitfld.long 0x18 13. "CLRIDINTLVL,Clear ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x18 9. "CLRRXINTLVL,Clear Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line." "0,1" bitfld.long 0x18 8. "CLRTXINTLVL,Clear Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line." "0,1" bitfld.long 0x18 7. "CLRTOA3WUSINTLVL,Clear Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x18 6. "CLRTOAWUSINTLVL,Clear Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 4. "CLRTIMEOUTINTLVL,Clear Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 1. "CLRWAKEUPINTLVL,Clear Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line." "0,1" newline bitfld.long 0x18 0. "CLRBRKDTINTLVL,Clear Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only." "0,1" line.long 0x1C "LIN0_SCIFLR,The SCIFLR register indicates the current status of the various interrupt sources of the LIN module." bitfld.long 0x1C 31. "BE,Bit Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 30. "PBE,Physical Bus Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 29. "CE,Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by:- Reading the.." "0,1" newline bitfld.long 0x1C 28. "ISFE,Inconsistent Sync Field Error Flag.This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the Header Reception and Adaptive Baudrate.." "0,1" bitfld.long 0x1C 27. "NRE,No-Response Error Flag.This bit is effective in LIN mode only. This bit is set when there is no response to a master's header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length [identifiers 0 to 61]. This.." "0,1" bitfld.long 0x1C 26. "FE,Framing error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode only the first stop bit is checked. The missing stop bit indicates that synchronization with the.." "0,1" newline bitfld.long 0x1C 25. "OE,Overrun error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to.." "0,1" bitfld.long 0x1C 24. "PE,Parity error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode the parity is calculated on the data and address bit fields of the received frame. In.." "?,?" bitfld.long 0x1C 14. "IDRXFLAG,Identifier On Receive Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the Message Filtering and Validation section for more details. When this flag is set.." "0,1" newline bitfld.long 0x1C 13. "IDTXFLAG,Identifier On Transmit Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the Message Filtering and Validation section for more details. When this flag is set.." "0,1" rbitfld.long 0x1C 12. "RXWAKE,Receiver wakeup detect flag.This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by:- RESET bit- Setting the SWnRESET bit [SCIGCR1.7]- System.." "0,1" rbitfld.long 0x1C 11. "TXEMPTY,Transmitter Empty flag.The value of this flag indicates the contents of the transmitter's buffer register[s] [SCITD/TDy] and shift register [SCITXSHF]. In multibuffer mode this flag indicates the value of the TDx registers and shift register.." "0,1" newline bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wakeup method select.This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or.." "0,1" bitfld.long 0x1C 9. "RXRDY,Receiver ready flag. In SCI compatibility mode the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode RXRDY is set once a valid frame is received in multibuffer mode a valid frame.." "0,1" rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag.When set this bit indicates that the transmit buffer[s] register [SCITD in compatibility mode and LINTD0 LINTD1 in MBUF mode] is/are ready to get another character from a CPU write. In SCI compatibility.." "0,1" newline bitfld.long 0x1C 7. "TOA3WUS,Timeout After 3 Wakeup Signals flag.This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another.." "0,1" bitfld.long 0x1C 6. "TOAWUS,Timeout After Wakeup Signal flag.This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal." "0,1" bitfld.long 0x1C 4. "TIMEOUT,LIN Bus IDLE timeout flag.This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by:- Reading the.." "0,1" newline rbitfld.long 0x1C 3. "BUSY,Bus BUSY flag.This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit the BUSY bit is set to 1. When the.." "0,1" rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state.This bit is effective in SCI-compatible mode only. While this bit is set the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus.." "0,1" bitfld.long 0x1C 1. "WAKEUP,Wake-up flag.This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit [SCISETINT.1] is set. This.." "0,1" newline bitfld.long 0x1C 0. "BRKDT,SCI break-detect flag.This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a.." "0,1" rgroup.long 0x20++0x7 line.long 0x0 "LIN0_SCIINTVECT0,The SCIINTVECT0 register indicates the offset for the INT0 interrupt line." hexmask.long.byte 0x0 0.--4. 1. "INTVECT0,Interrupt vector offset for INT0.This register indicates the offset for interrupt line INT0. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." line.long 0x4 "LIN0_SCIINTVECT1,The SCIINTVECT1 register indicates the offset for the INT1 interrupt line." hexmask.long.byte 0x4 0.--4. 1. "INTVECT1,Interrupt vector offset for INT1.This register indicates the offset for interrupt line INT1. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." group.long 0x28++0x7 line.long 0x0 "LIN0_SCIFORMAT,The SCIFORMAT register is used to set up the character and frame lengths." bitfld.long 0x0 16.--18. "LENGTH,Frame length control bits.In LIN mode these bits indicate the number of bytes in the response field from 1 to 8 bytes. In buffered SCI mode these bits indicate the number of characters. When these bits are used to indicate LIN response length.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "CHAR,Character length control bits.These bits are effective in SCI compatible mode only. These bits set the SCI character length from 1 to 8 bits. Note: In compatibility mode or buffered SCI mode when data of fewer than eight bits in length is received .." "0,1,2,3,4,5,6,7" line.long 0x4 "LIN0_BRSR,The BRSR register is used to configure the baud rate of the LIN module." bitfld.long 0x4 28.--30. "U,Superfractional Divider Selection. [U]These bits are an additional fractional part for the baudrate specification. These bits allow a super fine tuning of the fractional baudrate with 7 more intermediate values for each of the M fractional divider.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--27. 1. "M,SCI/LIN 4-bit Fractional Divider Selection. [M]These bits are effective in LIN or SCI asynchronous mode. These bits are used to select a baud rate for the SCI/LIN module and they are a fractional part for the baud rate specification. The M divider.." hexmask.long.byte 0x4 16.--23. 1. "SCI_LIN_PSH,PRESCALER P [High Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." newline hexmask.long.word 0x4 0.--15. 1. "SCI_LIN_PSL,PRESCALER P [Low Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." rgroup.long 0x30++0x7 line.long 0x0 "LIN0_SCIED,The SCIED register is a duplicate copy of SCIRD register that has no affect on the RXRDY flag for use with an emulator." hexmask.long.byte 0x0 0.--7. 1. "ED,Receiver Emulation Data.This bit is effective in SCI-compatible mode only. Reading SCIED[7-0] does not clear the RXRDY flag. This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag." line.long 0x4 "LIN0_SCIRD,The SCIRD register is where received data is stored and can be read from." hexmask.long.byte 0x4 0.--7. 1. "RD,Received Data.This bit is effective in SCI-compatible mode only. When a frame has been completely received the data in the frame is transferred from the receiver shift register SCIRXSHF to this register. As this transfer occurs the RXRDY flag is set.." group.long 0x38++0xB line.long 0x0 "LIN0_SCITD,The SCITD register is where data to be transmitted is written to by application software." hexmask.long.byte 0x0 0.--7. 1. "TD,Transmit dataThis bit is effective in SCI-compatible mode only. Data to be transmitted is written to this register. The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag [SCIFLR.23] which indicates that.." line.long 0x4 "LIN0_SCIPIO0,The SCIPIO0 register is used to enable the LINTX and LINRX pins." bitfld.long 0x4 2. "TXFUNC,Transmit pin function.This bit is effective in LIN or SCI mode. This bit defines the function of LINTX pin." "0,1" bitfld.long 0x4 1. "RXFUNC,Receive pin function.This bit is effective in LIN or SCI mode. This bit defines the function of the LINRX pin." "0,1" line.long 0x8 "LIN0_SCIPIO1,Pin control Register 1" bitfld.long 0x8 2. "TXDIR,Transmit pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINTX pin if it is configured with general-purpose I/O functionality [TX FUNC = 0]. 0: general purpose input pin. 1: general-purpose.." "0: general purpose input pin,1: general-purpose output pin" bitfld.long 0x8 1. "RXDIR,Receive pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINRX pin if it is configured with general-purpose I/O functionality [RX FUNC = 0]. 0: general purpose input pin. 1: general-purpose.." "0: general purpose input pin,1: general-purpose output pin" rgroup.long 0x44++0x3 line.long 0x0 "LIN0_SCIPIO2,The SCIPIO2 register indicates the current status of the LINTX and LINRX pins." bitfld.long 0x0 2. "TXIN,Transmit data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINTX pin." "0,1" bitfld.long 0x0 1. "RXIN,Receive data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINRX pin." "0,1" group.long 0x48++0x1B line.long 0x0 "LIN0_SCIPIO3,Pin control Register 3" bitfld.long 0x0 2. "TXOUT,Transmit pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINTX." "0,1" bitfld.long 0x0 1. "RXOUT,Receive pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINRX." "0,1" line.long 0x4 "LIN0_SCIPIO4,Pin control Register 4" bitfld.long 0x4 2. "TXSET,Transmit pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX." "0,1" bitfld.long 0x4 1. "RXSET,Receive pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX." "0,1" line.long 0x8 "LIN0_SCIPIO5,Pin control Register 5" bitfld.long 0x8 2. "TXCLR,Transmit pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINTX." "0,1" bitfld.long 0x8 1. "RXCLR,Receive pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINRX." "0,1" line.long 0xC "LIN0_SCIPIO6,Pin control Register 6" bitfld.long 0xC 2. "TXPDR,Transmit pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINTX." "0,1" bitfld.long 0xC 1. "RXPDR,Receive pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINRX." "0,1" line.long 0x10 "LIN0_SCIPIO7,Pin control Register 7" bitfld.long 0x10 2. "TXPD,Transmit pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINTX." "0,1" bitfld.long 0x10 1. "RXPD,Receive pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINRX." "0,1" line.long 0x14 "LIN0_SCIPIO8,Pin control Register 8" bitfld.long 0x14 2. "TXPSL,TX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINTX." "0,1" bitfld.long 0x14 1. "RXPSL,RX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINRX." "0,1" line.long 0x18 "LIN0_LINCOMP,The LINCOMPARE register is used to configure the sync delimeter and sync break extension." bitfld.long 0x18 8.--9. "SDEL,2-bit Sync Delimiter compare.These bits are effective in LIN mode only. These bits are used to configure the number of Tbit for the sync delimiter in the sync field.The time delay calculation for the synchronization delimiter is:TSDEL = [SDEL +.." "0,1,2,3" bitfld.long 0x18 0.--2. "SBREAK,3-bit Sync Break extend.LIN mode only. These bits are used to configure the number of Tbits for the sync break to extend the minimum 13 Tbit in the Sync Field to a maximum of 20 Tbit.The time delay calculation for the sync break is:TSYNBRK =.." "0,1,2,3,4,5,6,7" rgroup.long 0x64++0x7 line.long 0x0 "LIN0_LINRD0,The LINRD0 register contains the lower 4 bytes of the received LIN frame data." hexmask.long.byte 0x0 24.--31. 1. "RD0,8-bit Receive Buffer 0Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received.A read of this byte clears the RXDY byte.Note: RD<x-1> is.." hexmask.long.byte 0x0 16.--23. 1. "RD1,8-bit Receive Buffer 1.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x0 8.--15. 1. "RD2,8-bit Receive Buffer 2.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x0 0.--7. 1. "RD3,8-bit Receive Buffer 3.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." line.long 0x4 "LIN0_LINRD1,The LINRD1 regsiter contains the upper 4 bytes of the received LIN frame data." hexmask.long.byte 0x4 24.--31. 1. "RD4,8-bit Receive Buffer 4 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 16.--23. 1. "RD5,8-bit Receive Buffer 5.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 8.--15. 1. "RD6,8-bit Receive Buffer 6.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x4 0.--7. 1. "RD7,8-bit Receive Buffer 7.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." group.long 0x6C++0x17 line.long 0x0 "LIN0_LINMASK,The LINMASK register is used to configure the masks used for filtering incoming ID messages for receive and transmit frames." hexmask.long.byte 0x0 16.--23. 1. "RXIDMASK,Receive ID mask.This field is effective in LIN mode only.This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID witht the RX ID mask will set the ID RX flag and trigger and.." hexmask.long.byte 0x0 0.--7. 1. "TXIDMASK,Transmit ID mask.This field is effective in LIN mode only. This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID with the TX ID Mask will set the ID TX flag and trigger an.." line.long 0x4 "LIN0_LINID,The LINID register contains the identification fields for LIN communication.[[br]]NOTE: For software compatibility with future LIN modules. the HGEN CTRL bit must be set to 1. the RX ID MASK field must be set to FFh. and the TX ID MASK field.." hexmask.long.byte 0x4 16.--23. 1. "RECEIVEDID,Received ID.This bit is effective in LIN mode only. This byte contains the current message identifier. During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID-parity error and there has been.." hexmask.long.byte 0x4 8.--15. 1. "IDSLAVETASKBYTE,ID Slave Task byte.This field is effective in LIN mode only. This byte contains the identifier to which the received ID of an incoming header will be compared in order to decide whether a RX response a TX response or no action needs to.." hexmask.long.byte 0x4 0.--7. 1. "IDBYTE,ID byte.This field is effective in LIN mode only. This byte is the LIN mode message ID. On a master node a write to this register by the CPU initiates a header transmission. For a slave task this byte is used for message filtering when HGENCTRL.." line.long 0x8 "LIN0_LINTD0,The LINTD0 register contains the lower 4 bytes of the data to be transmitted.[[br]]NOTE: TD<x-1> is equivalent to Data byte <x> of the LIN frame." hexmask.long.byte 0x8 24.--31. 1. "TD0,8-bit Transmit Buffer 0.Byte 0 to be transmitted is written into this register and then copied to SCITXSHF for transmission. Once byte 0 is written in TDO buffer transmission will be initiated." hexmask.long.byte 0x8 16.--23. 1. "TD1,8-bit Transmit Buffer 3.Byte 1 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0x8 8.--15. 1. "TD2,8-bit Transmit Buffer 2.Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0x8 0.--7. 1. "TD3,8-bit Transmit Buffer 3.Byte 3 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0xC "LIN0_LINTD1,The LINTD1 register contains the upper 4 bytes of the data to be transmitted.[[br]]NOTE: TD<x-1> is equivalent to Data byte <x> of the LIN frame." hexmask.long.byte 0xC 24.--31. 1. "TD4,8-bit Transmit Buffer 4.Byte4 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 16.--23. 1. "TD5,8-bit Transmit Buffer 5.Byte 5 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 8.--15. 1. "TD6,8-bit Transmit Buffer 6.Byte 6 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0xC 0.--7. 1. "TD7,8-bit Transmit Buffer 7.Byte 7 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0x10 "LIN0_MBRSR,The MBRSR register is used to configure the expected maximum baud rate of the LIN network." hexmask.long.word 0x10 0.--12. 1. "MBR,Maximum Baud Rate Prescaler.This field is effective in LIN mode only. This 13-bit prescaler is used during the synchronization phase [see the Header Reception and Adaptive Baudrate section] of a slave module if the ADAPT bit is set. In this way a.." line.long 0x14 "LIN0_Reserved_1,tbd" group.long 0x90++0x7 line.long 0x0 "LIN0_IODFTCTRL,The IODFTCTRL register is used to emulate various error and test conditions." bitfld.long 0x0 31. "BERRENA,Bit Errror Enable bit.This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set the bit received is ORed with 1 and passed to the Bit monitor circuitry." "0,1" bitfld.long 0x0 30. "PBERRENA,Physical Bus Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor.." "0,1" bitfld.long 0x0 29. "CERRENA,Checksum Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set the polarity of the CTYPE [checksum type] in the receive checksum calculator is changed so that a checksum error.." "0,1" newline bitfld.long 0x0 28. "ISFERRENA,Inconsistent Sync Field Error Enable bit.This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set the bit widths in the sync field are varied so that the ISF check fails and the error flag is set." "0,1" bitfld.long 0x0 26. "FERRENA,This bit is used to create a Frame Error.This bit is effective in SCI-compatible mode only. When this bit is set the stop bit received is ANDed with '0' and passed to the stop bit check circuitry." "0,1" bitfld.long 0x0 25. "PERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set in compatible mode the parity bit received is toggled so that a parity error occurs." "0,1" newline bitfld.long 0x0 24. "BRKDTERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error [SCI mode only]. When this bit is set the stop bit of the frame is ANDed with '0' and passed to the RSM so that a frame error.." "0,1" bitfld.long 0x0 19.--20. "PINSAMPLEMASK,Pin sample mask.These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry.Note: During IODFT mode testing for.." "0,1,2,3" bitfld.long 0x0 16.--18. "TXSHIFT,Transmit shift.These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. [Not applicable to Start Bit]" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "IODFTENA,IO DFT Enable KeyThis field is used to enable the IODFT mode of the SCI/LIN module for testing." bitfld.long 0x0 1. "LPBENA,Module loopback enable.In analog loopback mode the complete communication path through the I/Os can be tested whereas in digital loopback mode the I/O buffers are excluded from this path." "0,1" bitfld.long 0x0 0. "RXPENA,Module Analog loopback through receive pin enable.This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only." "0,1" line.long 0x4 "LIN0_Reserved_2,tbd" group.long 0xE0++0x3 line.long 0x0 "LIN0_LIN_GLB_INT_EN,The LIN_GLB_INT_EN register is used to enable the INT0 and INT1 interrupt lines to propagate to the PIE block." bitfld.long 0x0 1. "GLBINT1_EN,Global Interrupt Enable for LIN INT1.This bit determines whether the INT1 interrupt line generates an interrupt to the PIE or not" "0,1" bitfld.long 0x0 0. "GLBINT0_EN,Global Interrupt Enable for LIN INT0.This bit determines whether the INT0 interrupt line generates an interrupt to the PIE or not." "0,1" rgroup.long 0xE4++0x3 line.long 0x0 "LIN0_LIN_GLB_INT_FLG,The LIN_GLB_INT_FLG register contains the current status of the INT0 and INT1 flags." bitfld.long 0x0 1. "INT1_FLG,Global Interrupt Flag for LIN INT1.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT1 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" bitfld.long 0x0 0. "INT0_FLG,Global Interrupt Flag for LIN INT0.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT0 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" group.long 0xE8++0x3 line.long 0x0 "LIN0_LIN_GLB_INT_CLR,The LIN_GLB_INT_CLR register is used to clear the interrupt flags in LIN_GLB_INT_FLG register." bitfld.long 0x0 1. "INT1_FLG_CLR,Global Interrupt flag clear for LIN INT1.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT1_FLG bit. Writing 0 has no effect." "0,1" bitfld.long 0x0 0. "INT0_FLG_CLR,Global Interrupt flag clear for LIN INT0.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT0_FLG bit. Writing 0 has no effect." "0,1" tree.end tree "LIN1" base ad:0x52401000 group.long 0x0++0x1F line.long 0x0 "LIN1_SCIGCR0,The SCIGCR0 register defines the module reset." bitfld.long 0x0 0. "RESET,This bit resets the SCI/LIN module. This bit is effective in LIN or SCI-compatible mode.. This bit affects the reset state of the SCI/LIN module." "0,1" line.long 0x4 "LIN1_SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI." bitfld.long 0x4 25. "TXENA,Transmit enable.This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy [with y=0 1 ...7] buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the.." "0,1" bitfld.long 0x4 24. "RXENA,Receive enable.This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the.." "0,1" bitfld.long 0x4 17. "CONT,Continue on suspend.This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set the counters are.." "0,1" newline bitfld.long 0x4 16. "LOOPBACK,Loopback bit.This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality then the LINTX pin is internally.." "0,1" bitfld.long 0x4 13. "STOPEXTFRAME,Stop extended frame communication.This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped this bit is cleared automatically." "0,1" bitfld.long 0x4 12. "HGENCTRL,HGEN control bit.This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison." "0,1" newline bitfld.long 0x4 11. "CTYPE,Checksum type.This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced." "0,1" bitfld.long 0x4 10. "MBUFMODE,Multibuffer mode.This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage that is whether the RX/TX multibuffers are used or a single register RD0/TD0 is used." "0,1" bitfld.long 0x4 9. "ADAPT,Adapt mode enable.This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file.." "0,1" newline bitfld.long 0x4 8. "SLEEP,SCI sleep.SCI compatibility mode only. In a multiprocessor configuration this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however RXRDY is.." "0,1" bitfld.long 0x4 7. "SWNRST,Software reset [active low].This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime [i.e. while SWnRESET = 1]:- STOP EXT Frame.." "0,1" bitfld.long 0x4 6. "LINMODE,LIN modeThis bit controls the mode of operation of the module." "0,1" newline bitfld.long 0x4 5. "CLK_MASTER,SCI internal clock enable or LIN Master/Slave configuration.In the SCI mode this bit enables the clock to the SCI module. In LIN mode this bit determines whether a LIN node is a slave or master." "0,1" bitfld.long 0x4 4. "STOP,SCI number of stop bits.This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode the receiver waits until the end of the second stop bit [if STOP = 1] to begin checking for an.." "0,1" bitfld.long 0x4 3. "PARITY,SCI parity odd/even selection.This bit is effective in SCI-compatible mode only. If the PARITY ENA bit [SCIGCR1.2] is set PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit.." "0,1" newline bitfld.long 0x4 2. "PARITYENA,Parity enable.Enables or disables the parity function." "0,1" bitfld.long 0x4 1. "TIMINGMODE,SCI timing mode bit.This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation." "0,1" bitfld.long 0x4 0. "COMMMODE,SCI/LIN communication mode bit.In compatibility mode it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5." "0,1" line.long 0x8 "LIN1_SCIGCR2,The SCIGCR2 register is used to send or compare a checksum byte during extended frames. to generate a wakeup and for low-power mode control of the LIN module." bitfld.long 0x8 17. "CC,Compare Checksum.This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by writing a one to this bit.In non multibuffer mode once the CC bit.." "0,1" bitfld.long 0x8 16. "SC,Send ChecksumThis mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the.." "0,1" bitfld.long 0x8 8. "GENWU,Generate wakeup signal.This bit controls the generation of a wakeup signal by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break." "0,1" newline bitfld.long 0x8 0. "POWERDOWN,Power down.This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup.." "0,1" line.long 0xC "LIN1_SCISETINT,The SCISETINT register is used to enable the various interrupts available in the LIN module." bitfld.long 0xC 31. "SETBEINT,Set bit error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 30. "SETPBEINT,Set physical bus error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 29. "SETCEINT,Set checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only." "0,1" newline bitfld.long 0xC 28. "SETISFEINT,Set inconsistent-sync-field-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 27. "SETNREINT,Set no-response-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 26. "SETFEINT,Set framing-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs." "0,1" newline bitfld.long 0xC 25. "SETOEINT,Set overrun-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs." "0,1" bitfld.long 0xC 24. "SETPEINT,Set parity interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs." "0,1" bitfld.long 0xC 18. "SET_RX_DMA_ALL,Set receiver DMA for Address & Data frames.This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared RX interrupt request is generated for address.." "0,1" newline bitfld.long 0xC 17. "SET_RX_DMA,Set receiver DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared interrupt requests are generated depending on SETRXINT." "0,1" bitfld.long 0xC 16. "SET_TX_DMA,Set transmit DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter this bit must be set. If it is cleared interrupt requests are generated depending on SETTXINT." "0,1" bitfld.long 0xC 13. "SETIDINT,Set Identification interrupt.This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received." "0,1" newline bitfld.long 0xC 9. "SETRXINT,Set Receiver interrupt.Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD." "0,1" bitfld.long 0xC 8. "SETTXINT,Set Transmitter interrupt.Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set." "0,1" bitfld.long 0xC 7. "SETTOA3WUSINT,Set Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN.." "0,1" newline bitfld.long 0xC 6. "SETTOAWUSINT,Set Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode.." "0,1" bitfld.long 0xC 4. "SETTIMEOUTINT,Set timeout interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity [bus idle] occurs for at least 4 seconds. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 1. "SETWAKEUPINT,Set wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up.." "0,1" newline bitfld.long 0xC 0. "SETBRKDTINT,Set break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only." "0,1" line.long 0x10 "LIN1_SCICLEARINT,The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register." bitfld.long 0x10 31. "CLRBEINT,Clear Bit Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 30. "CLRPBEINT,Clear Physical Bus Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 29. "CLRCEINT,Clear checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x10 28. "CLRISFEINT,Clear Inconsistent-Sync-Field-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 27. "CLRNREINT,Clear No-Reponse-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 26. "CLRFEINT,Clear Framing-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt." "0,1" newline bitfld.long 0x10 25. "CLROEINT,Clear Overrun-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt." "0,1" bitfld.long 0x10 24. "CLRPEINT,Clear Parity Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt." "0,1" bitfld.long 0x10 17. "SETRXDMA,Clear receiver DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request." "0,1" newline bitfld.long 0x10 16. "CLRTXDMA,Clear transmit DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request." "0,1" bitfld.long 0x10 13. "CLRIDINT,Clear Identifier interrupt.This bit is effective in LIN mode only. Setting this bit disables the ID interrupt." "0,1" bitfld.long 0x10 9. "CLRRXINT,Clear Receiver interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt." "0,1" newline bitfld.long 0x10 8. "CLRTXINT,Clear Transmitter interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt." "0,1" bitfld.long 0x10 7. "CLRTOA3WUSINT,Clear Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 6. "CLRTOAWUSINT,Clear Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x10 4. "CLRTIMEOUTINT,Clear Timeout interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout [LIN bus idle] interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 1. "CLRWAKEUPINT,Clear Wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt." "0,1" bitfld.long 0x10 0. "CLRBRKDTINT,Clear Break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only." "0,1" line.long 0x14 "LIN1_SCISETINTLVL,The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line." bitfld.long 0x14 31. "SETBEINTLVL,Set Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 30. "SETPBEINTLVL,Set Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 29. "SETCEINTLVL,Set Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x14 28. "SETISFEINTLVL,Set Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 27. "SETNREINTLVL,Set No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 26. "SETFEINTLVL,Set Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line." "0,1" newline bitfld.long 0x14 25. "SETOEINTLVL,Set Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line." "0,1" bitfld.long 0x14 24. "SETPEINTLVL,Set Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line." "0,1" bitfld.long 0x14 13. "SETIDINTLVL,Set ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x14 9. "SETRXINTOVO,Set Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line." "0,1" bitfld.long 0x14 8. "SETTXINTLVL,Set Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line." "0,1" bitfld.long 0x14 7. "SETTOA3WUSINTLVL,Set Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x14 6. "SETTOAWUSINTLVL,Set Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 4. "SETTIMEOUTINTLVL,Set Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 1. "SETWAKEUPINTLVL,Set Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line." "0,1" newline bitfld.long 0x14 0. "SETBRKDTINTLVL,Set Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only." "0,1" line.long 0x18 "LIN1_SCICLEARINTLVL,The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line." bitfld.long 0x18 31. "CLRBEINTLVL,Clear Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 30. "CLRPBEINTLVL,Clear Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 29. "CLRCEINTLVL,Clear Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x18 28. "CLRISFEINTLVL,Clear Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 27. "CLRNREINTLVL,Clear No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 26. "CLRFEINTLVL,Clear Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line." "0,1" newline bitfld.long 0x18 25. "CLROEINTLVL,Clear Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line." "0,1" bitfld.long 0x18 24. "CLRPEINTLVL,Clear Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line." "0,1" bitfld.long 0x18 13. "CLRIDINTLVL,Clear ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x18 9. "CLRRXINTLVL,Clear Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line." "0,1" bitfld.long 0x18 8. "CLRTXINTLVL,Clear Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line." "0,1" bitfld.long 0x18 7. "CLRTOA3WUSINTLVL,Clear Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x18 6. "CLRTOAWUSINTLVL,Clear Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 4. "CLRTIMEOUTINTLVL,Clear Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 1. "CLRWAKEUPINTLVL,Clear Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line." "0,1" newline bitfld.long 0x18 0. "CLRBRKDTINTLVL,Clear Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only." "0,1" line.long 0x1C "LIN1_SCIFLR,The SCIFLR register indicates the current status of the various interrupt sources of the LIN module." bitfld.long 0x1C 31. "BE,Bit Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 30. "PBE,Physical Bus Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 29. "CE,Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by:- Reading the.." "0,1" newline bitfld.long 0x1C 28. "ISFE,Inconsistent Sync Field Error Flag.This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the Header Reception and Adaptive Baudrate.." "0,1" bitfld.long 0x1C 27. "NRE,No-Response Error Flag.This bit is effective in LIN mode only. This bit is set when there is no response to a master's header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length [identifiers 0 to 61]. This.." "0,1" bitfld.long 0x1C 26. "FE,Framing error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode only the first stop bit is checked. The missing stop bit indicates that synchronization with the.." "0,1" newline bitfld.long 0x1C 25. "OE,Overrun error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to.." "0,1" bitfld.long 0x1C 24. "PE,Parity error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode the parity is calculated on the data and address bit fields of the received frame. In.." "?,?" bitfld.long 0x1C 14. "IDRXFLAG,Identifier On Receive Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the Message Filtering and Validation section for more details. When this flag is set.." "0,1" newline bitfld.long 0x1C 13. "IDTXFLAG,Identifier On Transmit Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the Message Filtering and Validation section for more details. When this flag is set.." "0,1" rbitfld.long 0x1C 12. "RXWAKE,Receiver wakeup detect flag.This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by:- RESET bit- Setting the SWnRESET bit [SCIGCR1.7]- System.." "0,1" rbitfld.long 0x1C 11. "TXEMPTY,Transmitter Empty flag.The value of this flag indicates the contents of the transmitter's buffer register[s] [SCITD/TDy] and shift register [SCITXSHF]. In multibuffer mode this flag indicates the value of the TDx registers and shift register.." "0,1" newline bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wakeup method select.This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or.." "0,1" bitfld.long 0x1C 9. "RXRDY,Receiver ready flag. In SCI compatibility mode the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode RXRDY is set once a valid frame is received in multibuffer mode a valid frame.." "0,1" rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag.When set this bit indicates that the transmit buffer[s] register [SCITD in compatibility mode and LINTD0 LINTD1 in MBUF mode] is/are ready to get another character from a CPU write. In SCI compatibility.." "0,1" newline bitfld.long 0x1C 7. "TOA3WUS,Timeout After 3 Wakeup Signals flag.This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another.." "0,1" bitfld.long 0x1C 6. "TOAWUS,Timeout After Wakeup Signal flag.This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal." "0,1" bitfld.long 0x1C 4. "TIMEOUT,LIN Bus IDLE timeout flag.This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by:- Reading the.." "0,1" newline rbitfld.long 0x1C 3. "BUSY,Bus BUSY flag.This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit the BUSY bit is set to 1. When the.." "0,1" rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state.This bit is effective in SCI-compatible mode only. While this bit is set the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus.." "0,1" bitfld.long 0x1C 1. "WAKEUP,Wake-up flag.This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit [SCISETINT.1] is set. This.." "0,1" newline bitfld.long 0x1C 0. "BRKDT,SCI break-detect flag.This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a.." "0,1" rgroup.long 0x20++0x7 line.long 0x0 "LIN1_SCIINTVECT0,The SCIINTVECT0 register indicates the offset for the INT0 interrupt line." hexmask.long.byte 0x0 0.--4. 1. "INTVECT0,Interrupt vector offset for INT0.This register indicates the offset for interrupt line INT0. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." line.long 0x4 "LIN1_SCIINTVECT1,The SCIINTVECT1 register indicates the offset for the INT1 interrupt line." hexmask.long.byte 0x4 0.--4. 1. "INTVECT1,Interrupt vector offset for INT1.This register indicates the offset for interrupt line INT1. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." group.long 0x28++0x7 line.long 0x0 "LIN1_SCIFORMAT,The SCIFORMAT register is used to set up the character and frame lengths." bitfld.long 0x0 16.--18. "LENGTH,Frame length control bits.In LIN mode these bits indicate the number of bytes in the response field from 1 to 8 bytes. In buffered SCI mode these bits indicate the number of characters. When these bits are used to indicate LIN response length.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "CHAR,Character length control bits.These bits are effective in SCI compatible mode only. These bits set the SCI character length from 1 to 8 bits. Note: In compatibility mode or buffered SCI mode when data of fewer than eight bits in length is received .." "0,1,2,3,4,5,6,7" line.long 0x4 "LIN1_BRSR,The BRSR register is used to configure the baud rate of the LIN module." bitfld.long 0x4 28.--30. "U,Superfractional Divider Selection. [U]These bits are an additional fractional part for the baudrate specification. These bits allow a super fine tuning of the fractional baudrate with 7 more intermediate values for each of the M fractional divider.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--27. 1. "M,SCI/LIN 4-bit Fractional Divider Selection. [M]These bits are effective in LIN or SCI asynchronous mode. These bits are used to select a baud rate for the SCI/LIN module and they are a fractional part for the baud rate specification. The M divider.." hexmask.long.byte 0x4 16.--23. 1. "SCI_LIN_PSH,PRESCALER P [High Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." newline hexmask.long.word 0x4 0.--15. 1. "SCI_LIN_PSL,PRESCALER P [Low Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." rgroup.long 0x30++0x7 line.long 0x0 "LIN1_SCIED,The SCIED register is a duplicate copy of SCIRD register that has no affect on the RXRDY flag for use with an emulator." hexmask.long.byte 0x0 0.--7. 1. "ED,Receiver Emulation Data.This bit is effective in SCI-compatible mode only. Reading SCIED[7-0] does not clear the RXRDY flag. This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag." line.long 0x4 "LIN1_SCIRD,The SCIRD register is where received data is stored and can be read from." hexmask.long.byte 0x4 0.--7. 1. "RD,Received Data.This bit is effective in SCI-compatible mode only. When a frame has been completely received the data in the frame is transferred from the receiver shift register SCIRXSHF to this register. As this transfer occurs the RXRDY flag is set.." group.long 0x38++0xB line.long 0x0 "LIN1_SCITD,The SCITD register is where data to be transmitted is written to by application software." hexmask.long.byte 0x0 0.--7. 1. "TD,Transmit dataThis bit is effective in SCI-compatible mode only. Data to be transmitted is written to this register. The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag [SCIFLR.23] which indicates that.." line.long 0x4 "LIN1_SCIPIO0,The SCIPIO0 register is used to enable the LINTX and LINRX pins." bitfld.long 0x4 2. "TXFUNC,Transmit pin function.This bit is effective in LIN or SCI mode. This bit defines the function of LINTX pin." "0,1" bitfld.long 0x4 1. "RXFUNC,Receive pin function.This bit is effective in LIN or SCI mode. This bit defines the function of the LINRX pin." "0,1" line.long 0x8 "LIN1_SCIPIO1,Pin control Register 1" bitfld.long 0x8 2. "TXDIR,Transmit pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINTX pin if it is configured with general-purpose I/O functionality [TX FUNC = 0]. 0: general purpose input pin. 1: general-purpose.." "0: general purpose input pin,1: general-purpose output pin" bitfld.long 0x8 1. "RXDIR,Receive pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINRX pin if it is configured with general-purpose I/O functionality [RX FUNC = 0]. 0: general purpose input pin. 1: general-purpose.." "0: general purpose input pin,1: general-purpose output pin" rgroup.long 0x44++0x3 line.long 0x0 "LIN1_SCIPIO2,The SCIPIO2 register indicates the current status of the LINTX and LINRX pins." bitfld.long 0x0 2. "TXIN,Transmit data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINTX pin." "0,1" bitfld.long 0x0 1. "RXIN,Receive data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINRX pin." "0,1" group.long 0x48++0x1B line.long 0x0 "LIN1_SCIPIO3,Pin control Register 3" bitfld.long 0x0 2. "TXOUT,Transmit pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINTX." "0,1" bitfld.long 0x0 1. "RXOUT,Receive pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINRX." "0,1" line.long 0x4 "LIN1_SCIPIO4,Pin control Register 4" bitfld.long 0x4 2. "TXSET,Transmit pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX." "0,1" bitfld.long 0x4 1. "RXSET,Receive pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX." "0,1" line.long 0x8 "LIN1_SCIPIO5,Pin control Register 5" bitfld.long 0x8 2. "TXCLR,Transmit pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINTX." "0,1" bitfld.long 0x8 1. "RXCLR,Receive pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINRX." "0,1" line.long 0xC "LIN1_SCIPIO6,Pin control Register 6" bitfld.long 0xC 2. "TXPDR,Transmit pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINTX." "0,1" bitfld.long 0xC 1. "RXPDR,Receive pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINRX." "0,1" line.long 0x10 "LIN1_SCIPIO7,Pin control Register 7" bitfld.long 0x10 2. "TXPD,Transmit pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINTX." "0,1" bitfld.long 0x10 1. "RXPD,Receive pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINRX." "0,1" line.long 0x14 "LIN1_SCIPIO8,Pin control Register 8" bitfld.long 0x14 2. "TXPSL,TX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINTX." "0,1" bitfld.long 0x14 1. "RXPSL,RX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINRX." "0,1" line.long 0x18 "LIN1_LINCOMP,The LINCOMPARE register is used to configure the sync delimeter and sync break extension." bitfld.long 0x18 8.--9. "SDEL,2-bit Sync Delimiter compare.These bits are effective in LIN mode only. These bits are used to configure the number of Tbit for the sync delimiter in the sync field.The time delay calculation for the synchronization delimiter is:TSDEL = [SDEL +.." "0,1,2,3" bitfld.long 0x18 0.--2. "SBREAK,3-bit Sync Break extend.LIN mode only. These bits are used to configure the number of Tbits for the sync break to extend the minimum 13 Tbit in the Sync Field to a maximum of 20 Tbit.The time delay calculation for the sync break is:TSYNBRK =.." "0,1,2,3,4,5,6,7" rgroup.long 0x64++0x7 line.long 0x0 "LIN1_LINRD0,The LINRD0 register contains the lower 4 bytes of the received LIN frame data." hexmask.long.byte 0x0 24.--31. 1. "RD0,8-bit Receive Buffer 0Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received.A read of this byte clears the RXDY byte.Note: RD<x-1> is.." hexmask.long.byte 0x0 16.--23. 1. "RD1,8-bit Receive Buffer 1.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x0 8.--15. 1. "RD2,8-bit Receive Buffer 2.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x0 0.--7. 1. "RD3,8-bit Receive Buffer 3.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." line.long 0x4 "LIN1_LINRD1,The LINRD1 regsiter contains the upper 4 bytes of the received LIN frame data." hexmask.long.byte 0x4 24.--31. 1. "RD4,8-bit Receive Buffer 4 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 16.--23. 1. "RD5,8-bit Receive Buffer 5.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 8.--15. 1. "RD6,8-bit Receive Buffer 6.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x4 0.--7. 1. "RD7,8-bit Receive Buffer 7.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." group.long 0x6C++0x17 line.long 0x0 "LIN1_LINMASK,The LINMASK register is used to configure the masks used for filtering incoming ID messages for receive and transmit frames." hexmask.long.byte 0x0 16.--23. 1. "RXIDMASK,Receive ID mask.This field is effective in LIN mode only.This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID witht the RX ID mask will set the ID RX flag and trigger and.." hexmask.long.byte 0x0 0.--7. 1. "TXIDMASK,Transmit ID mask.This field is effective in LIN mode only. This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID with the TX ID Mask will set the ID TX flag and trigger an.." line.long 0x4 "LIN1_LINID,The LINID register contains the identification fields for LIN communication.[[br]]NOTE: For software compatibility with future LIN modules. the HGEN CTRL bit must be set to 1. the RX ID MASK field must be set to FFh. and the TX ID MASK field.." hexmask.long.byte 0x4 16.--23. 1. "RECEIVEDID,Received ID.This bit is effective in LIN mode only. This byte contains the current message identifier. During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID-parity error and there has been.." hexmask.long.byte 0x4 8.--15. 1. "IDSLAVETASKBYTE,ID Slave Task byte.This field is effective in LIN mode only. This byte contains the identifier to which the received ID of an incoming header will be compared in order to decide whether a RX response a TX response or no action needs to.." hexmask.long.byte 0x4 0.--7. 1. "IDBYTE,ID byte.This field is effective in LIN mode only. This byte is the LIN mode message ID. On a master node a write to this register by the CPU initiates a header transmission. For a slave task this byte is used for message filtering when HGENCTRL.." line.long 0x8 "LIN1_LINTD0,The LINTD0 register contains the lower 4 bytes of the data to be transmitted.[[br]]NOTE: TD<x-1> is equivalent to Data byte <x> of the LIN frame." hexmask.long.byte 0x8 24.--31. 1. "TD0,8-bit Transmit Buffer 0.Byte 0 to be transmitted is written into this register and then copied to SCITXSHF for transmission. Once byte 0 is written in TDO buffer transmission will be initiated." hexmask.long.byte 0x8 16.--23. 1. "TD1,8-bit Transmit Buffer 3.Byte 1 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0x8 8.--15. 1. "TD2,8-bit Transmit Buffer 2.Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0x8 0.--7. 1. "TD3,8-bit Transmit Buffer 3.Byte 3 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0xC "LIN1_LINTD1,The LINTD1 register contains the upper 4 bytes of the data to be transmitted.[[br]]NOTE: TD<x-1> is equivalent to Data byte <x> of the LIN frame." hexmask.long.byte 0xC 24.--31. 1. "TD4,8-bit Transmit Buffer 4.Byte4 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 16.--23. 1. "TD5,8-bit Transmit Buffer 5.Byte 5 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 8.--15. 1. "TD6,8-bit Transmit Buffer 6.Byte 6 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0xC 0.--7. 1. "TD7,8-bit Transmit Buffer 7.Byte 7 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0x10 "LIN1_MBRSR,The MBRSR register is used to configure the expected maximum baud rate of the LIN network." hexmask.long.word 0x10 0.--12. 1. "MBR,Maximum Baud Rate Prescaler.This field is effective in LIN mode only. This 13-bit prescaler is used during the synchronization phase [see the Header Reception and Adaptive Baudrate section] of a slave module if the ADAPT bit is set. In this way a.." line.long 0x14 "LIN1_Reserved_1,tbd" group.long 0x90++0x7 line.long 0x0 "LIN1_IODFTCTRL,The IODFTCTRL register is used to emulate various error and test conditions." bitfld.long 0x0 31. "BERRENA,Bit Errror Enable bit.This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set the bit received is ORed with 1 and passed to the Bit monitor circuitry." "0,1" bitfld.long 0x0 30. "PBERRENA,Physical Bus Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor.." "0,1" bitfld.long 0x0 29. "CERRENA,Checksum Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set the polarity of the CTYPE [checksum type] in the receive checksum calculator is changed so that a checksum error.." "0,1" newline bitfld.long 0x0 28. "ISFERRENA,Inconsistent Sync Field Error Enable bit.This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set the bit widths in the sync field are varied so that the ISF check fails and the error flag is set." "0,1" bitfld.long 0x0 26. "FERRENA,This bit is used to create a Frame Error.This bit is effective in SCI-compatible mode only. When this bit is set the stop bit received is ANDed with '0' and passed to the stop bit check circuitry." "0,1" bitfld.long 0x0 25. "PERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set in compatible mode the parity bit received is toggled so that a parity error occurs." "0,1" newline bitfld.long 0x0 24. "BRKDTERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error [SCI mode only]. When this bit is set the stop bit of the frame is ANDed with '0' and passed to the RSM so that a frame error.." "0,1" bitfld.long 0x0 19.--20. "PINSAMPLEMASK,Pin sample mask.These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry.Note: During IODFT mode testing for.." "0,1,2,3" bitfld.long 0x0 16.--18. "TXSHIFT,Transmit shift.These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. [Not applicable to Start Bit]" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "IODFTENA,IO DFT Enable KeyThis field is used to enable the IODFT mode of the SCI/LIN module for testing." bitfld.long 0x0 1. "LPBENA,Module loopback enable.In analog loopback mode the complete communication path through the I/Os can be tested whereas in digital loopback mode the I/O buffers are excluded from this path." "0,1" bitfld.long 0x0 0. "RXPENA,Module Analog loopback through receive pin enable.This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only." "0,1" line.long 0x4 "LIN1_Reserved_2,tbd" group.long 0xE0++0x3 line.long 0x0 "LIN1_LIN_GLB_INT_EN,The LIN_GLB_INT_EN register is used to enable the INT0 and INT1 interrupt lines to propagate to the PIE block." bitfld.long 0x0 1. "GLBINT1_EN,Global Interrupt Enable for LIN INT1.This bit determines whether the INT1 interrupt line generates an interrupt to the PIE or not" "0,1" bitfld.long 0x0 0. "GLBINT0_EN,Global Interrupt Enable for LIN INT0.This bit determines whether the INT0 interrupt line generates an interrupt to the PIE or not." "0,1" rgroup.long 0xE4++0x3 line.long 0x0 "LIN1_LIN_GLB_INT_FLG,The LIN_GLB_INT_FLG register contains the current status of the INT0 and INT1 flags." bitfld.long 0x0 1. "INT1_FLG,Global Interrupt Flag for LIN INT1.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT1 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" bitfld.long 0x0 0. "INT0_FLG,Global Interrupt Flag for LIN INT0.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT0 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" group.long 0xE8++0x3 line.long 0x0 "LIN1_LIN_GLB_INT_CLR,The LIN_GLB_INT_CLR register is used to clear the interrupt flags in LIN_GLB_INT_FLG register." bitfld.long 0x0 1. "INT1_FLG_CLR,Global Interrupt flag clear for LIN INT1.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT1_FLG bit. Writing 0 has no effect." "0,1" bitfld.long 0x0 0. "INT0_FLG_CLR,Global Interrupt flag clear for LIN INT0.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT0_FLG bit. Writing 0 has no effect." "0,1" tree.end tree "LIN2" base ad:0x52402000 group.long 0x0++0x1F line.long 0x0 "LIN2_SCIGCR0,The SCIGCR0 register defines the module reset." bitfld.long 0x0 0. "RESET,This bit resets the SCI/LIN module. This bit is effective in LIN or SCI-compatible mode.. This bit affects the reset state of the SCI/LIN module." "0,1" line.long 0x4 "LIN2_SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI." bitfld.long 0x4 25. "TXENA,Transmit enable.This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy [with y=0 1 ...7] buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the.." "0,1" bitfld.long 0x4 24. "RXENA,Receive enable.This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the.." "0,1" bitfld.long 0x4 17. "CONT,Continue on suspend.This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set the counters are.." "0,1" newline bitfld.long 0x4 16. "LOOPBACK,Loopback bit.This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality then the LINTX pin is internally.." "0,1" bitfld.long 0x4 13. "STOPEXTFRAME,Stop extended frame communication.This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped this bit is cleared automatically." "0,1" bitfld.long 0x4 12. "HGENCTRL,HGEN control bit.This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison." "0,1" newline bitfld.long 0x4 11. "CTYPE,Checksum type.This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced." "0,1" bitfld.long 0x4 10. "MBUFMODE,Multibuffer mode.This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage that is whether the RX/TX multibuffers are used or a single register RD0/TD0 is used." "0,1" bitfld.long 0x4 9. "ADAPT,Adapt mode enable.This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file.." "0,1" newline bitfld.long 0x4 8. "SLEEP,SCI sleep.SCI compatibility mode only. In a multiprocessor configuration this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however RXRDY is.." "0,1" bitfld.long 0x4 7. "SWNRST,Software reset [active low].This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime [i.e. while SWnRESET = 1]:- STOP EXT Frame.." "0,1" bitfld.long 0x4 6. "LINMODE,LIN modeThis bit controls the mode of operation of the module." "0,1" newline bitfld.long 0x4 5. "CLK_MASTER,SCI internal clock enable or LIN Master/Slave configuration.In the SCI mode this bit enables the clock to the SCI module. In LIN mode this bit determines whether a LIN node is a slave or master." "0,1" bitfld.long 0x4 4. "STOP,SCI number of stop bits.This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode the receiver waits until the end of the second stop bit [if STOP = 1] to begin checking for an.." "0,1" bitfld.long 0x4 3. "PARITY,SCI parity odd/even selection.This bit is effective in SCI-compatible mode only. If the PARITY ENA bit [SCIGCR1.2] is set PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit.." "0,1" newline bitfld.long 0x4 2. "PARITYENA,Parity enable.Enables or disables the parity function." "0,1" bitfld.long 0x4 1. "TIMINGMODE,SCI timing mode bit.This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation." "0,1" bitfld.long 0x4 0. "COMMMODE,SCI/LIN communication mode bit.In compatibility mode it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5." "0,1" line.long 0x8 "LIN2_SCIGCR2,The SCIGCR2 register is used to send or compare a checksum byte during extended frames. to generate a wakeup and for low-power mode control of the LIN module." bitfld.long 0x8 17. "CC,Compare Checksum.This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by writing a one to this bit.In non multibuffer mode once the CC bit.." "0,1" bitfld.long 0x8 16. "SC,Send ChecksumThis mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the.." "0,1" bitfld.long 0x8 8. "GENWU,Generate wakeup signal.This bit controls the generation of a wakeup signal by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break." "0,1" newline bitfld.long 0x8 0. "POWERDOWN,Power down.This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup.." "0,1" line.long 0xC "LIN2_SCISETINT,The SCISETINT register is used to enable the various interrupts available in the LIN module." bitfld.long 0xC 31. "SETBEINT,Set bit error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 30. "SETPBEINT,Set physical bus error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 29. "SETCEINT,Set checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only." "0,1" newline bitfld.long 0xC 28. "SETISFEINT,Set inconsistent-sync-field-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 27. "SETNREINT,Set no-response-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 26. "SETFEINT,Set framing-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs." "0,1" newline bitfld.long 0xC 25. "SETOEINT,Set overrun-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs." "0,1" bitfld.long 0xC 24. "SETPEINT,Set parity interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs." "0,1" bitfld.long 0xC 18. "SET_RX_DMA_ALL,Set receiver DMA for Address & Data frames.This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared RX interrupt request is generated for address.." "0,1" newline bitfld.long 0xC 17. "SET_RX_DMA,Set receiver DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared interrupt requests are generated depending on SETRXINT." "0,1" bitfld.long 0xC 16. "SET_TX_DMA,Set transmit DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter this bit must be set. If it is cleared interrupt requests are generated depending on SETTXINT." "0,1" bitfld.long 0xC 13. "SETIDINT,Set Identification interrupt.This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received." "0,1" newline bitfld.long 0xC 9. "SETRXINT,Set Receiver interrupt.Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD." "0,1" bitfld.long 0xC 8. "SETTXINT,Set Transmitter interrupt.Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set." "0,1" bitfld.long 0xC 7. "SETTOA3WUSINT,Set Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN.." "0,1" newline bitfld.long 0xC 6. "SETTOAWUSINT,Set Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode.." "0,1" bitfld.long 0xC 4. "SETTIMEOUTINT,Set timeout interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity [bus idle] occurs for at least 4 seconds. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 1. "SETWAKEUPINT,Set wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up.." "0,1" newline bitfld.long 0xC 0. "SETBRKDTINT,Set break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only." "0,1" line.long 0x10 "LIN2_SCICLEARINT,The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register." bitfld.long 0x10 31. "CLRBEINT,Clear Bit Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 30. "CLRPBEINT,Clear Physical Bus Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 29. "CLRCEINT,Clear checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x10 28. "CLRISFEINT,Clear Inconsistent-Sync-Field-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 27. "CLRNREINT,Clear No-Reponse-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 26. "CLRFEINT,Clear Framing-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt." "0,1" newline bitfld.long 0x10 25. "CLROEINT,Clear Overrun-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt." "0,1" bitfld.long 0x10 24. "CLRPEINT,Clear Parity Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt." "0,1" bitfld.long 0x10 17. "SETRXDMA,Clear receiver DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request." "0,1" newline bitfld.long 0x10 16. "CLRTXDMA,Clear transmit DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request." "0,1" bitfld.long 0x10 13. "CLRIDINT,Clear Identifier interrupt.This bit is effective in LIN mode only. Setting this bit disables the ID interrupt." "0,1" bitfld.long 0x10 9. "CLRRXINT,Clear Receiver interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt." "0,1" newline bitfld.long 0x10 8. "CLRTXINT,Clear Transmitter interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt." "0,1" bitfld.long 0x10 7. "CLRTOA3WUSINT,Clear Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 6. "CLRTOAWUSINT,Clear Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x10 4. "CLRTIMEOUTINT,Clear Timeout interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout [LIN bus idle] interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 1. "CLRWAKEUPINT,Clear Wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt." "0,1" bitfld.long 0x10 0. "CLRBRKDTINT,Clear Break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only." "0,1" line.long 0x14 "LIN2_SCISETINTLVL,The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line." bitfld.long 0x14 31. "SETBEINTLVL,Set Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 30. "SETPBEINTLVL,Set Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 29. "SETCEINTLVL,Set Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x14 28. "SETISFEINTLVL,Set Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 27. "SETNREINTLVL,Set No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 26. "SETFEINTLVL,Set Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line." "0,1" newline bitfld.long 0x14 25. "SETOEINTLVL,Set Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line." "0,1" bitfld.long 0x14 24. "SETPEINTLVL,Set Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line." "0,1" bitfld.long 0x14 13. "SETIDINTLVL,Set ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x14 9. "SETRXINTOVO,Set Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line." "0,1" bitfld.long 0x14 8. "SETTXINTLVL,Set Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line." "0,1" bitfld.long 0x14 7. "SETTOA3WUSINTLVL,Set Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x14 6. "SETTOAWUSINTLVL,Set Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 4. "SETTIMEOUTINTLVL,Set Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 1. "SETWAKEUPINTLVL,Set Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line." "0,1" newline bitfld.long 0x14 0. "SETBRKDTINTLVL,Set Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only." "0,1" line.long 0x18 "LIN2_SCICLEARINTLVL,The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line." bitfld.long 0x18 31. "CLRBEINTLVL,Clear Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 30. "CLRPBEINTLVL,Clear Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 29. "CLRCEINTLVL,Clear Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x18 28. "CLRISFEINTLVL,Clear Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 27. "CLRNREINTLVL,Clear No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 26. "CLRFEINTLVL,Clear Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line." "0,1" newline bitfld.long 0x18 25. "CLROEINTLVL,Clear Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line." "0,1" bitfld.long 0x18 24. "CLRPEINTLVL,Clear Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line." "0,1" bitfld.long 0x18 13. "CLRIDINTLVL,Clear ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x18 9. "CLRRXINTLVL,Clear Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line." "0,1" bitfld.long 0x18 8. "CLRTXINTLVL,Clear Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line." "0,1" bitfld.long 0x18 7. "CLRTOA3WUSINTLVL,Clear Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x18 6. "CLRTOAWUSINTLVL,Clear Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 4. "CLRTIMEOUTINTLVL,Clear Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 1. "CLRWAKEUPINTLVL,Clear Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line." "0,1" newline bitfld.long 0x18 0. "CLRBRKDTINTLVL,Clear Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only." "0,1" line.long 0x1C "LIN2_SCIFLR,The SCIFLR register indicates the current status of the various interrupt sources of the LIN module." bitfld.long 0x1C 31. "BE,Bit Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 30. "PBE,Physical Bus Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 29. "CE,Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by:- Reading the.." "0,1" newline bitfld.long 0x1C 28. "ISFE,Inconsistent Sync Field Error Flag.This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the Header Reception and Adaptive Baudrate.." "0,1" bitfld.long 0x1C 27. "NRE,No-Response Error Flag.This bit is effective in LIN mode only. This bit is set when there is no response to a master's header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length [identifiers 0 to 61]. This.." "0,1" bitfld.long 0x1C 26. "FE,Framing error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode only the first stop bit is checked. The missing stop bit indicates that synchronization with the.." "0,1" newline bitfld.long 0x1C 25. "OE,Overrun error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to.." "0,1" bitfld.long 0x1C 24. "PE,Parity error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode the parity is calculated on the data and address bit fields of the received frame. In.." "?,?" bitfld.long 0x1C 14. "IDRXFLAG,Identifier On Receive Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the Message Filtering and Validation section for more details. When this flag is set.." "0,1" newline bitfld.long 0x1C 13. "IDTXFLAG,Identifier On Transmit Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the Message Filtering and Validation section for more details. When this flag is set.." "0,1" rbitfld.long 0x1C 12. "RXWAKE,Receiver wakeup detect flag.This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by:- RESET bit- Setting the SWnRESET bit [SCIGCR1.7]- System.." "0,1" rbitfld.long 0x1C 11. "TXEMPTY,Transmitter Empty flag.The value of this flag indicates the contents of the transmitter's buffer register[s] [SCITD/TDy] and shift register [SCITXSHF]. In multibuffer mode this flag indicates the value of the TDx registers and shift register.." "0,1" newline bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wakeup method select.This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or.." "0,1" bitfld.long 0x1C 9. "RXRDY,Receiver ready flag. In SCI compatibility mode the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode RXRDY is set once a valid frame is received in multibuffer mode a valid frame.." "0,1" rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag.When set this bit indicates that the transmit buffer[s] register [SCITD in compatibility mode and LINTD0 LINTD1 in MBUF mode] is/are ready to get another character from a CPU write. In SCI compatibility.." "0,1" newline bitfld.long 0x1C 7. "TOA3WUS,Timeout After 3 Wakeup Signals flag.This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another.." "0,1" bitfld.long 0x1C 6. "TOAWUS,Timeout After Wakeup Signal flag.This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal." "0,1" bitfld.long 0x1C 4. "TIMEOUT,LIN Bus IDLE timeout flag.This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by:- Reading the.." "0,1" newline rbitfld.long 0x1C 3. "BUSY,Bus BUSY flag.This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit the BUSY bit is set to 1. When the.." "0,1" rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state.This bit is effective in SCI-compatible mode only. While this bit is set the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus.." "0,1" bitfld.long 0x1C 1. "WAKEUP,Wake-up flag.This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit [SCISETINT.1] is set. This.." "0,1" newline bitfld.long 0x1C 0. "BRKDT,SCI break-detect flag.This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a.." "0,1" rgroup.long 0x20++0x7 line.long 0x0 "LIN2_SCIINTVECT0,The SCIINTVECT0 register indicates the offset for the INT0 interrupt line." hexmask.long.byte 0x0 0.--4. 1. "INTVECT0,Interrupt vector offset for INT0.This register indicates the offset for interrupt line INT0. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." line.long 0x4 "LIN2_SCIINTVECT1,The SCIINTVECT1 register indicates the offset for the INT1 interrupt line." hexmask.long.byte 0x4 0.--4. 1. "INTVECT1,Interrupt vector offset for INT1.This register indicates the offset for interrupt line INT1. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." group.long 0x28++0x7 line.long 0x0 "LIN2_SCIFORMAT,The SCIFORMAT register is used to set up the character and frame lengths." bitfld.long 0x0 16.--18. "LENGTH,Frame length control bits.In LIN mode these bits indicate the number of bytes in the response field from 1 to 8 bytes. In buffered SCI mode these bits indicate the number of characters. When these bits are used to indicate LIN response length.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "CHAR,Character length control bits.These bits are effective in SCI compatible mode only. These bits set the SCI character length from 1 to 8 bits. Note: In compatibility mode or buffered SCI mode when data of fewer than eight bits in length is received .." "0,1,2,3,4,5,6,7" line.long 0x4 "LIN2_BRSR,The BRSR register is used to configure the baud rate of the LIN module." bitfld.long 0x4 28.--30. "U,Superfractional Divider Selection. [U]These bits are an additional fractional part for the baudrate specification. These bits allow a super fine tuning of the fractional baudrate with 7 more intermediate values for each of the M fractional divider.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--27. 1. "M,SCI/LIN 4-bit Fractional Divider Selection. [M]These bits are effective in LIN or SCI asynchronous mode. These bits are used to select a baud rate for the SCI/LIN module and they are a fractional part for the baud rate specification. The M divider.." hexmask.long.byte 0x4 16.--23. 1. "SCI_LIN_PSH,PRESCALER P [High Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." newline hexmask.long.word 0x4 0.--15. 1. "SCI_LIN_PSL,PRESCALER P [Low Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." rgroup.long 0x30++0x7 line.long 0x0 "LIN2_SCIED,The SCIED register is a duplicate copy of SCIRD register that has no affect on the RXRDY flag for use with an emulator." hexmask.long.byte 0x0 0.--7. 1. "ED,Receiver Emulation Data.This bit is effective in SCI-compatible mode only. Reading SCIED[7-0] does not clear the RXRDY flag. This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag." line.long 0x4 "LIN2_SCIRD,The SCIRD register is where received data is stored and can be read from." hexmask.long.byte 0x4 0.--7. 1. "RD,Received Data.This bit is effective in SCI-compatible mode only. When a frame has been completely received the data in the frame is transferred from the receiver shift register SCIRXSHF to this register. As this transfer occurs the RXRDY flag is set.." group.long 0x38++0xB line.long 0x0 "LIN2_SCITD,The SCITD register is where data to be transmitted is written to by application software." hexmask.long.byte 0x0 0.--7. 1. "TD,Transmit dataThis bit is effective in SCI-compatible mode only. Data to be transmitted is written to this register. The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag [SCIFLR.23] which indicates that.." line.long 0x4 "LIN2_SCIPIO0,The SCIPIO0 register is used to enable the LINTX and LINRX pins." bitfld.long 0x4 2. "TXFUNC,Transmit pin function.This bit is effective in LIN or SCI mode. This bit defines the function of LINTX pin." "0,1" bitfld.long 0x4 1. "RXFUNC,Receive pin function.This bit is effective in LIN or SCI mode. This bit defines the function of the LINRX pin." "0,1" line.long 0x8 "LIN2_SCIPIO1,Pin control Register 1" bitfld.long 0x8 2. "TXDIR,Transmit pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINTX pin if it is configured with general-purpose I/O functionality [TX FUNC = 0]. 0: general purpose input pin. 1: general-purpose.." "0: general purpose input pin,1: general-purpose output pin" bitfld.long 0x8 1. "RXDIR,Receive pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINRX pin if it is configured with general-purpose I/O functionality [RX FUNC = 0]. 0: general purpose input pin. 1: general-purpose.." "0: general purpose input pin,1: general-purpose output pin" rgroup.long 0x44++0x3 line.long 0x0 "LIN2_SCIPIO2,The SCIPIO2 register indicates the current status of the LINTX and LINRX pins." bitfld.long 0x0 2. "TXIN,Transmit data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINTX pin." "0,1" bitfld.long 0x0 1. "RXIN,Receive data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINRX pin." "0,1" group.long 0x48++0x1B line.long 0x0 "LIN2_SCIPIO3,Pin control Register 3" bitfld.long 0x0 2. "TXOUT,Transmit pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINTX." "0,1" bitfld.long 0x0 1. "RXOUT,Receive pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINRX." "0,1" line.long 0x4 "LIN2_SCIPIO4,Pin control Register 4" bitfld.long 0x4 2. "TXSET,Transmit pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX." "0,1" bitfld.long 0x4 1. "RXSET,Receive pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX." "0,1" line.long 0x8 "LIN2_SCIPIO5,Pin control Register 5" bitfld.long 0x8 2. "TXCLR,Transmit pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINTX." "0,1" bitfld.long 0x8 1. "RXCLR,Receive pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINRX." "0,1" line.long 0xC "LIN2_SCIPIO6,Pin control Register 6" bitfld.long 0xC 2. "TXPDR,Transmit pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINTX." "0,1" bitfld.long 0xC 1. "RXPDR,Receive pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINRX." "0,1" line.long 0x10 "LIN2_SCIPIO7,Pin control Register 7" bitfld.long 0x10 2. "TXPD,Transmit pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINTX." "0,1" bitfld.long 0x10 1. "RXPD,Receive pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINRX." "0,1" line.long 0x14 "LIN2_SCIPIO8,Pin control Register 8" bitfld.long 0x14 2. "TXPSL,TX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINTX." "0,1" bitfld.long 0x14 1. "RXPSL,RX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINRX." "0,1" line.long 0x18 "LIN2_LINCOMP,The LINCOMPARE register is used to configure the sync delimeter and sync break extension." bitfld.long 0x18 8.--9. "SDEL,2-bit Sync Delimiter compare.These bits are effective in LIN mode only. These bits are used to configure the number of Tbit for the sync delimiter in the sync field.The time delay calculation for the synchronization delimiter is:TSDEL = [SDEL +.." "0,1,2,3" bitfld.long 0x18 0.--2. "SBREAK,3-bit Sync Break extend.LIN mode only. These bits are used to configure the number of Tbits for the sync break to extend the minimum 13 Tbit in the Sync Field to a maximum of 20 Tbit.The time delay calculation for the sync break is:TSYNBRK =.." "0,1,2,3,4,5,6,7" rgroup.long 0x64++0x7 line.long 0x0 "LIN2_LINRD0,The LINRD0 register contains the lower 4 bytes of the received LIN frame data." hexmask.long.byte 0x0 24.--31. 1. "RD0,8-bit Receive Buffer 0Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received.A read of this byte clears the RXDY byte.Note: RD<x-1> is.." hexmask.long.byte 0x0 16.--23. 1. "RD1,8-bit Receive Buffer 1.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x0 8.--15. 1. "RD2,8-bit Receive Buffer 2.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x0 0.--7. 1. "RD3,8-bit Receive Buffer 3.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." line.long 0x4 "LIN2_LINRD1,The LINRD1 regsiter contains the upper 4 bytes of the received LIN frame data." hexmask.long.byte 0x4 24.--31. 1. "RD4,8-bit Receive Buffer 4 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 16.--23. 1. "RD5,8-bit Receive Buffer 5.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 8.--15. 1. "RD6,8-bit Receive Buffer 6.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x4 0.--7. 1. "RD7,8-bit Receive Buffer 7.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." group.long 0x6C++0x17 line.long 0x0 "LIN2_LINMASK,The LINMASK register is used to configure the masks used for filtering incoming ID messages for receive and transmit frames." hexmask.long.byte 0x0 16.--23. 1. "RXIDMASK,Receive ID mask.This field is effective in LIN mode only.This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID witht the RX ID mask will set the ID RX flag and trigger and.." hexmask.long.byte 0x0 0.--7. 1. "TXIDMASK,Transmit ID mask.This field is effective in LIN mode only. This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID with the TX ID Mask will set the ID TX flag and trigger an.." line.long 0x4 "LIN2_LINID,The LINID register contains the identification fields for LIN communication.[[br]]NOTE: For software compatibility with future LIN modules. the HGEN CTRL bit must be set to 1. the RX ID MASK field must be set to FFh. and the TX ID MASK field.." hexmask.long.byte 0x4 16.--23. 1. "RECEIVEDID,Received ID.This bit is effective in LIN mode only. This byte contains the current message identifier. During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID-parity error and there has been.." hexmask.long.byte 0x4 8.--15. 1. "IDSLAVETASKBYTE,ID Slave Task byte.This field is effective in LIN mode only. This byte contains the identifier to which the received ID of an incoming header will be compared in order to decide whether a RX response a TX response or no action needs to.." hexmask.long.byte 0x4 0.--7. 1. "IDBYTE,ID byte.This field is effective in LIN mode only. This byte is the LIN mode message ID. On a master node a write to this register by the CPU initiates a header transmission. For a slave task this byte is used for message filtering when HGENCTRL.." line.long 0x8 "LIN2_LINTD0,The LINTD0 register contains the lower 4 bytes of the data to be transmitted.[[br]]NOTE: TD<x-1> is equivalent to Data byte <x> of the LIN frame." hexmask.long.byte 0x8 24.--31. 1. "TD0,8-bit Transmit Buffer 0.Byte 0 to be transmitted is written into this register and then copied to SCITXSHF for transmission. Once byte 0 is written in TDO buffer transmission will be initiated." hexmask.long.byte 0x8 16.--23. 1. "TD1,8-bit Transmit Buffer 3.Byte 1 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0x8 8.--15. 1. "TD2,8-bit Transmit Buffer 2.Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0x8 0.--7. 1. "TD3,8-bit Transmit Buffer 3.Byte 3 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0xC "LIN2_LINTD1,The LINTD1 register contains the upper 4 bytes of the data to be transmitted.[[br]]NOTE: TD<x-1> is equivalent to Data byte <x> of the LIN frame." hexmask.long.byte 0xC 24.--31. 1. "TD4,8-bit Transmit Buffer 4.Byte4 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 16.--23. 1. "TD5,8-bit Transmit Buffer 5.Byte 5 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 8.--15. 1. "TD6,8-bit Transmit Buffer 6.Byte 6 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0xC 0.--7. 1. "TD7,8-bit Transmit Buffer 7.Byte 7 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0x10 "LIN2_MBRSR,The MBRSR register is used to configure the expected maximum baud rate of the LIN network." hexmask.long.word 0x10 0.--12. 1. "MBR,Maximum Baud Rate Prescaler.This field is effective in LIN mode only. This 13-bit prescaler is used during the synchronization phase [see the Header Reception and Adaptive Baudrate section] of a slave module if the ADAPT bit is set. In this way a.." line.long 0x14 "LIN2_Reserved_1,tbd" group.long 0x90++0x7 line.long 0x0 "LIN2_IODFTCTRL,The IODFTCTRL register is used to emulate various error and test conditions." bitfld.long 0x0 31. "BERRENA,Bit Errror Enable bit.This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set the bit received is ORed with 1 and passed to the Bit monitor circuitry." "0,1" bitfld.long 0x0 30. "PBERRENA,Physical Bus Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor.." "0,1" bitfld.long 0x0 29. "CERRENA,Checksum Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set the polarity of the CTYPE [checksum type] in the receive checksum calculator is changed so that a checksum error.." "0,1" newline bitfld.long 0x0 28. "ISFERRENA,Inconsistent Sync Field Error Enable bit.This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set the bit widths in the sync field are varied so that the ISF check fails and the error flag is set." "0,1" bitfld.long 0x0 26. "FERRENA,This bit is used to create a Frame Error.This bit is effective in SCI-compatible mode only. When this bit is set the stop bit received is ANDed with '0' and passed to the stop bit check circuitry." "0,1" bitfld.long 0x0 25. "PERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set in compatible mode the parity bit received is toggled so that a parity error occurs." "0,1" newline bitfld.long 0x0 24. "BRKDTERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error [SCI mode only]. When this bit is set the stop bit of the frame is ANDed with '0' and passed to the RSM so that a frame error.." "0,1" bitfld.long 0x0 19.--20. "PINSAMPLEMASK,Pin sample mask.These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry.Note: During IODFT mode testing for.." "0,1,2,3" bitfld.long 0x0 16.--18. "TXSHIFT,Transmit shift.These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. [Not applicable to Start Bit]" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "IODFTENA,IO DFT Enable KeyThis field is used to enable the IODFT mode of the SCI/LIN module for testing." bitfld.long 0x0 1. "LPBENA,Module loopback enable.In analog loopback mode the complete communication path through the I/Os can be tested whereas in digital loopback mode the I/O buffers are excluded from this path." "0,1" bitfld.long 0x0 0. "RXPENA,Module Analog loopback through receive pin enable.This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only." "0,1" line.long 0x4 "LIN2_Reserved_2,tbd" group.long 0xE0++0x3 line.long 0x0 "LIN2_LIN_GLB_INT_EN,The LIN_GLB_INT_EN register is used to enable the INT0 and INT1 interrupt lines to propagate to the PIE block." bitfld.long 0x0 1. "GLBINT1_EN,Global Interrupt Enable for LIN INT1.This bit determines whether the INT1 interrupt line generates an interrupt to the PIE or not" "0,1" bitfld.long 0x0 0. "GLBINT0_EN,Global Interrupt Enable for LIN INT0.This bit determines whether the INT0 interrupt line generates an interrupt to the PIE or not." "0,1" rgroup.long 0xE4++0x3 line.long 0x0 "LIN2_LIN_GLB_INT_FLG,The LIN_GLB_INT_FLG register contains the current status of the INT0 and INT1 flags." bitfld.long 0x0 1. "INT1_FLG,Global Interrupt Flag for LIN INT1.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT1 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" bitfld.long 0x0 0. "INT0_FLG,Global Interrupt Flag for LIN INT0.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT0 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" group.long 0xE8++0x3 line.long 0x0 "LIN2_LIN_GLB_INT_CLR,The LIN_GLB_INT_CLR register is used to clear the interrupt flags in LIN_GLB_INT_FLG register." bitfld.long 0x0 1. "INT1_FLG_CLR,Global Interrupt flag clear for LIN INT1.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT1_FLG bit. Writing 0 has no effect." "0,1" bitfld.long 0x0 0. "INT0_FLG_CLR,Global Interrupt flag clear for LIN INT0.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT0_FLG bit. Writing 0 has no effect." "0,1" tree.end tree "LIN3" base ad:0x52403000 group.long 0x0++0x1F line.long 0x0 "LIN3_SCIGCR0,The SCIGCR0 register defines the module reset." bitfld.long 0x0 0. "RESET,This bit resets the SCI/LIN module. This bit is effective in LIN or SCI-compatible mode.. This bit affects the reset state of the SCI/LIN module." "0,1" line.long 0x4 "LIN3_SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI." bitfld.long 0x4 25. "TXENA,Transmit enable.This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy [with y=0 1 ...7] buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the.." "0,1" bitfld.long 0x4 24. "RXENA,Receive enable.This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the.." "0,1" bitfld.long 0x4 17. "CONT,Continue on suspend.This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set the counters are.." "0,1" newline bitfld.long 0x4 16. "LOOPBACK,Loopback bit.This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality then the LINTX pin is internally.." "0,1" bitfld.long 0x4 13. "STOPEXTFRAME,Stop extended frame communication.This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped this bit is cleared automatically." "0,1" bitfld.long 0x4 12. "HGENCTRL,HGEN control bit.This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison." "0,1" newline bitfld.long 0x4 11. "CTYPE,Checksum type.This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced." "0,1" bitfld.long 0x4 10. "MBUFMODE,Multibuffer mode.This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage that is whether the RX/TX multibuffers are used or a single register RD0/TD0 is used." "0,1" bitfld.long 0x4 9. "ADAPT,Adapt mode enable.This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file.." "0,1" newline bitfld.long 0x4 8. "SLEEP,SCI sleep.SCI compatibility mode only. In a multiprocessor configuration this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however RXRDY is.." "0,1" bitfld.long 0x4 7. "SWNRST,Software reset [active low].This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime [i.e. while SWnRESET = 1]:- STOP EXT Frame.." "0,1" bitfld.long 0x4 6. "LINMODE,LIN modeThis bit controls the mode of operation of the module." "0,1" newline bitfld.long 0x4 5. "CLK_MASTER,SCI internal clock enable or LIN Master/Slave configuration.In the SCI mode this bit enables the clock to the SCI module. In LIN mode this bit determines whether a LIN node is a slave or master." "0,1" bitfld.long 0x4 4. "STOP,SCI number of stop bits.This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode the receiver waits until the end of the second stop bit [if STOP = 1] to begin checking for an.." "0,1" bitfld.long 0x4 3. "PARITY,SCI parity odd/even selection.This bit is effective in SCI-compatible mode only. If the PARITY ENA bit [SCIGCR1.2] is set PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit.." "0,1" newline bitfld.long 0x4 2. "PARITYENA,Parity enable.Enables or disables the parity function." "0,1" bitfld.long 0x4 1. "TIMINGMODE,SCI timing mode bit.This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation." "0,1" bitfld.long 0x4 0. "COMMMODE,SCI/LIN communication mode bit.In compatibility mode it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5." "0,1" line.long 0x8 "LIN3_SCIGCR2,The SCIGCR2 register is used to send or compare a checksum byte during extended frames. to generate a wakeup and for low-power mode control of the LIN module." bitfld.long 0x8 17. "CC,Compare Checksum.This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by writing a one to this bit.In non multibuffer mode once the CC bit.." "0,1" bitfld.long 0x8 16. "SC,Send ChecksumThis mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the.." "0,1" bitfld.long 0x8 8. "GENWU,Generate wakeup signal.This bit controls the generation of a wakeup signal by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break." "0,1" newline bitfld.long 0x8 0. "POWERDOWN,Power down.This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup.." "0,1" line.long 0xC "LIN3_SCISETINT,The SCISETINT register is used to enable the various interrupts available in the LIN module." bitfld.long 0xC 31. "SETBEINT,Set bit error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 30. "SETPBEINT,Set physical bus error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 29. "SETCEINT,Set checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only." "0,1" newline bitfld.long 0xC 28. "SETISFEINT,Set inconsistent-sync-field-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 27. "SETNREINT,Set no-response-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 26. "SETFEINT,Set framing-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs." "0,1" newline bitfld.long 0xC 25. "SETOEINT,Set overrun-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs." "0,1" bitfld.long 0xC 24. "SETPEINT,Set parity interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs." "0,1" bitfld.long 0xC 18. "SET_RX_DMA_ALL,Set receiver DMA for Address & Data frames.This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared RX interrupt request is generated for address.." "0,1" newline bitfld.long 0xC 17. "SET_RX_DMA,Set receiver DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared interrupt requests are generated depending on SETRXINT." "0,1" bitfld.long 0xC 16. "SET_TX_DMA,Set transmit DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter this bit must be set. If it is cleared interrupt requests are generated depending on SETTXINT." "0,1" bitfld.long 0xC 13. "SETIDINT,Set Identification interrupt.This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received." "0,1" newline bitfld.long 0xC 9. "SETRXINT,Set Receiver interrupt.Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD." "0,1" bitfld.long 0xC 8. "SETTXINT,Set Transmitter interrupt.Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set." "0,1" bitfld.long 0xC 7. "SETTOA3WUSINT,Set Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN.." "0,1" newline bitfld.long 0xC 6. "SETTOAWUSINT,Set Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode.." "0,1" bitfld.long 0xC 4. "SETTIMEOUTINT,Set timeout interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity [bus idle] occurs for at least 4 seconds. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 1. "SETWAKEUPINT,Set wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up.." "0,1" newline bitfld.long 0xC 0. "SETBRKDTINT,Set break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only." "0,1" line.long 0x10 "LIN3_SCICLEARINT,The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register." bitfld.long 0x10 31. "CLRBEINT,Clear Bit Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 30. "CLRPBEINT,Clear Physical Bus Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 29. "CLRCEINT,Clear checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x10 28. "CLRISFEINT,Clear Inconsistent-Sync-Field-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 27. "CLRNREINT,Clear No-Reponse-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 26. "CLRFEINT,Clear Framing-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt." "0,1" newline bitfld.long 0x10 25. "CLROEINT,Clear Overrun-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt." "0,1" bitfld.long 0x10 24. "CLRPEINT,Clear Parity Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt." "0,1" bitfld.long 0x10 17. "SETRXDMA,Clear receiver DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request." "0,1" newline bitfld.long 0x10 16. "CLRTXDMA,Clear transmit DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request." "0,1" bitfld.long 0x10 13. "CLRIDINT,Clear Identifier interrupt.This bit is effective in LIN mode only. Setting this bit disables the ID interrupt." "0,1" bitfld.long 0x10 9. "CLRRXINT,Clear Receiver interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt." "0,1" newline bitfld.long 0x10 8. "CLRTXINT,Clear Transmitter interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt." "0,1" bitfld.long 0x10 7. "CLRTOA3WUSINT,Clear Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 6. "CLRTOAWUSINT,Clear Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x10 4. "CLRTIMEOUTINT,Clear Timeout interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout [LIN bus idle] interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 1. "CLRWAKEUPINT,Clear Wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt." "0,1" bitfld.long 0x10 0. "CLRBRKDTINT,Clear Break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only." "0,1" line.long 0x14 "LIN3_SCISETINTLVL,The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line." bitfld.long 0x14 31. "SETBEINTLVL,Set Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 30. "SETPBEINTLVL,Set Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 29. "SETCEINTLVL,Set Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x14 28. "SETISFEINTLVL,Set Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 27. "SETNREINTLVL,Set No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 26. "SETFEINTLVL,Set Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line." "0,1" newline bitfld.long 0x14 25. "SETOEINTLVL,Set Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line." "0,1" bitfld.long 0x14 24. "SETPEINTLVL,Set Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line." "0,1" bitfld.long 0x14 13. "SETIDINTLVL,Set ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x14 9. "SETRXINTOVO,Set Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line." "0,1" bitfld.long 0x14 8. "SETTXINTLVL,Set Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line." "0,1" bitfld.long 0x14 7. "SETTOA3WUSINTLVL,Set Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x14 6. "SETTOAWUSINTLVL,Set Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 4. "SETTIMEOUTINTLVL,Set Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 1. "SETWAKEUPINTLVL,Set Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line." "0,1" newline bitfld.long 0x14 0. "SETBRKDTINTLVL,Set Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only." "0,1" line.long 0x18 "LIN3_SCICLEARINTLVL,The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line." bitfld.long 0x18 31. "CLRBEINTLVL,Clear Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 30. "CLRPBEINTLVL,Clear Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 29. "CLRCEINTLVL,Clear Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x18 28. "CLRISFEINTLVL,Clear Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 27. "CLRNREINTLVL,Clear No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 26. "CLRFEINTLVL,Clear Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line." "0,1" newline bitfld.long 0x18 25. "CLROEINTLVL,Clear Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line." "0,1" bitfld.long 0x18 24. "CLRPEINTLVL,Clear Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line." "0,1" bitfld.long 0x18 13. "CLRIDINTLVL,Clear ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x18 9. "CLRRXINTLVL,Clear Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line." "0,1" bitfld.long 0x18 8. "CLRTXINTLVL,Clear Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line." "0,1" bitfld.long 0x18 7. "CLRTOA3WUSINTLVL,Clear Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x18 6. "CLRTOAWUSINTLVL,Clear Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 4. "CLRTIMEOUTINTLVL,Clear Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 1. "CLRWAKEUPINTLVL,Clear Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line." "0,1" newline bitfld.long 0x18 0. "CLRBRKDTINTLVL,Clear Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only." "0,1" line.long 0x1C "LIN3_SCIFLR,The SCIFLR register indicates the current status of the various interrupt sources of the LIN module." bitfld.long 0x1C 31. "BE,Bit Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 30. "PBE,Physical Bus Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 29. "CE,Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by:- Reading the.." "0,1" newline bitfld.long 0x1C 28. "ISFE,Inconsistent Sync Field Error Flag.This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the Header Reception and Adaptive Baudrate.." "0,1" bitfld.long 0x1C 27. "NRE,No-Response Error Flag.This bit is effective in LIN mode only. This bit is set when there is no response to a master's header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length [identifiers 0 to 61]. This.." "0,1" bitfld.long 0x1C 26. "FE,Framing error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode only the first stop bit is checked. The missing stop bit indicates that synchronization with the.." "0,1" newline bitfld.long 0x1C 25. "OE,Overrun error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to.." "0,1" bitfld.long 0x1C 24. "PE,Parity error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode the parity is calculated on the data and address bit fields of the received frame. In.." "?,?" bitfld.long 0x1C 14. "IDRXFLAG,Identifier On Receive Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the Message Filtering and Validation section for more details. When this flag is set.." "0,1" newline bitfld.long 0x1C 13. "IDTXFLAG,Identifier On Transmit Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the Message Filtering and Validation section for more details. When this flag is set.." "0,1" rbitfld.long 0x1C 12. "RXWAKE,Receiver wakeup detect flag.This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by:- RESET bit- Setting the SWnRESET bit [SCIGCR1.7]- System.." "0,1" rbitfld.long 0x1C 11. "TXEMPTY,Transmitter Empty flag.The value of this flag indicates the contents of the transmitter's buffer register[s] [SCITD/TDy] and shift register [SCITXSHF]. In multibuffer mode this flag indicates the value of the TDx registers and shift register.." "0,1" newline bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wakeup method select.This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or.." "0,1" bitfld.long 0x1C 9. "RXRDY,Receiver ready flag. In SCI compatibility mode the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode RXRDY is set once a valid frame is received in multibuffer mode a valid frame.." "0,1" rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag.When set this bit indicates that the transmit buffer[s] register [SCITD in compatibility mode and LINTD0 LINTD1 in MBUF mode] is/are ready to get another character from a CPU write. In SCI compatibility.." "0,1" newline bitfld.long 0x1C 7. "TOA3WUS,Timeout After 3 Wakeup Signals flag.This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another.." "0,1" bitfld.long 0x1C 6. "TOAWUS,Timeout After Wakeup Signal flag.This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal." "0,1" bitfld.long 0x1C 4. "TIMEOUT,LIN Bus IDLE timeout flag.This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by:- Reading the.." "0,1" newline rbitfld.long 0x1C 3. "BUSY,Bus BUSY flag.This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit the BUSY bit is set to 1. When the.." "0,1" rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state.This bit is effective in SCI-compatible mode only. While this bit is set the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus.." "0,1" bitfld.long 0x1C 1. "WAKEUP,Wake-up flag.This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit [SCISETINT.1] is set. This.." "0,1" newline bitfld.long 0x1C 0. "BRKDT,SCI break-detect flag.This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a.." "0,1" rgroup.long 0x20++0x7 line.long 0x0 "LIN3_SCIINTVECT0,The SCIINTVECT0 register indicates the offset for the INT0 interrupt line." hexmask.long.byte 0x0 0.--4. 1. "INTVECT0,Interrupt vector offset for INT0.This register indicates the offset for interrupt line INT0. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." line.long 0x4 "LIN3_SCIINTVECT1,The SCIINTVECT1 register indicates the offset for the INT1 interrupt line." hexmask.long.byte 0x4 0.--4. 1. "INTVECT1,Interrupt vector offset for INT1.This register indicates the offset for interrupt line INT1. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." group.long 0x28++0x7 line.long 0x0 "LIN3_SCIFORMAT,The SCIFORMAT register is used to set up the character and frame lengths." bitfld.long 0x0 16.--18. "LENGTH,Frame length control bits.In LIN mode these bits indicate the number of bytes in the response field from 1 to 8 bytes. In buffered SCI mode these bits indicate the number of characters. When these bits are used to indicate LIN response length.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "CHAR,Character length control bits.These bits are effective in SCI compatible mode only. These bits set the SCI character length from 1 to 8 bits. Note: In compatibility mode or buffered SCI mode when data of fewer than eight bits in length is received .." "0,1,2,3,4,5,6,7" line.long 0x4 "LIN3_BRSR,The BRSR register is used to configure the baud rate of the LIN module." bitfld.long 0x4 28.--30. "U,Superfractional Divider Selection. [U]These bits are an additional fractional part for the baudrate specification. These bits allow a super fine tuning of the fractional baudrate with 7 more intermediate values for each of the M fractional divider.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--27. 1. "M,SCI/LIN 4-bit Fractional Divider Selection. [M]These bits are effective in LIN or SCI asynchronous mode. These bits are used to select a baud rate for the SCI/LIN module and they are a fractional part for the baud rate specification. The M divider.." hexmask.long.byte 0x4 16.--23. 1. "SCI_LIN_PSH,PRESCALER P [High Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." newline hexmask.long.word 0x4 0.--15. 1. "SCI_LIN_PSL,PRESCALER P [Low Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." rgroup.long 0x30++0x7 line.long 0x0 "LIN3_SCIED,The SCIED register is a duplicate copy of SCIRD register that has no affect on the RXRDY flag for use with an emulator." hexmask.long.byte 0x0 0.--7. 1. "ED,Receiver Emulation Data.This bit is effective in SCI-compatible mode only. Reading SCIED[7-0] does not clear the RXRDY flag. This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag." line.long 0x4 "LIN3_SCIRD,The SCIRD register is where received data is stored and can be read from." hexmask.long.byte 0x4 0.--7. 1. "RD,Received Data.This bit is effective in SCI-compatible mode only. When a frame has been completely received the data in the frame is transferred from the receiver shift register SCIRXSHF to this register. As this transfer occurs the RXRDY flag is set.." group.long 0x38++0xB line.long 0x0 "LIN3_SCITD,The SCITD register is where data to be transmitted is written to by application software." hexmask.long.byte 0x0 0.--7. 1. "TD,Transmit dataThis bit is effective in SCI-compatible mode only. Data to be transmitted is written to this register. The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag [SCIFLR.23] which indicates that.." line.long 0x4 "LIN3_SCIPIO0,The SCIPIO0 register is used to enable the LINTX and LINRX pins." bitfld.long 0x4 2. "TXFUNC,Transmit pin function.This bit is effective in LIN or SCI mode. This bit defines the function of LINTX pin." "0,1" bitfld.long 0x4 1. "RXFUNC,Receive pin function.This bit is effective in LIN or SCI mode. This bit defines the function of the LINRX pin." "0,1" line.long 0x8 "LIN3_SCIPIO1,Pin control Register 1" bitfld.long 0x8 2. "TXDIR,Transmit pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINTX pin if it is configured with general-purpose I/O functionality [TX FUNC = 0]. 0: general purpose input pin. 1: general-purpose.." "0: general purpose input pin,1: general-purpose output pin" bitfld.long 0x8 1. "RXDIR,Receive pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINRX pin if it is configured with general-purpose I/O functionality [RX FUNC = 0]. 0: general purpose input pin. 1: general-purpose.." "0: general purpose input pin,1: general-purpose output pin" rgroup.long 0x44++0x3 line.long 0x0 "LIN3_SCIPIO2,The SCIPIO2 register indicates the current status of the LINTX and LINRX pins." bitfld.long 0x0 2. "TXIN,Transmit data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINTX pin." "0,1" bitfld.long 0x0 1. "RXIN,Receive data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINRX pin." "0,1" group.long 0x48++0x1B line.long 0x0 "LIN3_SCIPIO3,Pin control Register 3" bitfld.long 0x0 2. "TXOUT,Transmit pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINTX." "0,1" bitfld.long 0x0 1. "RXOUT,Receive pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINRX." "0,1" line.long 0x4 "LIN3_SCIPIO4,Pin control Register 4" bitfld.long 0x4 2. "TXSET,Transmit pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX." "0,1" bitfld.long 0x4 1. "RXSET,Receive pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX." "0,1" line.long 0x8 "LIN3_SCIPIO5,Pin control Register 5" bitfld.long 0x8 2. "TXCLR,Transmit pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINTX." "0,1" bitfld.long 0x8 1. "RXCLR,Receive pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINRX." "0,1" line.long 0xC "LIN3_SCIPIO6,Pin control Register 6" bitfld.long 0xC 2. "TXPDR,Transmit pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINTX." "0,1" bitfld.long 0xC 1. "RXPDR,Receive pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINRX." "0,1" line.long 0x10 "LIN3_SCIPIO7,Pin control Register 7" bitfld.long 0x10 2. "TXPD,Transmit pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINTX." "0,1" bitfld.long 0x10 1. "RXPD,Receive pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINRX." "0,1" line.long 0x14 "LIN3_SCIPIO8,Pin control Register 8" bitfld.long 0x14 2. "TXPSL,TX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINTX." "0,1" bitfld.long 0x14 1. "RXPSL,RX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINRX." "0,1" line.long 0x18 "LIN3_LINCOMP,The LINCOMPARE register is used to configure the sync delimeter and sync break extension." bitfld.long 0x18 8.--9. "SDEL,2-bit Sync Delimiter compare.These bits are effective in LIN mode only. These bits are used to configure the number of Tbit for the sync delimiter in the sync field.The time delay calculation for the synchronization delimiter is:TSDEL = [SDEL +.." "0,1,2,3" bitfld.long 0x18 0.--2. "SBREAK,3-bit Sync Break extend.LIN mode only. These bits are used to configure the number of Tbits for the sync break to extend the minimum 13 Tbit in the Sync Field to a maximum of 20 Tbit.The time delay calculation for the sync break is:TSYNBRK =.." "0,1,2,3,4,5,6,7" rgroup.long 0x64++0x7 line.long 0x0 "LIN3_LINRD0,The LINRD0 register contains the lower 4 bytes of the received LIN frame data." hexmask.long.byte 0x0 24.--31. 1. "RD0,8-bit Receive Buffer 0Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received.A read of this byte clears the RXDY byte.Note: RD<x-1> is.." hexmask.long.byte 0x0 16.--23. 1. "RD1,8-bit Receive Buffer 1.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x0 8.--15. 1. "RD2,8-bit Receive Buffer 2.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x0 0.--7. 1. "RD3,8-bit Receive Buffer 3.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." line.long 0x4 "LIN3_LINRD1,The LINRD1 regsiter contains the upper 4 bytes of the received LIN frame data." hexmask.long.byte 0x4 24.--31. 1. "RD4,8-bit Receive Buffer 4 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 16.--23. 1. "RD5,8-bit Receive Buffer 5.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 8.--15. 1. "RD6,8-bit Receive Buffer 6.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x4 0.--7. 1. "RD7,8-bit Receive Buffer 7.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." group.long 0x6C++0x17 line.long 0x0 "LIN3_LINMASK,The LINMASK register is used to configure the masks used for filtering incoming ID messages for receive and transmit frames." hexmask.long.byte 0x0 16.--23. 1. "RXIDMASK,Receive ID mask.This field is effective in LIN mode only.This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID witht the RX ID mask will set the ID RX flag and trigger and.." hexmask.long.byte 0x0 0.--7. 1. "TXIDMASK,Transmit ID mask.This field is effective in LIN mode only. This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID with the TX ID Mask will set the ID TX flag and trigger an.." line.long 0x4 "LIN3_LINID,The LINID register contains the identification fields for LIN communication.[[br]]NOTE: For software compatibility with future LIN modules. the HGEN CTRL bit must be set to 1. the RX ID MASK field must be set to FFh. and the TX ID MASK field.." hexmask.long.byte 0x4 16.--23. 1. "RECEIVEDID,Received ID.This bit is effective in LIN mode only. This byte contains the current message identifier. During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID-parity error and there has been.." hexmask.long.byte 0x4 8.--15. 1. "IDSLAVETASKBYTE,ID Slave Task byte.This field is effective in LIN mode only. This byte contains the identifier to which the received ID of an incoming header will be compared in order to decide whether a RX response a TX response or no action needs to.." hexmask.long.byte 0x4 0.--7. 1. "IDBYTE,ID byte.This field is effective in LIN mode only. This byte is the LIN mode message ID. On a master node a write to this register by the CPU initiates a header transmission. For a slave task this byte is used for message filtering when HGENCTRL.." line.long 0x8 "LIN3_LINTD0,The LINTD0 register contains the lower 4 bytes of the data to be transmitted.[[br]]NOTE: TD<x-1> is equivalent to Data byte <x> of the LIN frame." hexmask.long.byte 0x8 24.--31. 1. "TD0,8-bit Transmit Buffer 0.Byte 0 to be transmitted is written into this register and then copied to SCITXSHF for transmission. Once byte 0 is written in TDO buffer transmission will be initiated." hexmask.long.byte 0x8 16.--23. 1. "TD1,8-bit Transmit Buffer 3.Byte 1 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0x8 8.--15. 1. "TD2,8-bit Transmit Buffer 2.Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0x8 0.--7. 1. "TD3,8-bit Transmit Buffer 3.Byte 3 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0xC "LIN3_LINTD1,The LINTD1 register contains the upper 4 bytes of the data to be transmitted.[[br]]NOTE: TD<x-1> is equivalent to Data byte <x> of the LIN frame." hexmask.long.byte 0xC 24.--31. 1. "TD4,8-bit Transmit Buffer 4.Byte4 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 16.--23. 1. "TD5,8-bit Transmit Buffer 5.Byte 5 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 8.--15. 1. "TD6,8-bit Transmit Buffer 6.Byte 6 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0xC 0.--7. 1. "TD7,8-bit Transmit Buffer 7.Byte 7 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0x10 "LIN3_MBRSR,The MBRSR register is used to configure the expected maximum baud rate of the LIN network." hexmask.long.word 0x10 0.--12. 1. "MBR,Maximum Baud Rate Prescaler.This field is effective in LIN mode only. This 13-bit prescaler is used during the synchronization phase [see the Header Reception and Adaptive Baudrate section] of a slave module if the ADAPT bit is set. In this way a.." line.long 0x14 "LIN3_Reserved_1,tbd" group.long 0x90++0x7 line.long 0x0 "LIN3_IODFTCTRL,The IODFTCTRL register is used to emulate various error and test conditions." bitfld.long 0x0 31. "BERRENA,Bit Errror Enable bit.This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set the bit received is ORed with 1 and passed to the Bit monitor circuitry." "0,1" bitfld.long 0x0 30. "PBERRENA,Physical Bus Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor.." "0,1" bitfld.long 0x0 29. "CERRENA,Checksum Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set the polarity of the CTYPE [checksum type] in the receive checksum calculator is changed so that a checksum error.." "0,1" newline bitfld.long 0x0 28. "ISFERRENA,Inconsistent Sync Field Error Enable bit.This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set the bit widths in the sync field are varied so that the ISF check fails and the error flag is set." "0,1" bitfld.long 0x0 26. "FERRENA,This bit is used to create a Frame Error.This bit is effective in SCI-compatible mode only. When this bit is set the stop bit received is ANDed with '0' and passed to the stop bit check circuitry." "0,1" bitfld.long 0x0 25. "PERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set in compatible mode the parity bit received is toggled so that a parity error occurs." "0,1" newline bitfld.long 0x0 24. "BRKDTERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error [SCI mode only]. When this bit is set the stop bit of the frame is ANDed with '0' and passed to the RSM so that a frame error.." "0,1" bitfld.long 0x0 19.--20. "PINSAMPLEMASK,Pin sample mask.These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry.Note: During IODFT mode testing for.." "0,1,2,3" bitfld.long 0x0 16.--18. "TXSHIFT,Transmit shift.These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. [Not applicable to Start Bit]" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "IODFTENA,IO DFT Enable KeyThis field is used to enable the IODFT mode of the SCI/LIN module for testing." bitfld.long 0x0 1. "LPBENA,Module loopback enable.In analog loopback mode the complete communication path through the I/Os can be tested whereas in digital loopback mode the I/O buffers are excluded from this path." "0,1" bitfld.long 0x0 0. "RXPENA,Module Analog loopback through receive pin enable.This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only." "0,1" line.long 0x4 "LIN3_Reserved_2,tbd" group.long 0xE0++0x3 line.long 0x0 "LIN3_LIN_GLB_INT_EN,The LIN_GLB_INT_EN register is used to enable the INT0 and INT1 interrupt lines to propagate to the PIE block." bitfld.long 0x0 1. "GLBINT1_EN,Global Interrupt Enable for LIN INT1.This bit determines whether the INT1 interrupt line generates an interrupt to the PIE or not" "0,1" bitfld.long 0x0 0. "GLBINT0_EN,Global Interrupt Enable for LIN INT0.This bit determines whether the INT0 interrupt line generates an interrupt to the PIE or not." "0,1" rgroup.long 0xE4++0x3 line.long 0x0 "LIN3_LIN_GLB_INT_FLG,The LIN_GLB_INT_FLG register contains the current status of the INT0 and INT1 flags." bitfld.long 0x0 1. "INT1_FLG,Global Interrupt Flag for LIN INT1.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT1 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" bitfld.long 0x0 0. "INT0_FLG,Global Interrupt Flag for LIN INT0.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT0 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" group.long 0xE8++0x3 line.long 0x0 "LIN3_LIN_GLB_INT_CLR,The LIN_GLB_INT_CLR register is used to clear the interrupt flags in LIN_GLB_INT_FLG register." bitfld.long 0x0 1. "INT1_FLG_CLR,Global Interrupt flag clear for LIN INT1.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT1_FLG bit. Writing 0 has no effect." "0,1" bitfld.long 0x0 0. "INT0_FLG_CLR,Global Interrupt flag clear for LIN INT0.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT0_FLG bit. Writing 0 has no effect." "0,1" tree.end tree "LIN4" base ad:0x52404000 group.long 0x0++0x1F line.long 0x0 "LIN4_SCIGCR0,The SCIGCR0 register defines the module reset." bitfld.long 0x0 0. "RESET,This bit resets the SCI/LIN module. This bit is effective in LIN or SCI-compatible mode.. This bit affects the reset state of the SCI/LIN module." "0,1" line.long 0x4 "LIN4_SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI." bitfld.long 0x4 25. "TXENA,Transmit enable.This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy [with y=0 1 ...7] buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the.." "0,1" bitfld.long 0x4 24. "RXENA,Receive enable.This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the.." "0,1" bitfld.long 0x4 17. "CONT,Continue on suspend.This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set the counters are.." "0,1" newline bitfld.long 0x4 16. "LOOPBACK,Loopback bit.This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality then the LINTX pin is internally.." "0,1" bitfld.long 0x4 13. "STOPEXTFRAME,Stop extended frame communication.This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped this bit is cleared automatically." "0,1" bitfld.long 0x4 12. "HGENCTRL,HGEN control bit.This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison." "0,1" newline bitfld.long 0x4 11. "CTYPE,Checksum type.This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced." "0,1" bitfld.long 0x4 10. "MBUFMODE,Multibuffer mode.This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage that is whether the RX/TX multibuffers are used or a single register RD0/TD0 is used." "0,1" bitfld.long 0x4 9. "ADAPT,Adapt mode enable.This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file.." "0,1" newline bitfld.long 0x4 8. "SLEEP,SCI sleep.SCI compatibility mode only. In a multiprocessor configuration this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however RXRDY is.." "0,1" bitfld.long 0x4 7. "SWNRST,Software reset [active low].This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime [i.e. while SWnRESET = 1]:- STOP EXT Frame.." "0,1" bitfld.long 0x4 6. "LINMODE,LIN modeThis bit controls the mode of operation of the module." "0,1" newline bitfld.long 0x4 5. "CLK_MASTER,SCI internal clock enable or LIN Master/Slave configuration.In the SCI mode this bit enables the clock to the SCI module. In LIN mode this bit determines whether a LIN node is a slave or master." "0,1" bitfld.long 0x4 4. "STOP,SCI number of stop bits.This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode the receiver waits until the end of the second stop bit [if STOP = 1] to begin checking for an.." "0,1" bitfld.long 0x4 3. "PARITY,SCI parity odd/even selection.This bit is effective in SCI-compatible mode only. If the PARITY ENA bit [SCIGCR1.2] is set PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit.." "0,1" newline bitfld.long 0x4 2. "PARITYENA,Parity enable.Enables or disables the parity function." "0,1" bitfld.long 0x4 1. "TIMINGMODE,SCI timing mode bit.This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation." "0,1" bitfld.long 0x4 0. "COMMMODE,SCI/LIN communication mode bit.In compatibility mode it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5." "0,1" line.long 0x8 "LIN4_SCIGCR2,The SCIGCR2 register is used to send or compare a checksum byte during extended frames. to generate a wakeup and for low-power mode control of the LIN module." bitfld.long 0x8 17. "CC,Compare Checksum.This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by writing a one to this bit.In non multibuffer mode once the CC bit.." "0,1" bitfld.long 0x8 16. "SC,Send ChecksumThis mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the.." "0,1" bitfld.long 0x8 8. "GENWU,Generate wakeup signal.This bit controls the generation of a wakeup signal by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break." "0,1" newline bitfld.long 0x8 0. "POWERDOWN,Power down.This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup.." "0,1" line.long 0xC "LIN4_SCISETINT,The SCISETINT register is used to enable the various interrupts available in the LIN module." bitfld.long 0xC 31. "SETBEINT,Set bit error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 30. "SETPBEINT,Set physical bus error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 29. "SETCEINT,Set checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only." "0,1" newline bitfld.long 0xC 28. "SETISFEINT,Set inconsistent-sync-field-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 27. "SETNREINT,Set no-response-error interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 26. "SETFEINT,Set framing-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs." "0,1" newline bitfld.long 0xC 25. "SETOEINT,Set overrun-error interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs." "0,1" bitfld.long 0xC 24. "SETPEINT,Set parity interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs." "0,1" bitfld.long 0xC 18. "SET_RX_DMA_ALL,Set receiver DMA for Address & Data frames.This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared RX interrupt request is generated for address.." "0,1" newline bitfld.long 0xC 17. "SET_RX_DMA,Set receiver DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared interrupt requests are generated depending on SETRXINT." "0,1" bitfld.long 0xC 16. "SET_TX_DMA,Set transmit DMA.This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter this bit must be set. If it is cleared interrupt requests are generated depending on SETTXINT." "0,1" bitfld.long 0xC 13. "SETIDINT,Set Identification interrupt.This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received." "0,1" newline bitfld.long 0xC 9. "SETRXINT,Set Receiver interrupt.Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD." "0,1" bitfld.long 0xC 8. "SETTXINT,Set Transmitter interrupt.Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set." "0,1" bitfld.long 0xC 7. "SETTOA3WUSINT,Set Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN.." "0,1" newline bitfld.long 0xC 6. "SETTOAWUSINT,Set Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode.." "0,1" bitfld.long 0xC 4. "SETTIMEOUTINT,Set timeout interrupt.This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity [bus idle] occurs for at least 4 seconds. This field is writable in LIN mode only." "0,1" bitfld.long 0xC 1. "SETWAKEUPINT,Set wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up.." "0,1" newline bitfld.long 0xC 0. "SETBRKDTINT,Set break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only." "0,1" line.long 0x10 "LIN4_SCICLEARINT,The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register." bitfld.long 0x10 31. "CLRBEINT,Clear Bit Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 30. "CLRPBEINT,Clear Physical Bus Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 29. "CLRCEINT,Clear checksum-error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x10 28. "CLRISFEINT,Clear Inconsistent-Sync-Field-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 27. "CLRNREINT,Clear No-Reponse-Error Interrupt.This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 26. "CLRFEINT,Clear Framing-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt." "0,1" newline bitfld.long 0x10 25. "CLROEINT,Clear Overrun-Error Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt." "0,1" bitfld.long 0x10 24. "CLRPEINT,Clear Parity Interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt." "0,1" bitfld.long 0x10 17. "SETRXDMA,Clear receiver DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request." "0,1" newline bitfld.long 0x10 16. "CLRTXDMA,Clear transmit DMA.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request." "0,1" bitfld.long 0x10 13. "CLRIDINT,Clear Identifier interrupt.This bit is effective in LIN mode only. Setting this bit disables the ID interrupt." "0,1" bitfld.long 0x10 9. "CLRRXINT,Clear Receiver interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt." "0,1" newline bitfld.long 0x10 8. "CLRTXINT,Clear Transmitter interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt." "0,1" bitfld.long 0x10 7. "CLRTOA3WUSINT,Clear Timeout After 3 Wakeup Signals interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 6. "CLRTOAWUSINT,Clear Timeout After Wakeup Signal interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x10 4. "CLRTIMEOUTINT,Clear Timeout interrupt.This bit is effective in LIN mode only. Setting this bit disables the timeout [LIN bus idle] interrupt. This field is writable in LIN mode only." "0,1" bitfld.long 0x10 1. "CLRWAKEUPINT,Clear Wake-up interrupt.This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt." "0,1" bitfld.long 0x10 0. "CLRBRKDTINT,Clear Break-detect interrupt.This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only." "0,1" line.long 0x14 "LIN4_SCISETINTLVL,The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line." bitfld.long 0x14 31. "SETBEINTLVL,Set Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 30. "SETPBEINTLVL,Set Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 29. "SETCEINTLVL,Set Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x14 28. "SETISFEINTLVL,Set Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 27. "SETNREINTLVL,Set No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 26. "SETFEINTLVL,Set Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line." "0,1" newline bitfld.long 0x14 25. "SETOEINTLVL,Set Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line." "0,1" bitfld.long 0x14 24. "SETPEINTLVL,Set Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line." "0,1" bitfld.long 0x14 13. "SETIDINTLVL,Set ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x14 9. "SETRXINTOVO,Set Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line." "0,1" bitfld.long 0x14 8. "SETTXINTLVL,Set Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line." "0,1" bitfld.long 0x14 7. "SETTOA3WUSINTLVL,Set Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x14 6. "SETTOAWUSINTLVL,Set Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 4. "SETTIMEOUTINTLVL,Set Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x14 1. "SETWAKEUPINTLVL,Set Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line." "0,1" newline bitfld.long 0x14 0. "SETBRKDTINTLVL,Set Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only." "0,1" line.long 0x18 "LIN4_SCICLEARINTLVL,The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line." bitfld.long 0x18 31. "CLRBEINTLVL,Clear Bit Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 30. "CLRPBEINTLVL,Clear Physical Bus Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 29. "CLRCEINTLVL,Clear Checksum-error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x18 28. "CLRISFEINTLVL,Clear Inconsistent-Sync-Field-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 27. "CLRNREINTLVL,Clear No-Reponse-Error interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 26. "CLRFEINTLVL,Clear Framing-Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line." "0,1" newline bitfld.long 0x18 25. "CLROEINTLVL,Clear Overrun-Error Interrupt Level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line." "0,1" bitfld.long 0x18 24. "CLRPEINTLVL,Clear Parity Error interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line." "0,1" bitfld.long 0x18 13. "CLRIDINTLVL,Clear ID interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x18 9. "CLRRXINTLVL,Clear Receiver interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line." "0,1" bitfld.long 0x18 8. "CLRTXINTLVL,Clear Transmitter interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line." "0,1" bitfld.long 0x18 7. "CLRTOA3WUSINTLVL,Clear Timeout After 3 Wakeup Signals interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" newline bitfld.long 0x18 6. "CLRTOAWUSINTLVL,Clear Timeout After Wakeup Signal interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 4. "CLRTIMEOUTINTLVL,Clear Timeout interrupt level.This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only." "0,1" bitfld.long 0x18 1. "CLRWAKEUPINTLVL,Clear Wake-up interrupt level.This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line." "0,1" newline bitfld.long 0x18 0. "CLRBRKDTINTLVL,Clear Break-detect interrupt level.This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only." "0,1" line.long 0x1C "LIN4_SCIFLR,The SCIFLR register indicates the current status of the various interrupt sources of the LIN module." bitfld.long 0x1C 31. "BE,Bit Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 30. "PBE,Physical Bus Error Flag.This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by:- Reading the corresponding interrupt offset in the.." "0,1" bitfld.long 0x1C 29. "CE,Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by:- Reading the.." "0,1" newline bitfld.long 0x1C 28. "ISFE,Inconsistent Sync Field Error Flag.This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the Header Reception and Adaptive Baudrate.." "0,1" bitfld.long 0x1C 27. "NRE,No-Response Error Flag.This bit is effective in LIN mode only. This bit is set when there is no response to a master's header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length [identifiers 0 to 61]. This.." "0,1" bitfld.long 0x1C 26. "FE,Framing error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode only the first stop bit is checked. The missing stop bit indicates that synchronization with the.." "0,1" newline bitfld.long 0x1C 25. "OE,Overrun error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to.." "0,1" bitfld.long 0x1C 24. "PE,Parity error flag.This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode the parity is calculated on the data and address bit fields of the received frame. In.." "?,?" bitfld.long 0x1C 14. "IDRXFLAG,Identifier On Receive Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the Message Filtering and Validation section for more details. When this flag is set.." "0,1" newline bitfld.long 0x1C 13. "IDTXFLAG,Identifier On Transmit Flag.This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the Message Filtering and Validation section for more details. When this flag is set.." "0,1" rbitfld.long 0x1C 12. "RXWAKE,Receiver wakeup detect flag.This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by:- RESET bit- Setting the SWnRESET bit [SCIGCR1.7]- System.." "0,1" rbitfld.long 0x1C 11. "TXEMPTY,Transmitter Empty flag.The value of this flag indicates the contents of the transmitter's buffer register[s] [SCITD/TDy] and shift register [SCITXSHF]. In multibuffer mode this flag indicates the value of the TDx registers and shift register.." "0,1" newline bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wakeup method select.This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or.." "0,1" bitfld.long 0x1C 9. "RXRDY,Receiver ready flag. In SCI compatibility mode the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode RXRDY is set once a valid frame is received in multibuffer mode a valid frame.." "0,1" rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag.When set this bit indicates that the transmit buffer[s] register [SCITD in compatibility mode and LINTD0 LINTD1 in MBUF mode] is/are ready to get another character from a CPU write. In SCI compatibility.." "0,1" newline bitfld.long 0x1C 7. "TOA3WUS,Timeout After 3 Wakeup Signals flag.This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another.." "0,1" bitfld.long 0x1C 6. "TOAWUS,Timeout After Wakeup Signal flag.This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal." "0,1" bitfld.long 0x1C 4. "TIMEOUT,LIN Bus IDLE timeout flag.This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by:- Reading the.." "0,1" newline rbitfld.long 0x1C 3. "BUSY,Bus BUSY flag.This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit the BUSY bit is set to 1. When the.." "0,1" rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state.This bit is effective in SCI-compatible mode only. While this bit is set the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus.." "0,1" bitfld.long 0x1C 1. "WAKEUP,Wake-up flag.This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit [SCISETINT.1] is set. This.." "0,1" newline bitfld.long 0x1C 0. "BRKDT,SCI break-detect flag.This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a.." "0,1" rgroup.long 0x20++0x7 line.long 0x0 "LIN4_SCIINTVECT0,The SCIINTVECT0 register indicates the offset for the INT0 interrupt line." hexmask.long.byte 0x0 0.--4. 1. "INTVECT0,Interrupt vector offset for INT0.This register indicates the offset for interrupt line INT0. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." line.long 0x4 "LIN4_SCIINTVECT1,The SCIINTVECT1 register indicates the offset for the INT1 interrupt line." hexmask.long.byte 0x4 0.--4. 1. "INTVECT1,Interrupt vector offset for INT1.This register indicates the offset for interrupt line INT1. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that.." group.long 0x28++0x7 line.long 0x0 "LIN4_SCIFORMAT,The SCIFORMAT register is used to set up the character and frame lengths." bitfld.long 0x0 16.--18. "LENGTH,Frame length control bits.In LIN mode these bits indicate the number of bytes in the response field from 1 to 8 bytes. In buffered SCI mode these bits indicate the number of characters. When these bits are used to indicate LIN response length.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. "CHAR,Character length control bits.These bits are effective in SCI compatible mode only. These bits set the SCI character length from 1 to 8 bits. Note: In compatibility mode or buffered SCI mode when data of fewer than eight bits in length is received .." "0,1,2,3,4,5,6,7" line.long 0x4 "LIN4_BRSR,The BRSR register is used to configure the baud rate of the LIN module." bitfld.long 0x4 28.--30. "U,Superfractional Divider Selection. [U]These bits are an additional fractional part for the baudrate specification. These bits allow a super fine tuning of the fractional baudrate with 7 more intermediate values for each of the M fractional divider.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--27. 1. "M,SCI/LIN 4-bit Fractional Divider Selection. [M]These bits are effective in LIN or SCI asynchronous mode. These bits are used to select a baud rate for the SCI/LIN module and they are a fractional part for the baud rate specification. The M divider.." hexmask.long.byte 0x4 16.--23. 1. "SCI_LIN_PSH,PRESCALER P [High Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." newline hexmask.long.word 0x4 0.--15. 1. "SCI_LIN_PSL,PRESCALER P [Low Bits].SCI/LIN 24-bit Integer Prescaler Selection.These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial.." rgroup.long 0x30++0x7 line.long 0x0 "LIN4_SCIED,The SCIED register is a duplicate copy of SCIRD register that has no affect on the RXRDY flag for use with an emulator." hexmask.long.byte 0x0 0.--7. 1. "ED,Receiver Emulation Data.This bit is effective in SCI-compatible mode only. Reading SCIED[7-0] does not clear the RXRDY flag. This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag." line.long 0x4 "LIN4_SCIRD,The SCIRD register is where received data is stored and can be read from." hexmask.long.byte 0x4 0.--7. 1. "RD,Received Data.This bit is effective in SCI-compatible mode only. When a frame has been completely received the data in the frame is transferred from the receiver shift register SCIRXSHF to this register. As this transfer occurs the RXRDY flag is set.." group.long 0x38++0xB line.long 0x0 "LIN4_SCITD,The SCITD register is where data to be transmitted is written to by application software." hexmask.long.byte 0x0 0.--7. 1. "TD,Transmit dataThis bit is effective in SCI-compatible mode only. Data to be transmitted is written to this register. The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag [SCIFLR.23] which indicates that.." line.long 0x4 "LIN4_SCIPIO0,The SCIPIO0 register is used to enable the LINTX and LINRX pins." bitfld.long 0x4 2. "TXFUNC,Transmit pin function.This bit is effective in LIN or SCI mode. This bit defines the function of LINTX pin." "0,1" bitfld.long 0x4 1. "RXFUNC,Receive pin function.This bit is effective in LIN or SCI mode. This bit defines the function of the LINRX pin." "0,1" line.long 0x8 "LIN4_SCIPIO1,Pin control Register 1" bitfld.long 0x8 2. "TXDIR,Transmit pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINTX pin if it is configured with general-purpose I/O functionality [TX FUNC = 0]. 0: general purpose input pin. 1: general-purpose.." "0: general purpose input pin,1: general-purpose output pin" bitfld.long 0x8 1. "RXDIR,Receive pin direction.This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINRX pin if it is configured with general-purpose I/O functionality [RX FUNC = 0]. 0: general purpose input pin. 1: general-purpose.." "0: general purpose input pin,1: general-purpose output pin" rgroup.long 0x44++0x3 line.long 0x0 "LIN4_SCIPIO2,The SCIPIO2 register indicates the current status of the LINTX and LINRX pins." bitfld.long 0x0 2. "TXIN,Transmit data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINTX pin." "0,1" bitfld.long 0x0 1. "RXIN,Receive data in.This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINRX pin." "0,1" group.long 0x48++0x1B line.long 0x0 "LIN4_SCIPIO3,Pin control Register 3" bitfld.long 0x0 2. "TXOUT,Transmit pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINTX." "0,1" bitfld.long 0x0 1. "RXOUT,Receive pin out.This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINRX." "0,1" line.long 0x4 "LIN4_SCIPIO4,Pin control Register 4" bitfld.long 0x4 2. "TXSET,Transmit pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX." "0,1" bitfld.long 0x4 1. "RXSET,Receive pin set.This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX." "0,1" line.long 0x8 "LIN4_SCIPIO5,Pin control Register 5" bitfld.long 0x8 2. "TXCLR,Transmit pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINTX." "0,1" bitfld.long 0x8 1. "RXCLR,Receive pin clear.This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINRX." "0,1" line.long 0xC "LIN4_SCIPIO6,Pin control Register 6" bitfld.long 0xC 2. "TXPDR,Transmit pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINTX." "0,1" bitfld.long 0xC 1. "RXPDR,Receive pin open drain enable.This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINRX." "0,1" line.long 0x10 "LIN4_SCIPIO7,Pin control Register 7" bitfld.long 0x10 2. "TXPD,Transmit pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINTX." "0,1" bitfld.long 0x10 1. "RXPD,Receive pin pull control disable.This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINRX." "0,1" line.long 0x14 "LIN4_SCIPIO8,Pin control Register 8" bitfld.long 0x14 2. "TXPSL,TX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINTX." "0,1" bitfld.long 0x14 1. "RXPSL,RX pin pull select.This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINRX." "0,1" line.long 0x18 "LIN4_LINCOMP,The LINCOMPARE register is used to configure the sync delimeter and sync break extension." bitfld.long 0x18 8.--9. "SDEL,2-bit Sync Delimiter compare.These bits are effective in LIN mode only. These bits are used to configure the number of Tbit for the sync delimiter in the sync field.The time delay calculation for the synchronization delimiter is:TSDEL = [SDEL +.." "0,1,2,3" bitfld.long 0x18 0.--2. "SBREAK,3-bit Sync Break extend.LIN mode only. These bits are used to configure the number of Tbits for the sync break to extend the minimum 13 Tbit in the Sync Field to a maximum of 20 Tbit.The time delay calculation for the sync break is:TSYNBRK =.." "0,1,2,3,4,5,6,7" rgroup.long 0x64++0x7 line.long 0x0 "LIN4_LINRD0,The LINRD0 register contains the lower 4 bytes of the received LIN frame data." hexmask.long.byte 0x0 24.--31. 1. "RD0,8-bit Receive Buffer 0Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received.A read of this byte clears the RXDY byte.Note: RD<x-1> is.." hexmask.long.byte 0x0 16.--23. 1. "RD1,8-bit Receive Buffer 1.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x0 8.--15. 1. "RD2,8-bit Receive Buffer 2.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x0 0.--7. 1. "RD3,8-bit Receive Buffer 3.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." line.long 0x4 "LIN4_LINRD1,The LINRD1 regsiter contains the upper 4 bytes of the received LIN frame data." hexmask.long.byte 0x4 24.--31. 1. "RD4,8-bit Receive Buffer 4 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 16.--23. 1. "RD5,8-bit Receive Buffer 5.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." hexmask.long.byte 0x4 8.--15. 1. "RD6,8-bit Receive Buffer 6.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." newline hexmask.long.byte 0x4 0.--7. 1. "RD7,8-bit Receive Buffer 7.Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received." group.long 0x6C++0x17 line.long 0x0 "LIN4_LINMASK,The LINMASK register is used to configure the masks used for filtering incoming ID messages for receive and transmit frames." hexmask.long.byte 0x0 16.--23. 1. "RXIDMASK,Receive ID mask.This field is effective in LIN mode only.This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID witht the RX ID mask will set the ID RX flag and trigger and.." hexmask.long.byte 0x0 0.--7. 1. "TXIDMASK,Transmit ID mask.This field is effective in LIN mode only. This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID with the TX ID Mask will set the ID TX flag and trigger an.." line.long 0x4 "LIN4_LINID,The LINID register contains the identification fields for LIN communication.[[br]]NOTE: For software compatibility with future LIN modules. the HGEN CTRL bit must be set to 1. the RX ID MASK field must be set to FFh. and the TX ID MASK field.." hexmask.long.byte 0x4 16.--23. 1. "RECEIVEDID,Received ID.This bit is effective in LIN mode only. This byte contains the current message identifier. During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID-parity error and there has been.." hexmask.long.byte 0x4 8.--15. 1. "IDSLAVETASKBYTE,ID Slave Task byte.This field is effective in LIN mode only. This byte contains the identifier to which the received ID of an incoming header will be compared in order to decide whether a RX response a TX response or no action needs to.." hexmask.long.byte 0x4 0.--7. 1. "IDBYTE,ID byte.This field is effective in LIN mode only. This byte is the LIN mode message ID. On a master node a write to this register by the CPU initiates a header transmission. For a slave task this byte is used for message filtering when HGENCTRL.." line.long 0x8 "LIN4_LINTD0,The LINTD0 register contains the lower 4 bytes of the data to be transmitted.[[br]]NOTE: TD<x-1> is equivalent to Data byte <x> of the LIN frame." hexmask.long.byte 0x8 24.--31. 1. "TD0,8-bit Transmit Buffer 0.Byte 0 to be transmitted is written into this register and then copied to SCITXSHF for transmission. Once byte 0 is written in TDO buffer transmission will be initiated." hexmask.long.byte 0x8 16.--23. 1. "TD1,8-bit Transmit Buffer 3.Byte 1 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0x8 8.--15. 1. "TD2,8-bit Transmit Buffer 2.Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0x8 0.--7. 1. "TD3,8-bit Transmit Buffer 3.Byte 3 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0xC "LIN4_LINTD1,The LINTD1 register contains the upper 4 bytes of the data to be transmitted.[[br]]NOTE: TD<x-1> is equivalent to Data byte <x> of the LIN frame." hexmask.long.byte 0xC 24.--31. 1. "TD4,8-bit Transmit Buffer 4.Byte4 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 16.--23. 1. "TD5,8-bit Transmit Buffer 5.Byte 5 to be transmitted is written into this register and then copied to SCITXSHF for transmission." hexmask.long.byte 0xC 8.--15. 1. "TD6,8-bit Transmit Buffer 6.Byte 6 to be transmitted is written into this register and then copied to SCITXSHF for transmission." newline hexmask.long.byte 0xC 0.--7. 1. "TD7,8-bit Transmit Buffer 7.Byte 7 to be transmitted is written into this register and then copied to SCITXSHF for transmission." line.long 0x10 "LIN4_MBRSR,The MBRSR register is used to configure the expected maximum baud rate of the LIN network." hexmask.long.word 0x10 0.--12. 1. "MBR,Maximum Baud Rate Prescaler.This field is effective in LIN mode only. This 13-bit prescaler is used during the synchronization phase [see the Header Reception and Adaptive Baudrate section] of a slave module if the ADAPT bit is set. In this way a.." line.long 0x14 "LIN4_Reserved_1,tbd" group.long 0x90++0x7 line.long 0x0 "LIN4_IODFTCTRL,The IODFTCTRL register is used to emulate various error and test conditions." bitfld.long 0x0 31. "BERRENA,Bit Errror Enable bit.This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set the bit received is ORed with 1 and passed to the Bit monitor circuitry." "0,1" bitfld.long 0x0 30. "PBERRENA,Physical Bus Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor.." "0,1" bitfld.long 0x0 29. "CERRENA,Checksum Error Enable bit.This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set the polarity of the CTYPE [checksum type] in the receive checksum calculator is changed so that a checksum error.." "0,1" newline bitfld.long 0x0 28. "ISFERRENA,Inconsistent Sync Field Error Enable bit.This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set the bit widths in the sync field are varied so that the ISF check fails and the error flag is set." "0,1" bitfld.long 0x0 26. "FERRENA,This bit is used to create a Frame Error.This bit is effective in SCI-compatible mode only. When this bit is set the stop bit received is ANDed with '0' and passed to the stop bit check circuitry." "0,1" bitfld.long 0x0 25. "PERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set in compatible mode the parity bit received is toggled so that a parity error occurs." "0,1" newline bitfld.long 0x0 24. "BRKDTERRENA,Compatible Mode onlyThis bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error [SCI mode only]. When this bit is set the stop bit of the frame is ANDed with '0' and passed to the RSM so that a frame error.." "0,1" bitfld.long 0x0 19.--20. "PINSAMPLEMASK,Pin sample mask.These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry.Note: During IODFT mode testing for.." "0,1,2,3" bitfld.long 0x0 16.--18. "TXSHIFT,Transmit shift.These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. [Not applicable to Start Bit]" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "IODFTENA,IO DFT Enable KeyThis field is used to enable the IODFT mode of the SCI/LIN module for testing." bitfld.long 0x0 1. "LPBENA,Module loopback enable.In analog loopback mode the complete communication path through the I/Os can be tested whereas in digital loopback mode the I/O buffers are excluded from this path." "0,1" bitfld.long 0x0 0. "RXPENA,Module Analog loopback through receive pin enable.This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only." "0,1" line.long 0x4 "LIN4_Reserved_2,tbd" group.long 0xE0++0x3 line.long 0x0 "LIN4_LIN_GLB_INT_EN,The LIN_GLB_INT_EN register is used to enable the INT0 and INT1 interrupt lines to propagate to the PIE block." bitfld.long 0x0 1. "GLBINT1_EN,Global Interrupt Enable for LIN INT1.This bit determines whether the INT1 interrupt line generates an interrupt to the PIE or not" "0,1" bitfld.long 0x0 0. "GLBINT0_EN,Global Interrupt Enable for LIN INT0.This bit determines whether the INT0 interrupt line generates an interrupt to the PIE or not." "0,1" rgroup.long 0xE4++0x3 line.long 0x0 "LIN4_LIN_GLB_INT_FLG,The LIN_GLB_INT_FLG register contains the current status of the INT0 and INT1 flags." bitfld.long 0x0 1. "INT1_FLG,Global Interrupt Flag for LIN INT1.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT1 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" bitfld.long 0x0 0. "INT0_FLG,Global Interrupt Flag for LIN INT0.This bit indicates if an interrupt was generated to the PIE due to an enabled interrupt on the INT0 interrupt line. Refer to the LIN Interrupt Status Register for the condition that generated the interrupt.This.." "0,1" group.long 0xE8++0x3 line.long 0x0 "LIN4_LIN_GLB_INT_CLR,The LIN_GLB_INT_CLR register is used to clear the interrupt flags in LIN_GLB_INT_FLG register." bitfld.long 0x0 1. "INT1_FLG_CLR,Global Interrupt flag clear for LIN INT1.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT1_FLG bit. Writing 0 has no effect." "0,1" bitfld.long 0x0 0. "INT0_FLG_CLR,Global Interrupt flag clear for LIN INT0.This bit is used to clear the corresponding bit in the LIN_GLB_INT_FLG register. Write 1 to clear the INT0_FLG bit. Writing 0 has no effect." "0,1" tree.end tree.end tree "MBOX_SRAM" base ad:0x72000000 group.long 0x0++0x3 line.long 0x0 "MBOX_SRAM_START" hexmask.long 0x0 0.--31. 1. "START,L2 Memory start address" group.long 0x3FFC++0x3 line.long 0x0 "MBOX_SRAM_END" hexmask.long 0x0 0.--31. 1. "END,L2 Memory end address" tree.end tree "MCAN" base ad:0x0 tree "MCAN0" tree "MCAN0_CFG" base ad:0x52608000 rgroup.long 0x0++0x3 line.long 0x0 "MCAN0_CFG_SS_PID" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "MCAN0_CFG_SS_CTRL" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MCAN0_CFG_SS_STAT" bitfld.long 0x0 2. "EN_FDOE,Reflects the value of mcanss_enable_fdoe configuration portx=mcanss_enable_fdoe" "0,1" bitfld.long 0x0 1. "MMI_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0xC++0x3 line.long 0x0 "MCAN0_CFG_SS_ICS" bitfld.long 0x0 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. (ICS - Interrupt Clear Shadow Register)" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MCAN0_CFG_SS_IRS" bitfld.long 0x0 0. "IRS,External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. (IRS - Interrupt Raw Status Register)" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "MCAN0_CFG_SS_IECS" bitfld.long 0x0 0. "IECS,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. (IECS - Interrupt Enable Clear Shadow Register)" "0,1" group.long 0x18++0x3 line.long 0x0 "MCAN0_CFG_SS_IE" bitfld.long 0x0 0. "IE,External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. (IE - Interrupt Enable Register)" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCAN0_CFG_SS_IES" bitfld.long 0x0 0. "IES,External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. (IES - Interrupt Enable Status)" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "MCAN0_CFG_SS_EOI" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0).Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: ext_ts_eoi(0): EOI value for External TS interrupt.." group.long 0x24++0x3 line.long 0x0 "MCAN0_CFG_SS_EXT_TS_PS" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value.External Timestamp count rate is host clock rate divided by this valuewith one exception: a value of 0 has the same effect as 1 ." rgroup.long 0x28++0x3 line.long 0x0 "MCAN0_CFG_SS_EXT_TS_USIC" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt (EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter)" rgroup.long 0x200++0xB line.long 0x0 "MCAN0_CFG_CREL" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN0_CFG_ENDN" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" line.long 0x8 "MCAN0_CFG_CUST" hexmask.long 0x8 0.--31. 1. "CUST,Custom" group.long 0x20C++0x33 line.long 0x0 "MCAN0_CFG_DBTP" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before smaple point" newline hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x4 "MCAN0_CFG_TEST" rbitfld.long 0x4 7. "RX,Receive Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0,1" line.long 0x8 "MCAN0_CFG_RWD" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0xC "MCAN0_CFG_CCCR" bitfld.long 0xC 14. "TXP,Transmit Pause" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering durign Bus Integration" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0,1" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0xC 7. "TEST,Test Mode enable" "0,1" newline bitfld.long 0xC 6. "DAR,Disable Automatic Regransmission" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0,1" newline rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0xC 2. "ASM,Restriced Operation Mode" "0,1" bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0,1" newline bitfld.long 0xC 0. "INIT,Initialization" "0,1" line.long 0x10 "MCAN0_CFG_NBTP" hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x14 "MCAN0_CFG_TSCC" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x18 "MCAN0_CFG_TSCV" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "MCAN0_CFG_TOCC" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x20 "MCAN0_CFG_TOCV" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter" line.long 0x24 "MCAN0_CFG_RES00" line.long 0x28 "MCAN0_CFG_RES01" line.long 0x2C "MCAN0_CFG_RES02" line.long 0x30 "MCAN0_CFG_RES03" rgroup.long 0x240++0x7 line.long 0x0 "MCAN0_CFG_ECR" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Recieve Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Recieve Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN0_CFG_PSR" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Recieved a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last recieved CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last recieved CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" group.long 0x248++0x4B line.long 0x0 "MCAN0_CFG_TDCR" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN0_CFG_RES04" line.long 0x8 "MCAN0_CFG_IR" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 20. "BEC,Bit Error Corrected" "0,1" bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" newline bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" newline bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" newline bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" newline bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" newline bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN0_CFG_IE" bitfld.long 0xC 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN0_CFG_ILS" bitfld.long 0x10 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN0_CFG_ILE" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN0_CFG_RES05" line.long 0x1C "MCAN0_CFG_RES06" line.long 0x20 "MCAN0_CFG_RES07" line.long 0x24 "MCAN0_CFG_RES08" line.long 0x28 "MCAN0_CFG_RES09" line.long 0x2C "MCAN0_CFG_RES10" line.long 0x30 "MCAN0_CFG_RES11" line.long 0x34 "MCAN0_CFG_RES12" line.long 0x38 "MCAN0_CFG_GFC" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN0_CFG_SIDFC" hexmask.long.byte 0x3C 16.--23. 1. "LSS_S,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA_S,Filter List Standard Start Address" line.long 0x40 "MCAN0_CFG_XIDFC" hexmask.long.byte 0x40 16.--23. 1. "LSS_X,List Size Standard" hexmask.long.word 0x40 2.--15. 1. "FLSSA_X,Filter List Standard Start Address" line.long 0x44 "MCAN0_CFG_RES13" line.long 0x48 "MCAN0_CFG_XIDAM" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x294++0x3 line.long 0x0 "MCAN0_CFG_HPMS" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storeage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x298++0xB line.long 0x0 "MCAN0_CFG_NDAT1" hexmask.long 0x0 0.--31. 1. "ND0_31,New Data 0-31" line.long 0x4 "MCAN0_CFG_NDAT2" hexmask.long 0x4 0.--31. 1. "ND32_63,New Data 32-63" line.long 0x8 "MCAN0_CFG_RXF0C" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--14. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0x2A4++0x3 line.long 0x0 "MCAN0_CFG_RXF0S" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x2A8++0xB line.long 0x0 "MCAN0_CFG_RXF0A" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN0_CFG_RXBC" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN0_CFG_RXF1C" bitfld.long 0x8 31. "F1OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--14. 1. "F1SA,Rx FIFO 0 Start Address" rgroup.long 0x2B4++0x3 line.long 0x0 "MCAN0_CFG_RXF1S" bitfld.long 0x0 25. "RF1L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 0 Fill Level" group.long 0x2B8++0x7 line.long 0x0 "MCAN0_CFG_RXF1A" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN0_CFG_RXESC" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0x2C0++0x7 line.long 0x0 "MCAN0_CFG_TXBC" bitfld.long 0x0 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx Buffers Start Address" line.long 0x4 "MCAN0_CFG_TXFQS" bitfld.long 0x4 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x4 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x4 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x4 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0x2C8++0x3 line.long 0x0 "MCAN0_CFG_TXESC" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0x2CC++0x3 line.long 0x0 "MCAN0_CFG_TXBRP" hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending" group.long 0x2D0++0x7 line.long 0x0 "MCAN0_CFG_TXBAR" hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "MCAN0_CFG_TXBCR" hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" rgroup.long 0x2D8++0x7 line.long 0x0 "MCAN0_CFG_TXBTO" hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred" line.long 0x4 "MCAN0_CFG_TXBCF" hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished" group.long 0x2E0++0x13 line.long 0x0 "MCAN0_CFG_TXBTIE" hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable" line.long 0x4 "MCAN0_CFG_TXBCIE" hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable" line.long 0x8 "MCAN0_CFG_RES14" line.long 0xC "MCAN0_CFG_RES15" line.long 0x10 "MCAN0_CFG_TXEFC" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0x2F4++0x7 line.long 0x0 "MCAN0_CFG_TXEFS" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO FIll Level" line.long 0x4 "MCAN0_CFG_TXEFA" hexmask.long.byte 0x4 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" group.long 0x2FC++0x3 line.long 0x0 "MCAN0_CFG_RES16" tree.end tree "MCAN0_ECC" base ad:0x52700000 rgroup.long 0x0++0x3 line.long 0x0 "MCAN0_ECC_REV" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "MCAN0_ECC_VECTOR" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDR,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MCAN0_ECC_STAT" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x14++0xF line.long 0x0 "MCAN0_ECC_CTRL" hexmask.long.tbyte 0x0 9.--31. 1. "NU3,TI Internal : Reserved" bitfld.long 0x0 8. "CHECK_TIMEOUT,TI Internal : Check timeout" "0,1" bitfld.long 0x0 7. "CHECK_PARITY,TI Internal : Check Parity" "0,1" newline bitfld.long 0x0 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1" bitfld.long 0x0 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM read" "0,1" bitfld.long 0x0 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1" newline bitfld.long 0x0 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1" bitfld.long 0x0 2. "EN_RMW,TI Internal : Enable rmw" "0,1" bitfld.long 0x0 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1" newline bitfld.long 0x0 0. "ECC_EN,TI Internal : Enable ECC" "0,1" line.long 0x4 "MCAN0_ECC_ERR_CTRL1" hexmask.long 0x4 0.--31. 1. "ECC_ROW,TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "MCAN0_ECC_ERR_CTRL2" hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set" line.long 0xC "MCAN0_ECC_ERR_STAT1" hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error" bitfld.long 0xC 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing." "0,1" bitfld.long 0xC 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing." "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "MCAN0_ECC_ERR_STAT2" hexmask.long 0x0 0.--31. 1. "ECC_ROW,TI Internal : Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "MCAN0_ECC_ERR_STAT3" hexmask.long.tbyte 0x0 10.--31. 1. "NU6,TI Internal : Reserved" bitfld.long 0x0 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1" hexmask.long.byte 0x0 2.--8. 1. "NU5,TI Internal : Reserved" newline bitfld.long 0x0 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1" rbitfld.long 0x0 0. "NU4,TI Internal : Reserved" "0,1" group.long 0x3C++0x3 line.long 0x0 "MCAN0_ECC_SEC_EOI_REG" bitfld.long 0x0 0. "SEC_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing reading this bit will return 0." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MCAN0_ECC_SEC_STATUS_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x80++0x3 line.long 0x0 "MCAN0_ECC_SEC_ENABLE_SET_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0xC0++0x3 line.long 0x0 "MCAN0_ECC_SEC_ENABLE_CLR_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x13C++0x3 line.long 0x0 "MCAN0_ECC_DED_EOI_REG" bitfld.long 0x0 0. "DED_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing reading this bit will return 0." "0,1" rgroup.long 0x140++0x3 line.long 0x0 "MCAN0_ECC_DED_STATUS_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "DED_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x180++0x3 line.long 0x0 "MCAN0_ECC_DED_ENABLE_SET_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCAN0_ECC_DED_ENABLE_CLR_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x200++0xF line.long 0x0 "MCAN0_ECC_AGGR_ENABLE_SET" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" line.long 0x4 "MCAN0_ECC_AGGR_ENABLE_CLR" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" line.long 0x8 "MCAN0_ECC_AGGR_STATUS_SET" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" line.long 0xC "MCAN0_ECC_AGGR_STATUS_CLR" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" tree.end tree "MCAN0_MSG_RAM" base ad:0x52600000 group.long 0x0++0x3 line.long 0x0 "MCAN0_MSG_RAM_START" hexmask.long 0x0 0.--31. 1. "START,MCAN message mem Start address" tree.end tree.end tree "MCAN1" tree "MCAN1_CFG" base ad:0x52618000 rgroup.long 0x0++0x3 line.long 0x0 "MCAN1_CFG_SS_PID" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "MCAN1_CFG_SS_CTRL" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MCAN1_CFG_SS_STAT" bitfld.long 0x0 2. "EN_FDOE,Reflects the value of mcanss_enable_fdoe configuration portx=mcanss_enable_fdoe" "0,1" bitfld.long 0x0 1. "MMI_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0xC++0x3 line.long 0x0 "MCAN1_CFG_SS_ICS" bitfld.long 0x0 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. (ICS - Interrupt Clear Shadow Register)" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MCAN1_CFG_SS_IRS" bitfld.long 0x0 0. "IRS,External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. (IRS - Interrupt Raw Status Register)" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "MCAN1_CFG_SS_IECS" bitfld.long 0x0 0. "IECS,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. (IECS - Interrupt Enable Clear Shadow Register)" "0,1" group.long 0x18++0x3 line.long 0x0 "MCAN1_CFG_SS_IE" bitfld.long 0x0 0. "IE,External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. (IE - Interrupt Enable Register)" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCAN1_CFG_SS_IES" bitfld.long 0x0 0. "IES,External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. (IES - Interrupt Enable Status)" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "MCAN1_CFG_SS_EOI" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0).Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: ext_ts_eoi(0): EOI value for External TS interrupt.." group.long 0x24++0x3 line.long 0x0 "MCAN1_CFG_SS_EXT_TS_PS" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value.External Timestamp count rate is host clock rate divided by this valuewith one exception: a value of 0 has the same effect as 1 ." rgroup.long 0x28++0x3 line.long 0x0 "MCAN1_CFG_SS_EXT_TS_USIC" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt (EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter)" rgroup.long 0x200++0xB line.long 0x0 "MCAN1_CFG_CREL" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN1_CFG_ENDN" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" line.long 0x8 "MCAN1_CFG_CUST" hexmask.long 0x8 0.--31. 1. "CUST,Custom" group.long 0x20C++0x33 line.long 0x0 "MCAN1_CFG_DBTP" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before smaple point" newline hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x4 "MCAN1_CFG_TEST" rbitfld.long 0x4 7. "RX,Receive Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0,1" line.long 0x8 "MCAN1_CFG_RWD" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0xC "MCAN1_CFG_CCCR" bitfld.long 0xC 14. "TXP,Transmit Pause" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering durign Bus Integration" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0,1" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0xC 7. "TEST,Test Mode enable" "0,1" newline bitfld.long 0xC 6. "DAR,Disable Automatic Regransmission" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0,1" newline rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0xC 2. "ASM,Restriced Operation Mode" "0,1" bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0,1" newline bitfld.long 0xC 0. "INIT,Initialization" "0,1" line.long 0x10 "MCAN1_CFG_NBTP" hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x14 "MCAN1_CFG_TSCC" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x18 "MCAN1_CFG_TSCV" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "MCAN1_CFG_TOCC" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x20 "MCAN1_CFG_TOCV" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter" line.long 0x24 "MCAN1_CFG_RES00" line.long 0x28 "MCAN1_CFG_RES01" line.long 0x2C "MCAN1_CFG_RES02" line.long 0x30 "MCAN1_CFG_RES03" rgroup.long 0x240++0x7 line.long 0x0 "MCAN1_CFG_ECR" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Recieve Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Recieve Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN1_CFG_PSR" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Recieved a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last recieved CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last recieved CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" group.long 0x248++0x4B line.long 0x0 "MCAN1_CFG_TDCR" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN1_CFG_RES04" line.long 0x8 "MCAN1_CFG_IR" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 20. "BEC,Bit Error Corrected" "0,1" bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" newline bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" newline bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" newline bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" newline bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" newline bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN1_CFG_IE" bitfld.long 0xC 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN1_CFG_ILS" bitfld.long 0x10 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN1_CFG_ILE" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN1_CFG_RES05" line.long 0x1C "MCAN1_CFG_RES06" line.long 0x20 "MCAN1_CFG_RES07" line.long 0x24 "MCAN1_CFG_RES08" line.long 0x28 "MCAN1_CFG_RES09" line.long 0x2C "MCAN1_CFG_RES10" line.long 0x30 "MCAN1_CFG_RES11" line.long 0x34 "MCAN1_CFG_RES12" line.long 0x38 "MCAN1_CFG_GFC" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN1_CFG_SIDFC" hexmask.long.byte 0x3C 16.--23. 1. "LSS_S,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA_S,Filter List Standard Start Address" line.long 0x40 "MCAN1_CFG_XIDFC" hexmask.long.byte 0x40 16.--23. 1. "LSS_X,List Size Standard" hexmask.long.word 0x40 2.--15. 1. "FLSSA_X,Filter List Standard Start Address" line.long 0x44 "MCAN1_CFG_RES13" line.long 0x48 "MCAN1_CFG_XIDAM" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x294++0x3 line.long 0x0 "MCAN1_CFG_HPMS" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storeage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x298++0xB line.long 0x0 "MCAN1_CFG_NDAT1" hexmask.long 0x0 0.--31. 1. "ND0_31,New Data 0-31" line.long 0x4 "MCAN1_CFG_NDAT2" hexmask.long 0x4 0.--31. 1. "ND32_63,New Data 32-63" line.long 0x8 "MCAN1_CFG_RXF0C" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--14. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0x2A4++0x3 line.long 0x0 "MCAN1_CFG_RXF0S" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x2A8++0xB line.long 0x0 "MCAN1_CFG_RXF0A" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN1_CFG_RXBC" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN1_CFG_RXF1C" bitfld.long 0x8 31. "F1OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--14. 1. "F1SA,Rx FIFO 0 Start Address" rgroup.long 0x2B4++0x3 line.long 0x0 "MCAN1_CFG_RXF1S" bitfld.long 0x0 25. "RF1L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 0 Fill Level" group.long 0x2B8++0x7 line.long 0x0 "MCAN1_CFG_RXF1A" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN1_CFG_RXESC" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0x2C0++0x7 line.long 0x0 "MCAN1_CFG_TXBC" bitfld.long 0x0 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx Buffers Start Address" line.long 0x4 "MCAN1_CFG_TXFQS" bitfld.long 0x4 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x4 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x4 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x4 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0x2C8++0x3 line.long 0x0 "MCAN1_CFG_TXESC" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0x2CC++0x3 line.long 0x0 "MCAN1_CFG_TXBRP" hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending" group.long 0x2D0++0x7 line.long 0x0 "MCAN1_CFG_TXBAR" hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "MCAN1_CFG_TXBCR" hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" rgroup.long 0x2D8++0x7 line.long 0x0 "MCAN1_CFG_TXBTO" hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred" line.long 0x4 "MCAN1_CFG_TXBCF" hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished" group.long 0x2E0++0x13 line.long 0x0 "MCAN1_CFG_TXBTIE" hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable" line.long 0x4 "MCAN1_CFG_TXBCIE" hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable" line.long 0x8 "MCAN1_CFG_RES14" line.long 0xC "MCAN1_CFG_RES15" line.long 0x10 "MCAN1_CFG_TXEFC" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0x2F4++0x7 line.long 0x0 "MCAN1_CFG_TXEFS" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO FIll Level" line.long 0x4 "MCAN1_CFG_TXEFA" hexmask.long.byte 0x4 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" group.long 0x2FC++0x3 line.long 0x0 "MCAN1_CFG_RES16" tree.end tree "MCAN1_ECC" base ad:0x52701000 rgroup.long 0x0++0x3 line.long 0x0 "MCAN1_ECC_REV" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "MCAN1_ECC_VECTOR" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDR,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MCAN1_ECC_STAT" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x14++0xF line.long 0x0 "MCAN1_ECC_CTRL" hexmask.long.tbyte 0x0 9.--31. 1. "NU3,TI Internal : Reserved" bitfld.long 0x0 8. "CHECK_TIMEOUT,TI Internal : Check timeout" "0,1" bitfld.long 0x0 7. "CHECK_PARITY,TI Internal : Check Parity" "0,1" newline bitfld.long 0x0 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1" bitfld.long 0x0 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM read" "0,1" bitfld.long 0x0 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1" newline bitfld.long 0x0 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1" bitfld.long 0x0 2. "EN_RMW,TI Internal : Enable rmw" "0,1" bitfld.long 0x0 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1" newline bitfld.long 0x0 0. "ECC_EN,TI Internal : Enable ECC" "0,1" line.long 0x4 "MCAN1_ECC_ERR_CTRL1" hexmask.long 0x4 0.--31. 1. "ECC_ROW,TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "MCAN1_ECC_ERR_CTRL2" hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set" line.long 0xC "MCAN1_ECC_ERR_STAT1" hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error" bitfld.long 0xC 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing." "0,1" bitfld.long 0xC 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing." "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "MCAN1_ECC_ERR_STAT2" hexmask.long 0x0 0.--31. 1. "ECC_ROW,TI Internal : Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "MCAN1_ECC_ERR_STAT3" hexmask.long.tbyte 0x0 10.--31. 1. "NU6,TI Internal : Reserved" bitfld.long 0x0 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1" hexmask.long.byte 0x0 2.--8. 1. "NU5,TI Internal : Reserved" newline bitfld.long 0x0 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1" rbitfld.long 0x0 0. "NU4,TI Internal : Reserved" "0,1" group.long 0x3C++0x3 line.long 0x0 "MCAN1_ECC_SEC_EOI_REG" bitfld.long 0x0 0. "SEC_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing reading this bit will return 0." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MCAN1_ECC_SEC_STATUS_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x80++0x3 line.long 0x0 "MCAN1_ECC_SEC_ENABLE_SET_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0xC0++0x3 line.long 0x0 "MCAN1_ECC_SEC_ENABLE_CLR_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x13C++0x3 line.long 0x0 "MCAN1_ECC_DED_EOI_REG" bitfld.long 0x0 0. "DED_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing reading this bit will return 0." "0,1" rgroup.long 0x140++0x3 line.long 0x0 "MCAN1_ECC_DED_STATUS_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "DED_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x180++0x3 line.long 0x0 "MCAN1_ECC_DED_ENABLE_SET_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCAN1_ECC_DED_ENABLE_CLR_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x200++0xF line.long 0x0 "MCAN1_ECC_AGGR_ENABLE_SET" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" line.long 0x4 "MCAN1_ECC_AGGR_ENABLE_CLR" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" line.long 0x8 "MCAN1_ECC_AGGR_STATUS_SET" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" line.long 0xC "MCAN1_ECC_AGGR_STATUS_CLR" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" tree.end tree "MCAN1_MSG_RAM" base ad:0x52610000 group.long 0x0++0x3 line.long 0x0 "MCAN1_MSG_RAM_START" hexmask.long 0x0 0.--31. 1. "START,MCAN message mem Start address" tree.end tree.end tree "MCAN2" tree "MCAN2_CFG" base ad:0x52628000 rgroup.long 0x0++0x3 line.long 0x0 "MCAN2_CFG_SS_PID" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "MCAN2_CFG_SS_CTRL" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MCAN2_CFG_SS_STAT" bitfld.long 0x0 2. "EN_FDOE,Reflects the value of mcanss_enable_fdoe configuration portx=mcanss_enable_fdoe" "0,1" bitfld.long 0x0 1. "MMI_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0xC++0x3 line.long 0x0 "MCAN2_CFG_SS_ICS" bitfld.long 0x0 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. (ICS - Interrupt Clear Shadow Register)" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MCAN2_CFG_SS_IRS" bitfld.long 0x0 0. "IRS,External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. (IRS - Interrupt Raw Status Register)" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "MCAN2_CFG_SS_IECS" bitfld.long 0x0 0. "IECS,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. (IECS - Interrupt Enable Clear Shadow Register)" "0,1" group.long 0x18++0x3 line.long 0x0 "MCAN2_CFG_SS_IE" bitfld.long 0x0 0. "IE,External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. (IE - Interrupt Enable Register)" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCAN2_CFG_SS_IES" bitfld.long 0x0 0. "IES,External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. (IES - Interrupt Enable Status)" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "MCAN2_CFG_SS_EOI" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0).Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: ext_ts_eoi(0): EOI value for External TS interrupt.." group.long 0x24++0x3 line.long 0x0 "MCAN2_CFG_SS_EXT_TS_PS" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value.External Timestamp count rate is host clock rate divided by this valuewith one exception: a value of 0 has the same effect as 1 ." rgroup.long 0x28++0x3 line.long 0x0 "MCAN2_CFG_SS_EXT_TS_USIC" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt (EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter)" rgroup.long 0x200++0xB line.long 0x0 "MCAN2_CFG_CREL" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN2_CFG_ENDN" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" line.long 0x8 "MCAN2_CFG_CUST" hexmask.long 0x8 0.--31. 1. "CUST,Custom" group.long 0x20C++0x33 line.long 0x0 "MCAN2_CFG_DBTP" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before smaple point" newline hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x4 "MCAN2_CFG_TEST" rbitfld.long 0x4 7. "RX,Receive Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0,1" line.long 0x8 "MCAN2_CFG_RWD" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0xC "MCAN2_CFG_CCCR" bitfld.long 0xC 14. "TXP,Transmit Pause" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering durign Bus Integration" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0,1" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0xC 7. "TEST,Test Mode enable" "0,1" newline bitfld.long 0xC 6. "DAR,Disable Automatic Regransmission" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0,1" newline rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0xC 2. "ASM,Restriced Operation Mode" "0,1" bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0,1" newline bitfld.long 0xC 0. "INIT,Initialization" "0,1" line.long 0x10 "MCAN2_CFG_NBTP" hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x14 "MCAN2_CFG_TSCC" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x18 "MCAN2_CFG_TSCV" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "MCAN2_CFG_TOCC" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x20 "MCAN2_CFG_TOCV" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter" line.long 0x24 "MCAN2_CFG_RES00" line.long 0x28 "MCAN2_CFG_RES01" line.long 0x2C "MCAN2_CFG_RES02" line.long 0x30 "MCAN2_CFG_RES03" rgroup.long 0x240++0x7 line.long 0x0 "MCAN2_CFG_ECR" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Recieve Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Recieve Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN2_CFG_PSR" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Recieved a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last recieved CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last recieved CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" group.long 0x248++0x4B line.long 0x0 "MCAN2_CFG_TDCR" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN2_CFG_RES04" line.long 0x8 "MCAN2_CFG_IR" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 20. "BEC,Bit Error Corrected" "0,1" bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" newline bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" newline bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" newline bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" newline bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" newline bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN2_CFG_IE" bitfld.long 0xC 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN2_CFG_ILS" bitfld.long 0x10 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN2_CFG_ILE" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN2_CFG_RES05" line.long 0x1C "MCAN2_CFG_RES06" line.long 0x20 "MCAN2_CFG_RES07" line.long 0x24 "MCAN2_CFG_RES08" line.long 0x28 "MCAN2_CFG_RES09" line.long 0x2C "MCAN2_CFG_RES10" line.long 0x30 "MCAN2_CFG_RES11" line.long 0x34 "MCAN2_CFG_RES12" line.long 0x38 "MCAN2_CFG_GFC" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN2_CFG_SIDFC" hexmask.long.byte 0x3C 16.--23. 1. "LSS_S,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA_S,Filter List Standard Start Address" line.long 0x40 "MCAN2_CFG_XIDFC" hexmask.long.byte 0x40 16.--23. 1. "LSS_X,List Size Standard" hexmask.long.word 0x40 2.--15. 1. "FLSSA_X,Filter List Standard Start Address" line.long 0x44 "MCAN2_CFG_RES13" line.long 0x48 "MCAN2_CFG_XIDAM" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x294++0x3 line.long 0x0 "MCAN2_CFG_HPMS" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storeage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x298++0xB line.long 0x0 "MCAN2_CFG_NDAT1" hexmask.long 0x0 0.--31. 1. "ND0_31,New Data 0-31" line.long 0x4 "MCAN2_CFG_NDAT2" hexmask.long 0x4 0.--31. 1. "ND32_63,New Data 32-63" line.long 0x8 "MCAN2_CFG_RXF0C" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--14. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0x2A4++0x3 line.long 0x0 "MCAN2_CFG_RXF0S" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x2A8++0xB line.long 0x0 "MCAN2_CFG_RXF0A" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN2_CFG_RXBC" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN2_CFG_RXF1C" bitfld.long 0x8 31. "F1OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--14. 1. "F1SA,Rx FIFO 0 Start Address" rgroup.long 0x2B4++0x3 line.long 0x0 "MCAN2_CFG_RXF1S" bitfld.long 0x0 25. "RF1L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 0 Fill Level" group.long 0x2B8++0x7 line.long 0x0 "MCAN2_CFG_RXF1A" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN2_CFG_RXESC" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0x2C0++0x7 line.long 0x0 "MCAN2_CFG_TXBC" bitfld.long 0x0 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx Buffers Start Address" line.long 0x4 "MCAN2_CFG_TXFQS" bitfld.long 0x4 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x4 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x4 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x4 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0x2C8++0x3 line.long 0x0 "MCAN2_CFG_TXESC" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0x2CC++0x3 line.long 0x0 "MCAN2_CFG_TXBRP" hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending" group.long 0x2D0++0x7 line.long 0x0 "MCAN2_CFG_TXBAR" hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "MCAN2_CFG_TXBCR" hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" rgroup.long 0x2D8++0x7 line.long 0x0 "MCAN2_CFG_TXBTO" hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred" line.long 0x4 "MCAN2_CFG_TXBCF" hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished" group.long 0x2E0++0x13 line.long 0x0 "MCAN2_CFG_TXBTIE" hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable" line.long 0x4 "MCAN2_CFG_TXBCIE" hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable" line.long 0x8 "MCAN2_CFG_RES14" line.long 0xC "MCAN2_CFG_RES15" line.long 0x10 "MCAN2_CFG_TXEFC" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0x2F4++0x7 line.long 0x0 "MCAN2_CFG_TXEFS" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO FIll Level" line.long 0x4 "MCAN2_CFG_TXEFA" hexmask.long.byte 0x4 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" group.long 0x2FC++0x3 line.long 0x0 "MCAN2_CFG_RES16" tree.end tree "MCAN2_ECC" base ad:0x52702000 rgroup.long 0x0++0x3 line.long 0x0 "MCAN2_ECC_REV" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "MCAN2_ECC_VECTOR" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDR,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MCAN2_ECC_STAT" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x14++0xF line.long 0x0 "MCAN2_ECC_CTRL" hexmask.long.tbyte 0x0 9.--31. 1. "NU3,TI Internal : Reserved" bitfld.long 0x0 8. "CHECK_TIMEOUT,TI Internal : Check timeout" "0,1" bitfld.long 0x0 7. "CHECK_PARITY,TI Internal : Check Parity" "0,1" newline bitfld.long 0x0 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1" bitfld.long 0x0 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM read" "0,1" bitfld.long 0x0 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1" newline bitfld.long 0x0 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1" bitfld.long 0x0 2. "EN_RMW,TI Internal : Enable rmw" "0,1" bitfld.long 0x0 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1" newline bitfld.long 0x0 0. "ECC_EN,TI Internal : Enable ECC" "0,1" line.long 0x4 "MCAN2_ECC_ERR_CTRL1" hexmask.long 0x4 0.--31. 1. "ECC_ROW,TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "MCAN2_ECC_ERR_CTRL2" hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set" line.long 0xC "MCAN2_ECC_ERR_STAT1" hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error" bitfld.long 0xC 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing." "0,1" bitfld.long 0xC 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing." "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "MCAN2_ECC_ERR_STAT2" hexmask.long 0x0 0.--31. 1. "ECC_ROW,TI Internal : Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "MCAN2_ECC_ERR_STAT3" hexmask.long.tbyte 0x0 10.--31. 1. "NU6,TI Internal : Reserved" bitfld.long 0x0 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1" hexmask.long.byte 0x0 2.--8. 1. "NU5,TI Internal : Reserved" newline bitfld.long 0x0 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1" rbitfld.long 0x0 0. "NU4,TI Internal : Reserved" "0,1" group.long 0x3C++0x3 line.long 0x0 "MCAN2_ECC_SEC_EOI_REG" bitfld.long 0x0 0. "SEC_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing reading this bit will return 0." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MCAN2_ECC_SEC_STATUS_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x80++0x3 line.long 0x0 "MCAN2_ECC_SEC_ENABLE_SET_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0xC0++0x3 line.long 0x0 "MCAN2_ECC_SEC_ENABLE_CLR_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x13C++0x3 line.long 0x0 "MCAN2_ECC_DED_EOI_REG" bitfld.long 0x0 0. "DED_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing reading this bit will return 0." "0,1" rgroup.long 0x140++0x3 line.long 0x0 "MCAN2_ECC_DED_STATUS_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "DED_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x180++0x3 line.long 0x0 "MCAN2_ECC_DED_ENABLE_SET_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCAN2_ECC_DED_ENABLE_CLR_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x200++0xF line.long 0x0 "MCAN2_ECC_AGGR_ENABLE_SET" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" line.long 0x4 "MCAN2_ECC_AGGR_ENABLE_CLR" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" line.long 0x8 "MCAN2_ECC_AGGR_STATUS_SET" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" line.long 0xC "MCAN2_ECC_AGGR_STATUS_CLR" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" tree.end tree "MCAN2_MSG_RAM" base ad:0x52620000 group.long 0x0++0x3 line.long 0x0 "MCAN2_MSG_RAM_START" hexmask.long 0x0 0.--31. 1. "START,MCAN message mem Start address" tree.end tree.end tree "MCAN3" tree "MCAN3_CFG" base ad:0x52638000 rgroup.long 0x0++0x3 line.long 0x0 "MCAN3_CFG_SS_PID" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" group.long 0x4++0x3 line.long 0x0 "MCAN3_CFG_SS_CTRL" bitfld.long 0x0 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1" bitfld.long 0x0 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1" bitfld.long 0x0 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1" newline bitfld.long 0x0 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "MCAN3_CFG_SS_STAT" bitfld.long 0x0 2. "EN_FDOE,Reflects the value of mcanss_enable_fdoe configuration portx=mcanss_enable_fdoe" "0,1" bitfld.long 0x0 1. "MMI_DONE,0:Memory Initialization is in progress 1:Memory Intialization Done" "0: Memory Initialization is in progress,1: Memory Intialization Done" wgroup.long 0xC++0x3 line.long 0x0 "MCAN3_CFG_SS_ICS" bitfld.long 0x0 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. (ICS - Interrupt Clear Shadow Register)" "0,1" rgroup.long 0x10++0x3 line.long 0x0 "MCAN3_CFG_SS_IRS" bitfld.long 0x0 0. "IRS,External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. (IRS - Interrupt Raw Status Register)" "0,1" wgroup.long 0x14++0x3 line.long 0x0 "MCAN3_CFG_SS_IECS" bitfld.long 0x0 0. "IECS,External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. (IECS - Interrupt Enable Clear Shadow Register)" "0,1" group.long 0x18++0x3 line.long 0x0 "MCAN3_CFG_SS_IE" bitfld.long 0x0 0. "IE,External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. (IE - Interrupt Enable Register)" "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "MCAN3_CFG_SS_IES" bitfld.long 0x0 0. "IES,External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. (IES - Interrupt Enable Status)" "0,1" wgroup.long 0x20++0x3 line.long 0x0 "MCAN3_CFG_SS_EOI" hexmask.long.byte 0x0 0.--7. 1. "EOI,Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0).Upon write level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: ext_ts_eoi(0): EOI value for External TS interrupt.." group.long 0x24++0x3 line.long 0x0 "MCAN3_CFG_SS_EXT_TS_PS" hexmask.long.tbyte 0x0 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value.External Timestamp count rate is host clock rate divided by this valuewith one exception: a value of 0 has the same effect as 1 ." rgroup.long 0x28++0x3 line.long 0x0 "MCAN3_CFG_SS_EXT_TS_USIC" hexmask.long.byte 0x0 0.--4. 1. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt (EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter)" rgroup.long 0x200++0xB line.long 0x0 "MCAN3_CFG_CREL" hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release" hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release" hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-Step of Core Release" newline hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year" hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month" hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day" line.long 0x4 "MCAN3_CFG_ENDN" hexmask.long 0x4 0.--31. 1. "ETV,Endianess test value" line.long 0x8 "MCAN3_CFG_CUST" hexmask.long 0x8 0.--31. 1. "CUST,Custom" group.long 0x20C++0x33 line.long 0x0 "MCAN3_CFG_DBTP" bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0,1" hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Baud Rate Prescaler" hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before smaple point" newline hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point" hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data resynchronization Jump Width" line.long 0x4 "MCAN3_CFG_TEST" rbitfld.long 0x4 7. "RX,Receive Pin" "0,1" bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3" bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0,1" line.long 0x8 "MCAN3_CFG_RWD" hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value" hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Counter Value" line.long 0xC "MCAN3_CFG_CCCR" bitfld.long 0xC 14. "TXP,Transmit Pause" "0,1" bitfld.long 0xC 13. "EFBI,Edge Filtering durign Bus Integration" "0,1" bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0,1" newline bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0,1" bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0,1" bitfld.long 0xC 7. "TEST,Test Mode enable" "0,1" newline bitfld.long 0xC 6. "DAR,Disable Automatic Regransmission" "0,1" bitfld.long 0xC 5. "MON,Bus Monitoring Mode" "0,1" bitfld.long 0xC 4. "CSR,Clock Stop Request" "0,1" newline rbitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0,1" bitfld.long 0xC 2. "ASM,Restriced Operation Mode" "0,1" bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0,1" newline bitfld.long 0xC 0. "INIT,Initialization" "0,1" line.long 0x10 "MCAN3_CFG_NBTP" hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width" hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler" hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point" newline hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point" line.long 0x14 "MCAN3_CFG_TSCC" hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler" bitfld.long 0x14 0.--1. "TSS,Timestamp Select" "0,1,2,3" line.long 0x18 "MCAN3_CFG_TSCV" hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter" line.long 0x1C "MCAN3_CFG_TOCC" hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period" bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0,1,2,3" bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0,1" line.long 0x20 "MCAN3_CFG_TOCV" hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter" line.long 0x24 "MCAN3_CFG_RES00" line.long 0x28 "MCAN3_CFG_RES01" line.long 0x2C "MCAN3_CFG_RES02" line.long 0x30 "MCAN3_CFG_RES03" rgroup.long 0x240++0x7 line.long 0x0 "MCAN3_CFG_ECR" hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging" bitfld.long 0x0 15. "RP,Recieve Error Passive" "0,1" hexmask.long.byte 0x0 8.--14. 1. "REC,Recieve Error Counter" newline hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter" line.long 0x4 "MCAN3_CFG_PSR" hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value" bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1" bitfld.long 0x4 13. "RFDF,Recieved a CAN FD Message" "0,1" newline bitfld.long 0x4 12. "RBRS,BRS flag of last recieved CAN FD Message" "0,1" bitfld.long 0x4 11. "RESI,ESI flag of last recieved CAN FD Message" "0,1" bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "BO,Bus_Off status" "0,1" bitfld.long 0x4 6. "EW,Warning Status" "0,1" bitfld.long 0x4 5. "EP,Error Passive" "0,1" newline bitfld.long 0x4 3.--4. "ACT,Activity" "0,1,2,3" bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7" group.long 0x248++0x4B line.long 0x0 "MCAN3_CFG_TDCR" hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset" hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length" line.long 0x4 "MCAN3_CFG_RES04" line.long 0x8 "MCAN3_CFG_IR" bitfld.long 0x8 29. "ARA,Access to Reserved Address" "0,1" bitfld.long 0x8 28. "PED,Protocol Error in data Phase" "0,1" bitfld.long 0x8 27. "PEA,Protocol Error in Arbitration Phase" "0,1" newline bitfld.long 0x8 26. "WDI,Watchdog Interrupt" "0,1" bitfld.long 0x8 25. "BO,Bus_Off Status" "0,1" bitfld.long 0x8 24. "EW,Warning Status" "0,1" newline bitfld.long 0x8 23. "EP,Error Passive" "0,1" bitfld.long 0x8 22. "ELO,Error Logging Overflow" "0,1" bitfld.long 0x8 21. "BEU,Bit Error Uncorrected" "0,1" newline bitfld.long 0x8 20. "BEC,Bit Error Corrected" "0,1" bitfld.long 0x8 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1" bitfld.long 0x8 18. "TOO,Timeout Occurred" "0,1" newline bitfld.long 0x8 17. "MRAF,Message RAM Access Failure" "0,1" bitfld.long 0x8 16. "TSW,Timestamp Wraparound" "0,1" bitfld.long 0x8 15. "TEFL,Tx Event FIFO Element Lost" "0,1" newline bitfld.long 0x8 14. "TEFF,Tx Event FIFO Full" "0,1" bitfld.long 0x8 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1" bitfld.long 0x8 12. "TEFN,Tx Event FIFO New Entry" "0,1" newline bitfld.long 0x8 11. "TFE,Tx FIFO Empty" "0,1" bitfld.long 0x8 10. "TCF,Transmission Cancellation Finished" "0,1" bitfld.long 0x8 9. "TC,Transmission Complete" "0,1" newline bitfld.long 0x8 8. "HPM,High Priority Message" "0,1" bitfld.long 0x8 7. "RF1L,Rx FIFO 1 Message Lost" "0,1" bitfld.long 0x8 6. "RF1F,Rx FIFO 1 Full" "0,1" newline bitfld.long 0x8 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1" bitfld.long 0x8 4. "RF1N,Rx FIFO 1 New Message" "0,1" bitfld.long 0x8 3. "RF0L,Rx FIFO 0 Message Lost" "0,1" newline bitfld.long 0x8 2. "RF0F,Rx FIFO 0 Full" "0,1" bitfld.long 0x8 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1" bitfld.long 0x8 0. "RF0N,Rx FIFO 0 New Message" "0,1" line.long 0xC "MCAN3_CFG_IE" bitfld.long 0xC 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1" bitfld.long 0xC 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1" bitfld.long 0xC 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1" newline bitfld.long 0xC 26. "WDIE,Watchdog Interrupt Enable" "0,1" bitfld.long 0xC 25. "BOE,Bus_Off Status Interrupt Enable" "0,1" bitfld.long 0xC 24. "EWE,Warning Status Interrupt Enable" "0,1" newline bitfld.long 0xC 23. "EPE,Error Passive Interrupt Enable" "0,1" bitfld.long 0xC 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1" bitfld.long 0xC 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1" newline bitfld.long 0xC 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1" bitfld.long 0xC 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1" bitfld.long 0xC 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1" newline bitfld.long 0xC 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1" bitfld.long 0xC 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1" bitfld.long 0xC 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1" bitfld.long 0xC 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1" bitfld.long 0xC 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1" newline bitfld.long 0xC 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1" bitfld.long 0xC 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1" bitfld.long 0xC 9. "TCE,Transmission Completed Interrupt Enable" "0,1" newline bitfld.long 0xC 8. "HPME,High Priority message Interrupt Enable" "0,1" bitfld.long 0xC 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1" bitfld.long 0xC 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1" newline bitfld.long 0xC 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1" bitfld.long 0xC 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1" newline bitfld.long 0xC 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1" bitfld.long 0xC 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1" bitfld.long 0xC 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1" line.long 0x10 "MCAN3_CFG_ILS" bitfld.long 0x10 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1" bitfld.long 0x10 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1" bitfld.long 0x10 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1" newline bitfld.long 0x10 26. "WDIL,Watchdog Interrupt Line" "0,1" bitfld.long 0x10 25. "BOL,Bus_Off Status Interrupt Line" "0,1" bitfld.long 0x10 24. "EWL,Warning Status Interrupt Line" "0,1" newline bitfld.long 0x10 23. "EPL,Error Passive Interrupt Line" "0,1" bitfld.long 0x10 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1" bitfld.long 0x10 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1" newline bitfld.long 0x10 20. "BECL,Bit Error Corrected Interrupt Line" "0,1" bitfld.long 0x10 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1" bitfld.long 0x10 18. "TOOL,Timeout Occurred Interrupt Line" "0,1" newline bitfld.long 0x10 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1" bitfld.long 0x10 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1" bitfld.long 0x10 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1" newline bitfld.long 0x10 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1" bitfld.long 0x10 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1" newline bitfld.long 0x10 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1" bitfld.long 0x10 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1" bitfld.long 0x10 9. "TCL,Transmission Completed Interrupt Line" "0,1" newline bitfld.long 0x10 8. "HPML,High Priority message Interrupt Line" "0,1" bitfld.long 0x10 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1" bitfld.long 0x10 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1" newline bitfld.long 0x10 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1" bitfld.long 0x10 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1" newline bitfld.long 0x10 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1" bitfld.long 0x10 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1" bitfld.long 0x10 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1" line.long 0x14 "MCAN3_CFG_ILE" bitfld.long 0x14 1. "EINT1,Enable Interrupt Line 1" "0,1" bitfld.long 0x14 0. "EINT0,Enable Interrupt Line 0" "0,1" line.long 0x18 "MCAN3_CFG_RES05" line.long 0x1C "MCAN3_CFG_RES06" line.long 0x20 "MCAN3_CFG_RES07" line.long 0x24 "MCAN3_CFG_RES08" line.long 0x28 "MCAN3_CFG_RES09" line.long 0x2C "MCAN3_CFG_RES10" line.long 0x30 "MCAN3_CFG_RES11" line.long 0x34 "MCAN3_CFG_RES12" line.long 0x38 "MCAN3_CFG_GFC" bitfld.long 0x38 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3" bitfld.long 0x38 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3" bitfld.long 0x38 1. "RRFS,reject Remote Frames Standard" "0,1" newline bitfld.long 0x38 0. "RRFE,reject Remote Frames Extended" "0,1" line.long 0x3C "MCAN3_CFG_SIDFC" hexmask.long.byte 0x3C 16.--23. 1. "LSS_S,List Size Standard" hexmask.long.word 0x3C 2.--15. 1. "FLSSA_S,Filter List Standard Start Address" line.long 0x40 "MCAN3_CFG_XIDFC" hexmask.long.byte 0x40 16.--23. 1. "LSS_X,List Size Standard" hexmask.long.word 0x40 2.--15. 1. "FLSSA_X,Filter List Standard Start Address" line.long 0x44 "MCAN3_CFG_RES13" line.long 0x48 "MCAN3_CFG_XIDAM" hexmask.long 0x48 0.--28. 1. "EIDM,Extended ID Mask" rgroup.long 0x294++0x3 line.long 0x0 "MCAN3_CFG_HPMS" bitfld.long 0x0 15. "FLST,Filter List" "0,1" hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index" bitfld.long 0x0 6.--7. "MSI,Message Storeage Indicator" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index" group.long 0x298++0xB line.long 0x0 "MCAN3_CFG_NDAT1" hexmask.long 0x0 0.--31. 1. "ND0_31,New Data 0-31" line.long 0x4 "MCAN3_CFG_NDAT2" hexmask.long 0x4 0.--31. 1. "ND32_63,New Data 32-63" line.long 0x8 "MCAN3_CFG_RXF0C" bitfld.long 0x8 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--14. 1. "F0SA,Rx FIFO 0 Start Address" rgroup.long 0x2A4++0x3 line.long 0x0 "MCAN3_CFG_RXF0S" bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level" group.long 0x2A8++0xB line.long 0x0 "MCAN3_CFG_RXF0A" hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN3_CFG_RXBC" hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address" line.long 0x8 "MCAN3_CFG_RXF1C" bitfld.long 0x8 31. "F1OM,Rx FIFO 0 Operation Mode" "0,1" hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 0 Watermark" hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 0 Size" newline hexmask.long.word 0x8 2.--14. 1. "F1SA,Rx FIFO 0 Start Address" rgroup.long 0x2B4++0x3 line.long 0x0 "MCAN3_CFG_RXF1S" bitfld.long 0x0 25. "RF1L,Rx FIFO 0 Message Lost" "0,1" bitfld.long 0x0 24. "F1F,Rx FIFO 0 Full" "0,1" hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 0 Put Index" newline hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 0 Get Index" hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 0 Fill Level" group.long 0x2B8++0x7 line.long 0x0 "MCAN3_CFG_RXF1A" hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 0 Acknowledge Index" line.long 0x4 "MCAN3_CFG_RXESC" bitfld.long 0x4 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0x2C0++0x7 line.long 0x0 "MCAN3_CFG_TXBC" bitfld.long 0x0 30. "TFQM,Tx FIFO/Queue Mode" "0,1" hexmask.long.byte 0x0 24.--29. 1. "TFQS,Transmit FIFO/Queue Size" hexmask.long.byte 0x0 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers" newline hexmask.long.word 0x0 2.--15. 1. "TBSA,Tx Buffers Start Address" line.long 0x4 "MCAN3_CFG_TXFQS" bitfld.long 0x4 21. "TFQF,Tx FIFO/Queue Full" "0,1" hexmask.long.byte 0x4 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index" hexmask.long.byte 0x4 8.--12. 1. "TFGI,Tx Queue Get Index" newline hexmask.long.byte 0x4 0.--5. 1. "TFFL,Tx FIFO Free Level" group.long 0x2C8++0x3 line.long 0x0 "MCAN3_CFG_TXESC" bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7" rgroup.long 0x2CC++0x3 line.long 0x0 "MCAN3_CFG_TXBRP" hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending" group.long 0x2D0++0x7 line.long 0x0 "MCAN3_CFG_TXBAR" hexmask.long 0x0 0.--31. 1. "AR,Add request" line.long 0x4 "MCAN3_CFG_TXBCR" hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request" rgroup.long 0x2D8++0x7 line.long 0x0 "MCAN3_CFG_TXBTO" hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred" line.long 0x4 "MCAN3_CFG_TXBCF" hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished" group.long 0x2E0++0x13 line.long 0x0 "MCAN3_CFG_TXBTIE" hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable" line.long 0x4 "MCAN3_CFG_TXBCIE" hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable" line.long 0x8 "MCAN3_CFG_RES14" line.long 0xC "MCAN3_CFG_RES15" line.long 0x10 "MCAN3_CFG_TXEFC" hexmask.long.byte 0x10 24.--29. 1. "EFWM,Event FIFO Watermark" hexmask.long.byte 0x10 16.--21. 1. "EFS,Event FIFO Size" hexmask.long.word 0x10 2.--15. 1. "EFSA,Event FIFO Start Address" rgroup.long 0x2F4++0x7 line.long 0x0 "MCAN3_CFG_TXEFS" bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1" bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1" hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index" newline hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index" hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO FIll Level" line.long 0x4 "MCAN3_CFG_TXEFA" hexmask.long.byte 0x4 0.--4. 1. "EFAI,Event FIFO Acknowledge Index" group.long 0x2FC++0x3 line.long 0x0 "MCAN3_CFG_RES16" tree.end tree "MCAN3_ECC" base ad:0x52703000 rgroup.long 0x0++0x3 line.long 0x0 "MCAN3_ECC_REV" bitfld.long 0x0 30.--31. "SCHEME,Scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODULE_ID,Module ID" newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL version" bitfld.long 0x0 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom version" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor version" group.long 0x8++0x3 line.long 0x0 "MCAN3_ECC_VECTOR" bitfld.long 0x0 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field." "0,1" hexmask.long.byte 0x0 16.--23. 1. "RD_SVBUS_ADDR,Read address" bitfld.long 0x0 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status" rgroup.long 0xC++0x3 line.long 0x0 "MCAN3_ECC_STAT" hexmask.long.word 0x0 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator" group.long 0x14++0xF line.long 0x0 "MCAN3_ECC_CTRL" hexmask.long.tbyte 0x0 9.--31. 1. "NU3,TI Internal : Reserved" bitfld.long 0x0 8. "CHECK_TIMEOUT,TI Internal : Check timeout" "0,1" bitfld.long 0x0 7. "CHECK_PARITY,TI Internal : Check Parity" "0,1" newline bitfld.long 0x0 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1" bitfld.long 0x0 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM read" "0,1" bitfld.long 0x0 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1" newline bitfld.long 0x0 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1" bitfld.long 0x0 2. "EN_RMW,TI Internal : Enable rmw" "0,1" bitfld.long 0x0 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1" newline bitfld.long 0x0 0. "ECC_EN,TI Internal : Enable ECC" "0,1" line.long 0x4 "MCAN3_ECC_ERR_CTRL1" hexmask.long 0x4 0.--31. 1. "ECC_ROW,TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set" line.long 0x8 "MCAN3_ECC_ERR_CTRL2" hexmask.long.word 0x8 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced" hexmask.long.word 0x8 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set" line.long 0xC "MCAN3_ECC_ERR_STAT1" hexmask.long.word 0xC 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error" bitfld.long 0xC 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing." "0,1" bitfld.long 0xC 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing." "0,1,2,3" newline bitfld.long 0xC 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing." "0,1" bitfld.long 0xC 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing." "0,1" newline bitfld.long 0xC 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" bitfld.long 0xC 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing." "0,1,2,3" rgroup.long 0x24++0x3 line.long 0x0 "MCAN3_ECC_ERR_STAT2" hexmask.long 0x0 0.--31. 1. "ECC_ROW,TI Internal : Row address where the single or double-bit error has occurred" group.long 0x28++0x3 line.long 0x0 "MCAN3_ECC_ERR_STAT3" hexmask.long.tbyte 0x0 10.--31. 1. "NU6,TI Internal : Reserved" bitfld.long 0x0 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1" hexmask.long.byte 0x0 2.--8. 1. "NU5,TI Internal : Reserved" newline bitfld.long 0x0 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1" rbitfld.long 0x0 0. "NU4,TI Internal : Reserved" "0,1" group.long 0x3C++0x3 line.long 0x0 "MCAN3_ECC_SEC_EOI_REG" bitfld.long 0x0 0. "SEC_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing reading this bit will return 0." "0,1" rgroup.long 0x40++0x3 line.long 0x0 "MCAN3_ECC_SEC_STATUS_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x80++0x3 line.long 0x0 "MCAN3_ECC_SEC_ENABLE_SET_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0xC0++0x3 line.long 0x0 "MCAN3_ECC_SEC_ENABLE_CLR_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x13C++0x3 line.long 0x0 "MCAN3_ECC_DED_EOI_REG" bitfld.long 0x0 0. "DED_EOI_WR,EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing reading this bit will return 0." "0,1" rgroup.long 0x140++0x3 line.long 0x0 "MCAN3_ECC_DED_STATUS_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend." "0,1" bitfld.long 0x0 0. "DED_PEND,Interrupt Pending Status for msgmem_pend." "0,1" group.long 0x180++0x3 line.long 0x0 "MCAN3_ECC_DED_ENABLE_SET_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" group.long 0x1C0++0x3 line.long 0x0 "MCAN3_ECC_DED_ENABLE_CLR_REG0" bitfld.long 0x0 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x0 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" group.long 0x200++0xF line.long 0x0 "MCAN3_ECC_AGGR_ENABLE_SET" bitfld.long 0x0 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" bitfld.long 0x0 0. "PARITY,Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field." "0,1" line.long 0x4 "MCAN3_ECC_AGGR_ENABLE_CLR" bitfld.long 0x4 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" bitfld.long 0x4 0. "PARITY,Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0." "0,1" line.long 0x8 "MCAN3_ECC_AGGR_STATUS_SET" bitfld.long 0x8 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" bitfld.long 0x8 0.--1. "PARITY,Interrupt status set for parity errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" line.long 0xC "MCAN3_ECC_AGGR_STATUS_CLR" bitfld.long 0xC 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" bitfld.long 0xC 0.--1. "PARITY,Interrupt status clear for parity errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field." "0,1,2,3" tree.end tree "MCAN3_MSG_RAM" base ad:0x52630000 group.long 0x0++0x3 line.long 0x0 "MCAN3_MSG_RAM_START" hexmask.long 0x0 0.--31. 1. "START,MCAN message mem Start address" tree.end tree.end tree.end tree "MCRC" base ad:0x35000000 group.long 0x0++0x3 line.long 0x0 "MCRC0_CRC_CTRL0" bitfld.long 0x0 15. "CH2_CRC_SEL2,Refer 'CH2_DW_SEL' field description" "0,1" newline bitfld.long 0x0 14. "CH2_BYTE_SWAP,BYTE SWAP Enable across Data Size0 ? Byte Swap Disabled1 ? Byte Swap enabled." "0,1" newline bitfld.long 0x0 13. "CH2_BIT_SWAP,msb/lsb SWAPPING 0 ? msb (most significant bit First)1 ? lsb (least significant bit First)" "0,1" newline bitfld.long 0x0 11.--12. "CH2_CRC_SEL,CRC type select. {CH1_CRC_SEL2 CH1_CRC_SEL[1:0]}000 ? CRC-64001 - CRC-16010 ? CRC-32100 - VDA CAN SAE-J1850 CRC-8101 - H2F Autosar 4.0110 - CASTAGNOLI iSCSI111 / 011 - E2E Profile 4" "0,1,2,3" newline bitfld.long 0x0 9.--10. "CH2_DW_SEL,CRC Data Size select.000 ? 64 bit Data Size001 - 16 bit Data Size010 ? 32 Bit Data Size" "0,1,2,3" newline bitfld.long 0x0 8. "CH2_PSA_SWREST,Channel 2 PSA Software Reset. When set the PSA SignatureRegister is reset to all zero. Software reset does not reset softwarereset bit itself. Therefore CPU is required to clear this bit by writinga ?0?.0 = PSA Signature Register not.." "0: PSA Signature Register not reset1 = PSA..,?" newline bitfld.long 0x0 7. "CH1_CRC_SEL2,Refer 'CH1_DW_SEL' field description" "0,1" newline bitfld.long 0x0 6. "CH1_BYTE_SWAP,BYTE SWAP Enable across Data Size0 ? Byte Swap Disabled1 ? Byte Swap enabled." "0,1" newline bitfld.long 0x0 5. "CH1_BIT_SWAP,msb/lsb SWAPPING 0 ? msb (most significant bit First)1 ? lsb (least significant bit First)" "0,1" newline bitfld.long 0x0 3.--4. "CH1_CRC_SEL,CRC type select. {CH1_CRC_SEL2 CH1_CRC_SEL[1:0]}000 ? CRC-64001 - CRC-16010 ? CRC-32100 - VDA CAN SAE-J1850 CRC-8101 - H2F Autosar 4.0110 - CASTAGNOLI iSCSI111 / 011 - E2E Profile 4" "0,1,2,3" newline bitfld.long 0x0 1.--2. "CH1_DW_SEL,CRC Data Size select.000 ? 64 bit Data Size001 - 16 bit Data Size010 ? 32 Bit Data Size" "0,1,2,3" newline bitfld.long 0x0 0. "CH1_PSA_SWREST,Channel 1 PSA Software Reset. When set the PSA SignatureRegister is reset to all zero. Software reset does not reset softwarereset bit itself. Therefore CPU is required to clear this bit by writinga ?0?.0 = PSA Signature Register not.." "0: PSA Signature Register not reset1 = PSA..,?" group.long 0x8++0x3 line.long 0x0 "MCRC0_CRC_CTRL1" hexmask.long 0x0 1.--31. 1. "RESERVED1,Not Defined" newline bitfld.long 0x0 0. "PWDN,Power Down. When set MCRC moduleMCRC Module is put inpower down mode.0 = MCRC is not in power down mode1 = MCRC is in power down mode" "0: MCRC is not in power down mode1 = MCRC is in..,?" group.long 0x10++0x3 line.long 0x0 "MCRC0_CRC_CTRL2" hexmask.long.byte 0x0 26.--31. 1. "RESERVED5,Not Defined" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED4,Not Defined" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED3,Not Defined" newline bitfld.long 0x0 8.--9. "CH2_MODE,Channel 2 Mode:0 0 = Data Capture mode. In this mode the PSA Signature Registerdoes not compress data when it is written. Any datawritten to PSA Signature Register is simply captured byPSA Signature Register without any compression. Thismode.." "0: reserved1,1: Full-CPU mode,?,?" newline rbitfld.long 0x0 5.--7. "RESERVED2,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "CH1_TRACEEN,Channel 1 Data Trace Enable. When set the channel is put intodata trace mode. The channel snoops on the CPU VBUSM ITCM DTCM buses for any read transaction. Any read data onthese buses is compressed by the PSA Signature Register. Whensuspend.." "0: Data Trace disable1 = Data Trace enable,?" newline rbitfld.long 0x0 2.--3. "RESERVED1,Not Defined" "0,1,2,3" newline bitfld.long 0x0 0.--1. "CH1_MODE,Channel 1 Mode:0 0 = Data Capture mode. In this mode the PSA Signature Registerdoes not compress data when it is written. Any datawritten to PSA Signature Register is simply captured byPSA Signature Register without any compression. Thismode.." "0: reserved1,1: Full-CPU mode,?,?" group.long 0x18++0x3 line.long 0x0 "MCRC0_CRC_INTS" rbitfld.long 0x0 29.--31. "RESERVED5,Not Defined" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 21.--24. 1. "RESERVED4,Not Defined" newline hexmask.long.byte 0x0 13.--16. 1. "RESERVED3,Not Defined" newline bitfld.long 0x0 12. "CH2_TIMEOUTENS,Channel 2 Timeout Interrupt Enable Bit. Writing a one to thisbit enable the timeout interrupt. Writing a zero has no effect.Reading from this bit gives the status (interrupt enable/disable).User and privileged mode read:0 = Timeout.." "0: Has no effect1 = Timeout Interrupt enable,?" newline bitfld.long 0x0 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit. Writing a one tothis bit enable the underrun interrupt. Writing a zero has no effect.Reading from this bit gives the status (interrupt enable/disable).User and privileged mode read:0 = Underrun.." "0: Has no effect1 = Underrun Interrupt enable,?" newline bitfld.long 0x0 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit. Writing a one to thisbit enable the overrun interrupt. Writing a zero has no effect.Reading from this bit gives the status (interrupt enable/disable).User and privileged mode read:0 = Overrun Interrupt.." "0: Has no effect1 = Overrun Interrupt enable,?" newline bitfld.long 0x0 9. "CH2_CRCFAILENS,Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to thisbit enable the CRC fail interrupt. Writing a zero has no effect.Reading from this bit gives the status (interrupt enable/disable).User and privileged mode read:0 = CRC Fail.." "0: Has no effect1 = CRC Fail Interrupt enable,?" newline hexmask.long.byte 0x0 5.--8. 1. "RESERVED2,Not Defined" newline bitfld.long 0x0 4. "CH1_TIMEOUTENS,Channel 1 Timeout Interrupt Enable Bit. Writing a one to thisbit enable the timeout interrupt. Writing a zero has no effect.Reading from this bit gives the status (interrupt enable/disable).User and privileged mode read:0 = Timeout.." "0: Has no effect1 = Timeout Interrupt enable,?" newline bitfld.long 0x0 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit. Writing a one tothis bit enable the underrun interrupt. Writing a zero has no effect.Reading from this bit gives the status (interrupt enable/disable).User and privileged mode read:0 = Underrun.." "0: Has no effect1 = Underrun Interrupt enable,?" newline bitfld.long 0x0 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit. Writing a one to thisbit enable the overrun interrupt. Writing a zero has no effect.Reading from this bit gives the status (interrupt enable/disable).User and privileged mode read:0 = Overrun Interrupt.." "0: Has no effect1 = Overrun Interrupt enable,?" newline bitfld.long 0x0 1. "CH1_CRCFAILENS,Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to thisbit enable the CRC fail interrupt. Writing a zero has no effect.Reading from this bit gives the status (interrupt enable/disable).User and privileged mode read:0 = CRC Fail.." "0: Has no effect1 = CRC Fail Interrupt enable,?" newline rbitfld.long 0x0 0. "RESERVED1,Not Defined" "0,1" group.long 0x20++0x3 line.long 0x0 "MCRC0_CRC_INTR" rbitfld.long 0x0 29.--31. "RESERVED5,Not Defined" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 21.--24. 1. "RESERVED4,Not Defined" newline hexmask.long.byte 0x0 13.--16. 1. "RESERVED3,Not Defined" newline bitfld.long 0x0 12. "CH2_TIMEOUTENR,Channel 2 Timeout Interrupt Disable Bit. Writing a one to thisbit disable the timeout interrupt. Writing a zero has no effect.Reading from this bit gives the status (interrupt enable/disable).User and privileged mode read:0 = Timeout.." "0: Has no effect1 = Timeout Interrupt disable,?" newline bitfld.long 0x0 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit. Writing a one tothis bit disable the underrun interrupt. Writing a zero has noeffect. Reading from this bit gives the status (interrupt enable/dis-able).User and privileged mode read:0 = Underrun.." "0: Has no effect1 = Underrun Interrupt disable,?" newline bitfld.long 0x0 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit. Writing a one to thisbit disable the overrun interrupt. Writing a zero has no effect.Reading from this bit gives the status (interrupt enable/disable).User and privileged mode read:0 = Overrun.." "0: Has no effect1 = Overrun Interrupt disable,?" newline bitfld.long 0x0 9. "CH2_CRCFAILENR,Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to thisbit disable the CRC fail interrupt. Writing a zero has no effect.Reading from this bit gives the status (interrupt enable/disable).User and privileged mode read:0 = CRC Fail.." "0: Has no effect1 = CRC Fail Interrupt disable,?" newline hexmask.long.byte 0x0 5.--8. 1. "RESERVED2,Not Defined" newline bitfld.long 0x0 4. "CH1_TIMEOUTENR,Channel 1 Timeout Interrupt Disable Bit. Writing a one to thisbit disable the timeout interrupt. Writing a zero has no effect.Reading from this bit gives the status (interrupt enable/disable).User and privileged mode read:0 = Timeout.." "0: Has no effect1 = Timeout Interrupt disable,?" newline bitfld.long 0x0 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit. Writing a one tothis bit disable the underrun interrupt. Writing a zero has noeffect. Reading from this bit gives the status (interrupt enable/dis-able).User and privileged mode read:0 = Underrun.." "0: Has no effect1 = Underrun Interrupt disable,?" newline bitfld.long 0x0 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit. Writing a one to thisbit disable the overrun interrupt. Writing a zero has no effect.Reading from this bit gives the status (interrupt enable/disable).User and privileged mode read:0 = Overrun.." "0: Has no effect1 = Overrun Interrupt disable,?" newline bitfld.long 0x0 1. "CH1_CRCFAILENR,Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to thisbit disable the CRC fail interrupt. Writing a zero has no effect.Reading from this bit gives the status (interrupt enable/disable).User and privileged mode read:0 = CRC Fail.." "0: Has no effect1 = CRC Fail Interrupt disable,?" newline rbitfld.long 0x0 0. "RESERVED1,Not Defined" "0,1" group.long 0x28++0x3 line.long 0x0 "MCRC0_CRC_STATUS_REG" rbitfld.long 0x0 29.--31. "RESERVED5,Not Defined" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 21.--24. 1. "RESERVED4,Not Defined" newline hexmask.long.byte 0x0 13.--16. 1. "RESERVED3,Not Defined" newline bitfld.long 0x0 12. "CH2_TIMEOUT,Channel 2 CRC Timeout Status Flag. This bit is cleared bywriting a ?1? to it only. Writing ?0? has no effect. This bit is set inAUTO mode.0 = No timeout interrupt is active1 = Timeout interrupt is active" "0: No timeout interrupt is active1 = Timeout..,?" newline bitfld.long 0x0 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag. This bit is cleared bywriting a ?1? to it only. Writing ?0? has no effect. This bit is set inAUTO mode only0 = No underrun interrupt is active1 = Underrun interrupt is active" "0,1" newline bitfld.long 0x0 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag. This bit is cleared bywriting a ?1? to it only. Writing ?0? has no effect. This bit is set inAUTO mode0 = No overrun interrupt is active1 = Overrun interrupt is active" "0,1" newline bitfld.long 0x0 9. "CH2_CRCFAIL,Channel 2 CRC Compare Fail Status Flag. This bit is clearedby writing a ?1? to it only. Writing ?0? has no effect. This bit is setin AUTO mode only.0 = No CRC compare fail interrupt is active1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active1 = CRC..,?" newline hexmask.long.byte 0x0 5.--8. 1. "RESERVED2,Not Defined" newline bitfld.long 0x0 4. "CH1_TIMEOUT,Channel 1 CRC Timeout Status Flag. This bit is cleared bywriting a ?1? to it only. Writing ?0? has no effect. This bit is set inAUTO mode.0 = No timeout interrupt is active1 = Timeout interrupt is active" "0: No timeout interrupt is active1 = Timeout..,?" newline bitfld.long 0x0 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag. This bit is cleared bywriting a ?1? to it only. Writing ?0? has no effect. This bit is set inAUTO mode only0 = No underrun interrupt is active1 = Underrun interrupt is active" "0,1" newline bitfld.long 0x0 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag. This bit is cleared bywriting a ?1? to it only. Writing ?0? has no effect. This bit is set inAUTO mode0 = No overrun interrupt is active1 = Overrun interrupt is active" "0,1" newline bitfld.long 0x0 1. "CH1_CRCFAIL,Channel 1 CRC Compare Fail Status Flag. This bit is clearedby writing a ?1? to it only. Writing ?0? has no effect. This bit is setin AUTO mode only.0 = No CRC compare fail interrupt is active1 = CRC compare fail interrupt is active" "0: No CRC compare fail interrupt is active1 = CRC..,?" newline rbitfld.long 0x0 0. "RESERVED1,Not Defined" "0,1" group.long 0x30++0x3 line.long 0x0 "MCRC0_CRC_INT_OFFSET_REG" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "OFSTREG,CRC Interrupt Offset. This register indicates the highest prioritypending interrupt vector address. Reading the offset register auto-matically clear the respective interrupt flag. Please referenceTable 1?3. for details." rgroup.long 0x38++0x3 line.long 0x0 "MCRC0_CRC_BUSY" hexmask.long.byte 0x0 25.--31. 1. "RESERVED4,Not Defined" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED3,Not Defined" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED2,Not Defined" newline bitfld.long 0x0 8. "CH2_BUSY,Ch2_BUSY. During AUTO mode the busy flag is set when thefirst data pattern of the block is compressed and remains set untilthe the last data pattern of the block is compressed. The flag iscleared when the last data pattern of the block is.." "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED1,Not Defined" newline bitfld.long 0x0 0. "CH1_BUSY,CH1_BUSY. During AUTO mode the busy flag is set when thefirst data pattern of the block is compressed and remains set untilthe the last data pattern of the block is compressed. The flag iscleared when the last data pattern of the block is.." "0,1" group.long 0x40++0x13 line.long 0x0 "MCRC0_CRC_PCOUNT_REG1" hexmask.long.word 0x0 20.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register. This register con-tains the number of data patterns in one sector to be compressedbefore a CRC is performed." line.long 0x4 "MCRC0_CRC_SCOUNT_REG1" hexmask.long.word 0x4 16.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register. This register con-tains the number of sectors in one block of memory." line.long 0x8 "MCRC0_CRC_CURSEC_REG1" hexmask.long.word 0x8 16.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.word 0x8 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register. In AUTO mode thisregister contains the current sector number of which the signatureverification fails. The sector counter is a free running up counter.When a sector fails the erroneous sector number is.." line.long 0xC "MCRC0_CRC_WDTOPLD1" hexmask.long.byte 0xC 24.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.tbyte 0xC 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register. Thisregister contains the number of clock cycles within which theDMA must transfer the next block of data patterns." line.long 0x10 "MCRC0_CRC_BCTOPLD1" hexmask.long.byte 0x10 24.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Regis-ter. This register contains the number of clock cycles withinwhich the CRC for an entire block needs to complete before atimeout interrupt is generated." group.long 0x60++0xF line.long 0x0 "MCRC0_PSA_SIGREGL1" hexmask.long 0x0 0.--31. 1. "PSASIG1_31_0,Channel 1 PSA Signature Low Register. This register containsthe value stored at PSASIG1[31:0] register." line.long 0x4 "MCRC0_PSA_SIGREGH1" hexmask.long 0x4 0.--31. 1. "PSA_SIG1_63_32,Channel 1 PSA Signature High Register. This register containsthe value stored at PSASIG1[63:32] register." line.long 0x8 "MCRC0_CRC_REGL1" hexmask.long 0x8 0.--31. 1. "CRC1_31_0,Channel 1 CRC Value Low Register. This register contains thecurrent known good signature value stored at CRC1[31:0] regis-ter." line.long 0xC "MCRC0_CRC_REGH1" hexmask.long 0xC 0.--31. 1. "CRC1_63_32,Channel 1 CRC Value High Register. This register contains thecurrent known good signature value stored at CRC1[63:32] regis-ter." rgroup.long 0x70++0xF line.long 0x0 "MCRC0_PSA_SECSIGREGL1" hexmask.long 0x0 0.--31. 1. "PSASECSIG1_31_0,Channel 1 PSA Sector Signature Low Register. This registercontains the value stored at PSASECSIG1[31:0] register." line.long 0x4 "MCRC0_PSA_SECSIGREGH1" hexmask.long 0x4 0.--31. 1. "PSASECSIG1_63_32,Channel 1 PSA Sector Signature High Register. This registercontains the value stored at PSASECSIG1[63:32] register." line.long 0x8 "MCRC0_RAW_DATAREGL1" hexmask.long 0x8 0.--31. 1. "RAW_DATA1_31_0,Channel 1 Raw Data Low Register. This register contains bit31:0 of the un-compressed raw data." line.long 0xC "MCRC0_RAW_DATAREGH1" hexmask.long 0xC 0.--31. 1. "RAW_DATA1_63_32,Channel 1 Raw Data High Register. This register contains bit63:32 of the un-compressed raw data." group.long 0x80++0x13 line.long 0x0 "MCRC0_CRC_PCOUNT_REG2" hexmask.long.word 0x0 20.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.tbyte 0x0 0.--19. 1. "CRC_PAT_COUNT2,Channel 2 Pattern Counter Preload Register. This register con-tains the number of data patterns in one sector to be compressedbefore a CRC is performed." line.long 0x4 "MCRC0_CRC_SCOUNT_REG2" hexmask.long.word 0x4 16.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.word 0x4 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register. This register con-tains the number of sectors in one block of memory." line.long 0x8 "MCRC0_CRC_CURSEC_REG2" hexmask.long.word 0x8 16.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.word 0x8 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register. In AUTO mode thisregister contains the current sector number of which the signatureverification fails. The sector counter is a free running up counter.When a sector fails the erroneous sector number is.." line.long 0xC "MCRC0_CRC_WDTOPLD2" hexmask.long.byte 0xC 24.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.tbyte 0xC 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register. Thisregister contains the number of clock cycles within which theDMA must transfer the next block of data patterns." line.long 0x10 "MCRC0_CRC_BCTOPLD2" hexmask.long.byte 0x10 24.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Regis-ter. This register contains the number of clock cycles withinwhich the CRC for an entire block needs to complete before atimeout interrupt is generated." group.long 0xA0++0xF line.long 0x0 "MCRC0_PSA_SIGREGL2" hexmask.long 0x0 0.--31. 1. "PSASIG2_31_0,Channel 2 PSA Signature Low Register. This register containsthe value stored at PSASIG2[31:0] register." line.long 0x4 "MCRC0_PSA_SIGREGH2" hexmask.long 0x4 0.--31. 1. "PSA_SIG2_63_32,Channel 2 PSA Signature High Register. This register containsthe value stored at PSASIG2[63:32] register." line.long 0x8 "MCRC0_CRC_REGL2" hexmask.long 0x8 0.--31. 1. "CRC2_31_0,Channel 2 CRC Value Low Register. This register contains thecurrent known good signature value stored at CRC2[31:0] regis-ter." line.long 0xC "MCRC0_CRC_REGH2" hexmask.long 0xC 0.--31. 1. "CRC2_63_32,Channel 2 CRC Value High Register. This register contains thecurrent known good signature value stored at CRC2[63:32] regis-ter." rgroup.long 0xB0++0x23 line.long 0x0 "MCRC0_PSA_SECSIGREGL2" hexmask.long 0x0 0.--31. 1. "PSASECSIG2_31_0,Channel 2 PSA Sector Signature Low Register. This registercontains the value stored at PSASECSIG2[31:0] register." line.long 0x4 "MCRC0_PSA_SECSIGREGH2" hexmask.long 0x4 0.--31. 1. "PSASECSIG2_63_32,Channel 2 PSA Sector Signature High Register. This registercontains the value stored at PSASECSIG2[63:32] register." line.long 0x8 "MCRC0_RAW_DATAREGL2" hexmask.long 0x8 0.--31. 1. "RAW_DATA2_31_0,Channel 2 Raw Data Low Register. This register contains bit31:0 of the un-compressed raw data." line.long 0xC "MCRC0_RAW_DATAREGH2" hexmask.long 0xC 0.--31. 1. "RAW_DATA2_63_32,Channel 2 Raw Data High Register. This register contains bit63:32 of the un-compressed raw data." line.long 0x10 "MCRC0_CRC_PCOUNT_REG3" hexmask.long.word 0x10 20.--31. 1. "RESERVED1,Not Defined" line.long 0x14 "MCRC0_CRC_SCOUNT_REG3" hexmask.long.word 0x14 16.--31. 1. "RESERVED1,Not Defined" line.long 0x18 "MCRC0_CRC_CURSEC_REG3" hexmask.long.word 0x18 16.--31. 1. "RESERVED1,Not Defined" line.long 0x1C "MCRC0_CRC_WDTOPLD3" hexmask.long.byte 0x1C 24.--31. 1. "RESERVED1,Not Defined" line.long 0x20 "MCRC0_CRC_BCTOPLD3" hexmask.long.byte 0x20 24.--31. 1. "RESERVED1,Not Defined" group.long 0xE0++0x1F line.long 0x0 "MCRC0_PSA_SIGREGL3" line.long 0x4 "MCRC0_PSA_SIGREGH3" line.long 0x8 "MCRC0_CRC_REGL3" line.long 0xC "MCRC0_CRC_REGH3" line.long 0x10 "MCRC0_PSA_SECSIGREGL3" line.long 0x14 "MCRC0_PSA_SECSIGREGH3" line.long 0x18 "MCRC0_RAW_DATAREGL3" line.long 0x1C "MCRC0_RAW_DATAREGH3" rgroup.long 0x100++0x13 line.long 0x0 "MCRC0_CRC_PCOUNT_REG4" hexmask.long.word 0x0 20.--31. 1. "RESERVED1,Not Defined" line.long 0x4 "MCRC0_CRC_SCOUNT_REG4" hexmask.long.word 0x4 16.--31. 1. "RESERVED1,Not Defined" line.long 0x8 "MCRC0_CRC_CURSEC_REG4" hexmask.long.word 0x8 16.--31. 1. "RESERVED1,Not Defined" line.long 0xC "MCRC0_CRC_WDTOPLD4" hexmask.long.byte 0xC 24.--31. 1. "RESERVED1,Not Defined" line.long 0x10 "MCRC0_CRC_BCTOPLD4" hexmask.long.byte 0x10 24.--31. 1. "RESERVED1,Not Defined" group.long 0x120++0x23 line.long 0x0 "MCRC0_PSA_SIGREGL4" line.long 0x4 "MCRC0_PSA_SIGREGH4" line.long 0x8 "MCRC0_CRC_REGL4" line.long 0xC "MCRC0_CRC_REGH4" line.long 0x10 "MCRC0_PSA_SECSIGREGL4" line.long 0x14 "MCRC0_PSA_SECSIGREGH4" line.long 0x18 "MCRC0_RAW_DATAREGL4" line.long 0x1C "MCRC0_RAW_DATAREGH4" line.long 0x20 "MCRC0_MCRC_BUS_SEL" bitfld.long 0x20 2. "MEN,MEn. Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled" "0: Tracing of VBUSM master bus has been disabled,1: Tracing of VBUSM master bus has been enabled" newline bitfld.long 0x20 1. "DTCMEN,DTCMEn. Enable/disables the tracing of data TCM0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled" "0,1" newline bitfld.long 0x20 0. "ITCMEN,ITCMEn. Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled" "0: Tracing of ITCM bus has been disabled,1: Tracing of ITCM bus has been enabled" rgroup.long 0x144++0x3 line.long 0x0 "MCRC0_MCRC_RESERVED" hexmask.long 0x0 0.--31. 1. "NU68,0x144 to 0x1FF is reserved area." tree.end tree "MCSPI" base ad:0x0 tree "MCSPI0" base ad:0x52200000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI0_HL_REV" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "MCSPI0_HL_HWINFO" hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI0_HL_SYSCONFIG" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI0_REVISION" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x3 line.long 0x0 "MCSPI0_SYSCONFIG" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI0_SYSSTATUS" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI0_IRQSTATUS" hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x0 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" rbitfld.long 0x0 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" rbitfld.long 0x0 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" rbitfld.long 0x0 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0x4 "MCSPI0_IRQENABLE" hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0x4 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" rbitfld.long 0x4 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" rbitfld.long 0x4 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" rbitfld.long 0x4 7. "RESERVED,Reads return 0" "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x8 "MCSPI0_WAKEUPENABLE" hexmask.long 0x8 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0xC "MCSPI0_SYST" hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0xC 11. "SSB,Set status bit" "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x10 "MCSPI0_MODULCTRL" hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x10 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x10 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode" "0,1" newline bitfld.long 0x10 2. "MS,Master/ Slave" "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x10 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x14 "MCSPI0_CH0CONF" rbitfld.long 0x14 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x14 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x14 18. "IS,Input Select" "0,1" bitfld.long 0x14 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x14 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x14 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length" bitfld.long 0x14 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x14 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI0_CH0STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI0_CH0CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI0_TX0" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI0_RX0" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0x3 line.long 0x0 "MCSPI0_CH1CONF" rbitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI0_CH1STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI0_CH1CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI0_TX1" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI0_RX1" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0x3 line.long 0x0 "MCSPI0_CH2CONF" rbitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI0_CH2STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI0_CH2CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI0_TX2" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI0_RX2" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0x3 line.long 0x0 "MCSPI0_CH3CONF" rbitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI0_CH3STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI0_CH3CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI0_TX3" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI0_RX3" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "MCSPI0_XFERLEVEL" hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "MCSPI0_DAFTX" hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI0_DAFRX" hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." tree.end tree "MCSPI1" base ad:0x52201000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI1_HL_REV" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "MCSPI1_HL_HWINFO" hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI1_HL_SYSCONFIG" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI1_REVISION" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x3 line.long 0x0 "MCSPI1_SYSCONFIG" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI1_SYSSTATUS" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI1_IRQSTATUS" hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x0 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" rbitfld.long 0x0 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" rbitfld.long 0x0 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" rbitfld.long 0x0 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0x4 "MCSPI1_IRQENABLE" hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0x4 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" rbitfld.long 0x4 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" rbitfld.long 0x4 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" rbitfld.long 0x4 7. "RESERVED,Reads return 0" "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x8 "MCSPI1_WAKEUPENABLE" hexmask.long 0x8 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0xC "MCSPI1_SYST" hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0xC 11. "SSB,Set status bit" "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x10 "MCSPI1_MODULCTRL" hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x10 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x10 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode" "0,1" newline bitfld.long 0x10 2. "MS,Master/ Slave" "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x10 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x14 "MCSPI1_CH0CONF" rbitfld.long 0x14 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x14 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x14 18. "IS,Input Select" "0,1" bitfld.long 0x14 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x14 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x14 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length" bitfld.long 0x14 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x14 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI1_CH0STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI1_CH0CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI1_TX0" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI1_RX0" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0x3 line.long 0x0 "MCSPI1_CH1CONF" rbitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI1_CH1STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI1_CH1CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI1_TX1" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI1_RX1" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0x3 line.long 0x0 "MCSPI1_CH2CONF" rbitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI1_CH2STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI1_CH2CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI1_TX2" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI1_RX2" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0x3 line.long 0x0 "MCSPI1_CH3CONF" rbitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI1_CH3STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI1_CH3CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI1_TX3" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI1_RX3" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "MCSPI1_XFERLEVEL" hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "MCSPI1_DAFTX" hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI1_DAFRX" hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." tree.end tree "MCSPI2" base ad:0x52202000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI2_HL_REV" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "MCSPI2_HL_HWINFO" hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI2_HL_SYSCONFIG" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI2_REVISION" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x3 line.long 0x0 "MCSPI2_SYSCONFIG" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI2_SYSSTATUS" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI2_IRQSTATUS" hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x0 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" rbitfld.long 0x0 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" rbitfld.long 0x0 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" rbitfld.long 0x0 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0x4 "MCSPI2_IRQENABLE" hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0x4 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" rbitfld.long 0x4 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" rbitfld.long 0x4 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" rbitfld.long 0x4 7. "RESERVED,Reads return 0" "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x8 "MCSPI2_WAKEUPENABLE" hexmask.long 0x8 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0xC "MCSPI2_SYST" hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0xC 11. "SSB,Set status bit" "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x10 "MCSPI2_MODULCTRL" hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x10 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x10 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode" "0,1" newline bitfld.long 0x10 2. "MS,Master/ Slave" "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x10 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x14 "MCSPI2_CH0CONF" rbitfld.long 0x14 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x14 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x14 18. "IS,Input Select" "0,1" bitfld.long 0x14 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x14 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x14 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length" bitfld.long 0x14 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x14 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI2_CH0STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI2_CH0CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI2_TX0" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI2_RX0" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0x3 line.long 0x0 "MCSPI2_CH1CONF" rbitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI2_CH1STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI2_CH1CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI2_TX1" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI2_RX1" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0x3 line.long 0x0 "MCSPI2_CH2CONF" rbitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI2_CH2STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI2_CH2CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI2_TX2" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI2_RX2" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0x3 line.long 0x0 "MCSPI2_CH3CONF" rbitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI2_CH3STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI2_CH3CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI2_TX3" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI2_RX3" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "MCSPI2_XFERLEVEL" hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "MCSPI2_DAFTX" hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI2_DAFRX" hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." tree.end tree "MCSPI3" base ad:0x52203000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI3_HL_REV" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "MCSPI3_HL_HWINFO" hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI3_HL_SYSCONFIG" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI3_REVISION" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x3 line.long 0x0 "MCSPI3_SYSCONFIG" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI3_SYSSTATUS" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI3_IRQSTATUS" hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x0 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" rbitfld.long 0x0 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" rbitfld.long 0x0 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" rbitfld.long 0x0 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0x4 "MCSPI3_IRQENABLE" hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0x4 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" rbitfld.long 0x4 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" rbitfld.long 0x4 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" rbitfld.long 0x4 7. "RESERVED,Reads return 0" "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x8 "MCSPI3_WAKEUPENABLE" hexmask.long 0x8 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0xC "MCSPI3_SYST" hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0xC 11. "SSB,Set status bit" "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x10 "MCSPI3_MODULCTRL" hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x10 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x10 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode" "0,1" newline bitfld.long 0x10 2. "MS,Master/ Slave" "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x10 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x14 "MCSPI3_CH0CONF" rbitfld.long 0x14 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x14 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x14 18. "IS,Input Select" "0,1" bitfld.long 0x14 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x14 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x14 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length" bitfld.long 0x14 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x14 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI3_CH0STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI3_CH0CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI3_TX0" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI3_RX0" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0x3 line.long 0x0 "MCSPI3_CH1CONF" rbitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI3_CH1STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI3_CH1CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI3_TX1" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI3_RX1" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0x3 line.long 0x0 "MCSPI3_CH2CONF" rbitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI3_CH2STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI3_CH2CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI3_TX2" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI3_RX2" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0x3 line.long 0x0 "MCSPI3_CH3CONF" rbitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI3_CH3STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI3_CH3CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI3_TX3" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI3_RX3" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "MCSPI3_XFERLEVEL" hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "MCSPI3_DAFTX" hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI3_DAFRX" hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." tree.end tree "MCSPI4" base ad:0x52204000 rgroup.long 0x0++0x7 line.long 0x0 "MCSPI4_HL_REV" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish between old scheme and current" "0,1,2,3" bitfld.long 0x0 28.--29. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned" hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or.." bitfld.long 0x0 8.--10. "X_MAJOR,Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that.." line.long 0x4 "MCSPI4_HL_HWINFO" hexmask.long 0x4 7.--31. 1. "RSVD,Reserved These bits are initialized to zero and writes to them are ignored" bitfld.long 0x4 6. "RETMODE,This bit field indicates whether the retention mode is supported using the pin PIRFFRET" "0,1" hexmask.long.byte 0x4 1.--5. 1. "FFNBYTE,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account" bitfld.long 0x4 0. "USEFIFO,Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management" "0,1" group.long 0x10++0x3 line.long 0x0 "MCSPI4_HL_SYSCONFIG" bitfld.long 0x0 2.--3. "IDLEMODE,Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state" "0,1,2,3" bitfld.long 0x0 1. "FREEEMU,Sensitivity to emulation [debug] suspend input signal" "0,1" bitfld.long 0x0 0. "SOFTRESET,Software reset [Optional]" "0,1" rgroup.long 0x100++0x3 line.long 0x0 "MCSPI4_REVISION" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reads returns 0" hexmask.long.byte 0x0 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21" group.long 0x110++0x3 line.long 0x0 "MCSPI4_SYSCONFIG" hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 8.--9. "CLOCKACTIVITY,Clocks activity during wake up mode period" "0,1,2,3" rbitfld.long 0x0 5.--7. "RESERVED,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. "SIDLEMODE,Power management" "0,1,2,3" bitfld.long 0x0 2. "ENAWAKEUP,WakeUp feature control" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset During reads it always returns 0" "0,1" bitfld.long 0x0 0. "AUTOIDLE,Internal OCP Clock gating strategy" "0,1" rgroup.long 0x114++0x3 line.long 0x0 "MCSPI4_SYSSTATUS" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved for module specific status information Read returns 0" bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring" "0,1" group.long 0x118++0x17 line.long 0x0 "MCSPI4_IRQSTATUS" hexmask.long.word 0x0 18.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x0 17. "EOW,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT]" "0,1" bitfld.long 0x0 16. "WKS,Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" rbitfld.long 0x0 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 14. "RX3_FULL,Receiver register is full or almost full Only when Channel 3 is enabled" "0,1" newline bitfld.long 0x0 13. "TX3_UNDERFLOW,Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into.." "0,1" bitfld.long 0x0 12. "TX3_EMPTY,Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event" "0,1" rbitfld.long 0x0 11. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 10. "RX2_FULL,Receiver register full or almost full Channel 2" "0,1" bitfld.long 0x0 9. "TX2_UNDERFLOW,Transmitter register underflow Channel 2" "0,1" newline bitfld.long 0x0 8. "TX2_EMPTY,Transmitter register empty or almost empty Channel 2" "0,1" rbitfld.long 0x0 7. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x0 6. "RX1_FULL,Receiver register full or almost full Channel 1" "0,1" bitfld.long 0x0 5. "TX1_UNDERFLOW,Transmitter register underflow Channel 1" "0,1" bitfld.long 0x0 4. "TX1_EMPTY,Transmitter register empty or almost empty Channel 1" "0,1" newline bitfld.long 0x0 3. "RX0_OVERFLOW,Receiver register overflow [slave mode only] Channel 0" "0,1" bitfld.long 0x0 2. "RX0_FULL,Receiver register full or almost full Channel 0" "0,1" bitfld.long 0x0 1. "TX0_UNDERFLOW,Transmitter register underflow Channel 0" "0,1" bitfld.long 0x0 0. "TX0_EMPTY,Transmitter register empty or almost empty Channel 0" "0,1" line.long 0x4 "MCSPI4_IRQENABLE" hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reads return 0" bitfld.long 0x4 17. "EOW_ENABLE,End of Word count Interrupt Enable" "0,1" bitfld.long 0x4 16. "WKE,Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" rbitfld.long 0x4 15. "RESERVED,Reads returns 0" "0,1" bitfld.long 0x4 14. "RX3_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 3" "0,1" newline bitfld.long 0x4 13. "TX3_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 3" "0,1" bitfld.long 0x4 12. "TX3_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch3" "0,1" rbitfld.long 0x4 11. "RESERVED,Reads return 0" "0,1" bitfld.long 0x4 10. "RX2_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 2" "0,1" bitfld.long 0x4 9. "TX2_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 2" "0,1" newline bitfld.long 0x4 8. "TX2_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 2" "0,1" rbitfld.long 0x4 7. "RESERVED,Reads return 0" "0,1" bitfld.long 0x4 6. "RX1_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 1" "0,1" bitfld.long 0x4 5. "TX1_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 1" "0,1" bitfld.long 0x4 4. "TX1_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 1" "0,1" newline bitfld.long 0x4 3. "RX0_OVERFLOW_ENABLE,Receiver register Overflow Interrupt Enable Ch 0" "0,1" bitfld.long 0x4 2. "RX0_FULL_ENABLE,Receiver register Full Interrupt Enable Ch 0" "0,1" bitfld.long 0x4 1. "TX0_UNDERFLOW_ENABLE,Transmitter register Underflow Interrupt Enable Ch 0" "0,1" bitfld.long 0x4 0. "TX0_EMPTY_ENABLE,Transmitter register Empty Interrupt Enable Ch 0" "0,1" line.long 0x8 "MCSPI4_WAKEUPENABLE" hexmask.long 0x8 1.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x8 0. "WKEN,WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" line.long 0xC "MCSPI4_SYST" hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0xC 11. "SSB,Set status bit" "0,1" bitfld.long 0xC 10. "SPIENDIR,Set the direction of the SPIEN[3:0] lines and SPICLK line" "0,1" bitfld.long 0xC 9. "SPIDATDIR1,Set the direction of the SPIDAT[1]" "0,1" bitfld.long 0xC 8. "SPIDATDIR0,Set the direction of the SPIDAT[0]" "0,1" newline bitfld.long 0xC 7. "WAKD,SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit" "0,1" bitfld.long 0xC 6. "SPICLK,SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the.." "0,1" bitfld.long 0xC 5. "SPIDAT_1,SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 4. "SPIDAT_0,SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit.." "0,1" bitfld.long 0xC 3. "SPIEN_3,SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" newline bitfld.long 0xC 2. "SPIEN_2,SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 1. "SPIEN_1,SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" bitfld.long 0xC 0. "SPIEN_0,SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns.." "0,1" line.long 0x10 "MCSPI4_MODULCTRL" hexmask.long.tbyte 0x10 9.--31. 1. "RESERVED,Reads returns 0" bitfld.long 0x10 8. "FDAA,FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed.." "0,1" bitfld.long 0x10 7. "MOA,Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16" "0,1" bitfld.long 0x10 4.--6. "INITDLY,Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 3. "SYSTEM_TEST,Enables the system test mode" "0,1" newline bitfld.long 0x10 2. "MS,Master/ Slave" "0,1" bitfld.long 0x10 1. "PIN34,Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMO SOMI and SPICLK clock pin for spi transfers" "0,1" bitfld.long 0x10 0. "SINGLE,Single channel / Multi Channel [master mode only]" "0,1" line.long 0x14 "MCSPI4_CH0CONF" rbitfld.long 0x14 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x14 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x14 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x14 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x14 25.--26. "TCS0,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x14 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x14 23. "SBE,Start bit enable for SPI transfer" "0,1" bitfld.long 0x14 21.--22. "SPIENSLV,Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases" "0,1,2,3" bitfld.long 0x14 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x14 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x14 18. "IS,Input Select" "0,1" bitfld.long 0x14 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x14 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x14 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x14 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x14 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x14 7.--11. 1. "WL,SPI word length" bitfld.long 0x14 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x14 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x14 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x14 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x130++0x3 line.long 0x0 "MCSPI4_CH0STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x134++0x7 line.long 0x0 "MCSPI4_CH0CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI4_TX0" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 0 Data to transmit" rgroup.long 0x13C++0x3 line.long 0x0 "MCSPI4_RX0" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 0 Received Data" group.long 0x140++0x3 line.long 0x0 "MCSPI4_CH1CONF" rbitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS1,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x144++0x3 line.long 0x0 "MCSPI4_CH1STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x148++0x7 line.long 0x0 "MCSPI4_CH1CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI4_TX1" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 1 Data to transmit" rgroup.long 0x150++0x3 line.long 0x0 "MCSPI4_RX1" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 1 Received Data" group.long 0x154++0x3 line.long 0x0 "MCSPI4_CH2CONF" rbitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS2,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x158++0x3 line.long 0x0 "MCSPI4_CH2STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x15C++0x7 line.long 0x0 "MCSPI4_CH2CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI4_TX2" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 2 Data to transmit" rgroup.long 0x164++0x3 line.long 0x0 "MCSPI4_RX2" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 2 Received Data" group.long 0x168++0x3 line.long 0x0 "MCSPI4_CH3CONF" rbitfld.long 0x0 30.--31. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 29. "CLKG,Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider.." "0,1" bitfld.long 0x0 28. "FFER,FIFO enabled for receive:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 27. "FFEW,FIFO enabled for Transmit:Only one channel can have this bit field set" "0,1" bitfld.long 0x0 25.--26. "TCS3,Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock" "0,1,2,3" newline bitfld.long 0x0 24. "SBPOL,Start bit polarity" "0,1" bitfld.long 0x0 23. "SBE,Start bit enable for SPI transfer" "0,1" rbitfld.long 0x0 21.--22. "RESERVED,read returns 0" "0,1,2,3" bitfld.long 0x0 20. "FORCE,Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only]" "0,1" bitfld.long 0x0 19. "TURBO,Turbo mode" "0,1" newline bitfld.long 0x0 18. "IS,Input Select" "0,1" bitfld.long 0x0 17. "DPE1,Transmission Enable for data line 1 [SPIDATAGZEN[1]]" "0,1" bitfld.long 0x0 16. "DPE0,Transmission Enable for data line 0 [SPIDATAGZEN[0]]" "0,1" bitfld.long 0x0 15. "DMAR,DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel" "0,1" bitfld.long 0x0 14. "DMAW,DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel" "0,1" newline bitfld.long 0x0 12.--13. "TRM,Transmit/Receive modes" "0,1,2,3" hexmask.long.byte 0x0 7.--11. 1. "WL,SPI word length" bitfld.long 0x0 6. "EPOL,SPIEN polarity" "0,1" hexmask.long.byte 0x0 2.--5. 1. "CLKD,Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By.." bitfld.long 0x0 1. "POL,SPICLK polarity" "0,1" newline bitfld.long 0x0 0. "PHA,SPICLK phase" "0,1" rgroup.long 0x16C++0x3 line.long 0x0 "MCSPI4_CH3STAT" hexmask.long 0x0 7.--31. 1. "RESERVED,Read returns 0" bitfld.long 0x0 6. "RXFFF,Channel 'i' FIFO Receive Buffer Full Status" "0,1" bitfld.long 0x0 5. "RXFFE,Channel 'i' FIFO Receive Buffer Empty Status" "0,1" bitfld.long 0x0 4. "TXFFF,Channel 'i' FIFO Transmit Buffer Full Status" "0,1" bitfld.long 0x0 3. "TXFFE,Channel 'i' FIFO Transmit Buffer Empty Status" "0,1" newline bitfld.long 0x0 2. "EOT,Channel 'i' End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details" "0,1" bitfld.long 0x0 1. "TXS,Channel 'i' Transmitter Register Status" "0,1" bitfld.long 0x0 0. "RXS,Channel 'i' Receiver Register Status" "0,1" group.long 0x170++0x7 line.long 0x0 "MCSPI4_CH3CTRL" hexmask.long.word 0x0 16.--31. 1. "RESERVED,Read returns 0" hexmask.long.byte 0x0 8.--15. 1. "EXTCLK,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio" hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Read returns 0" bitfld.long 0x0 0. "EN,Channel Enable" "0,1" line.long 0x4 "MCSPI4_TX3" hexmask.long 0x4 0.--31. 1. "TDATA,Channel 3 Data to transmit" rgroup.long 0x178++0x3 line.long 0x0 "MCSPI4_RX3" hexmask.long 0x0 0.--31. 1. "RDATA,Channel 3 Received Data" group.long 0x17C++0x7 line.long 0x0 "MCSPI4_XFERLEVEL" hexmask.long.word 0x0 16.--31. 1. "WCNT,Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index" hexmask.long.byte 0x0 8.--15. 1. "AFL,Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at.." hexmask.long.byte 0x0 0.--7. 1. "AEL,Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is.." line.long 0x4 "MCSPI4_DAFTX" hexmask.long 0x4 0.--31. 1. "DAFTDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." rgroup.long 0x1A0++0x3 line.long 0x0 "MCSPI4_DAFRX" hexmask.long 0x0 0.--31. 1. "DAFRDATA,FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to '1' and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access.." tree.end tree.end tree "MPU" base ad:0x0 tree "MPU_HSM" base ad:0x40240000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_HSM_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_HSM_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_HSM_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_HSM_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_HSM_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_HSM_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_HSM_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_HSM_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_HSM_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_HSM_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_HSM_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_HSM_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_HSM_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_HSM_DTHE" base ad:0x40120000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_HSM_DTHE_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_HSM_DTHE_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_HSM_DTHE_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_HSM_DTHE_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_HSM_DTHE_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_HSM_DTHE_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_HSM_DTHE_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_HSM_DTHE_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_HSM_DTHE_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_DTHE_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_DTHE_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_HSM_DTHE_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_HSM_DTHE_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_HSM_DTHE_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_HSM_DTHE_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_HSM_DTHE_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_HSM_DTHE_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end base ad:0x0 tree "MPU_L2OCRAM" tree "MPU_L2OCRAM_BANK0" base ad:0x40020000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_L2OCRAM_BANK0_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_L2OCRAM_BANK0_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_L2OCRAM_BANK0_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_L2OCRAM_BANK0_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_L2OCRAM_BANK0_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_L2OCRAM_BANK0_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_L2OCRAM_BANK0_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_L2OCRAM_BANK0_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK0_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK0_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK0_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_L2OCRAM_BANK0_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_L2OCRAM_BANK0_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_L2OCRAM_BANK0_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_L2OCRAM_BANK1" base ad:0x40040000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_L2OCRAM_BANK1_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_L2OCRAM_BANK1_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_L2OCRAM_BANK1_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_L2OCRAM_BANK1_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_L2OCRAM_BANK1_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_L2OCRAM_BANK1_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_L2OCRAM_BANK1_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_L2OCRAM_BANK1_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK1_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK1_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK1_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_L2OCRAM_BANK1_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_L2OCRAM_BANK1_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_L2OCRAM_BANK1_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_L2OCRAM_BANK2" base ad:0x40060000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_L2OCRAM_BANK2_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_L2OCRAM_BANK2_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_L2OCRAM_BANK2_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_L2OCRAM_BANK2_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_L2OCRAM_BANK2_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_L2OCRAM_BANK2_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_L2OCRAM_BANK2_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_L2OCRAM_BANK2_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK2_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK2_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK2_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_L2OCRAM_BANK2_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_L2OCRAM_BANK2_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_L2OCRAM_BANK2_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_L2OCRAM_BANK3" base ad:0x40080000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_L2OCRAM_BANK3_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_L2OCRAM_BANK3_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_L2OCRAM_BANK3_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_L2OCRAM_BANK3_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_L2OCRAM_BANK3_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_L2OCRAM_BANK3_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_L2OCRAM_BANK3_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_L2OCRAM_BANK3_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK3_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK3_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_L2OCRAM_BANK3_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_L2OCRAM_BANK3_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_L2OCRAM_BANK3_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_L2OCRAM_BANK3_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree.end tree "MPU_MBOX_SRAM" base ad:0x40140000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_MBOX_SRAM_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_MBOX_SRAM_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_MBOX_SRAM_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_MBOX_SRAM_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_MBOX_SRAM_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_MBOX_SRAM_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_MBOX_SRAM_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_MBOX_SRAM_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_MBOX_SRAM_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_MBOX_SRAM_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_MBOX_SRAM_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_MBOX_SRAM_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_MBOX_SRAM_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_MBOX_SRAM_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_MBOX_SRAM_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_MBOX_SRAM_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_MBOX_SRAM_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_QSPI0" base ad:0x40160000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_QSPI0_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_QSPI0_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_QSPI0_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_QSPI0_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_QSPI0_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_QSPI0_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_QSPI0_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_QSPI0_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_QSPI0_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_QSPI0_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_QSPI0_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_QSPI0_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_QSPI0_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_QSPI0_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_QSPI0_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_QSPI0_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_QSPI0_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end base ad:0x0 tree "MPU_R5SS0" tree "MPU_R5SS0_CORE0_AHB" base ad:0x401C0000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_R5SS0_CORE0_AHB_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_R5SS0_CORE0_AHB_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_R5SS0_CORE0_AHB_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_R5SS0_CORE0_AHB_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_R5SS0_CORE0_AHB_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_R5SS0_CORE0_AHB_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_R5SS0_CORE0_AHB_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_R5SS0_CORE0_AHB_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AHB_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AHB_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AHB_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_R5SS0_CORE0_AHB_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_R5SS0_CORE0_AHB_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_R5SS0_CORE0_AHB_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_R5SS0_CORE0_AXIS" base ad:0x400A0000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_R5SS0_CORE0_AXIS_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_R5SS0_CORE0_AXIS_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_R5SS0_CORE0_AXIS_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_R5SS0_CORE0_AXIS_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_R5SS0_CORE0_AXIS_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_R5SS0_CORE0_AXIS_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_R5SS0_CORE0_AXIS_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_R5SS0_CORE0_AXIS_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AXIS_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AXIS_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE0_AXIS_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_R5SS0_CORE0_AXIS_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_R5SS0_CORE0_AXIS_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_R5SS0_CORE0_AXIS_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_R5SS0_CORE1_AHB" base ad:0x401E0000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_R5SS0_CORE1_AHB_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_R5SS0_CORE1_AHB_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_R5SS0_CORE1_AHB_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_R5SS0_CORE1_AHB_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_R5SS0_CORE1_AHB_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_R5SS0_CORE1_AHB_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_R5SS0_CORE1_AHB_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_R5SS0_CORE1_AHB_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AHB_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AHB_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AHB_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_R5SS0_CORE1_AHB_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_R5SS0_CORE1_AHB_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_R5SS0_CORE1_AHB_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_R5SS0_CORE1_AXIS" base ad:0x400C0000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_R5SS0_CORE1_AXIS_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_R5SS0_CORE1_AXIS_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_R5SS0_CORE1_AXIS_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_R5SS0_CORE1_AXIS_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_R5SS0_CORE1_AXIS_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_R5SS0_CORE1_AXIS_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_R5SS0_CORE1_AXIS_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_R5SS0_CORE1_AXIS_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AXIS_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AXIS_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS0_CORE1_AXIS_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_R5SS0_CORE1_AXIS_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_R5SS0_CORE1_AXIS_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_R5SS0_CORE1_AXIS_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree.end tree "MPU_R5SS1" tree "MPU_R5SS1_CORE0_AHB" base ad:0x40200000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_R5SS1_CORE0_AHB_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_R5SS1_CORE0_AHB_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_R5SS1_CORE0_AHB_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_R5SS1_CORE0_AHB_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_R5SS1_CORE0_AHB_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_R5SS1_CORE0_AHB_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_R5SS1_CORE0_AHB_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_R5SS1_CORE0_AHB_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AHB_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AHB_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AHB_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_R5SS1_CORE0_AHB_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_R5SS1_CORE0_AHB_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_R5SS1_CORE0_AHB_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_R5SS1_CORE0_AXIS" base ad:0x400E0000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_R5SS1_CORE0_AXIS_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_R5SS1_CORE0_AXIS_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_R5SS1_CORE0_AXIS_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_R5SS1_CORE0_AXIS_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_R5SS1_CORE0_AXIS_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_R5SS1_CORE0_AXIS_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_R5SS1_CORE0_AXIS_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_R5SS1_CORE0_AXIS_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AXIS_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AXIS_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE0_AXIS_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_R5SS1_CORE0_AXIS_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_R5SS1_CORE0_AXIS_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_R5SS1_CORE0_AXIS_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_R5SS1_CORE1_AHB" base ad:0x40220000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_R5SS1_CORE1_AHB_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_R5SS1_CORE1_AHB_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_R5SS1_CORE1_AHB_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_R5SS1_CORE1_AHB_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_R5SS1_CORE1_AHB_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_R5SS1_CORE1_AHB_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_R5SS1_CORE1_AHB_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_R5SS1_CORE1_AHB_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AHB_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AHB_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AHB_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_R5SS1_CORE1_AHB_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_R5SS1_CORE1_AHB_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_R5SS1_CORE1_AHB_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_R5SS1_CORE1_AXIS" base ad:0x40100000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_R5SS1_CORE1_AXIS_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_R5SS1_CORE1_AXIS_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_R5SS1_CORE1_AXIS_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_R5SS1_CORE1_AXIS_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_R5SS1_CORE1_AXIS_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_R5SS1_CORE1_AXIS_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_R5SS1_CORE1_AXIS_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_R5SS1_CORE1_AXIS_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AXIS_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AXIS_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_R5SS1_CORE1_AXIS_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_R5SS1_CORE1_AXIS_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_R5SS1_CORE1_AXIS_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_R5SS1_CORE1_AXIS_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree.end tree "MPU_SCRM2SCRP" tree "MPU_SCRM2SCRP0" base ad:0x40180000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_SCRM2SCRP0_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_SCRM2SCRP0_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_SCRM2SCRP0_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_SCRM2SCRP0_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_SCRM2SCRP0_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_SCRM2SCRP0_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_SCRM2SCRP0_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_SCRM2SCRP0_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_SCRM2SCRP0_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP0_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP0_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_SCRM2SCRP0_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP0_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP0_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_SCRM2SCRP0_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_SCRM2SCRP0_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_SCRM2SCRP0_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree "MPU_SCRM2SCRP1" base ad:0x401A0000 rgroup.long 0x0++0x7 line.long 0x0 "MPU_SCRM2SCRP1_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Scheme." "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read a s0. Writes have no affect." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "MODID,Module ID field." newline hexmask.long.byte 0x0 11.--15. 1. "REVRTL,RTL revision.Will vary depending on release." bitfld.long 0x0 8.--10. "REVMAJ,Majo revision." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "REVCUSTOM,Custom revision." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "REVMIN,Minor revision." line.long 0x4 "MPU_SCRM2SCRP1_CONFIGURATION" hexmask.long.byte 0x4 24.--31. 1. "ADDRESS_ALIGN,Address alignment for range checking." hexmask.long.byte 0x4 20.--23. 1. "NUM_FIXED,Number of fixed address ranges Configurable as 0 or 1." hexmask.long.byte 0x4 16.--19. 1. "NUM_PROG,Number of programmable address ranges.Value is determined by configuration" newline hexmask.long.byte 0x4 12.--15. 1. "NUM_FIXED_AIDS,Number of supported AIDs.0 = no specific AIDs supported (all treated equally)N = PrivIDs from 0 to N-1 supported others use AIDX" hexmask.long.word 0x4 1.--11. 1. "RESERVED,Always read as 0." bitfld.long 0x4 0. "ASSUMED_ALLOWED,Assumed allowed mode. 0 = assumed disallowed 1 = assumed allowed" "0: assumed disallowed,1: assumed allowed" group.long 0x10++0x13 line.long 0x0 "MPU_SCRM2SCRP1_INTERRUPT_RAW_STATUSSET" hexmask.long 0x0 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read.Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.long 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" line.long 0x4 "MPU_SCRM2SCRP1_INTERRUPT_ENABLED_STATUSCLEAR" hexmask.long 0x4 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x4 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read.Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.long 0x4 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" line.long 0x8 "MPU_SCRM2SCRP1_INTERRUPT_ENABLE" hexmask.long 0x8 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x8 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.long 0x8 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" line.long 0xC "MPU_SCRM2SCRP1_INTERRUPT_ENABLE_CLEAR" hexmask.long 0xC 2.--31. 1. "RESERVED,Always read as 0." bitfld.long 0xC 1. "ADDR_ERR_EN_CLR,Addressing violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.long 0xC 0. "PROT_ERR_EN_CLR,Protection violation error enable. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" line.long 0x10 "MPU_SCRM2SCRP1_EOI" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Always read as 0." hexmask.long.byte 0x10 0.--7. 1. "EOI_VECTOR,EOI vector value.Write this with the interrupt distribution value in the chip. This drives the mpu_eoi_vector output signal." rgroup.long 0x24++0x3 line.long 0x0 "MPU_SCRM2SCRP1_INTERRUPT_VECTOR" hexmask.long 0x0 0.--31. 1. "INTR_VEC,Interrupt vector. Reads mpu_intr_vector input signal." rgroup.long 0x100++0xB line.long 0x0 "MPU_SCRM2SCRP1_FIXED_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP1_FIXED_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP1_FIXED_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" group.long 0x200++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_1_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_1_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_1_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x210++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_2_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_2_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_2_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x220++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_3_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_3_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_3_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x230++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_4_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_4_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_4_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x240++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_5_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_5_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_5_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x250++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_6_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_6_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_6_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x260++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_7_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_7_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_7_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" group.long 0x270++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_8_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Start address for range N. Defaults to input signal value." line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_8_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,End address for range N. Defaults to input signal value." line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_8_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Always read as 0." hexmask.long.word 0x8 10.--25. 1. "AID15_0,AIDs checked for this region. Defaults to input value.0 = AID is not checked for these permissions.1 = AID is checked for these permissions." bitfld.long 0x8 9. "AIDX,Additional AIDs checked. Defaults to input value." "0,1" newline rbitfld.long 0x8 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x8 7. "NS,Non-secure permission. Defaults to input value." "0,1" bitfld.long 0x8 6. "EMU,Debug permission. Defaults to input value." "0,1" newline bitfld.long 0x8 5. "SR,Supervisor read permission. Defaults to input value." "0,1" bitfld.long 0x8 4. "SW,Supervisor write permission. Defaults to input value." "0,1" bitfld.long 0x8 3. "SX,Supervisor executable permission. Defaults to input value." "0,1" newline bitfld.long 0x8 2. "UR,User read permission. Defaults to input value." "0,1" bitfld.long 0x8 1. "UW,User write permission. Defaults to input value." "0,1" bitfld.long 0x8 0. "UX,User executable permission. Defaults to input value." "0,1" rgroup.long 0x280++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_9_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_9_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_9_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x290++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_10_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_10_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_10_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2A0++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_11_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_11_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_11_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2B0++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_12_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_12_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_12_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2C0++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_13_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_13_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_13_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2D0++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_14_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_14_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_14_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2E0++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_15_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_15_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_15_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x2F0++0xB line.long 0x0 "MPU_SCRM2SCRP1_PROGRAMMABLE_16_START_ADDRESS" hexmask.long 0x0 0.--31. 1. "START_ADDR,Reserved not used in Design" line.long 0x4 "MPU_SCRM2SCRP1_PROGRAMMABLE_16_END_ADDRESS" hexmask.long 0x4 0.--31. 1. "END_ADDR,Reserved not used in Design" line.long 0x8 "MPU_SCRM2SCRP1_PROGRAMMABLE_16_MPPA" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved not used in Design" hexmask.long.word 0x8 10.--25. 1. "AID15_0,Reserved not used in Design" bitfld.long 0x8 9. "AIDX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 8. "RESERVED1,Reserved not used in Design" "0,1" bitfld.long 0x8 7. "NS,Reserved not used in Design" "0,1" bitfld.long 0x8 6. "EMU,Reserved not used in Design" "0,1" newline bitfld.long 0x8 5. "SR,Reserved not used in Design" "0,1" bitfld.long 0x8 4. "SW,Reserved not used in Design" "0,1" bitfld.long 0x8 3. "SX,Reserved not used in Design" "0,1" newline bitfld.long 0x8 2. "UR,Reserved not used in Design" "0,1" bitfld.long 0x8 1. "UW,Reserved not used in Design" "0,1" bitfld.long 0x8 0. "UX,Reserved not used in Design" "0,1" rgroup.long 0x300++0x7 line.long 0x0 "MPU_SCRM2SCRP1_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault address." line.long 0x4 "MPU_SCRM2SCRP1_FAULT_STATUS" hexmask.long.byte 0x4 24.--31. 1. "ID,Transfer ID" hexmask.long.byte 0x4 16.--23. 1. "MSTID,Master ID." bitfld.long 0x4 13.--15. "RESERVED,Always read as 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 9.--12. 1. "PRIVID,Privilege ID." bitfld.long 0x4 8. "RESERVED1,Always read as 0." "0,1" bitfld.long 0x4 7. "NS,Non-secure access." "0,1" newline bitfld.long 0x4 6. "RESERVED2,Always read as 0." "0,1" hexmask.long.byte 0x4 0.--5. 1. "FAULT_TYPE,Fault type.100000 = supervisor read fault010000 = supervisor write fault001000 = supervisor execute fault000100 = user read fault000010 = user write fault000001 = user execute fault111111 = relaxed cache linefill fault010010 = relaxed cache.." group.long 0x308++0x3 line.long 0x0 "MPU_SCRM2SCRP1_FAULT_CLEAR" hexmask.long 0x0 1.--31. 1. "RESERVED,Always read as 0." bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a0 has no effect." "0,1" tree.end tree.end tree.end tree "MSS" base ad:0x0 tree "MSS_CTRL" base ad:0x50D00000 rgroup.long 0x0++0x3 line.long 0x0 "MSS_CTRL_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,Not Defined" newline hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,Not Defined" newline bitfld.long 0x0 8.--10. "PID_MAJOR,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM,Not Defined" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,Not Defined" group.long 0x20++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CONTROL" bitfld.long 0x0 24.--26. "ROM_WAIT_STATE,writing '111' enables a single cycle wait state with respect to CR5A_clk for rom access.This needs to be set when R5 clock is at 400MHZ and Interconnect-clk is at 200MHZ. (because it is a timing issue in this scenario)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "RESET_FSM_TRIGGER,Write pulse bit field:writing 3'b111 will trigger the reset FSM. Reset FSM ensures reset to R5SS and inturn ensures the latching of lock_step and also mem_swap bit" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "LOCK_STEP_SWITCH_WAIT,writing 3'b111 ensures switch happens only after R5SS reset. Orelse it will be a immediate switch." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "LOCK_STEP,writing 3'b000 ensures R5 to be in Dual-Core mode. Note: The change happens after the R5SS reset assertion if R5_CONTROL_lock_step_switch_wait is set. Or else the switiching to Dual-core happens on the fly." "0,1,2,3,4,5,6,7" group.byte 0x24++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CORE0_HALT" bitfld.byte 0x0 0.--2. "HALT,writing '000' will unhalt CR5A. This register should be written only once." "0,1,2,3,4,5,6,7" group.byte 0x28++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CORE1_HALT" bitfld.byte 0x0 0.--2. "HALT,writing '000' will unhalt for CR5B. This register should be written only once." "0,1,2,3,4,5,6,7" rgroup.word 0x2C++0x1 line.word 0x0 "MSS_CTRL_R5SS0_STATUS_REG" bitfld.word 0x0 8. "LOCK_STEP,Reading 1: confirms R5SS is in lockstep mode. Reading 0: confirms R5SS is in Dual-core mode." "0: confirms R5SS is in Dual-core mode,1: confirms R5SS is in lockstep mode" newline bitfld.word 0x0 0. "MEMSWAP,reading 1: confirms ROM is Eclipsed from with RAM for R5." "?,1: confirms ROM is Eclipsed from with RAM for R5" rgroup.byte 0x30++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CORE0_STAT" bitfld.byte 0x0 4. "WFE_STAT,WFE Status" "0,1" newline bitfld.byte 0x0 0. "WFI_STAT,WFI Status" "0,1" rgroup.byte 0x34++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CORE1_STAT" bitfld.byte 0x0 4. "WFE_STAT,WFE Status" "0,1" newline bitfld.byte 0x0 0. "WFI_STAT,WFI Status" "0,1" group.byte 0x38++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_FORCE_WFI" bitfld.byte 0x0 0.--2. "CR5_WFI_OVERIDE,writing 3'b111 will force the wfi signals of R5SS to 1" "0,1,2,3,4,5,6,7" group.tbyte 0x40++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CONTROL" bitfld.tbyte 0x0 16.--18. "RESET_FSM_TRIGGER,Write pulse bit field:writing 3'b111 will trigger the reset FSM. Reset FSM ensures reset to R5SS and inturn ensures the latching of lock_step and also mem_swap bit" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 8.--10. "LOCK_STEP_SWITCH_WAIT,writing 3'b111 ensures switch happens only after R5SS reset. Orelse it will be a immediate switch." "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 0.--2. "LOCK_STEP,writing 3'b000 ensures R5 to be in Dual-Core mode. Note: The change happens after the R5SS reset assertion if R5_CONTROL_lock_step_switch_wait is set. Or else the switiching to Dual-core happens on the fly." "0,1,2,3,4,5,6,7" group.byte 0x44++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CORE0_HALT" bitfld.byte 0x0 0.--2. "HALT,writing '000' will unhalt CR5A. This register should be written only once." "0,1,2,3,4,5,6,7" group.byte 0x48++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CORE1_HALT" bitfld.byte 0x0 0.--2. "HALT,writing '000' will unhalt for CR5B. This register should be written only once." "0,1,2,3,4,5,6,7" rgroup.word 0x4C++0x1 line.word 0x0 "MSS_CTRL_R5SS1_STATUS_REG" bitfld.word 0x0 8. "LOCK_STEP,Reading 1: confirms R5SS is in lockstep mode. Reading 0: confirms R5SS is in Dual-core mode." "0: confirms R5SS is in Dual-core mode,1: confirms R5SS is in lockstep mode" rgroup.byte 0x50++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CORE0_STAT" bitfld.byte 0x0 4. "WFE_STAT,WFE Status" "0,1" newline bitfld.byte 0x0 0. "WFI_STAT,WFI Status" "0,1" rgroup.byte 0x54++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CORE1_STAT" bitfld.byte 0x0 4. "WFE_STAT,WFE Status" "0,1" newline bitfld.byte 0x0 0. "WFI_STAT,WFI Status" "0,1" group.byte 0x58++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_FORCE_WFI" bitfld.byte 0x0 0.--2. "CR5_WFI_OVERIDE,writing 3'b111 will force the wfi signals of R5SS to 1" "0,1,2,3,4,5,6,7" group.word 0x80++0x1 line.word 0x0 "MSS_CTRL_R5SS0_ROM_ECLIPSE" bitfld.word 0x0 8.--10. "MEMSWAP_WAIT,writing 3'b111 ensures ROM-Eclipsing happens only after R5SS reset. Orelse it will be a immediate change." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "MEMSWAP,writing '111' ensures eclipsing of CR5A_ROM immediately if memswap_wait is not set. If memswap_wait is set then ROM is eclipsed after R5SS reset assertion." "0,1,2,3,4,5,6,7" group.long 0x90++0x7 line.long 0x0 "MSS_CTRL_R5SS0_TEINIT" bitfld.long 0x0 0. "TEINIT,Exception handling state at reset. 0-ARM 1-Thumb" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_TEINIT" bitfld.long 0x4 0. "TEINIT,Exception handling state at reset. 0-ARM 1-Thumb" "0,1" group.tbyte 0x98++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_AHB_EN" bitfld.tbyte 0x0 16.--18. "CPU1_AHB_INIT,Ti internal Register. Modifying this register is not recommendedSignal decides whehter ahb interface is enabled or not." "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 0.--2. "CPU0_AHB_INIT,Ti internal Register. Modifying this register is not recommendedSignal decides whehter ahb interface is enabled or not." "0,1,2,3,4,5,6,7" group.tbyte 0x9C++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_AHB_EN" bitfld.tbyte 0x0 16.--18. "CPU1_AHB_INIT,Ti internal Register. Modifying this register is not recommendedSignal decides whehter ahb interface is enabled or not." "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 0.--2. "CPU0_AHB_INIT,Ti internal Register. Modifying this register is not recommendedSignal decides whehter ahb interface is enabled or not." "0,1,2,3,4,5,6,7" group.tbyte 0xA0++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE0_AHB_BASE" hexmask.tbyte 0x0 0.--19. 1. "AHB_BASE,Ti internal Register. Modifying this register is not recommendedDecides the base address of ahb region" group.tbyte 0xA4++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE0_AHB_BASE" hexmask.tbyte 0x0 0.--19. 1. "AHB_BASE,Ti internal Register. Modifying this register is not recommendedDecides the base address of ahb region" group.byte 0xA8++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CORE0_AHB_SIZE" hexmask.byte 0x0 0.--4. 1. "AHB_SIZE,Ti internal Register. Modifying this register is not recommendedCode for selecting size for ahb.b00011 4KBb00100 8KBb00101 16KBb00110 32KBb00111 64KBb01000 128KBb01001 256KBb01010 512KBb01011 1MBb01100 2MBb01101.." group.byte 0xAC++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CORE0_AHB_SIZE" hexmask.byte 0x0 0.--4. 1. "AHB_SIZE,Ti internal Register. Modifying this register is not recommendedCode for selecting size for ahb.b00011 4KBb00100 8KBb00101 16KBb00110 32KBb00111 64KBb01000 128KBb01001 256KBb01010 512KBb01011 1MBb01100 2MBb01101.." group.tbyte 0xB0++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE1_AHB_BASE" hexmask.tbyte 0x0 0.--19. 1. "AHB_BASE,Ti internal Register. Modifying this register is not recommendedDecides the base address of ahb region" group.tbyte 0xB4++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE1_AHB_BASE" hexmask.tbyte 0x0 0.--19. 1. "AHB_BASE,Ti internal Register. Modifying this register is not recommendedDecides the base address of ahb region" group.byte 0xB8++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CORE1_AHB_SIZE" hexmask.byte 0x0 0.--4. 1. "AHB_SIZE,Ti internal Register. Modifying this register is not recommendedCode for selecting size for ahb.b00011 4KBb00100 8KBb00101 16KBb00110 32KBb00111 64KBb01000 128KBb01001 256KBb01010 512KBb01011 1MBb01100 2MBb01101.." group.byte 0xBC++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CORE1_AHB_SIZE" hexmask.byte 0x0 0.--4. 1. "AHB_SIZE,Ti internal Register. Modifying this register is not recommendedCode for selecting size for ahb.b00011 4KBb00100 8KBb00101 16KBb00110 32KBb00111 64KBb01000 128KBb01001 256KBb01010 512KBb01011 1MBb01100 2MBb01101.." group.tbyte 0xC0++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_TCM_EXT_ERR_EN" bitfld.tbyte 0x0 16.--18. "CPU1_TCM,Ti internal Register. Modifying this register is not recommendedTCMs external error enable. Tie each bit high to enable the external error signal for each TCM at reset" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 0.--2. "CPU0_TCM,Ti internal Register. Modifying this register is not recommendedTCMs external error enable. Tie each bit high to enable the external error signal for each TCM at reset" "0,1,2,3,4,5,6,7" group.tbyte 0xC4++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_TCM_EXT_ERR_EN" bitfld.tbyte 0x0 16.--18. "CPU1_TCM,Ti internal Register. Modifying this register is not recommendedTCMs external error enable. Tie each bit high to enable the external error signal for each TCM at reset" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 0.--2. "CPU0_TCM,Ti internal Register. Modifying this register is not recommendedTCMs external error enable. Tie each bit high to enable the external error signal for each TCM at reset" "0,1,2,3,4,5,6,7" group.tbyte 0xC8++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_TCM_ERR_EN" bitfld.tbyte 0x0 16.--18. "CPU1_TCM,Ti internal Register. Modifying this register is not recommendedTCMs ECC check enable. Tie each bit high to enable ECC checking on appropraite TCM" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 0.--2. "CPU0_TCM,Ti internal Register. Modifying this register is not recommendedTCMs ECC check enable. Tie each bit high to enable ECC checking on appropraite TCM" "0,1,2,3,4,5,6,7" group.tbyte 0xCC++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_TCM_ERR_EN" bitfld.tbyte 0x0 16.--18. "CPU1_TCM,Ti internal Register. Modifying this register is not recommendedTCMs ECC check enable. Tie each bit high to enable ECC checking on appropraite TCM" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 0.--2. "CPU0_TCM,Ti internal Register. Modifying this register is not recommendedTCMs ECC check enable. Tie each bit high to enable ECC checking on appropraite TCM" "0,1,2,3,4,5,6,7" group.tbyte 0xD0++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_INIT_TCM" bitfld.tbyte 0x0 20.--22. "LOCKZRAM_CPU1,Ti internal Register. Modifying this register is not recommendedWhen HIGH ATCM base address at reset is 0x0 when LOW BTCM base address at reset is 0x0" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 16.--18. "TCMB_CPU1,Ti internal Register. Modifying this register is not recommendedWhen HIGH enables BTCM interface out of reset" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 12.--14. "TCMA_CPU1,Ti internal Register. Modifying this register is not recommendedWhen HIGH enables ATCM interface out of reset" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 8.--10. "LOCKZRAM_CPU0,Ti internal Register. Modifying this register is not recommendedWhen HIGH ATCM base address at reset is 0x0 when LOW BTCM base address at reset is 0x0" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 4.--6. "TCMB_CPU0,Ti internal Register. Modifying this register is not recommendedWhen HIGH enables BTCM interface out of reset" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 0.--2. "TCMA_CPU0,Ti internal Register. Modifying this register is not recommendedWhen HIGH enables ATCM interface out of reset" "0,1,2,3,4,5,6,7" group.tbyte 0xD4++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_INIT_TCM" bitfld.tbyte 0x0 20.--22. "LOCKZRAM_CPU1,Ti internal Register. Modifying this register is not recommendedWhen HIGH ATCM base address at reset is 0x0 when LOW BTCM base address at reset is 0x0" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 16.--18. "TCMB_CPU1,Ti internal Register. Modifying this register is not recommendedWhen HIGH enables BTCM interface out of reset" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 12.--14. "TCMA_CPU1,Ti internal Register. Modifying this register is not recommendedWhen HIGH enables ATCM interface out of reset" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 8.--10. "LOCKZRAM_CPU0,Ti internal Register. Modifying this register is not recommendedWhen HIGH ATCM base address at reset is 0x0 when LOW BTCM base address at reset is 0x0" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 4.--6. "TCMB_CPU0,Ti internal Register. Modifying this register is not recommendedWhen HIGH enables BTCM interface out of reset" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 0.--2. "TCMA_CPU0,Ti internal Register. Modifying this register is not recommendedWhen HIGH enables ATCM interface out of reset" "0,1,2,3,4,5,6,7" group.tbyte 0xD8++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_TCM_ECC_WRENZ_EN" bitfld.tbyte 0x0 20.--22. "CPU1_TCMB1_WRENZ_EN,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5B.Writing '111' unblocks the writes to ECC-bits of TCMB1-RAM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 16.--18. "CPU1_TCMB0_WRENZ_EN,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5B.Writing '111' unblocks the writes to ECC-bits of TCMB0-RAM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 12.--14. "CPU1_TCMA_WRENZ_EN,writing '000' blocks the writes to ECC-bits of TCMA-RAM of CR5B.Writing '111' unblocks the writes to ECC-bits of TCMA-RAM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 8.--10. "CPU0_TCMB1_WRENZ_EN,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5A.Writing '111' unblocks the writes to ECC-bits of TCMB1-RAM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 4.--6. "CPU0_TCMB0_WRENZ_EN,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5A.Writing '111' unblocks the writes to ECC-bits of TCMB0-RAM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 0.--2. "CPU0_TCMA_WRENZ_EN,writing '000' blocks the writes to ECC-bits of TCMA-RAM of CR5A.Writing '111' unblocks the writes to ECC-bits of TCMA-RAM of CR5A" "0,1,2,3,4,5,6,7" group.tbyte 0xDC++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_TCM_ECC_WRENZ_EN" bitfld.tbyte 0x0 20.--22. "CPU1_TCMB1_WRENZ_EN,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5B.Writing '111' unblocks the writes to ECC-bits of TCMB1-RAM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 16.--18. "CPU1_TCMB0_WRENZ_EN,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5B.Writing '111' unblocks the writes to ECC-bits of TCMB0-RAM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 12.--14. "CPU1_TCMA_WRENZ_EN,writing '000' blocks the writes to ECC-bits of TCMA-RAM of CR5B.Writing '111' unblocks the writes to ECC-bits of TCMA-RAM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 8.--10. "CPU0_TCMB1_WRENZ_EN,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5A.Writing '111' unblocks the writes to ECC-bits of TCMB1-RAM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 4.--6. "CPU0_TCMB0_WRENZ_EN,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5A.Writing '111' unblocks the writes to ECC-bits of TCMB0-RAM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 0.--2. "CPU0_TCMA_WRENZ_EN,writing '000' blocks the writes to ECC-bits of TCMA-RAM of CR5A.Writing '111' unblocks the writes to ECC-bits of TCMA-RAM of CR5A" "0,1,2,3,4,5,6,7" group.long 0x100++0x1F line.long 0x0 "MSS_CTRL_BOOT_INFO_REG0" hexmask.long 0x0 0.--31. 1. "CONFIG,Reserved Register for Software use" line.long 0x4 "MSS_CTRL_BOOT_INFO_REG1" hexmask.long 0x4 0.--31. 1. "CONFIG,Reserved Register for Software use" line.long 0x8 "MSS_CTRL_BOOT_INFO_REG2" hexmask.long 0x8 0.--31. 1. "CONFIG,Reserved Register for Software use" line.long 0xC "MSS_CTRL_BOOT_INFO_REG3" hexmask.long 0xC 0.--31. 1. "CONFIG,Reserved Register for Software use" line.long 0x10 "MSS_CTRL_BOOT_INFO_REG4" hexmask.long 0x10 0.--31. 1. "CONFIG,Reserved Register for Software use" line.long 0x14 "MSS_CTRL_BOOT_INFO_REG5" hexmask.long 0x14 0.--31. 1. "CONFIG,Reserved Register for Software use" line.long 0x18 "MSS_CTRL_BOOT_INFO_REG6" hexmask.long 0x18 0.--31. 1. "CONFIG,Reserved Register for Software use" line.long 0x1C "MSS_CTRL_BOOT_INFO_REG7" hexmask.long 0x1C 0.--31. 1. "CONFIG,Reserved Register for Software use" group.long 0x200++0x7 line.long 0x0 "MSS_CTRL_R5SS0_ATCM_MEM_INIT" bitfld.long 0x0 0. "MEM_INIT,Write_pulse bit field:Writing 1'b1 will start initializing the ATCM banks of CR5A/B. Value in each row is initialized to 0x0C_0000_0000" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_ATCM_MEM_INIT_DONE" bitfld.long 0x4 0. "MEM_INIT_DONE,This field will be high once initialization of ATCM banks is finished. Writing '1' would clear the bit." "0,1" rgroup.long 0x208++0x3 line.long 0x0 "MSS_CTRL_R5SS0_ATCM_MEM_INIT_STATUS" bitfld.long 0x0 0. "MEM_STATUS,1'b0: No initialization is happening for ATCM banks of CR5A/B1'b1: Initialization is in progress for ATCM banks of CR5A/B" "0: No initialization is happening for ATCM banks of..,?" group.long 0x210++0x7 line.long 0x0 "MSS_CTRL_R5SS0_BTCM_MEM_INIT" bitfld.long 0x0 0. "MEM_INIT,Write_pulse bit field:Writing 1'b1 will start initializing the B0/1TCM banks of CR5A/B" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_BTCM_MEM_INIT_DONE" bitfld.long 0x4 0. "MEM_INIT_DONE,This field will be high once initialization of B0/1TCM banks is finished. Writing '1' would clear the bit." "0,1" rgroup.long 0x218++0x3 line.long 0x0 "MSS_CTRL_R5SS0_BTCM_MEM_INIT_STATUS" bitfld.long 0x0 0. "MEM_STATUS,1'b0: No initialization is happening for B0/1TCM banks of CR5A/B1'b1: Initialization is in progress for B0/1TCM banks of CR5A/B" "0: No initialization is happening for B0/1TCM banks..,?" group.long 0x220++0x7 line.long 0x0 "MSS_CTRL_R5SS1_ATCM_MEM_INIT" bitfld.long 0x0 0. "MEM_INIT,Write_pulse bit field:Writing 1'b1 will start initializing the ATCM banks of CR5A/B. Value in each row is initialized to 0x0C_0000_0000" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_ATCM_MEM_INIT_DONE" bitfld.long 0x4 0. "MEM_INIT_DONE,This field will be high once initialization of ATCM banks is finished. Writing '1' would clear the bit." "0,1" rgroup.long 0x228++0x3 line.long 0x0 "MSS_CTRL_R5SS1_ATCM_MEM_INIT_STATUS" bitfld.long 0x0 0. "MEM_STATUS,1'b0: No initialization is happening for ATCM banks of CR5A/B1'b1: Initialization is in progress for ATCM banks of CR5A/B" "0: No initialization is happening for ATCM banks of..,?" group.long 0x230++0x7 line.long 0x0 "MSS_CTRL_R5SS1_BTCM_MEM_INIT" bitfld.long 0x0 0. "MEM_INIT,Write_pulse bit field:Writing 1'b1 will start initializing the B0/1TCM banks of CR5A/B" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_BTCM_MEM_INIT_DONE" bitfld.long 0x4 0. "MEM_INIT_DONE,This field will be high once initialization of B0/1TCM banks is finished. Writing '1' would clear the bit." "0,1" rgroup.long 0x238++0x3 line.long 0x0 "MSS_CTRL_R5SS1_BTCM_MEM_INIT_STATUS" bitfld.long 0x0 0. "MEM_STATUS,1'b0: No initialization is happening for B0/1TCM banks of CR5A/B1'b1: Initialization is in progress for B0/1TCM banks of CR5A/B" "0: No initialization is happening for B0/1TCM banks..,?" group.byte 0x240++0x0 line.byte 0x0 "MSS_CTRL_L2IOCRAM_MEM_INIT" bitfld.byte 0x0 3. "PARTITION3,Write_pulse bit field:Writing 1'b1 will start initializing the L2 Bank3. Value in each row is initialized to 0x0" "0,1" newline bitfld.byte 0x0 2. "PARTITION2,Write_pulse bit field:Writing 1'b1 will start initializing the L2 Bank2. Value in each row is initialized to 0x0" "0,1" newline bitfld.byte 0x0 1. "PARTITION1,Write_pulse bit field:Writing 1'b1 will start initializing the L2 Bank1. Value in each row is initialized to 0x0" "0,1" newline bitfld.byte 0x0 0. "PARTITION0,Write_pulse bit field:Writing 1'b1 will start initializing the L2 Bank0. Value in each row is initialized to 0x0" "0,1" group.byte 0x244++0x0 line.byte 0x0 "MSS_CTRL_L2OCRAM_MEM_INIT_DONE" bitfld.byte 0x0 3. "PARTITION3,This field will be high once intialization of L2 bank3 is finished. Writing '1' would clear the bit" "0,1" newline bitfld.byte 0x0 2. "PARTITION2,This field will be high once intialization of L2 bank2 is finished. Writing '1' would clear the bit" "0,1" newline bitfld.byte 0x0 1. "PARTITION1,This field will be high once intialization of L2 bank1 is finished. Writing '1' would clear the bit" "0,1" newline bitfld.byte 0x0 0. "PARTITION0,This field will be high once intialization of L2 bank0 is finished. Writing '1' would clear the bit" "0,1" rgroup.byte 0x248++0x0 line.byte 0x0 "MSS_CTRL_L2OCRAM_MEM_INIT_STATUS" bitfld.byte 0x0 3. "PARTITION3,1'b0: No initialization is happening for L2 bank31'b1: Initialization is in progress for L2 bank3" "0: No initialization is happening for L2 bank31'b1:..,?" newline bitfld.byte 0x0 2. "PARTITION2,1'b0: No initialization is happening for L2 bank2 1'b1: Initialization is in progress for L2 bank2" "0: No initialization is happening for L2 bank2,1: Initialization is in progress for L2 bank2" newline bitfld.byte 0x0 1. "PARTITION1,1'b0: No initialization is happening for L2 bank11'b1: Initialization is in progress for L2 bank1" "0: No initialization is happening for L2 bank11'b1:..,?" newline bitfld.byte 0x0 0. "PARTITION0,1'b0: No initialization is happening for L2 bank0 1'b1: Initialization is in progress for L2 bank0" "0: No initialization is happening for L2 bank0,1: Initialization is in progress for L2 bank0" group.long 0x250++0x7 line.long 0x0 "MSS_CTRL_MAILBOXRAM_MEM_INIT" bitfld.long 0x0 0. "MEM0_INIT,Write_pulse bit field:Writing 1'b1 will start initializing the MSS_MBOX. Value in each row is initialized to 0x0" "0,1" line.long 0x4 "MSS_CTRL_MAILBOXRAM_MEM_INIT_DONE" bitfld.long 0x4 0. "MEM0_DONE,This field will be high once intialization of MSS_MBOX is finished. Writing '1' would clear the bit" "0,1" rgroup.long 0x258++0x3 line.long 0x0 "MSS_CTRL_MAILBOXRAM_MEM_INIT_STATUS" bitfld.long 0x0 0. "MEM0_STATUS,1'b0: No initialization is happening for MSS_MBOX 1'b1: Initialization is in progress for MSS_MBOX" "0: No initialization is happening for MSS_MBOX,1: Initialization is in progress for MSS_MBOX" group.long 0x260++0x7 line.long 0x0 "MSS_CTRL_TPCC_MEM_INIT" bitfld.long 0x0 0. "TPCC_A_MEMINIT_START,Write_pulse bit field:Writing 1'b1 will start initializing the MSS_TPCCA" "0,1" line.long 0x4 "MSS_CTRL_TPCC_MEM_INIT_DONE" bitfld.long 0x4 0. "TPCC_A_MEMINIT_DONE,This field will be high once intialization of MSS_TPCCA is finished. Writing '1' would clear the bit" "0,1" rgroup.long 0x268++0x3 line.long 0x0 "MSS_CTRL_TPCC_MEMINIT_STATUS" bitfld.long 0x0 0. "TPCC_A_MEMINIT_STATUS,1'b0: No initialization is happening for MSS_TPCCA1'b1: Initialization is in progress for MSS_TPCCB" "0: No initialization is happening for..,?" group.byte 0x300++0x0 line.byte 0x0 "MSS_CTRL_TOP_PBIST_KEY_RST" hexmask.byte 0x0 4.--7. 1. "PBIST_ST_RST,MSS PBIST controller will be brought out of reset when value is 0xA" newline hexmask.byte 0x0 0.--3. 1. "PBIST_ST_KEY,Top PBIST Selftest Key. Valid value is 0x5" group.long 0x304++0xB line.long 0x0 "MSS_CTRL_TOP_PBIST_REG0" hexmask.long 0x0 0.--31. 1. "PBIST_REG,Not Defined" line.long 0x4 "MSS_CTRL_TOP_PBIST_REG1" hexmask.long 0x4 0.--31. 1. "PBIST_REG,Not Defined" line.long 0x8 "MSS_CTRL_TOP_PBIST_REG2" hexmask.long 0x8 0.--31. 1. "PBIST_REG,Not Defined" group.word 0x400++0x1 line.word 0x0 "MSS_CTRL_R5SS0_CTI_TRIG_SEL" hexmask.word.byte 0x0 8.--15. 1. "TRIG1,Used for selecting the trigger source for 1st trigger of MSS_R5SS" newline hexmask.word.byte 0x0 0.--7. 1. "TRIG0,Used for selecting the trigger source for 0th trigger of MSS_R5SS" group.word 0x404++0x1 line.word 0x0 "MSS_CTRL_R5SS1_CTI_TRIG_SEL" hexmask.word.byte 0x0 8.--15. 1. "TRIG1,Used for selecting the trigger source for 1st trigger of MSS_R5SS" newline hexmask.word.byte 0x0 0.--7. 1. "TRIG0,Used for selecting the trigger source for 0th trigger of MSS_R5SS" group.long 0x408++0x3 line.long 0x0 "MSS_CTRL_DBGSS_CTI_TRIG_SEL" hexmask.long.byte 0x0 24.--31. 1. "TRIG3,Used for selecting the trigger source for 3rd trigger of ONE_MCU_CTI" newline hexmask.long.byte 0x0 16.--23. 1. "TRIG2,Used for selecting the trigger source for 2nd trigger of ONE_MCU_CTI" newline hexmask.long.byte 0x0 8.--15. 1. "TRIG1,Used for selecting the trigger source for 1st trigger of ONE_MCU_CTI" newline hexmask.long.byte 0x0 0.--7. 1. "TRIG0,Used for selecting the trigger source for 0th trigger of ONE_MCU_CTI" group.word 0x40C++0x1 line.word 0x0 "MSS_CTRL_DEBUGSS_CSETB_FLUSH" rbitfld.word 0x0 10. "CSETB_FULL,When HIGH indicates that the ETB RAM has overflowed or wrapped around to address zero" "0,1" newline rbitfld.word 0x0 9. "CSETB_ACQ_COMPLETE,When HIGH indicates that trace acquisition is complete by ETB that is the trigger counter is at zero" "0,1" newline rbitfld.word 0x0 8. "CSETB_FLUSHINACK,Return acknowledgement to CSETBFLUSHIN" "0,1" newline bitfld.word 0x0 0. "CSETB_FLUSHIN,External control used to assert the ATB signal AFVALIDS and drain any historical FIFO information on the bus" "0,1" group.word 0x410++0x1 line.word 0x0 "MSS_CTRL_DEBUGSS_STM_NSGUAREN" bitfld.word 0x0 10. "ENABLE,Non secure guarenteed access control0:Access does not stall the CPU. Trace not guarenteed1: Access may stall. Trace guarenteed" "0,1" group.byte 0x420++0x0 line.byte 0x0 "MSS_CTRL_MCAN0_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x424++0x0 line.byte 0x0 "MSS_CTRL_MCAN1_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x428++0x0 line.byte 0x0 "MSS_CTRL_MCAN2_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x42C++0x0 line.byte 0x0 "MSS_CTRL_MCAN3_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x430++0x0 line.byte 0x0 "MSS_CTRL_LIN0_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x434++0x0 line.byte 0x0 "MSS_CTRL_LIN1_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x438++0x0 line.byte 0x0 "MSS_CTRL_LIN2_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x43C++0x0 line.byte 0x0 "MSS_CTRL_LIN3_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x440++0x0 line.byte 0x0 "MSS_CTRL_LIN4_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x444++0x0 line.byte 0x0 "MSS_CTRL_I2C0_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x448++0x0 line.byte 0x0 "MSS_CTRL_I2C1_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x44C++0x0 line.byte 0x0 "MSS_CTRL_I2C2_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x450++0x0 line.byte 0x0 "MSS_CTRL_I2C3_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x454++0x0 line.byte 0x0 "MSS_CTRL_RTI0_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x458++0x0 line.byte 0x0 "MSS_CTRL_RTI1_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x45C++0x0 line.byte 0x0 "MSS_CTRL_RTI2_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x460++0x0 line.byte 0x0 "MSS_CTRL_RTI3_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x474++0x0 line.byte 0x0 "MSS_CTRL_CPSW_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x478++0x0 line.byte 0x0 "MSS_CTRL_MCRC0_HALTEN" bitfld.byte 0x0 3. "CR5B1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 2. "CR5A1_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 1. "CR5B0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" newline bitfld.byte 0x0 0. "CR5A0_HALTEN,1'b0: IP Halt disabled with corresponding CPU halt1'b1: IP Halt enabled with corresponding CPU halt" "0: IP Halt disabled with corresponding CPU..,?" group.byte 0x800++0x0 line.byte 0x0 "MSS_CTRL_TPTC_DBS_CONFIG" bitfld.byte 0x0 4.--5. "TPTC_A1,Default burst size tieoff value for TPTC_A1" "0,1,2,3" newline bitfld.byte 0x0 0.--1. "TPTC_A0,Default burst size tieoff value for TPTC_A0" "0,1,2,3" group.word 0x804++0x1 line.word 0x0 "MSS_CTRL_TPTC_BOUNDARY_CFG" hexmask.word.byte 0x0 8.--13. 1. "TPTC_A1_SIZE,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_A1Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB" newline hexmask.word.byte 0x0 0.--5. 1. "TPTC_A0_SIZE,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_A0Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB" group.word 0x808++0x1 line.word 0x0 "MSS_CTRL_TPTC_XID_REORDER_CFG" bitfld.word 0x0 8. "TPTC_A1_DISABLE,writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_A1" "0,1" newline bitfld.word 0x0 0. "TPTC_A0_DISABLE,writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_A0" "0,1" group.long 0x810++0x3 line.long 0x0 "MSS_CTRL_CPSW_CONTROL" bitfld.long 0x0 24. "RGMII2_ID_MODE,Internal delay mode for port 2. Only for TX0 : ID mode is disabled1 : ID mode is enabled" "0,1" newline bitfld.long 0x0 22. "RMII2_REF_CLK_SEL,To select the rmii_ref_clk loopback mux output either from PAD or from MSS_RCM. Write 0 to get clock will be from IO pad(pad loopback). Write 1 to get clock from internal loopback." "0,1" newline bitfld.long 0x0 20. "RMII2_REF_CLK_OE_N,RMII_REF_CLK IO Output enable control0: Output enable1: Output Disable" "0,1" newline bitfld.long 0x0 16.--18. "PORT2_MODE_SEL,Port 2 Interface 000 = MII001 = RMII010 = RGMII011 - 111 = Not Supported" "0: MII001 = RMII010 = RGMII011,?,?,?,?,?,?,?" newline bitfld.long 0x0 8. "RGMII1_ID_MODE,Internal delay mode for port 1. Only for TX0 : ID mode is disabled1 : ID mode is enabled" "0,1" newline bitfld.long 0x0 6. "RMII1_REF_CLK_SEL,To select the rmii_ref_clk loopback mux output either from PAD or from MSS_RCM. Write 0 to get clock will be from IO pad(pad loopback). Write 1 to get clock from internal source" "0,1" newline bitfld.long 0x0 4. "RMII1_REF_CLK_OE_N,RMII_REF_CLK IO Output enable control0: Output enable1: Output Disable" "0,1" newline bitfld.long 0x0 0.--2. "PORT1_MODE_SEL,Port 1 Interface 000 = MII001 = RMII010 = RGMII011 - 111 = Not Supported" "0: MII001 = RMII010 = RGMII011,?,?,?,?,?,?,?" group.byte 0x814++0x0 line.byte 0x0 "MSS_CTRL_QSPI_CONFIG" bitfld.byte 0x0 0.--2. "EXT_CLK,Write 3'b111 to external clock as QSPI baud clock source needed for DFT IO char." "0,1,2,3,4,5,6,7" group.long 0x818++0x13 line.long 0x0 "MSS_CTRL_ICSSM_IDLE_CONTROL" bitfld.long 0x0 0. "NOGATE,Writing 1'b0 will enable local auto-clock gating (lower power) at IP level with increase in access/functional latency. Following IPs are controlled with this signalICSSM" "0,1" line.long 0x4 "MSS_CTRL_ICSSM_PRU0_GPI_SEL" hexmask.long 0x4 0.--29. 1. "SEL,GPI or PWMXBar select for ICSM Port00: GPI1: PWMXBAR" line.long 0x8 "MSS_CTRL_ICSSM_PRU1_GPI_SEL" hexmask.long 0x8 0.--29. 1. "SEL,GPI or PWMXBar select for ICSM Port00: GPI1: PWMXBAR" line.long 0xC "MSS_CTRL_ICSSM_PRU0_GPIO_OUT_CTRL" hexmask.long 0xC 0.--29. 1. "OUTDISABLE,GPO output disable for ICSSM Port 0 IO. Disable output for using the pin as input. Each Bit maps to the corresponding bit in the IO0: Output Enable1: Output Disable" line.long 0x10 "MSS_CTRL_ICSSM_PRU1_GPIO_OUT_CTRL" hexmask.long 0x10 0.--29. 1. "OUTDISABLE,GPO output disable for ICSSM Port 1 IO. Disable output for using the pin as input. Each Bit maps to the corresponding bit in the IO0: Output Enable1: Output Disable" group.word 0x82C++0x1 line.word 0x0 "MSS_CTRL_GPMC_CONTROL" bitfld.word 0x0 12. "CLK_LB_OE_N,GPMC_CLK_LB oe_n1: GPMC_dev_clk is driven to pad0: GPMC_dev_clk is not driven to pad" "0,1" newline bitfld.word 0x0 8. "CLK_OE_N,GPMC_CLKOUT oe_n1: GPMC_dev_clk mux output is driven to pad0: GPMC_dev_clk mux output is not driven to pad" "0,1" newline bitfld.word 0x0 4. "CLK_LB_SEL,GPMC_CLK_LB sel0: GPMC_CLK_LB pad clock1: GPMC_CLK pad clock" "0,1" newline bitfld.word 0x0 0. "CLKOUT_SEL,GPMC_CLKOUT sel0: GPMC_func_clock1: GPMC_dev clock" "0,1" group.tbyte 0x830++0x2 line.tbyte 0x0 "MSS_CTRL_TPCC0_INTAGG_MASK" bitfld.tbyte 0x0 17. "TPTC_A1,Mask Interrupt from TPTC A1 to aggregated Interrupt MSS_TPCC_A_INTAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.tbyte 0x0 16. "TPTC_A0,Mask Interrupt from TPTC A0 to aggregated Interrupt MSS_TPCC_A_INTAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.tbyte 0x0 8. "TPCC_A_INT7,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.tbyte 0x0 7. "TPCC_A_INT6,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.tbyte 0x0 6. "TPCC_A_INT5,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.tbyte 0x0 5. "TPCC_A_INT4,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.tbyte 0x0 4. "TPCC_A_INT3,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.tbyte 0x0 3. "TPCC_A_INT2,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.tbyte 0x0 2. "TPCC_A_INT1,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.tbyte 0x0 1. "TPCC_A_INT0,Mask Interrupt from TPCC A to aggregated Interrupt MSS_TPCC_A_INTAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.tbyte 0x0 0. "TPCC_A_INTG,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" group.tbyte 0x834++0x2 line.tbyte 0x0 "MSS_CTRL_TPCC0_INTAGG_STATUS" bitfld.tbyte 0x0 17. "TPTC_A1,Status of Interrupt from TPTC A1. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.tbyte 0x0 16. "TPTC_A0,Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.tbyte 0x0 8. "TPCC_A_INT7,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.tbyte 0x0 7. "TPCC_A_INT6,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.tbyte 0x0 6. "TPCC_A_INT5,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.tbyte 0x0 5. "TPCC_A_INT4,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.tbyte 0x0 4. "TPCC_A_INT3,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.tbyte 0x0 3. "TPCC_A_INT2,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.tbyte 0x0 2. "TPCC_A_INT1,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.tbyte 0x0 1. "TPCC_A_INT0,Status of Interrupt from TPCC A Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" newline bitfld.tbyte 0x0 0. "TPCC_A_INTG,Status of Interrupt from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASKWrie 0x1 to clear this interrupt." "0,1" group.tbyte 0x838++0x2 line.tbyte 0x0 "MSS_CTRL_TPCC0_INTAGG_STATUS_RAW" bitfld.tbyte 0x0 17. "TPTC_A1,Raw Status of Interrupt from TPTC A1. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_INTAGG_MASK" "0,1" newline bitfld.tbyte 0x0 16. "TPTC_A0,Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_INTAGG_MASK" "0,1" newline bitfld.tbyte 0x0 8. "TPCC_A_INT7,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" newline bitfld.tbyte 0x0 7. "TPCC_A_INT6,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" newline bitfld.tbyte 0x0 6. "TPCC_A_INT5,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" newline bitfld.tbyte 0x0 5. "TPCC_A_INT4,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" newline bitfld.tbyte 0x0 4. "TPCC_A_INT3,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" newline bitfld.tbyte 0x0 3. "TPCC_A_INT2,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" newline bitfld.tbyte 0x0 2. "TPCC_A_INT1,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" newline bitfld.tbyte 0x0 1. "TPCC_A_INT0,Raw Status of Interrupt from TPCC A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_INTAGG_MASK" "0,1" newline bitfld.tbyte 0x0 0. "TPCC_A_INTG,Raw Status of Interrupt from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_C_INTAGG_MASK" "0,1" group.long 0xFD0++0xF line.long 0x0 "MSS_CTRL_HW_SPARE_RW0" hexmask.long 0x0 0.--31. 1. "HW_SPARE_RW0,Reserved for HW R&D" line.long 0x4 "MSS_CTRL_HW_SPARE_RW1" hexmask.long 0x4 0.--31. 1. "HW_SPARE_RW1,Reserved for HW R&D" line.long 0x8 "MSS_CTRL_HW_SPARE_RW2" hexmask.long 0x8 0.--31. 1. "HW_SPARE_RW2,Reserved for HW R&D" line.long 0xC "MSS_CTRL_HW_SPARE_RW3" hexmask.long 0xC 0.--31. 1. "HW_SPARE_RW3,Reserved for HW R&D" rgroup.long 0xFE0++0xF line.long 0x0 "MSS_CTRL_HW_SPARE_RO0" hexmask.long 0x0 0.--31. 1. "HW_SPARE_RO0,Reserved for HW R&D" line.long 0x4 "MSS_CTRL_HW_SPARE_RO1" hexmask.long 0x4 0.--31. 1. "HW_SPARE_RO1,Reserved for HW R&D" line.long 0x8 "MSS_CTRL_HW_SPARE_RO2" hexmask.long 0x8 0.--31. 1. "HW_SPARE_RO2,Reserved for HW R&D" line.long 0xC "MSS_CTRL_HW_SPARE_RO3" hexmask.long 0xC 0.--31. 1. "HW_SPARE_RO3,Reserved for HW R&D" group.long 0xFF0++0x3 line.long 0x0 "MSS_CTRL_HW_SPARE_REC" bitfld.long 0x0 31. "HW_SPARE_REC31,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 30. "HW_SPARE_REC30,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 29. "HW_SPARE_REC29,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 28. "HW_SPARE_REC28,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 27. "HW_SPARE_REC27,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 26. "HW_SPARE_REC26,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 25. "HW_SPARE_REC25,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 24. "HW_SPARE_REC24,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 23. "HW_SPARE_REC23,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 22. "HW_SPARE_REC22,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 21. "HW_SPARE_REC21,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 20. "HW_SPARE_REC20,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 19. "HW_SPARE_REC19,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 18. "HW_SPARE_REC18,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 17. "HW_SPARE_REC17,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 16. "HW_SPARE_REC16,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 15. "HW_SPARE_REC15,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 14. "HW_SPARE_REC14,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 13. "HW_SPARE_REC13,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 12. "HW_SPARE_REC12,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 11. "HW_SPARE_REC11,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 10. "HW_SPARE_REC10,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 9. "HW_SPARE_REC9,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 8. "HW_SPARE_REC8,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 7. "HW_SPARE_REC7,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 6. "HW_SPARE_REC6,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 5. "HW_SPARE_REC5,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 4. "HW_SPARE_REC4,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 3. "HW_SPARE_REC3,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 2. "HW_SPARE_REC2,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 1. "HW_SPARE_REC1,Reserved for HW R&D" "0,1" newline bitfld.long 0x0 0. "HW_SPARE_REC0,Reserved for HW R&D" "0,1" group.long 0x1008++0x7 line.long 0x0 "MSS_CTRL_LOCK0_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "MSS_CTRL_LOCK0_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" group.byte 0x1010++0x0 line.byte 0x0 "MSS_CTRL_INTR_RAW_STATUS" bitfld.byte 0x0 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" group.byte 0x1014++0x0 line.byte 0x0 "MSS_CTRL_INTR_ENABLED_STATUS_CLEAR" bitfld.byte 0x0 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" group.byte 0x1018++0x0 line.byte 0x0 "MSS_CTRL_INTR_ENABLE" bitfld.byte 0x0 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" group.byte 0x101C++0x0 line.byte 0x0 "MSS_CTRL_INTR_ENABLE_CLEAR" bitfld.byte 0x0 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.byte 0x1020++0x0 line.byte 0x0 "MSS_CTRL_EOI" hexmask.byte 0x0 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0x3 line.long 0x0 "MSS_CTRL_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." rgroup.byte 0x1028++0x0 line.byte 0x0 "MSS_CTRL_FAULT_TYPE_STATUS" bitfld.byte 0x0 6. "FAULT_NS,Non-secure access." "0,1" newline hexmask.byte 0x0 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1.." rgroup.long 0x102C++0x3 line.long 0x0 "MSS_CTRL_FAULT_ATTR_STATUS" hexmask.long.word 0x0 20.--31. 1. "FAULT_XID,XID." newline hexmask.long.word 0x0 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x0 0.--7. 1. "FAULT_PRIVID,Privilege ID." wgroup.long 0x1030++0x3 line.long 0x0 "MSS_CTRL_FAULT_CLEAR" bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" group.long 0x4000++0x7 line.long 0x0 "MSS_CTRL_R5SS0_CORE0_MBOX_WRITE_DONE" bitfld.long 0x0 28. "PROC_7,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 7" "0,1" newline bitfld.long 0x0 24. "PROC_6,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 6" "0,1" newline bitfld.long 0x0 20. "PROC_5,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 5" "0,1" newline bitfld.long 0x0 16. "PROC_4,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 4" "0,1" newline bitfld.long 0x0 12. "PROC_3,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 3" "0,1" newline bitfld.long 0x0 8. "PROC_2,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 2" "0,1" newline bitfld.long 0x0 4. "PROC_1,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 1" "0,1" newline bitfld.long 0x0 0. "PROC_0,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 0" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_CORE0_MBOX_READ_REQ" bitfld.long 0x4 28. "PROC_7,This is request from processor 7 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 24. "PROC_6,This is request from processor 6 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 20. "PROC_5,This is request from processor 5 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 16. "PROC_4,This is request from processor 4 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 12. "PROC_3,This is request from processor 3 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 8. "PROC_2,This is request from processor 2 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 4. "PROC_1,This is request from processor 1 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 0. "PROC_0,This is request from processor 0 to mss_cr5a. Requesting it to read from mailbox." "0,1" group.byte 0x4008++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CORE0_MBOX_READ_DONE_ACK" hexmask.byte 0x0 0.--7. 1. "PROC,Write pulse bit field:For bits 0 to 7:Wrting1'b1 : Generates pulse interrupt to corresponding proc from MSS_CR5" group.long 0x400C++0x7 line.long 0x0 "MSS_CTRL_R5SS0_CORE0_MBOX_READ_DONE" bitfld.long 0x0 28. "PROC_7,This register should be written once finishing reading from CR5A's mailbox written by proc 7" "0,1" newline bitfld.long 0x0 24. "PROC_6,This register should be written once finishing reading from CR5A's mailbox written by proc 6" "0,1" newline bitfld.long 0x0 20. "PROC_5,This register should be written once finishing reading from CR5A's mailbox written by proc 5" "0,1" newline bitfld.long 0x0 16. "PROC_4,This register should be written once finishing reading from CR5A's mailbox written by proc 4" "0,1" newline bitfld.long 0x0 12. "PROC_3,This register should be written once finishing reading from CR5A's mailbox written by proc 3" "0,1" newline bitfld.long 0x0 8. "PROC_2,This register should be written once finishing reading from CR5A's mailbox written by proc 2" "0,1" newline bitfld.long 0x0 4. "PROC_1,This register should be written once finishing reading from CR5A's mailbox written by proc 1" "0,1" newline bitfld.long 0x0 0. "PROC_0,This register should be written once finishing reading from CR5A's mailbox written by proc 0" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_CORE0_SW_INT" bitfld.long 0x4 0. "PULSE,Write_pulse bit field:writing 1'b1 to each bit will trigger MSS_SW_INT respectively to CR5A/B." "0,1" group.tbyte 0x4020++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS0_CPU0_MASK" bitfld.tbyte 0x0 17. "MPU_HSM_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" group.tbyte 0x4024++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS" bitfld.tbyte 0x0 17. "MPU_HSM_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" group.tbyte 0x4028++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS0_CPU0_STATUS_RAW" bitfld.tbyte 0x0 17. "MPU_HSM_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" group.tbyte 0x4030++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS0_CPU0_MASK" bitfld.tbyte 0x0 17. "MPU_HSM_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" group.tbyte 0x4034++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS" bitfld.tbyte 0x0 17. "MPU_HSM_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" group.tbyte 0x4038++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS0_CPU0_STATUS_RAW" bitfld.tbyte 0x0 17. "MPU_HSM_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" group.long 0x8000++0x7 line.long 0x0 "MSS_CTRL_R5SS0_CORE1_MBOX_WRITE_DONE" bitfld.long 0x0 28. "PROC_7,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 7" "0,1" newline bitfld.long 0x0 24. "PROC_6,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 6" "0,1" newline bitfld.long 0x0 20. "PROC_5,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 5" "0,1" newline bitfld.long 0x0 16. "PROC_4,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 4" "0,1" newline bitfld.long 0x0 12. "PROC_3,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 3" "0,1" newline bitfld.long 0x0 8. "PROC_2,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 2" "0,1" newline bitfld.long 0x0 4. "PROC_1,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 1" "0,1" newline bitfld.long 0x0 0. "PROC_0,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 0" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_CORE1_MBOX_READ_REQ" bitfld.long 0x4 28. "PROC_7,This is request from processor 7 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 24. "PROC_6,This is request from processor 6 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 20. "PROC_5,This is request from processor 5 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 16. "PROC_4,This is request from processor 4 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 12. "PROC_3,This is request from processor 3 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 8. "PROC_2,This is request from processor 2 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 4. "PROC_1,This is request from processor 1 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 0. "PROC_0,This is request from processor 0 to mss_CR5B. Requesting it to read from mailbox." "0,1" group.byte 0x8008++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CORE1_MBOX_READ_DONE_ACK" hexmask.byte 0x0 0.--7. 1. "PROC,Write pulse bit field:For bits 0 to 7:Wrting1'b1 : Generates pulse interrupt to corresponding proc from MSS_CR5" group.long 0x800C++0x7 line.long 0x0 "MSS_CTRL_R5SS0_CORE1_MBOX_READ_DONE" bitfld.long 0x0 28. "PROC_7,This register should be written once finishing reading from CR5B's mailbox written by proc 7" "0,1" newline bitfld.long 0x0 24. "PROC_6,This register should be written once finishing reading from CR5B's mailbox written by proc 6" "0,1" newline bitfld.long 0x0 20. "PROC_5,This register should be written once finishing reading from CR5B's mailbox written by proc 5" "0,1" newline bitfld.long 0x0 16. "PROC_4,This register should be written once finishing reading from CR5B's mailbox written by proc 4" "0,1" newline bitfld.long 0x0 12. "PROC_3,This register should be written once finishing reading from CR5B's mailbox written by proc 3" "0,1" newline bitfld.long 0x0 8. "PROC_2,This register should be written once finishing reading from CR5B's mailbox written by proc 2" "0,1" newline bitfld.long 0x0 4. "PROC_1,This register should be written once finishing reading from CR5B's mailbox written by proc 1" "0,1" newline bitfld.long 0x0 0. "PROC_0,This register should be written once finishing reading from CR5B's mailbox written by proc 0" "0,1" line.long 0x4 "MSS_CTRL_R5SS0_CORE1_SW_INT" bitfld.long 0x4 0. "PULSE,Write_pulse bit field:writing 1'b1 to each bit will trigger MSS_SW_INT respectively to CR5A/B." "0,1" group.tbyte 0x8020++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS0_CPU1_MASK" bitfld.tbyte 0x0 17. "MPU_HSM_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" group.tbyte 0x8024++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS" bitfld.tbyte 0x0 17. "MPU_HSM_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" group.tbyte 0x8028++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS0_CPU1_STATUS_RAW" bitfld.tbyte 0x0 17. "MPU_HSM_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" group.tbyte 0x8030++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS0_CPU1_MASK" bitfld.tbyte 0x0 17. "MPU_HSM_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" group.tbyte 0x8034++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS" bitfld.tbyte 0x0 17. "MPU_HSM_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" group.tbyte 0x8038++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS0_CPU1_STATUS_RAW" bitfld.tbyte 0x0 17. "MPU_HSM_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" group.long 0xC000++0x7 line.long 0x0 "MSS_CTRL_R5SS1_CORE0_MBOX_WRITE_DONE" bitfld.long 0x0 28. "PROC_7,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 7" "0,1" newline bitfld.long 0x0 24. "PROC_6,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 6" "0,1" newline bitfld.long 0x0 20. "PROC_5,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 5" "0,1" newline bitfld.long 0x0 16. "PROC_4,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 4" "0,1" newline bitfld.long 0x0 12. "PROC_3,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 3" "0,1" newline bitfld.long 0x0 8. "PROC_2,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 2" "0,1" newline bitfld.long 0x0 4. "PROC_1,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 1" "0,1" newline bitfld.long 0x0 0. "PROC_0,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 0" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_CORE0_MBOX_READ_REQ" bitfld.long 0x4 28. "PROC_7,This is request from processor 7 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 24. "PROC_6,This is request from processor 6 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 20. "PROC_5,This is request from processor 5 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 16. "PROC_4,This is request from processor 4 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 12. "PROC_3,This is request from processor 3 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 8. "PROC_2,This is request from processor 2 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 4. "PROC_1,This is request from processor 1 to mss_cr5a. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 0. "PROC_0,This is request from processor 0 to mss_cr5a. Requesting it to read from mailbox." "0,1" group.byte 0xC008++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CORE0_MBOX_READ_DONE_ACK" hexmask.byte 0x0 0.--7. 1. "PROC,Write pulse bit field:For bits 0 to 7:Wrting1'b1 : Generates pulse interrupt to corresponding proc from MSS_CR5" group.long 0xC00C++0x7 line.long 0x0 "MSS_CTRL_R5SS1_CORE0_MBOX_READ_DONE" bitfld.long 0x0 28. "PROC_7,This register should be written once finishing reading from CR5A's mailbox written by proc 7" "0,1" newline bitfld.long 0x0 24. "PROC_6,This register should be written once finishing reading from CR5A's mailbox written by proc 6" "0,1" newline bitfld.long 0x0 20. "PROC_5,This register should be written once finishing reading from CR5A's mailbox written by proc 5" "0,1" newline bitfld.long 0x0 16. "PROC_4,This register should be written once finishing reading from CR5A's mailbox written by proc 4" "0,1" newline bitfld.long 0x0 12. "PROC_3,This register should be written once finishing reading from CR5A's mailbox written by proc 3" "0,1" newline bitfld.long 0x0 8. "PROC_2,This register should be written once finishing reading from CR5A's mailbox written by proc 2" "0,1" newline bitfld.long 0x0 4. "PROC_1,This register should be written once finishing reading from CR5A's mailbox written by proc 1" "0,1" newline bitfld.long 0x0 0. "PROC_0,This register should be written once finishing reading from CR5A's mailbox written by proc 0" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_CORE0_SW_INT" bitfld.long 0x4 0. "PULSE,Write_pulse bit field:writing 1'b1 to each bit will trigger MSS_SW_INT respectively to CR5A/B." "0,1" group.tbyte 0xC020++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS1_CPU0_MASK" bitfld.tbyte 0x0 17. "MPU_HSM_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" group.tbyte 0xC024++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS" bitfld.tbyte 0x0 17. "MPU_HSM_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" group.tbyte 0xC028++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS1_CPU0_STATUS_RAW" bitfld.tbyte 0x0 17. "MPU_HSM_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" group.tbyte 0xC030++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS1_CPU0_MASK" bitfld.tbyte 0x0 17. "MPU_HSM_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" group.tbyte 0xC034++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS" bitfld.tbyte 0x0 17. "MPU_HSM_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" group.tbyte 0xC038++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS1_CPU0_STATUS_RAW" bitfld.tbyte 0x0 17. "MPU_HSM_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" group.long 0x10000++0x7 line.long 0x0 "MSS_CTRL_R5SS1_CORE1_MBOX_WRITE_DONE" bitfld.long 0x0 28. "PROC_7,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 7" "0,1" newline bitfld.long 0x0 24. "PROC_6,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 6" "0,1" newline bitfld.long 0x0 20. "PROC_5,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 5" "0,1" newline bitfld.long 0x0 16. "PROC_4,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 4" "0,1" newline bitfld.long 0x0 12. "PROC_3,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 3" "0,1" newline bitfld.long 0x0 8. "PROC_2,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 2" "0,1" newline bitfld.long 0x0 4. "PROC_1,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 1" "0,1" newline bitfld.long 0x0 0. "PROC_0,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 0" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_CORE1_MBOX_READ_REQ" bitfld.long 0x4 28. "PROC_7,This is request from processor 7 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 24. "PROC_6,This is request from processor 6 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 20. "PROC_5,This is request from processor 5 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 16. "PROC_4,This is request from processor 4 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 12. "PROC_3,This is request from processor 3 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 8. "PROC_2,This is request from processor 2 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 4. "PROC_1,This is request from processor 1 to mss_CR5B. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 0. "PROC_0,This is request from processor 0 to mss_CR5B. Requesting it to read from mailbox." "0,1" group.byte 0x10008++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CORE1_MBOX_READ_DONE_ACK" hexmask.byte 0x0 0.--7. 1. "PROC,Write pulse bit field:For bits 0 to 7:Wrting1'b1 : Generates pulse interrupt to corresponding proc from MSS_CR5" group.long 0x1000C++0x7 line.long 0x0 "MSS_CTRL_R5SS1_CORE1_MBOX_READ_DONE" bitfld.long 0x0 28. "PROC_7,This register should be written once finishing reading from CR5B's mailbox written by proc 7" "0,1" newline bitfld.long 0x0 24. "PROC_6,This register should be written once finishing reading from CR5B's mailbox written by proc 6" "0,1" newline bitfld.long 0x0 20. "PROC_5,This register should be written once finishing reading from CR5B's mailbox written by proc 5" "0,1" newline bitfld.long 0x0 16. "PROC_4,This register should be written once finishing reading from CR5B's mailbox written by proc 4" "0,1" newline bitfld.long 0x0 12. "PROC_3,This register should be written once finishing reading from CR5B's mailbox written by proc 3" "0,1" newline bitfld.long 0x0 8. "PROC_2,This register should be written once finishing reading from CR5B's mailbox written by proc 2" "0,1" newline bitfld.long 0x0 4. "PROC_1,This register should be written once finishing reading from CR5B's mailbox written by proc 1" "0,1" newline bitfld.long 0x0 0. "PROC_0,This register should be written once finishing reading from CR5B's mailbox written by proc 0" "0,1" line.long 0x4 "MSS_CTRL_R5SS1_CORE1_SW_INT" bitfld.long 0x4 0. "PULSE,Write_pulse bit field:writing 1'b1 to each bit will trigger MSS_SW_INT respectively to CR5A/B." "0,1" group.tbyte 0x10020++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS1_CPU1_MASK" bitfld.tbyte 0x0 17. "MPU_HSM_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_ADDR_ERR,Mask Error from MPU_ADDR_INTR to aggregated Error MPU_ADDR_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" group.tbyte 0x10024++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS" bitfld.tbyte 0x0 17. "MPU_HSM_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_ADDR_ERR,Status of Error from MPU_ADDR_INTR. Set only if Interupt is unmasked in MPU_ADDR_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" group.tbyte 0x10028++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_ADDR_ERRAGG_R5SS1_CPU1_STATUS_RAW" bitfld.tbyte 0x0 17. "MPU_HSM_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_ADDR_ERR,Raw Status of Error from MPU_ADDR_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_ADDR_INTR_ERRAGG_MASK" "0,1" group.tbyte 0x10030++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS1_CPU1_MASK" bitfld.tbyte 0x0 17. "MPU_HSM_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_PROT_ERR,Mask Error from MPU_PROT_INTR to aggregated Error MPU_PROT_INTR_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" group.tbyte 0x10034++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS" bitfld.tbyte 0x0 17. "MPU_HSM_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_PROT_ERR,Status of Error from MPU_PROT_INTR. Set only if Interupt is unmasked in MPU_PROT_INTR_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" group.tbyte 0x10038++0x2 line.tbyte 0x0 "MSS_CTRL_MPU_PROT_ERRAGG_R5SS1_CPU1_STATUS_RAW" bitfld.tbyte 0x0 17. "MPU_HSM_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 16. "MPU_CR5B1_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 15. "MPU_CR5A1_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 14. "MPU_CR5B0_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 13. "MPU_CR5A0_AHB_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 12. "MPU_SCRM2SCRP1_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 11. "MPU_SCRM2SCRP0_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 10. "MPU_QSPI_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 9. "MPU_MBOX_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 8. "MPU_DTHE_A_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 7. "MPU_CR5B1_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 6. "MPU_CR5A1_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 5. "MPU_CR5B0_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 4. "MPU_CR5A0_AXIS_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 3. "MPU_L2_BANK_D_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 2. "MPU_L2_BANK_C_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 1. "MPU_L2_BANK_B_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" newline bitfld.tbyte 0x0 0. "MPU_L2_BANK_A_PROT_ERR,Raw Status of Error from MPU_PROT_INTR. Set irrespective if the Interupt is masked or unmasked in MPU_PROT_INTR_ERRAGG_MASK" "0,1" group.long 0x14000++0x7 line.long 0x0 "MSS_CTRL_ICSSM_PRU0_MBOX_WRITE_DONE" bitfld.long 0x0 28. "PROC_7,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 7" "0,1" newline bitfld.long 0x0 24. "PROC_6,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 6" "0,1" newline bitfld.long 0x0 20. "PROC_5,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 5" "0,1" newline bitfld.long 0x0 16. "PROC_4,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 4" "0,1" newline bitfld.long 0x0 12. "PROC_3,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 3" "0,1" newline bitfld.long 0x0 8. "PROC_2,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 2" "0,1" newline bitfld.long 0x0 4. "PROC_1,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 1" "0,1" newline bitfld.long 0x0 0. "PROC_0,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 0" "0,1" line.long 0x4 "MSS_CTRL_ICSSM_PRU0_MBOX_READ_REQ" bitfld.long 0x4 28. "PROC_7,This is request from processor 7 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 24. "PROC_6,This is request from processor 6 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 20. "PROC_5,This is request from processor 5 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 16. "PROC_4,This is request from processor 4 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 12. "PROC_3,This is request from processor 3 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 8. "PROC_2,This is request from processor 2 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 4. "PROC_1,This is request from processor 1 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x4 0. "PROC_0,This is request from processor 0 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" group.byte 0x14008++0x0 line.byte 0x0 "MSS_CTRL_ICSSM_PRU0_MBOX_READ_DONE_ACK" hexmask.byte 0x0 0.--7. 1. "PROC,Write pulse bit field:For bits 0 to 7:Wrting1'b1 : Generates pulse interrupt to corresponding proc from ICSSM_PRU0.For bits 8 to 15:Wrting1'b1 : Generates pulse interrupt to corresponding proc from ICSSM_PRU1." group.long 0x1400C++0xB line.long 0x0 "MSS_CTRL_ICSSM_PRU0_MBOX_READ_DONE" bitfld.long 0x0 28. "PROC_7,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 7" "0,1" newline bitfld.long 0x0 24. "PROC_6,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 6" "0,1" newline bitfld.long 0x0 20. "PROC_5,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 5" "0,1" newline bitfld.long 0x0 16. "PROC_4,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 4" "0,1" newline bitfld.long 0x0 12. "PROC_3,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 3" "0,1" newline bitfld.long 0x0 8. "PROC_2,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 2" "0,1" newline bitfld.long 0x0 4. "PROC_1,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 1" "0,1" newline bitfld.long 0x0 0. "PROC_0,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 0" "0,1" line.long 0x4 "MSS_CTRL_ICSSM_PRU1_MBOX_WRITE_DONE" bitfld.long 0x4 28. "PROC_7,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 7" "0,1" newline bitfld.long 0x4 24. "PROC_6,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 6" "0,1" newline bitfld.long 0x4 20. "PROC_5,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 5" "0,1" newline bitfld.long 0x4 16. "PROC_4,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 4" "0,1" newline bitfld.long 0x4 12. "PROC_3,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 3" "0,1" newline bitfld.long 0x4 8. "PROC_2,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 2" "0,1" newline bitfld.long 0x4 4. "PROC_1,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 1" "0,1" newline bitfld.long 0x4 0. "PROC_0,Write pulse bit field:This register should be written once finishing writing into the mailbox memory of processor 0" "0,1" line.long 0x8 "MSS_CTRL_ICSSM_PRU1_MBOX_READ_REQ" bitfld.long 0x8 28. "PROC_7,This is request from processor 7 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x8 24. "PROC_6,This is request from processor 6 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x8 20. "PROC_5,This is request from processor 5 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x8 16. "PROC_4,This is request from processor 4 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x8 12. "PROC_3,This is request from processor 3 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x8 8. "PROC_2,This is request from processor 2 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x8 4. "PROC_1,This is request from processor 1 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" newline bitfld.long 0x8 0. "PROC_0,This is request from processor 0 to corresponding ICSSM_PRU. Requesting it to read from mailbox." "0,1" group.byte 0x14018++0x0 line.byte 0x0 "MSS_CTRL_ICSSM_PRU1_MBOX_READ_DONE_ACK" hexmask.byte 0x0 0.--7. 1. "PROC,Write pulse bit field:For bits 0 to 7:Wrting1'b1 : Generates pulse interrupt to corresponding proc from ICSSM_PRU0.For bits 8 to 15:Wrting1'b1 : Generates pulse interrupt to corresponding proc from ICSSM_PRU1." group.long 0x1401C++0x3 line.long 0x0 "MSS_CTRL_ICSSM_PRU1_MBOX_READ_DONE" bitfld.long 0x0 28. "PROC_7,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 7" "0,1" newline bitfld.long 0x0 24. "PROC_6,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 6" "0,1" newline bitfld.long 0x0 20. "PROC_5,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 5" "0,1" newline bitfld.long 0x0 16. "PROC_4,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 4" "0,1" newline bitfld.long 0x0 12. "PROC_3,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 3" "0,1" newline bitfld.long 0x0 8. "PROC_2,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 2" "0,1" newline bitfld.long 0x0 4. "PROC_1,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 1" "0,1" newline bitfld.long 0x0 0. "PROC_0,This register should be written once finishing reading from corresponding ICSSM_PRU's mailbox written by proc 0" "0,1" group.long 0x18000++0xB line.long 0x0 "MSS_CTRL_TPCC0_ERRAGG_MASK" bitfld.long 0x0 26. "TPTC_A1_READ_ACCESS_ERROR,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 25. "TPTC_A0_READ_ACCESS_ERROR,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 24. "TPCC_A_READ_ACCESS_ERROR,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 18. "TPTC_A1_WRITE_ACCESS_ERROR,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 17. "TPTC_A0_WRITE_ACCESS_ERROR,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 16. "TPCC_A_WRITE_ACCESS_ERROR,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 4. "TPCC_A_PAR_ERR,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 3. "TPTC_A1_ERR,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 2. "TPTC_A0_ERR,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 1. "TPCC_A_MPINT,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 0. "TPCC_A_ERRINT,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_TPCC0_ERRAGG_STATUS" bitfld.long 0x4 26. "TPTC_A1_READ_ACCESS_ERROR,Status of Error from MSS_TPTC_A1. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 25. "TPTC_A0_READ_ACCESS_ERROR,Status of Error from MSS_TPTC_A0. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 24. "TPCC_A_READ_ACCESS_ERROR,Status of Error from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 18. "TPTC_A1_WRITE_ACCESS_ERROR,Status of Error from MSS_TPTC_A1. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 17. "TPTC_A0_WRITE_ACCESS_ERROR,Status of Error from MSS_TPTC_A0. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 16. "TPCC_A_WRITE_ACCESS_ERROR,Status of Error from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 4. "TPCC_A_PAR_ERR,Status of Error from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 3. "TPTC_A1_ERR,Status of Error from MSS_TPTC_A1. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 2. "TPTC_A0_ERR,Status of Error from MSS_TPTC_A0. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 1. "TPCC_A_MPINT,Status of Error from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 0. "TPCC_A_ERRINT,Status of Error from MSS_TPCC_A. Set only if Interupt is unmasked in MSS_TPCC_A_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" line.long 0x8 "MSS_CTRL_TPCC0_ERRAGG_STATUS_RAW" bitfld.long 0x8 26. "TPTC_A1_READ_ACCESS_ERROR,Raw Status of Error from MSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 25. "TPTC_A0_READ_ACCESS_ERROR,Raw Status of Error from MSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 24. "TPCC_A_READ_ACCESS_ERROR,Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 18. "TPTC_A1_WRITE_ACCESS_ERROR,Raw Status of Error from MSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 17. "TPTC_A0_WRITE_ACCESS_ERROR,Raw Status of Error from MSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 16. "TPCC_A_WRITE_ACCESS_ERROR,Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 4. "TPCC_A_PAR_ERR,Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 3. "TPTC_A1_ERR,Raw Status of Error from MSS_TPTC_A1. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 2. "TPTC_A0_ERR,Raw Status of Error from MSS_TPTC_A0. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 1. "TPCC_A_MPINT,Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 0. "TPCC_A_ERRINT,Raw Status of Error from MSS_TPCC_A. Set irrespective if the Interupt is masked or unmasked in MSS_TPCC_A_ERRAGG_MASK" "0,1" group.word 0x18010++0x1 line.word 0x0 "MSS_CTRL_MMR_ACCESS_ERRAGG_MASK0" bitfld.word 0x0 11. "HSM_CTRL_WR,Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.word 0x0 10. "HSM_CTRL_RD,Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.word 0x0 9. "HSM_SOC_CTRL_WR,Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.word 0x0 8. "HSM_SOC_CTRL_RD,Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.word 0x0 7. "TOP_RCM_WR,Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.word 0x0 6. "TOP_RCM_RD,Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.word 0x0 5. "TOP_CTRL_WR,Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.word 0x0 4. "TOP_CTRL_RD,Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.word 0x0 3. "MSS_RCM_WR,Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.word 0x0 2. "MSS_RCM_RD,Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.word 0x0 1. "MSS_CTRL_WR,Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.word 0x0 0. "MSS_CTRL_RD,Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" group.word 0x18014++0x1 line.word 0x0 "MSS_CTRL_MMR_ACCESS_ERRAGG_STATUS0" bitfld.word 0x0 11. "HSM_CTRL_WR,Status of Interrupt from HSM_CTRLSet only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.word 0x0 10. "HSM_CTRL_RD,Status of Interrupt from HSM_CTRLSet only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.word 0x0 9. "HSM_SOC_CTRL_WR,Status of Interrupt from HSM_SOC_CTRLSet only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.word 0x0 8. "HSM_SOC_CTRL_RD,Status of Interrupt from HSM_SOC_CTRLSet only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.word 0x0 7. "TOP_RCM_WR,Status of Interrupt from TOP_RCMSet only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.word 0x0 6. "TOP_RCM_RD,Status of Interrupt from TOP_RCMSet only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.word 0x0 5. "TOP_CTRL_WR,Status of Interrupt from TOP_CTRLSet only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.word 0x0 4. "TOP_CTRL_RD,Status of Interrupt from TOP_CTRLSet only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.word 0x0 3. "MSS_RCM_WR,Status of Interrupt from MSS_RCMSet only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.word 0x0 2. "MSS_RCM_RD,Status of Interrupt from MSS_RCMSet only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.word 0x0 1. "MSS_CTRL_WR,Status of Interrupt from MSS_CTRLSet only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" newline bitfld.word 0x0 0. "MSS_CTRL_RD,Status of Interrupt from MSS_CTRLSet only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0Wrie 0x1 to clear this interrupt." "0,1" group.word 0x18018++0x1 line.word 0x0 "MSS_CTRL_MMR_ACCESS_ERRAGG_STATUS_RAW0" bitfld.word 0x0 11. "HSM_CTRL_WR,Raw Status of Interrupt from HSM_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1" newline bitfld.word 0x0 10. "HSM_CTRL_RD,Raw Status of Interrupt from HSM_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1" newline bitfld.word 0x0 9. "HSM_SOC_CTRL_WR,Raw Status of Interrupt from HSM_SOC_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1" newline bitfld.word 0x0 8. "HSM_SOC_CTRL_RD,Raw Status of Interrupt from HSM_SOC_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1" newline bitfld.word 0x0 7. "TOP_RCM_WR,Raw Status of Interrupt from TOP_RCM. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1" newline bitfld.word 0x0 6. "TOP_RCM_RD,Raw Status of Interrupt from TOP_RCM. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1" newline bitfld.word 0x0 5. "TOP_CTRL_WR,Raw Status of Interrupt from TOP_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1" newline bitfld.word 0x0 4. "TOP_CTRL_RD,Raw Status of Interrupt from TOP_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1" newline bitfld.word 0x0 3. "MSS_RCM_WR,Raw Status of Interrupt from MSS_RCM. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1" newline bitfld.word 0x0 2. "MSS_RCM_RD,Raw Status of Interrupt from MSS_RCM. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1" newline bitfld.word 0x0 1. "MSS_CTRL_WR,Raw Status of Interrupt from MSS_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1" newline bitfld.word 0x0 0. "MSS_CTRL_RD,Raw Status of Interrupt from MSS_CTRL. Set irrespective if the Interupt is masked or unmasked in MSS_PERIPH_ERRAGG_MASK0" "0,1" group.byte 0x18080++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU0_ECC_CORR_ERRAGG_MASK" bitfld.byte 0x0 6. "R5SS0_CPU0_IDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 5. "R5SS0_CPU0_ITAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 4. "R5SS0_CPU0_DDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 3. "R5SS0_CPU0_DTAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 2. "R5SS0_CPU0_B0TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU0_B1TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU0_ATCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" group.byte 0x18084++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS" bitfld.byte 0x0 6. "R5SS0_CPU0_IDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 5. "R5SS0_CPU0_ITAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 4. "R5SS0_CPU0_DDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS0_CPU0_DTAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS0_CPU0_B0TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU0_B1TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU0_ATCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x18088++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU0_ECC_CORR_ERRAGG_STATUS_RAW" bitfld.byte 0x0 6. "R5SS0_CPU0_IDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 5. "R5SS0_CPU0_ITAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 4. "R5SS0_CPU0_DDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS0_CPU0_DTAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS0_CPU0_B0TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU0_B1TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU0_ATCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x18090++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU0_ECC_UNCORR_ERRAGG_MASK" bitfld.byte 0x0 4. "R5SS0_CPU0_DDATA_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 3. "R5SS0_CPU0_DTAG_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 2. "R5SS0_CPU0_B0TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU0_B1TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU0_ATCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" group.byte 0x18094++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS" bitfld.byte 0x0 4. "R5SS0_CPU0_DDATA_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS0_CPU0_DTAG_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS0_CPU0_B0TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU0_B1TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU0_ATCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x18098++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW" bitfld.byte 0x0 4. "R5SS0_CPU0_DDATA_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS0_CPU0_DTAG_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS0_CPU0_B0TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU0_B1TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU0_ATCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x180A0++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU1_ECC_CORR_ERRAGG_MASK" bitfld.byte 0x0 6. "R5SS0_CPU1_IDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 5. "R5SS0_CPU1_ITAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 4. "R5SS0_CPU1_DDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 3. "R5SS0_CPU1_DTAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 2. "R5SS0_CPU1_B0TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU1_B1TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU1_ATCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" group.byte 0x180A4++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS" bitfld.byte 0x0 6. "R5SS0_CPU1_IDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 5. "R5SS0_CPU1_ITAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 4. "R5SS0_CPU1_DDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS0_CPU1_DTAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS0_CPU1_B0TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU1_B1TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU1_ATCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x180A8++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU1_ECC_CORR_ERRAGG_STATUS_RAW" bitfld.byte 0x0 6. "R5SS0_CPU1_IDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 5. "R5SS0_CPU1_ITAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 4. "R5SS0_CPU1_DDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS0_CPU1_DTAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS0_CPU1_B0TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU1_B1TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU1_ATCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x180B0++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU1_ECC_UNCORR_ERRAGG_MASK" bitfld.byte 0x0 4. "R5SS0_CPU1_DDATA_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 3. "R5SS0_CPU1_DTAG_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 2. "R5SS0_CPU1_B0TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU1_B1TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU1_ATCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" group.byte 0x180B4++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU1_ECC_UNCORR_ERRAGG_STATUS" bitfld.byte 0x0 4. "R5SS0_CPU1_DDATA_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS0_CPU1_DTAG_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS0_CPU1_B0TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU1_B1TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU1_ATCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x180B8++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU1_ECC_UNCORR_ERRAGG_STATUS_RAW" bitfld.byte 0x0 4. "R5SS0_CPU1_DDATA_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS0_CPU1_DTAG_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS0_CPU1_B0TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU1_B1TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU1_ATCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x180C0++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU0_ECC_CORR_ERRAGG_MASK" bitfld.byte 0x0 6. "R5SS1_CPU0_IDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 5. "R5SS1_CPU0_ITAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 4. "R5SS1_CPU0_DDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 3. "R5SS1_CPU0_DTAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 2. "R5SS1_CPU0_B0TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU0_B1TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU0_ATCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" group.byte 0x180C4++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS" bitfld.byte 0x0 6. "R5SS1_CPU0_IDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 5. "R5SS1_CPU0_ITAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 4. "R5SS1_CPU0_DDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS1_CPU0_DTAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS1_CPU0_B0TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU0_B1TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU0_ATCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x180C8++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU0_ECC_CORR_ERRAGG_STATUS_RAW" bitfld.byte 0x0 6. "R5SS1_CPU0_IDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 5. "R5SS1_CPU0_ITAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 4. "R5SS1_CPU0_DDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS1_CPU0_DTAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS1_CPU0_B0TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU0_B1TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU0_ATCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x180D0++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU0_ECC_UNCORR_ERRAGG_MASK" bitfld.byte 0x0 4. "R5SS1_CPU0_DDATA_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 3. "R5SS1_CPU0_DTAG_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 2. "R5SS1_CPU0_B0TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU0_B1TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU0_ATCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" group.byte 0x180D4++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU0_ECC_UNCORR_ERRAGG_STATUS" bitfld.byte 0x0 4. "R5SS1_CPU0_DDATA_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS1_CPU0_DTAG_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS1_CPU0_B0TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU0_B1TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU0_ATCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x180D8++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW" bitfld.byte 0x0 4. "R5SS1_CPU0_DDATA_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS1_CPU0_DTAG_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS1_CPU0_B0TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU0_B1TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU0_ATCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x180E0++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU1_ECC_CORR_ERRAGG_MASK" bitfld.byte 0x0 6. "R5SS1_CPU1_IDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 5. "R5SS1_CPU1_ITAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 4. "R5SS1_CPU1_DDATA_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 3. "R5SS1_CPU1_DTAG_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 2. "R5SS1_CPU1_B0TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU1_B1TCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU1_ATCM_CORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" group.byte 0x180E4++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS" bitfld.byte 0x0 6. "R5SS1_CPU1_IDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 5. "R5SS1_CPU1_ITAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 4. "R5SS1_CPU1_DDATA_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS1_CPU1_DTAG_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS1_CPU1_B0TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU1_B1TCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU1_ATCM_CORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x180E8++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU1_ECC_CORR_ERRAGG_STATUS_RAW" bitfld.byte 0x0 6. "R5SS1_CPU1_IDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 5. "R5SS1_CPU1_ITAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 4. "R5SS1_CPU1_DDATA_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS1_CPU1_DTAG_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS1_CPU1_B0TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU1_B1TCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU1_ATCM_CORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_CORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x180F0++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU1_ECC_UNCORR_ERRAGG_MASK" bitfld.byte 0x0 4. "R5SS1_CPU1_DDATA_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 3. "R5SS1_CPU1_DTAG_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 2. "R5SS1_CPU1_B0TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU1_B1TCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU1_ATCM_UNCORR_ERR,Mask Interrupt for correctable errors to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" group.byte 0x180F4++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU1_ECC_UNCORR_ERRAGG_STATUS" bitfld.byte 0x0 4. "R5SS1_CPU1_DDATA_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS1_CPU1_DTAG_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS1_CPU1_B0TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU1_B1TCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU1_ATCM_UNCORR_ERR,Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x180F8++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU1_ECC_UNCORR_ERRAGG_STATUS_RAW" bitfld.byte 0x0 4. "R5SS1_CPU1_DDATA_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 3. "R5SS1_CPU1_DTAG_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 2. "R5SS1_CPU1_B0TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU1_B1TCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU1_ATCM_UNCORR_ERR,Raw Status of Interrupt from correctable error of corresponding CPUSet only if Interupt is unmasked in corresponding R5SS*_CPU*_ECC_UNCORR_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x18100++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_MASK" bitfld.byte 0x0 2. "R5SS0_CPU0_B1TCM0_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU0_B0TCM0_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU0_ATCM0_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" group.byte 0x18104++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS" bitfld.byte 0x0 2. "R5SS0_CPU0_B1TCM0_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU0_B0TCM0_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU0_ATCM0_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x18108++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_RAW" bitfld.byte 0x0 2. "R5SS0_CPU0_B1TCM0_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU0_B0TCM0_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU0_ATCM0_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x18110++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_MASK" bitfld.byte 0x0 2. "R5SS0_CPU1_B1TCM1_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU1_B1TCM0_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU1_ATCM1_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" group.byte 0x18114++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS" bitfld.byte 0x0 2. "R5SS0_CPU1_B1TCM1_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU1_B0TCM1_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU1_ATCM1_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x18118++0x0 line.byte 0x0 "MSS_CTRL_R5SS0_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_RAW" bitfld.byte 0x0 2. "R5SS0_CPU1_B1TCM1_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS0_CPU1_B0TCM1_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS0_CPU1_ATCM1_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.tbyte 0x18120++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_TCM_ADDRPARITY_CLR" bitfld.tbyte 0x0 20.--22. "B1TCM1_ERRADDR_CLR,Write pulse bit field:writing 3'b111 clears the Address latched after parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 16.--18. "B1TCM0_ERRADDR_CLR,Write pulse bit field:writing 3'b111 clears the Address latched after parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 12.--14. "B0CM1_ERRADDR_CLR,Write pulse bit field:writing 3'b111 clears the Address latched after parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 8.--10. "B0TCM0_ERRADDR_CLR,Write pulse bit field:writing 3'b111 clears the Address latched after parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 4.--6. "ATCM1_ERRADDR_CLR,Write pulse bit field:writing 3'b111 clears the Address latched after parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 0.--2. "ATCM0_ERRADDR_CLR,Pulse bit-field writing 3'b111 clears the Address latched after parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7" rgroup.tbyte 0x18124++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE0_ADDRPARITY_ERR_ATCM" hexmask.tbyte 0x0 0.--19. 1. "ADDR,Address lathched when parity error is occurred for ATCM of CR5A" rgroup.tbyte 0x18128++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE1_ADDRPARITY_ERR_ATCM" hexmask.tbyte 0x0 0.--19. 1. "ADDR,Address lathched when parity error is occurred for ATCM of CR5B" rgroup.tbyte 0x1812C++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE0_ERR_ADDRPARITY_B0TCM" hexmask.tbyte 0x0 0.--19. 1. "ADDR,Address lathched when parity error is occurred for B0TCM of CR5A" rgroup.tbyte 0x18130++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE1_ERR_ADDRPARITY_B0TCM" hexmask.tbyte 0x0 0.--19. 1. "ADDR,Address lathched when parity error is occurred for B0TCM of CR5B" rgroup.tbyte 0x18134++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE0_ERR_ADDRPARITY_B1TCM" hexmask.tbyte 0x0 0.--19. 1. "ADDR,Address lathched when parity error is occurred for B1TCM of CR5A" rgroup.tbyte 0x18138++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE1_ERR_ADDRPARITY_B1TCM" hexmask.tbyte 0x0 0.--19. 1. "ADDR,Address lathched when parity error is occurred for B1TCM of CR5B" group.tbyte 0x1813C++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_TCM_ADDRPARITY_ERRFORCE" bitfld.tbyte 0x0 20.--22. "B1TCM1,Write pulse bit field:writing 3'b111 forces a parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 16.--18. "B1TCM0,Write pulse bit field:writing 3'b111 forces a parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 12.--14. "B0TCM1,Write pulse bit field:writing 3'b111 forces a parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 8.--10. "B0TCM0,Write pulse bit field:writing 3'b111 forces a parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 4.--6. "ATCM1,Write pulse bit field:writing 3'b111 forces a parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 0.--2. "ATCM0,Write pulse bit field:writing 3'b111 forces a parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7" group.byte 0x18140++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU0_TCM_ADDRPARITY_ERRAGG_MASK" bitfld.byte 0x0 2. "R5SS1_CPU0_B1TCM0_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU0_B0TCM0_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU0_ATCM0_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" group.byte 0x18144++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS" bitfld.byte 0x0 2. "R5SS1_CPU0_B1TCM0_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU0_B0TCM0_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU0_ATCM0_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x18148++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU0_TCM_ADDRPARITY_ERRAGG_STATUS_RAW" bitfld.byte 0x0 2. "R5SS1_CPU0_B1TCM0_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU0_B0TCM0_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU0_ATCM0_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x18150++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU1_TCM_ADDRPARITY_ERRAGG_MASK" bitfld.byte 0x0 2. "R5SS1_CPU1_B1TCM1_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU1_B0TCM1_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU1_ATCM1_PARITY_ERR,Mask Interrupt for address parity error s to aggregated Interrupt of corresponding CPU1 : Interrupt is Masked0 : Interrupt is Unmasked" "0,1" group.byte 0x18154++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS" bitfld.byte 0x0 2. "R5SS1_CPU1_B1TCM1_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU1_B0TCM1_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU1_ATCM1_PARITY_ERR,Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.byte 0x18158++0x0 line.byte 0x0 "MSS_CTRL_R5SS1_CPU1_TCM_ADDRPARITY_ERRAGG_STATUS_RAW" bitfld.byte 0x0 2. "R5SS1_CPU1_B1TCM1_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 1. "R5SS1_CPU1_B0TCM1_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" newline bitfld.byte 0x0 0. "R5SS1_CPU1_ATCM1_PARITY_ERR,Raw Status of Interrupt from address parity error of corresponding CPU*_TCM_ADDRPARITY_ERRAGG_MASK registerWrie 0x1 to clear this interrupt." "0,1" group.tbyte 0x18160++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_TCM_ADDRPARITY_CLR" bitfld.tbyte 0x0 20.--22. "B1TCM1_ERRADDR_CLR,Write pulse bit field:writing 3'b111 clears the Address latched after parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 16.--18. "B1TCM0_ERRADDR_CLR,Write pulse bit field:writing 3'b111 clears the Address latched after parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 12.--14. "B0CM1_ERRADDR_CLR,Write pulse bit field:writing 3'b111 clears the Address latched after parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 8.--10. "B0TCM0_ERRADDR_CLR,Write pulse bit field:writing 3'b111 clears the Address latched after parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 4.--6. "ATCM1_ERRADDR_CLR,Write pulse bit field:writing 3'b111 clears the Address latched after parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 0.--2. "ATCM0_ERRADDR_CLR,Pulse bit-field writing 3'b111 clears the Address latched after parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7" rgroup.tbyte 0x18164++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE0_ADDRPARITY_ERR_ATCM" hexmask.tbyte 0x0 0.--19. 1. "ADDR,Address lathched when parity error is occurred for ATCM of CR5A" rgroup.tbyte 0x18168++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE1_ADDRPARITY_ERR_ATCM" hexmask.tbyte 0x0 0.--19. 1. "ADDR,Address lathched when parity error is occurred for ATCM of CR5B" rgroup.tbyte 0x1816C++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE0_ERR_ADDRPARITY_B0TCM" hexmask.tbyte 0x0 0.--19. 1. "ADDR,Address lathched when parity error is occurred for B0TCM of CR5A" rgroup.tbyte 0x18170++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE1_ERR_ADDRPARITY_B0TCM" hexmask.tbyte 0x0 0.--19. 1. "ADDR,Address lathched when parity error is occurred for B0TCM of CR5B" rgroup.tbyte 0x18174++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE0_ERR_ADDRPARITY_B1TCM" hexmask.tbyte 0x0 0.--19. 1. "ADDR,Address lathched when parity error is occurred for B1TCM of CR5A" rgroup.tbyte 0x18178++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE1_ERR_ADDRPARITY_B1TCM" hexmask.tbyte 0x0 0.--19. 1. "ADDR,Address lathched when parity error is occurred for B1TCM of CR5B" group.tbyte 0x1817C++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_TCM_ADDRPARITY_ERRFORCE" bitfld.tbyte 0x0 20.--22. "B1TCM1,Write pulse bit field:writing 3'b111 forces a parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 16.--18. "B1TCM0,Write pulse bit field:writing 3'b111 forces a parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 12.--14. "B0TCM1,Write pulse bit field:writing 3'b111 forces a parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 8.--10. "B0TCM0,Write pulse bit field:writing 3'b111 forces a parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 4.--6. "ATCM1,Write pulse bit field:writing 3'b111 forces a parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7" newline bitfld.tbyte 0x0 0.--2. "ATCM0,Write pulse bit field:writing 3'b111 forces a parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7" group.long 0x18180++0x3 line.long 0x0 "MSS_CTRL_TPCC0_PARITY_CTRL" bitfld.long 0x0 16. "TPCC_A_PARITY_ERR_CLR,Write pulse bit field:parity clear bit. Writing 1'b1 will clear the tpcc_a_parity_addr" "0,1" newline bitfld.long 0x0 4. "TPCC_A_PARITY_TESTEN,parity test enable for tpcc a" "0,1" newline bitfld.long 0x0 0. "TPCC_A_PARITY_EN,writing 1'b1 enables parity for TPCC_A" "0,1" rgroup.word 0x18184++0x1 line.word 0x0 "MSS_CTRL_TPCC0_PARITY_STATUS" hexmask.word 0x0 0.--8. 1. "TPCC_A_PARITY_ADDR,address where parity error happened for tpcca" group.byte 0x18200++0x0 line.byte 0x0 "MSS_CTRL_BUS_SAFETY_CTRL" bitfld.byte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.tbyte 0x18220++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE0_AXI_RD_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18224++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE0_AXI_RD_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18228++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE0_AXI_RD_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1822C++0x1 line.word 0x0 "MSS_CTRL_R5SS0_CORE0_AXI_RD_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18230++0x7 line.long 0x0 "MSS_CTRL_R5SS0_CORE0_AXI_RD_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS0_CORE0_AXI_RD_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18240++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE1_AXI_RD_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18244++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE1_AXI_RD_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18248++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE1_AXI_RD_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1824C++0x1 line.word 0x0 "MSS_CTRL_R5SS0_CORE1_AXI_RD_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18250++0x7 line.long 0x0 "MSS_CTRL_R5SS0_CORE1_AXI_RD_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS0_CORE1_AXI_RD_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18260++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE0_AXI_RD_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18264++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE0_AXI_RD_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18268++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE0_AXI_RD_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1826C++0x1 line.word 0x0 "MSS_CTRL_R5SS1_CORE0_AXI_RD_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18270++0x7 line.long 0x0 "MSS_CTRL_R5SS1_CORE0_AXI_RD_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS1_CORE0_AXI_RD_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18280++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE1_AXI_RD_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18284++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE1_AXI_RD_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18288++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE1_AXI_RD_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1828C++0x1 line.word 0x0 "MSS_CTRL_R5SS1_CORE1_AXI_RD_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18290++0x7 line.long 0x0 "MSS_CTRL_R5SS1_CORE1_AXI_RD_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS1_CORE1_AXI_RD_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x182A0++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE0_AXI_WR_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x182A4++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE0_AXI_WR_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x182A8++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE0_AXI_WR_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x182AC++0x1 line.word 0x0 "MSS_CTRL_R5SS0_CORE0_AXI_WR_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x182B0++0xB line.long 0x0 "MSS_CTRL_R5SS0_CORE0_AXI_WR_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS0_CORE0_AXI_WR_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_R5SS0_CORE0_AXI_WR_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x182C0++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE1_AXI_WR_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x182C4++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE1_AXI_WR_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x182C8++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE1_AXI_WR_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x182CC++0x1 line.word 0x0 "MSS_CTRL_R5SS0_CORE1_AXI_WR_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x182D0++0xB line.long 0x0 "MSS_CTRL_R5SS0_CORE1_AXI_WR_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS0_CORE1_AXI_WR_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_R5SS0_CORE1_AXI_WR_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x182E0++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE0_AXI_WR_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x182E4++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE0_AXI_WR_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x182E8++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE0_AXI_WR_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x182EC++0x1 line.word 0x0 "MSS_CTRL_R5SS1_CORE0_AXI_WR_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x182F0++0xB line.long 0x0 "MSS_CTRL_R5SS1_CORE0_AXI_WR_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS1_CORE0_AXI_WR_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_R5SS1_CORE0_AXI_WR_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18300++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE1_AXI_WR_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18304++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE1_AXI_WR_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18308++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE1_AXI_WR_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1830C++0x1 line.word 0x0 "MSS_CTRL_R5SS1_CORE1_AXI_WR_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18310++0xB line.long 0x0 "MSS_CTRL_R5SS1_CORE1_AXI_WR_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS1_CORE1_AXI_WR_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_R5SS1_CORE1_AXI_WR_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18320++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE0_AXI_S_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18324++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE0_AXI_S_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18328++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE0_AXI_S_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1832C++0x1 line.word 0x0 "MSS_CTRL_R5SS0_CORE0_AXI_S_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18330++0xF line.long 0x0 "MSS_CTRL_R5SS0_CORE0_AXI_S_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS0_CORE0_AXI_S_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_R5SS0_CORE0_AXI_S_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_R5SS0_CORE0_AXI_S_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18340++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE1_AXI_S_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18344++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE1_AXI_S_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18348++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE1_AXI_S_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1834C++0x1 line.word 0x0 "MSS_CTRL_R5SS0_CORE1_AXI_S_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18350++0xF line.long 0x0 "MSS_CTRL_R5SS0_CORE1_AXI_S_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS0_CORE1_AXI_S_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_R5SS0_CORE1_AXI_S_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_R5SS0_CORE1_AXI_S_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18360++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE0_AXI_S_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18364++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE0_AXI_S_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18368++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE0_AXI_S_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1836C++0x1 line.word 0x0 "MSS_CTRL_R5SS1_CORE0_AXI_S_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18370++0xF line.long 0x0 "MSS_CTRL_R5SS1_CORE0_AXI_S_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS1_CORE0_AXI_S_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_R5SS1_CORE0_AXI_S_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_R5SS1_CORE0_AXI_S_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18380++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE1_AXI_S_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18384++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE1_AXI_S_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18388++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE1_AXI_S_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1838C++0x1 line.word 0x0 "MSS_CTRL_R5SS1_CORE1_AXI_S_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18390++0xF line.long 0x0 "MSS_CTRL_R5SS1_CORE1_AXI_S_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS1_CORE1_AXI_S_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_R5SS1_CORE1_AXI_S_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_R5SS1_CORE1_AXI_S_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x183A0++0x2 line.tbyte 0x0 "MSS_CTRL_TPTC00_RD_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x183A4++0x3 line.long 0x0 "MSS_CTRL_TPTC00_RD_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x183A8++0x3 line.long 0x0 "MSS_CTRL_TPTC00_RD_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x183AC++0x1 line.word 0x0 "MSS_CTRL_TPTC00_RD_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x183B0++0x7 line.long 0x0 "MSS_CTRL_TPTC00_RD_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_TPTC00_RD_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x183C0++0x2 line.tbyte 0x0 "MSS_CTRL_TPTC01_RD_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x183C4++0x3 line.long 0x0 "MSS_CTRL_TPTC01_RD_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x183C8++0x3 line.long 0x0 "MSS_CTRL_TPTC01_RD_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x183CC++0x1 line.word 0x0 "MSS_CTRL_TPTC01_RD_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x183D0++0x7 line.long 0x0 "MSS_CTRL_TPTC01_RD_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_TPTC01_RD_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x183E0++0x2 line.tbyte 0x0 "MSS_CTRL_TPTC00_WR_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x183E4++0x3 line.long 0x0 "MSS_CTRL_TPTC00_WR_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x183E8++0x3 line.long 0x0 "MSS_CTRL_TPTC00_WR_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x183EC++0x1 line.word 0x0 "MSS_CTRL_TPTC00_WR_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x183F0++0xB line.long 0x0 "MSS_CTRL_TPTC00_WR_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_TPTC00_WR_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_TPTC00_WR_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18400++0x2 line.tbyte 0x0 "MSS_CTRL_TPTC01_WR_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18404++0x3 line.long 0x0 "MSS_CTRL_TPTC01_WR_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18408++0x3 line.long 0x0 "MSS_CTRL_TPTC01_WR_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1840C++0x1 line.word 0x0 "MSS_CTRL_TPTC01_WR_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18410++0xB line.long 0x0 "MSS_CTRL_TPTC01_WR_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_TPTC01_WR_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_TPTC01_WR_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18420++0x2 line.tbyte 0x0 "MSS_CTRL_HSM_TPTC0_RD_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18424++0x3 line.long 0x0 "MSS_CTRL_HSM_TPTC0_RD_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18428++0x3 line.long 0x0 "MSS_CTRL_HSM_TPTC0_RD_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1842C++0x1 line.word 0x0 "MSS_CTRL_HSM_TPTC0_RD_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18430++0x7 line.long 0x0 "MSS_CTRL_HSM_TPTC0_RD_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_HSM_TPTC0_RD_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18440++0x2 line.tbyte 0x0 "MSS_CTRL_HSM_TPTC1_RD_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18444++0x3 line.long 0x0 "MSS_CTRL_HSM_TPTC1_RD_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18448++0x3 line.long 0x0 "MSS_CTRL_HSM_TPTC1_RD_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1844C++0x1 line.word 0x0 "MSS_CTRL_HSM_TPTC1_RD_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18450++0x7 line.long 0x0 "MSS_CTRL_HSM_TPTC1_RD_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_HSM_TPTC1_RD_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18460++0x2 line.tbyte 0x0 "MSS_CTRL_HSM_TPTC0_WR_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18464++0x3 line.long 0x0 "MSS_CTRL_HSM_TPTC0_WR_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18468++0x3 line.long 0x0 "MSS_CTRL_HSM_TPTC0_WR_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1846C++0x1 line.word 0x0 "MSS_CTRL_HSM_TPTC0_WR_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18470++0xB line.long 0x0 "MSS_CTRL_HSM_TPTC0_WR_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_HSM_TPTC0_WR_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_HSM_TPTC0_WR_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18480++0x2 line.tbyte 0x0 "MSS_CTRL_HSM_TPTC1_WR_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18484++0x3 line.long 0x0 "MSS_CTRL_HSM_TPTC1_WR_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18488++0x3 line.long 0x0 "MSS_CTRL_HSM_TPTC1_WR_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1848C++0x1 line.word 0x0 "MSS_CTRL_HSM_TPTC1_WR_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18490++0xB line.long 0x0 "MSS_CTRL_HSM_TPTC1_WR_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_HSM_TPTC1_WR_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_HSM_TPTC1_WR_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x184A0++0x2 line.tbyte 0x0 "MSS_CTRL_QSPI0_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x184A4++0x3 line.long 0x0 "MSS_CTRL_QSPI0_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x184A8++0x3 line.long 0x0 "MSS_CTRL_QSPI0_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x184AC++0x1 line.word 0x0 "MSS_CTRL_QSPI0_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x184B0++0xF line.long 0x0 "MSS_CTRL_QSPI0_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_QSPI0_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_QSPI0_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_QSPI0_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x184C0++0x2 line.tbyte 0x0 "MSS_CTRL_HSM_DTHE_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x184C4++0x3 line.long 0x0 "MSS_CTRL_HSM_DTHE_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x184C8++0x3 line.long 0x0 "MSS_CTRL_HSM_DTHE_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x184CC++0x1 line.word 0x0 "MSS_CTRL_HSM_DTHE_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x184D0++0xF line.long 0x0 "MSS_CTRL_HSM_DTHE_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_HSM_DTHE_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_HSM_DTHE_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_HSM_DTHE_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x184E0++0x2 line.tbyte 0x0 "MSS_CTRL_MSS_CPSW_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x184E4++0x3 line.long 0x0 "MSS_CTRL_MSS_CPSW_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x184E8++0x3 line.long 0x0 "MSS_CTRL_MSS_CPSW_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x184EC++0x1 line.word 0x0 "MSS_CTRL_MSS_CPSW_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x184F0++0xF line.long 0x0 "MSS_CTRL_MSS_CPSW_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_MSS_CPSW_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_MSS_CPSW_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_MSS_CPSW_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18500++0x2 line.tbyte 0x0 "MSS_CTRL_ICSSM_PDSP0_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18504++0x3 line.long 0x0 "MSS_CTRL_ICSSM_PDSP0_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18508++0x3 line.long 0x0 "MSS_CTRL_ICSSM_PDSP0_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1850C++0x1 line.word 0x0 "MSS_CTRL_ICSSM_PDSP0_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18510++0xF line.long 0x0 "MSS_CTRL_ICSSM_PDSP0_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_ICSSM_PDSP0_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_ICSSM_PDSP0_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_ICSSM_PDSP0_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18520++0x2 line.tbyte 0x0 "MSS_CTRL_ICSSM_PDSP1_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18524++0x3 line.long 0x0 "MSS_CTRL_ICSSM_PDSP1_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18528++0x3 line.long 0x0 "MSS_CTRL_ICSSM_PDSP1_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1852C++0x1 line.word 0x0 "MSS_CTRL_ICSSM_PDSP1_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18530++0xF line.long 0x0 "MSS_CTRL_ICSSM_PDSP1_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_ICSSM_PDSP1_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_ICSSM_PDSP1_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_ICSSM_PDSP1_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18540++0x2 line.tbyte 0x0 "MSS_CTRL_MCRC0_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18544++0x3 line.long 0x0 "MSS_CTRL_MCRC0_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18548++0x3 line.long 0x0 "MSS_CTRL_MCRC0_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1854C++0x1 line.word 0x0 "MSS_CTRL_MCRC0_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18550++0xF line.long 0x0 "MSS_CTRL_MCRC0_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_MCRC0_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_MCRC0_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_MCRC0_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18560++0x2 line.tbyte 0x0 "MSS_CTRL_SCRM2SCRP_0_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18564++0x3 line.long 0x0 "MSS_CTRL_SCRM2SCRP_0_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18568++0x3 line.long 0x0 "MSS_CTRL_SCRM2SCRP_0_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1856C++0x1 line.word 0x0 "MSS_CTRL_SCRM2SCRP_0_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18570++0xF line.long 0x0 "MSS_CTRL_SCRM2SCRP_0_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_SCRM2SCRP_0_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_SCRM2SCRP_0_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_SCRM2SCRP_0_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18580++0x2 line.tbyte 0x0 "MSS_CTRL_SCRM2SCRP_1_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18584++0x3 line.long 0x0 "MSS_CTRL_SCRM2SCRP_1_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18588++0x3 line.long 0x0 "MSS_CTRL_SCRM2SCRP_1_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1858C++0x1 line.word 0x0 "MSS_CTRL_SCRM2SCRP_1_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18590++0xF line.long 0x0 "MSS_CTRL_SCRM2SCRP_1_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_SCRM2SCRP_1_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_SCRM2SCRP_1_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_SCRM2SCRP_1_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x185A0++0x2 line.tbyte 0x0 "MSS_CTRL_HSM_M_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x185A4++0x3 line.long 0x0 "MSS_CTRL_HSM_M_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x185A8++0x3 line.long 0x0 "MSS_CTRL_HSM_M_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x185AC++0x1 line.word 0x0 "MSS_CTRL_HSM_M_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x185B0++0xF line.long 0x0 "MSS_CTRL_HSM_M_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_HSM_M_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_HSM_M_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_HSM_M_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x185C0++0x2 line.tbyte 0x0 "MSS_CTRL_HSM_S_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x185C4++0x3 line.long 0x0 "MSS_CTRL_HSM_S_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x185C8++0x3 line.long 0x0 "MSS_CTRL_HSM_S_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x185CC++0x1 line.word 0x0 "MSS_CTRL_HSM_S_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x185D0++0xF line.long 0x0 "MSS_CTRL_HSM_S_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_HSM_S_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_HSM_S_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_HSM_S_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x185E0++0x2 line.tbyte 0x0 "MSS_CTRL_ICSSM_S_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x185E4++0x3 line.long 0x0 "MSS_CTRL_ICSSM_S_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x185E8++0x3 line.long 0x0 "MSS_CTRL_ICSSM_S_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x185EC++0x1 line.word 0x0 "MSS_CTRL_ICSSM_S_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x185F0++0xF line.long 0x0 "MSS_CTRL_ICSSM_S_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_ICSSM_S_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_ICSSM_S_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_ICSSM_S_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18600++0x2 line.tbyte 0x0 "MSS_CTRL_DAP_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18604++0x3 line.long 0x0 "MSS_CTRL_DAP_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18608++0x3 line.long 0x0 "MSS_CTRL_DAP_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1860C++0x1 line.word 0x0 "MSS_CTRL_DAP_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18610++0xF line.long 0x0 "MSS_CTRL_DAP_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_DAP_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_DAP_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_DAP_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18620++0x2 line.tbyte 0x0 "MSS_CTRL_L2OCRAM_BANK0_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18624++0x3 line.long 0x0 "MSS_CTRL_L2OCRAM_BANK0_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18628++0x3 line.long 0x0 "MSS_CTRL_L2OCRAM_BANK0_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1862C++0x1 line.word 0x0 "MSS_CTRL_L2OCRAM_BANK0_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18630++0xF line.long 0x0 "MSS_CTRL_L2OCRAM_BANK0_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_L2OCRAM_BANK0_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_L2OCRAM_BANK0_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_L2OCRAM_BANK0_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18640++0x2 line.tbyte 0x0 "MSS_CTRL_L2OCRAM_BANK1_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18644++0x3 line.long 0x0 "MSS_CTRL_L2OCRAM_BANK1_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18648++0x3 line.long 0x0 "MSS_CTRL_L2OCRAM_BANK1_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1864C++0x1 line.word 0x0 "MSS_CTRL_L2OCRAM_BANK1_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18650++0xF line.long 0x0 "MSS_CTRL_L2OCRAM_BANK1_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_L2OCRAM_BANK1_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_L2OCRAM_BANK1_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_L2OCRAM_BANK1_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18660++0x2 line.tbyte 0x0 "MSS_CTRL_L2OCRAM_BANK2_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18664++0x3 line.long 0x0 "MSS_CTRL_L2OCRAM_BANK2_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18668++0x3 line.long 0x0 "MSS_CTRL_L2OCRAM_BANK2_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1866C++0x1 line.word 0x0 "MSS_CTRL_L2OCRAM_BANK2_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18670++0xF line.long 0x0 "MSS_CTRL_L2OCRAM_BANK2_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_L2OCRAM_BANK2_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_L2OCRAM_BANK2_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_L2OCRAM_BANK2_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18680++0x2 line.tbyte 0x0 "MSS_CTRL_L2OCRAM_BANK3_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18684++0x3 line.long 0x0 "MSS_CTRL_L2OCRAM_BANK3_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18688++0x3 line.long 0x0 "MSS_CTRL_L2OCRAM_BANK3_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1868C++0x1 line.word 0x0 "MSS_CTRL_L2OCRAM_BANK3_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18690++0xF line.long 0x0 "MSS_CTRL_L2OCRAM_BANK3_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_L2OCRAM_BANK3_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_L2OCRAM_BANK3_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_L2OCRAM_BANK3_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x186A0++0x2 line.tbyte 0x0 "MSS_CTRL_MBOX_SRAM_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x186A4++0x3 line.long 0x0 "MSS_CTRL_MBOX_SRAM_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x186A8++0x3 line.long 0x0 "MSS_CTRL_MBOX_SRAM_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x186AC++0x1 line.word 0x0 "MSS_CTRL_MBOX_SRAM_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x186B0++0xF line.long 0x0 "MSS_CTRL_MBOX_SRAM_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_MBOX_SRAM_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_MBOX_SRAM_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_MBOX_SRAM_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x186C0++0x2 line.tbyte 0x0 "MSS_CTRL_STM_STIM_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x186C4++0x3 line.long 0x0 "MSS_CTRL_STM_STIM_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x186C8++0x3 line.long 0x0 "MSS_CTRL_STM_STIM_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x186CC++0x1 line.word 0x0 "MSS_CTRL_STM_STIM_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x186D0++0xF line.long 0x0 "MSS_CTRL_STM_STIM_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_STM_STIM_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_STM_STIM_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_STM_STIM_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x186E0++0x2 line.tbyte 0x0 "MSS_CTRL_MMC0_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x186E4++0x3 line.long 0x0 "MSS_CTRL_MMC0_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x186E8++0x3 line.long 0x0 "MSS_CTRL_MMC0_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x186EC++0x1 line.word 0x0 "MSS_CTRL_MMC0_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x186F0++0xF line.long 0x0 "MSS_CTRL_MMC0_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_MMC0_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_MMC0_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_MMC0_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18700++0x2 line.tbyte 0x0 "MSS_CTRL_GPMC0_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18704++0x3 line.long 0x0 "MSS_CTRL_GPMC0_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18708++0x3 line.long 0x0 "MSS_CTRL_GPMC0_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1870C++0x1 line.word 0x0 "MSS_CTRL_GPMC0_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18710++0xF line.long 0x0 "MSS_CTRL_GPMC0_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_GPMC0_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_GPMC0_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_GPMC0_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18720++0x2 line.tbyte 0x0 "MSS_CTRL_MAIN_VBUSP_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18724++0x3 line.long 0x0 "MSS_CTRL_MAIN_VBUSP_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18728++0x3 line.long 0x0 "MSS_CTRL_MAIN_VBUSP_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1872C++0x1 line.word 0x0 "MSS_CTRL_MAIN_VBUSP_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18730++0xF line.long 0x0 "MSS_CTRL_MAIN_VBUSP_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_MAIN_VBUSP_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_MAIN_VBUSP_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_MAIN_VBUSP_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18740++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE0_AHB_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18744++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE0_AHB_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18748++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE0_AHB_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1874C++0x1 line.word 0x0 "MSS_CTRL_R5SS0_CORE0_AHB_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18750++0xF line.long 0x0 "MSS_CTRL_R5SS0_CORE0_AHB_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS0_CORE0_AHB_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_R5SS0_CORE0_AHB_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_R5SS0_CORE0_AHB_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18760++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS0_CORE1_AHB_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18764++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE1_AHB_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18768++0x3 line.long 0x0 "MSS_CTRL_R5SS0_CORE1_AHB_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1876C++0x1 line.word 0x0 "MSS_CTRL_R5SS0_CORE1_AHB_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18770++0xF line.long 0x0 "MSS_CTRL_R5SS0_CORE1_AHB_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS0_CORE1_AHB_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_R5SS0_CORE1_AHB_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_R5SS0_CORE1_AHB_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x18780++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE0_AHB_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x18784++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE0_AHB_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x18788++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE0_AHB_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x1878C++0x1 line.word 0x0 "MSS_CTRL_R5SS1_CORE0_AHB_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x18790++0xF line.long 0x0 "MSS_CTRL_R5SS1_CORE0_AHB_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS1_CORE0_AHB_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_R5SS1_CORE0_AHB_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_R5SS1_CORE0_AHB_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x187A0++0x2 line.tbyte 0x0 "MSS_CTRL_R5SS1_CORE1_AHB_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x187A4++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE1_AHB_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x187A8++0x3 line.long 0x0 "MSS_CTRL_R5SS1_CORE1_AHB_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x187AC++0x1 line.word 0x0 "MSS_CTRL_R5SS1_CORE1_AHB_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x187B0++0xF line.long 0x0 "MSS_CTRL_R5SS1_CORE1_AHB_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_R5SS1_CORE1_AHB_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_R5SS1_CORE1_AHB_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_R5SS1_CORE1_AHB_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.tbyte 0x187C0++0x2 line.tbyte 0x0 "MSS_CTRL_PERI_VBUSP_BUS_SAFETY_CTRL" hexmask.tbyte.byte 0x0 16.--23. 1. "TYPE,Refer to AM602 Substem Microarch document for more details" newline bitfld.tbyte 0x0 8. "ERR_CLEAR,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.tbyte 0x0 0.--2. "ENABLE,Refer to AM602 Substem Microarch document for more details" "0,1,2,3,4,5,6,7" group.long 0x187C4++0x3 line.long 0x0 "MSS_CTRL_PERI_VBUSP_BUS_SAFETY_FI" hexmask.long.byte 0x0 24.--31. 1. "SAFE,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "MAIN,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "DATA,Refer to AM602 Substem Microarch document for more details" newline bitfld.long 0x0 5. "DED,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 4. "SEC,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 3. "GLOBAL_SAFE_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 2. "GLOBAL_MAIN_REQ,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 1. "GLOBAL_SAFE,Refer to AM602 Substem Microarch document for more details" "0,1" newline bitfld.long 0x0 0. "GLOBAL_MAIN,Refer to AM602 Substem Microarch document for more details" "0,1" rgroup.long 0x187C8++0x3 line.long 0x0 "MSS_CTRL_PERI_VBUSP_BUS_SAFETY_ERR" hexmask.long.byte 0x0 24.--31. 1. "DED,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 16.--23. 1. "SEC,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 8.--15. 1. "COMP_CHECK,Refer to AM602 Substem Microarch document for more details" newline hexmask.long.byte 0x0 0.--7. 1. "COMP_ERR,Refer to AM602 Substem Microarch document for more details" rgroup.word 0x187CC++0x1 line.word 0x0 "MSS_CTRL_PERI_VBUSP_BUS_SAFETY_ERR_STAT_DATA0" hexmask.word.byte 0x0 8.--15. 1. "D1,Refer to AM602 Substem Microarch document for more details" newline hexmask.word.byte 0x0 0.--7. 1. "D0,Refer to AM602 Substem Microarch document for more details" rgroup.long 0x187D0++0xF line.long 0x0 "MSS_CTRL_PERI_VBUSP_BUS_SAFETY_ERR_STAT_CMD" hexmask.long 0x0 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x4 "MSS_CTRL_PERI_VBUSP_BUS_SAFETY_ERR_STAT_WRITE" hexmask.long 0x4 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0x8 "MSS_CTRL_PERI_VBUSP_BUS_SAFETY_ERR_STAT_READ" hexmask.long 0x8 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" line.long 0xC "MSS_CTRL_PERI_VBUSP_BUS_SAFETY_ERR_STAT_WRITERESP" hexmask.long 0xC 0.--31. 1. "STAT,Refer to AM602 Substem Microarch document for more details" group.byte 0x18820++0x0 line.byte 0x0 "MSS_CTRL_NERROR_MASK" bitfld.byte 0x0 0.--2. "MASK,writing 3'b111 will mask the Nerror propagation to padWriting 3'b000 will unmask the Nerror propagation to pad" "0,1,2,3,4,5,6,7" rgroup.long 0x18824++0x7 line.long 0x0 "MSS_CTRL_MSS_BUS_SAFETY_SEC_ERR_STAT0" bitfld.long 0x0 30. "ICSSM_SLAVE,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 29. "ICSSM_PDSP1,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 28. "ICSSM_PDSP0,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 27. "MSS_MBOX,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 26. "L2RAM3,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 25. "L2RAM2,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 24. "L2RAM1,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 23. "L2RAM0,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 22. "SCRM2SCRP_1,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 21. "SCRM2SCRP_0,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 20. "DTHE,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 19. "HSM_S,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 18. "MCRC,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 17. "QSPI,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 16. "HSM_TPTC_A1_WR,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 15. "HSM_TPTC_A1_RD,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 14. "HSM_TPTC_A0_WR,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 13. "HSM_TPTC_A0_RD,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 12. "MSS_TPTC_A1_WR,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 11. "MSS_TPTC_A0_WR,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 10. "MSS_TPTC_A1_RD,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 9. "MSS_TPTC_A0_RD,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 8. "CPSW,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 7. "HSM,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 6. "DAP,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 5. "CR5B_SLV,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 4. "CR5A_SLV,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 3. "CR5B_WR,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 2. "CR5A_WR,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 1. "CR5B_RD,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x0 0. "CR5A_RD,Bus safety single-bit-error of Node mentioned in the field" "0,1" line.long 0x4 "MSS_CTRL_MSS_BUS_SAFETY_SEC_ERR_STAT1" bitfld.long 0x4 26. "CR5A1_WR,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x4 25. "CR5B1_RD,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x4 24. "CR5A1_RD,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x4 5. "GPMC,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x4 4. "MMC,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x4 3. "STM_STIM,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x4 2. "CR5B1_SLV,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x4 1. "CR5A1_SLV,Bus safety single-bit-error of Node mentioned in the field" "0,1" newline bitfld.long 0x4 0. "CR5B1_WR,Bus safety single-bit-error of Node mentioned in the field" "0,1" group.long 0x18834++0xB line.long 0x0 "MSS_CTRL_MSS_VBUSM_SAFETY_H_ERRAGG_MASK0" bitfld.long 0x0 31. "DTHE_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 30. "MCRC_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 29. "QSPI_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 28. "ICSSM_PDSP1_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 27. "ICSSM_PDSP0_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 26. "HSM_TPTC1_WR_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 25. "HSM_TPTC1_RD_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 24. "HSM_TPTC0_WR_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 23. "HSM_TPTC0_RD_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 22. "TPTC1_WR_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 21. "TPTC0_WR_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 20. "TPTC1_RD_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 19. "TPTC0_RD_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 18. "L2RAM3_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 17. "L2RAM2_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 16. "L2RAM1_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 15. "L2RAM0_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 14. "CPSW_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 13. "HSM_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 12. "DAP_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 11. "CR5B1_SLV_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 10. "CR5A1_SLV_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 9. "CR5B1_WR_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 8. "CR5A1_WR_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 7. "CR5B1_RD_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 6. "CR5A1_RD_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 5. "CR5B0_SLV_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 4. "CR5A0_SLV_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 3. "CR5B0_WR_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 2. "CR5A0_WR_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 1. "CR5B0_RD_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 0. "CR5A0_RD_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_MSS_VBUSM_SAFETY_H_ERRAGG_STATUS0" bitfld.long 0x4 31. "DTHE_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 30. "MCRC_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 29. "QSPI_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 28. "ICSSM_PDSP1_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 27. "ICSSM_PDSP0_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 26. "HSM_TPTC1_WR_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 25. "HSM_TPTC1_RD_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 24. "HSM_TPTC0_WR_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 23. "HSM_TPTC0_RD_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 22. "TPTC1_WR_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 21. "TPTC0_WR_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 20. "TPTC1_RD_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 19. "TPTC0_RD_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 18. "L2RAM3_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 17. "L2RAM2_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 16. "L2RAM1_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 15. "L2RAM0_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 14. "CPSW_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 13. "HSM_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 12. "DAP_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 11. "CR5B1_SLV_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 10. "CR5A1_SLV_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 9. "CR5B1_WR_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 8. "CR5A1_WR_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 7. "CR5B1_RD_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 6. "CR5A1_RD_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 5. "CR5B0_SLV_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 4. "CR5A0_SLV_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 3. "CR5B0_WR_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 2. "CR5A0_WR_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 1. "CR5B0_RD_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 0. "CR5A0_RD_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" line.long 0x8 "MSS_CTRL_MSS_VBUSM_SAFETY_H_ERRAGG_STATUS_RAW0" bitfld.long 0x8 31. "DTHE_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 30. "MCRC_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 29. "QSPI_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 28. "ICSSM_PDSP1_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 27. "ICSSM_PDSP0_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 26. "HSM_TPTC1_WR_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 25. "HSM_TPTC1_RD_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 24. "HSM_TPTC0_WR_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 23. "HSM_TPTC0_RD_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 22. "TPTC1_WR_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 21. "TPTC0_WR_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 20. "TPTC1_RD_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 19. "TPTC0_RD_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 18. "L2RAM3_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 17. "L2RAM2_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 16. "L2RAM1_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 15. "L2RAM0_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 14. "CPSW_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 13. "HSM_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 12. "DAP_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 11. "CR5B1_SLV_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 10. "CR5A1_SLV_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 9. "CR5B1_WR_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 8. "CR5A1_WR_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 7. "CR5B1_RD_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 6. "CR5A1_RD_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 5. "CR5B0_SLV_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 4. "CR5A0_SLV_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 3. "CR5B0_WR_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 2. "CR5A0_WR_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 1. "CR5B0_RD_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 0. "CR5A0_RD_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H0_ERRAGG_ERRAGG_MASK" "0,1" group.byte 0x18844++0x0 line.byte 0x0 "MSS_CTRL_MSS_VBUSM_SAFETY_H_ERRAGG_MASK1" bitfld.byte 0x0 7. "GPMC_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 6. "MMC_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 5. "STM_STIM_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 4. "MSS_MBOX_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 3. "ICSSMSLAVE_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 2. "HSM_S_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 1. "SCRM2SCRP_1_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 0. "SCRM2SCRP_0_VBUSM_ERRH,Mask Error from MSS_VBUSM_SAFETY_H1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" group.byte 0x18848++0x0 line.byte 0x0 "MSS_CTRL_MSS_VBUSM_SAFETY_H_ERRAGG_STATUS1" bitfld.byte 0x0 7. "GPMC_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 6. "MMC_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 5. "STM_STIM_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 4. "MSS_MBOX_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 3. "ICSSMSLAVE_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 2. "HSM_S_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 1. "SCRM2SCRP_1_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 0. "SCRM2SCRP_0_VBUSM_ERRH,Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" group.byte 0x1884C++0x0 line.byte 0x0 "MSS_CTRL_MSS_VBUSM_SAFETY_H_ERRAGG_STATUS_RAW1" bitfld.byte 0x0 7. "GPMC_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 6. "MMC_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 5. "STM_STIM_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 4. "MSS_MBOX_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 3. "ICSSMSLAVE_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 2. "HSM_S_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 1. "SCRM2SCRP_1_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 0. "SCRM2SCRP_0_VBUSM_ERRH,Raw Status of Error from MSS_VBUSM_SAFETY_H1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_H1_ERRAGG_ERRAGG_MASK" "0,1" group.long 0x18854++0xB line.long 0x0 "MSS_CTRL_MSS_VBUSM_SAFETY_L_ERRAGG_MASK0" bitfld.long 0x0 31. "DTHE_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 30. "MCRC_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 29. "QSPI_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 28. "ICSSM_PDSP1_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 27. "ICSSM_PDSP0_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 26. "HSM_TPTC1_WR_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 25. "HSM_TPTC1_RD_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 24. "HSM_TPTC0_WR_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 23. "HSM_TPTC0_RD_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 22. "TPTC1_WR_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 21. "TPTC0_WR_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 20. "TPTC1_RD_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 19. "TPTC0_RD_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 18. "L2RAM3_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 17. "L2RAM2_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 16. "L2RAM1_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 15. "L2RAM0_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 14. "CPSW_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 13. "HSM_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 12. "DAP_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 11. "CR5B1_SLV_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 10. "CR5A1_SLV_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 9. "CR5B1_WR_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 8. "CR5A1_WR_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 7. "CR5B1_RD_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 6. "CR5A1_RD_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 5. "CR5B0_SLV_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 4. "CR5A0_SLV_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 3. "CR5B0_WR_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 2. "CR5A0_WR_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 1. "CR5B0_RD_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.long 0x0 0. "CR5A0_RD_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L0_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" line.long 0x4 "MSS_CTRL_MSS_VBUSM_SAFETY_L_ERRAGG_STATUS0" bitfld.long 0x4 31. "DTHE_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 30. "MCRC_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 29. "QSPI_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 28. "ICSSM_PDSP1_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 27. "ICSSM_PDSP0_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 26. "HSM_TPTC1_WR_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 25. "HSM_TPTC1_RD_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 24. "HSM_TPTC0_WR_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 23. "HSM_TPTC0_RD_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 22. "TPTC1_WR_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 21. "TPTC0_WR_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 20. "TPTC1_RD_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 19. "TPTC0_RD_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 18. "L2RAM3_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 17. "L2RAM2_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 16. "L2RAM1_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 15. "L2RAM0_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 14. "CPSW_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 13. "HSM_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 12. "DAP_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 11. "CR5B1_SLV_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 10. "CR5A1_SLV_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 9. "CR5B1_WR_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 8. "CR5A1_WR_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 7. "CR5B1_RD_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 6. "CR5A1_RD_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 5. "CR5B0_SLV_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 4. "CR5A0_SLV_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 3. "CR5B0_WR_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 2. "CR5A0_WR_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 1. "CR5B0_RD_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.long 0x4 0. "CR5A0_RD_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" line.long 0x8 "MSS_CTRL_MSS_VBUSM_SAFETY_L_ERRAGG_STATUS_RAW0" bitfld.long 0x8 31. "DTHE_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 30. "MCRC_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 29. "QSPI_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 28. "ICSSM_PDSP1_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 27. "ICSSM_PDSP0_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 26. "HSM_TPTC1_WR_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 25. "HSM_TPTC1_RD_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 24. "HSM_TPTC0_WR_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 23. "HSM_TPTC0_RD_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 22. "TPTC1_WR_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 21. "TPTC0_WR_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 20. "TPTC1_RD_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 19. "TPTC0_RD_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 18. "L2RAM3_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 17. "L2RAM2_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 16. "L2RAM1_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 15. "L2RAM0_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 14. "CPSW_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 13. "HSM_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 12. "DAP_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 11. "CR5B1_SLV_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 10. "CR5A1_SLV_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 9. "CR5B1_WR_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 8. "CR5A1_WR_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 7. "CR5B1_RD_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 6. "CR5A1_RD_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 5. "CR5B0_SLV_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 4. "CR5A0_SLV_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 3. "CR5B0_WR_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 2. "CR5A0_WR_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 1. "CR5B0_RD_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.long 0x8 0. "CR5A0_RD_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L0_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L0_ERRAGG_ERRAGG_MASK" "0,1" group.byte 0x18864++0x0 line.byte 0x0 "MSS_CTRL_MSS_VBUSM_SAFETY_L_ERRAGG_MASK1" bitfld.byte 0x0 7. "GPMC_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 6. "MMC_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 5. "STM_STIM_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 4. "MSS_MBOX_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 3. "ICSSMSLAVE_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 2. "HSM_S_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 1. "SCRM2SCRP_1_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 0. "SCRM2SCRP_0_VBUSM_ERRL,Mask Error from MSS_VBUSM_SAFETY_L1_ERRAGG to aggregated Error MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" group.byte 0x18868++0x0 line.byte 0x0 "MSS_CTRL_MSS_VBUSM_SAFETY_L_ERRAGG_STATUS1" bitfld.byte 0x0 7. "GPMC_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 6. "MMC_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 5. "STM_STIM_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 4. "MSS_MBOX_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 3. "ICSSMSLAVE_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 2. "HSM_S_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 1. "SCRM2SCRP_1_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 0. "SCRM2SCRP_0_VBUSM_ERRL,Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" group.byte 0x1886C++0x0 line.byte 0x0 "MSS_CTRL_MSS_VBUSM_SAFETY_L_ERRAGG_STATUS_RAW1" bitfld.byte 0x0 7. "GPMC_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 6. "MMC_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 5. "STM_STIM_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 4. "MSS_MBOX_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 3. "ICSSMSLAVE_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 2. "HSM_S_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 1. "SCRM2SCRP_1_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 0. "SCRM2SCRP_0_VBUSM_ERRL,Raw Status of Error from MSS_VBUSM_SAFETY_L1_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSM_SAFETY_L1_ERRAGG_ERRAGG_MASK" "0,1" group.byte 0x18874++0x0 line.byte 0x0 "MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG_MASK" bitfld.byte 0x0 5. "PERI_VBUSP_VBUSP_ERRH,Mask Error from MSS_VBUSP_SAFETY_H_ERRAGG to aggregated Error MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 4. "MAIN_VBUSP_VBUSP_ERRH,Mask Error from MSS_VBUSP_SAFETY_H_ERRAGG to aggregated Error MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 3. "CR5B1_AHB_VBUSP_ERRH,Mask Error from MSS_VBUSP_SAFETY_H_ERRAGG to aggregated Error MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 2. "CR5A1_AHB_VBUSP_ERRH,Mask Error from MSS_VBUSP_SAFETY_H_ERRAGG to aggregated Error MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 1. "CR5B0_AHB_VBUSP_ERRH,Mask Error from MSS_VBUSP_SAFETY_H_ERRAGG to aggregated Error MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" newline bitfld.byte 0x0 0. "CR5A0_AHB_VBUSP_ERRH,Mask Error from MSS_VBUSP_SAFETY_H_ERRAGG to aggregated Error MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG1 : Error is Masked0 : Error is Unmasked" "0,1" group.byte 0x18878++0x0 line.byte 0x0 "MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG_STATUS" bitfld.byte 0x0 5. "PERI_VBUSP_VBUSP_ERRH,Status of Error from MSS_VBUSP_SAFETY_H_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 4. "MAIN_VBUSP_VBUSP_ERRH,Status of Error from MSS_VBUSP_SAFETY_H_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 3. "CR5B1_AHB_VBUSP_ERRH,Status of Error from MSS_VBUSP_SAFETY_H_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 2. "CR5A1_AHB_VBUSP_ERRH,Status of Error from MSS_VBUSP_SAFETY_H_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 1. "CR5B0_AHB_VBUSP_ERRH,Status of Error from MSS_VBUSP_SAFETY_H_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" newline bitfld.byte 0x0 0. "CR5A0_AHB_VBUSP_ERRH,Status of Error from MSS_VBUSP_SAFETY_H_ERRAGG. Set only if Interupt is unmasked in MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG_MASKWrie 0x1 to clear this Error." "0,1" group.byte 0x1887C++0x0 line.byte 0x0 "MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG_STATUS_RAW" bitfld.byte 0x0 5. "PERI_VBUSP_VBUSP_ERRH,Raw Status of Error from MSS_VBUSP_SAFETY_H_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 4. "MAIN_VBUSP_VBUSP_ERRH,Raw Status of Error from MSS_VBUSP_SAFETY_H_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 3. "CR5B1_AHB_VBUSP_ERRH,Raw Status of Error from MSS_VBUSP_SAFETY_H_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 2. "CR5A1_AHB_VBUSP_ERRH,Raw Status of Error from MSS_VBUSP_SAFETY_H_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 1. "CR5B0_AHB_VBUSP_ERRH,Raw Status of Error from MSS_VBUSP_SAFETY_H_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG_MASK" "0,1" newline bitfld.byte 0x0 0. "CR5A0_AHB_VBUSP_ERRH,Raw Status of Error from MSS_VBUSP_SAFETY_H_ERRAGG. Set irrespective if the Interupt is masked or unmasked in MSS_VBUSP_SAFETY_H_ERRAGG_ERRAGG_MASK" "0,1" tree.end tree "MSS_RCM" base ad:0x53208000 rgroup.long 0x0++0x3 line.long 0x0 "MSS_RCM_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,Not Defined" hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,Not Defined" bitfld.long 0x0 8.--10. "PID_MAJOR,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM,Not Defined" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,Not Defined" rgroup.word 0x10++0x1 line.word 0x0 "MSS_RCM_R5SS0_RST_STATUS" hexmask.word 0x0 0.--10. 1. "CAUSE,Has the status because of which reset has happened. Bit0: POR ResetBit1: Warm Reset (ALso set during POR Reset)Bit2: CR5SS0 STC ResetBit3 Reset for CORE0 and MSS_CORE00_VIM using MSS_RCM::MSS_CR5SSA0_RST_CTRLBit4: Reset for CORE1 and.." group.byte 0x14++0x0 line.byte 0x0 "MSS_RCM_R5SS0_RST_CAUSE_CLR" bitfld.byte 0x0 0.--2. "CLR,Write pulse bit field:Clear bit for rst cause register (writing '111' will clear the rst cause register)" "0,1,2,3,4,5,6,7" group.tbyte 0x18++0x2 line.tbyte 0x0 "MSS_RCM_R5SS0_DBG_RST_EN" bitfld.tbyte 0x0 16.--18. "EN_CORE1,writing '111' will block debug reset request from CORE1 toggling reset for CORE1 of respective R5SS" "0,1,2,3,4,5,6,7" bitfld.tbyte 0x0 0.--2. "EN_CORE0,writing '111' will block debug reset request from CORE0 toggling reset for CORE0 of respective R5SS" "0,1,2,3,4,5,6,7" group.byte 0x1C++0x0 line.byte 0x0 "MSS_RCM_R5SS0_RST_ASSERDLY" hexmask.byte 0x0 0.--7. 1. "COUNT,Value decides number of cycles reset should be kept asserted for CR5SS related resets. Programming a value of 0xFF will keep the reset asserted untill a new value other than 0xFF is written to this registerThe actual duration is count + 2 cycles." group.long 0x20++0x7 line.long 0x0 "MSS_RCM_R5SS0_RST2ASSERTDLY" hexmask.long.byte 0x0 24.--31. 1. "R5_CORE1_COUNT,Value decides number of cycles to wait before asserting reset for local reset for CORE1" hexmask.long.byte 0x0 16.--23. 1. "R5_CORE0_COUNT,Value decides number of cycles to wait before asserting reset for local reset for CORE0." hexmask.long.byte 0x0 8.--15. 1. "R5SS_CORE1_COUNT,Value decides number of cycles to wait before asserting reset for global reset for CORE1" newline hexmask.long.byte 0x0 0.--7. 1. "R5SS_CORE0_COUNT,Value decides number of cycles to wait before asserting reset for global reset for CORE0." line.long 0x4 "MSS_RCM_R5SS0_RST_WFICHECK" bitfld.long 0x4 24.--26. "EN_R5_CORE1,writing '000' will disable check for WFI before local reset assertion of CORE0" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "EN_R5_CORE0,writing '000' will disable check for WFI before local reset assertion of CORE0" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "EN_R5SS_CORE1,writing '000' will disable check for WFI before global reset assertion of CORE1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "EN_R5SS_CORE0,writing '000' will disable check for WFI before global reset assertion of CORE0" "0,1,2,3,4,5,6,7" rgroup.word 0x30++0x1 line.word 0x0 "MSS_RCM_R5SS1_RST_STATUS" hexmask.word 0x0 0.--10. 1. "CAUSE,Has the status because of which reset has happened. Bit0: POR ResetBit1: Warm Reset (ALso set during POR Reset)Bit2: CR5SS1 STC ResetBit3 Reset for CORE0 and MSS_CORE00_VIM using MSS_RCM::MSS_CR5SSA0_RST_CTRLBit4: Reset for CORE1 and.." group.byte 0x34++0x0 line.byte 0x0 "MSS_RCM_R5SS1_RST_CAUSE_CLR" bitfld.byte 0x0 0.--2. "CLR,Write pulse bit field:Clear bit for rst cause register (writing '111' will clear the rst cause register)" "0,1,2,3,4,5,6,7" group.tbyte 0x38++0x2 line.tbyte 0x0 "MSS_RCM_R5SS1_DBG_RST_EN" bitfld.tbyte 0x0 16.--18. "EN_CORE1,writing '111' will block debug reset request from CORE1 toggling reset for CORE1 of respective R5SS" "0,1,2,3,4,5,6,7" bitfld.tbyte 0x0 0.--2. "EN_CORE0,writing '111' will block debug reset request from CORE0 toggling reset for CORE0 of respective R5SS" "0,1,2,3,4,5,6,7" group.byte 0x3C++0x0 line.byte 0x0 "MSS_RCM_R5SS1_RST_ASSERDLY" hexmask.byte 0x0 0.--7. 1. "COUNT,Value decides number of cycles reset should be kept asserted for CR5SS related resets. Programming a value of 0xFF will keep the reset asserted untill a new value other than 0xFF is written to this registerThe actual duration is count + 2 cycles." group.long 0x40++0x7 line.long 0x0 "MSS_RCM_R5SS1_RST2ASSERTDLY" hexmask.long.byte 0x0 24.--31. 1. "R5_CORE1_COUNT,Value decides number of cycles to wait before asserting reset for local reset for CORE1" hexmask.long.byte 0x0 16.--23. 1. "R5_CORE0_COUNT,Value decides number of cycles to wait before asserting reset for local reset for CORE0." hexmask.long.byte 0x0 8.--15. 1. "R5SS_CORE1_COUNT,Value decides number of cycles to wait before asserting reset for global reset for CORE1" newline hexmask.long.byte 0x0 0.--7. 1. "R5SS_CORE0_COUNT,Value decides number of cycles to wait before asserting reset for global reset for CORE0." line.long 0x4 "MSS_RCM_R5SS1_RST_WFICHECK" bitfld.long 0x4 24.--26. "EN_R5_CORE1,writing '000' will disable check for WFI before local reset assertion of CORE0" "0,1,2,3,4,5,6,7" bitfld.long 0x4 16.--18. "EN_R5_CORE0,writing '000' will disable check for WFI before local reset assertion of CORE0" "0,1,2,3,4,5,6,7" bitfld.long 0x4 8.--10. "EN_R5SS_CORE1,writing '000' will disable check for WFI before global reset assertion of CORE1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "EN_R5SS_CORE0,writing '000' will disable check for WFI before global reset assertion of CORE0" "0,1,2,3,4,5,6,7" group.word 0x100++0x1 line.word 0x0 "MSS_RCM_MCAN0_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for corresponding MCAN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock.." group.word 0x104++0x1 line.word 0x0 "MSS_RCM_MCAN1_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for corresponding MCAN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock.." group.word 0x108++0x1 line.word 0x0 "MSS_RCM_MCAN2_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for corresponding MCAN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock.." group.word 0x10C++0x1 line.word 0x0 "MSS_RCM_MCAN3_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for corresponding MCAN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock.." group.word 0x110++0x1 line.word 0x0 "MSS_RCM_QSPI0_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for QSPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x114++0x1 line.word 0x0 "MSS_RCM_RTI0_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for Corresponding RTI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x118++0x1 line.word 0x0 "MSS_RCM_RTI1_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for Corresponding RTI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x11C++0x1 line.word 0x0 "MSS_RCM_RTI2_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for Corresponding RTI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x120++0x1 line.word 0x0 "MSS_RCM_RTI3_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for Corresponding RTI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x128++0x1 line.word 0x0 "MSS_RCM_WDT0_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for WDT.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x12C++0x1 line.word 0x0 "MSS_RCM_WDT1_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for WDT.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x130++0x1 line.word 0x0 "MSS_RCM_WDT2_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for WDT.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x134++0x1 line.word 0x0 "MSS_RCM_WDT3_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for WDT.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x13C++0x1 line.word 0x0 "MSS_RCM_MCSPI0_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for Corresponding SPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x140++0x1 line.word 0x0 "MSS_RCM_MCSPI1_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for Corresponding SPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x144++0x1 line.word 0x0 "MSS_RCM_MCSPI2_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for Corresponding SPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x148++0x1 line.word 0x0 "MSS_RCM_MCSPI3_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for Corresponding SPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x14C++0x1 line.word 0x0 "MSS_RCM_MCSPI4_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for Corresponding SPI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x150++0x1 line.word 0x0 "MSS_RCM_MMC0_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for MMCSD.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x154++0x1 line.word 0x0 "MSS_RCM_ICSSM0_UART0_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for ICSSM_UCLK.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x158++0x1 line.word 0x0 "MSS_RCM_CPTS_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for CPTS.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x15C++0x1 line.word 0x0 "MSS_RCM_GPMC_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "GPMC_CLK_SRC_SEL,Select line for selecting source clock for GPMC. Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x160++0x1 line.word 0x0 "MSS_RCM_CONTROLSS_PLL_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for CONTROLSS_PLL.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x164++0x1 line.word 0x0 "MSS_RCM_I2C_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for I2C.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0x174++0x1 line.word 0x0 "MSS_RCM_LIN0_UART0_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for corresponding UART and LIN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source.." group.word 0x178++0x1 line.word 0x0 "MSS_RCM_LIN1_UART1_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for corresponding UART and LIN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source.." group.word 0x17C++0x1 line.word 0x0 "MSS_RCM_LIN2_UART2_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for corresponding UART and LIN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source.." group.word 0x180++0x1 line.word 0x0 "MSS_RCM_LIN3_UART3_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for corresponding UART and LIN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source.." group.word 0x184++0x1 line.word 0x0 "MSS_RCM_LIN4_UART4_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for corresponding UART and LIN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source.." group.word 0x188++0x1 line.word 0x0 "MSS_RCM_LIN5_UART5_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for corresponding UART and LIN.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source.." group.word 0x200++0x1 line.word 0x0 "MSS_RCM_MCAN0_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value corresponding MCAN selected clock.Data should be loaded as multibit. For example: if divider value of 8(1000) should be selected then '100010001000' should be configured to the register.Refer to AM602 clock planner for clock.." group.word 0x204++0x1 line.word 0x0 "MSS_RCM_MCAN1_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value corresponding MCAN selected clock.Data should be loaded as multibit. For example: if divider value of 8(1000) should be selected then '100010001000' should be configured to the register.Refer to AM602 clock planner for clock.." group.word 0x208++0x1 line.word 0x0 "MSS_RCM_MCAN2_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value corresponding MCAN selected clock.Data should be loaded as multibit. For example: if divider value of 8(1000) should be selected then '100010001000' should be configured to the register.Refer to AM602 clock planner for clock.." group.word 0x20C++0x1 line.word 0x0 "MSS_RCM_MCAN3_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value corresponding MCAN selected clock.Data should be loaded as multibit. For example: if divider value of 8(1000) should be selected then '100010001000' should be configured to the register.Refer to AM602 clock planner for clock.." group.word 0x210++0x1 line.word 0x0 "MSS_RCM_QSPI0_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value QSPI selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x214++0x1 line.word 0x0 "MSS_RCM_RTI0_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value Corresponding RTI selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x218++0x1 line.word 0x0 "MSS_RCM_RTI1_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value Corresponding RTI selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x21C++0x1 line.word 0x0 "MSS_RCM_RTI2_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value Corresponding RTI selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x220++0x1 line.word 0x0 "MSS_RCM_RTI3_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value Corresponding RTI selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x228++0x1 line.word 0x0 "MSS_RCM_WDT0_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value WDT selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x22C++0x1 line.word 0x0 "MSS_RCM_WDT1_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value WDT selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x230++0x1 line.word 0x0 "MSS_RCM_WDT2_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value WDT selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x234++0x1 line.word 0x0 "MSS_RCM_WDT3_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value WDT selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x23C++0x1 line.word 0x0 "MSS_RCM_MCSPI0_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value Corresponding SPI selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x240++0x1 line.word 0x0 "MSS_RCM_MCSPI1_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value Corresponding SPI selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x244++0x1 line.word 0x0 "MSS_RCM_MCSPI2_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value Corresponding SPI selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x248++0x1 line.word 0x0 "MSS_RCM_MCSPI3_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value Corresponding SPI selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x24C++0x1 line.word 0x0 "MSS_RCM_MCSPI4_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value Corresponding SPI selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x250++0x1 line.word 0x0 "MSS_RCM_MMC0_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value MMCSD selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x254++0x1 line.word 0x0 "MSS_RCM_ICSSM0_UART_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value ICSSM_UCLK selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x258++0x1 line.word 0x0 "MSS_RCM_CPTS_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value CPTS selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x25C++0x1 line.word 0x0 "MSS_RCM_GPMC_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value GPMC selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x260++0x1 line.word 0x0 "MSS_RCM_CONTROLSS_PLL_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value CONTROLSS_PLL selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x264++0x1 line.word 0x0 "MSS_RCM_I2C_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value I2C selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x274++0x1 line.word 0x0 "MSS_RCM_LIN0_UART0_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value for corresponding UART and LIN selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock.." group.word 0x278++0x1 line.word 0x0 "MSS_RCM_LIN1_UART1_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value for corresponding UART and LIN selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock.." group.word 0x27C++0x1 line.word 0x0 "MSS_RCM_LIN2_UART2_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value for corresponding UART and LIN selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock.." group.word 0x280++0x1 line.word 0x0 "MSS_RCM_LIN3_UART3_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value for corresponding UART and LIN selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock.." group.word 0x284++0x1 line.word 0x0 "MSS_RCM_LIN4_UART4_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value for corresponding UART and LIN selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock.." group.word 0x288++0x1 line.word 0x0 "MSS_RCM_LIN5_UART5_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value for corresponding UART and LIN selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock.." group.word 0x28C++0x1 line.word 0x0 "MSS_RCM_RGMII_250_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value RGMII selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x290++0x1 line.word 0x0 "MSS_RCM_RGMII_50_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value MII100 selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.tbyte 0x294++0x2 line.tbyte 0x0 "MSS_RCM_RGMII_5_CLK_DIV_VAL" hexmask.tbyte 0x0 0.--23. 1. "CLKDIVR,Divider value MII10 selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.long 0x298++0x7 line.long 0x0 "MSS_RCM_XTAL_MMC_32K_CLK_DIV_VAL" hexmask.long 0x0 0.--29. 1. "CLKDIVR,Divider value for XTAL_32K clock.Data should be loaded as multibit. For example: if divider value of '0x30C' is required then '0x30CC330C' should be configured to the register.Refer to AM602 clock spec for clock reference" line.long 0x4 "MSS_RCM_XTAL_TEMPSENSE_32K_CLK_DIV_VAL" hexmask.long 0x4 0.--29. 1. "CLKDIVR,Divider value for XTAL_32K clock.Data should be loaded as multibit. For example: if divider value of '0x30C' is required then '0x30CC330C' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x2A0++0x1 line.word 0x0 "MSS_RCM_MSS_ELM_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value ELM clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.byte 0x300++0x0 line.byte 0x0 "MSS_RCM_MCAN0_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for corresponding MCAN" "0,1,2,3,4,5,6,7" group.byte 0x304++0x0 line.byte 0x0 "MSS_RCM_MCAN1_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for corresponding MCAN" "0,1,2,3,4,5,6,7" group.byte 0x308++0x0 line.byte 0x0 "MSS_RCM_MCAN2_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for corresponding MCAN" "0,1,2,3,4,5,6,7" group.byte 0x30C++0x0 line.byte 0x0 "MSS_RCM_MCAN3_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for corresponding MCAN" "0,1,2,3,4,5,6,7" group.byte 0x310++0x0 line.byte 0x0 "MSS_RCM_QSPI0_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for QSPI" "0,1,2,3,4,5,6,7" group.byte 0x314++0x0 line.byte 0x0 "MSS_RCM_RTI0_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for Corresponding RTI" "0,1,2,3,4,5,6,7" group.byte 0x318++0x0 line.byte 0x0 "MSS_RCM_RTI1_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for Corresponding RTI" "0,1,2,3,4,5,6,7" group.byte 0x31C++0x0 line.byte 0x0 "MSS_RCM_RTI2_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for Corresponding RTI" "0,1,2,3,4,5,6,7" group.byte 0x320++0x0 line.byte 0x0 "MSS_RCM_RTI3_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for Corresponding RTI" "0,1,2,3,4,5,6,7" group.byte 0x328++0x0 line.byte 0x0 "MSS_RCM_WDT0_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for WDT" "0,1,2,3,4,5,6,7" group.byte 0x32C++0x0 line.byte 0x0 "MSS_RCM_WDT1_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for WDT" "0,1,2,3,4,5,6,7" group.byte 0x330++0x0 line.byte 0x0 "MSS_RCM_WDT2_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for WDT" "0,1,2,3,4,5,6,7" group.byte 0x334++0x0 line.byte 0x0 "MSS_RCM_WDT3_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for WDT" "0,1,2,3,4,5,6,7" group.byte 0x33C++0x0 line.byte 0x0 "MSS_RCM_MCSPI0_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for Corresponding SPI" "0,1,2,3,4,5,6,7" group.byte 0x340++0x0 line.byte 0x0 "MSS_RCM_MCSPI1_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for Corresponding SPI" "0,1,2,3,4,5,6,7" group.byte 0x344++0x0 line.byte 0x0 "MSS_RCM_MCSPI2_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for Corresponding SPI" "0,1,2,3,4,5,6,7" group.byte 0x348++0x0 line.byte 0x0 "MSS_RCM_MCSPI3_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for Corresponding SPI" "0,1,2,3,4,5,6,7" group.byte 0x34C++0x0 line.byte 0x0 "MSS_RCM_MCSPI4_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for Corresponding SPI" "0,1,2,3,4,5,6,7" group.byte 0x350++0x0 line.byte 0x0 "MSS_RCM_MMC0_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for MMCSD" "0,1,2,3,4,5,6,7" group.byte 0x354++0x0 line.byte 0x0 "MSS_RCM_ICSSM0_UART_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for ICSSM_UCLK" "0,1,2,3,4,5,6,7" group.byte 0x358++0x0 line.byte 0x0 "MSS_RCM_CPTS_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for CPTS" "0,1,2,3,4,5,6,7" group.byte 0x35C++0x0 line.byte 0x0 "MSS_RCM_GPMC_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for GPMC" "0,1,2,3,4,5,6,7" group.byte 0x360++0x0 line.byte 0x0 "MSS_RCM_CONTROLSS_PLL_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for CONTROLSS_PLL" "0,1,2,3,4,5,6,7" group.byte 0x364++0x0 line.byte 0x0 "MSS_RCM_I2C0_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for I2C" "0,1,2,3,4,5,6,7" group.byte 0x368++0x0 line.byte 0x0 "MSS_RCM_I2C1_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for I2C" "0,1,2,3,4,5,6,7" group.byte 0x36C++0x0 line.byte 0x0 "MSS_RCM_I2C2_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for I2C" "0,1,2,3,4,5,6,7" group.byte 0x370++0x0 line.byte 0x0 "MSS_RCM_I2C3_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for I2C" "0,1,2,3,4,5,6,7" group.byte 0x374++0x0 line.byte 0x0 "MSS_RCM_LIN0_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for SPIB" "0,1,2,3,4,5,6,7" group.byte 0x378++0x0 line.byte 0x0 "MSS_RCM_LIN1_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for SPIB" "0,1,2,3,4,5,6,7" group.byte 0x37C++0x0 line.byte 0x0 "MSS_RCM_LIN2_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for SPIB" "0,1,2,3,4,5,6,7" group.byte 0x380++0x0 line.byte 0x0 "MSS_RCM_LIN3_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for SPIB" "0,1,2,3,4,5,6,7" group.byte 0x384++0x0 line.byte 0x0 "MSS_RCM_LIN4_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for SPIB" "0,1,2,3,4,5,6,7" group.byte 0x38C++0x0 line.byte 0x0 "MSS_RCM_UART0_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for corresponding UART" "0,1,2,3,4,5,6,7" group.byte 0x390++0x0 line.byte 0x0 "MSS_RCM_UART1_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for corresponding UART" "0,1,2,3,4,5,6,7" group.byte 0x394++0x0 line.byte 0x0 "MSS_RCM_UART2_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for corresponding UART" "0,1,2,3,4,5,6,7" group.byte 0x398++0x0 line.byte 0x0 "MSS_RCM_UART3_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for corresponding UART" "0,1,2,3,4,5,6,7" group.byte 0x39C++0x0 line.byte 0x0 "MSS_RCM_UART4_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for corresponding UART" "0,1,2,3,4,5,6,7" group.byte 0x3A0++0x0 line.byte 0x0 "MSS_RCM_UART5_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for corresponding UART" "0,1,2,3,4,5,6,7" group.byte 0x3A4++0x0 line.byte 0x0 "MSS_RCM_RGMII_250_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for RGMII" "0,1,2,3,4,5,6,7" group.byte 0x3A8++0x0 line.byte 0x0 "MSS_RCM_RGMII_50_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for MII100" "0,1,2,3,4,5,6,7" group.byte 0x3AC++0x0 line.byte 0x0 "MSS_RCM_RGMII_5_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for MII10" "0,1,2,3,4,5,6,7" group.byte 0x3B0++0x0 line.byte 0x0 "MSS_RCM_MMC0_32K_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for MMCSD_32K" "0,1,2,3,4,5,6,7" group.byte 0x3B4++0x0 line.byte 0x0 "MSS_RCM_TEMPSENSE_32K_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for TEMPSENSE_32K" "0,1,2,3,4,5,6,7" group.byte 0x3B8++0x0 line.byte 0x0 "MSS_RCM_CPSW_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for CPSW CPPI" "0,1,2,3,4,5,6,7" group.byte 0x3BC++0x0 line.byte 0x0 "MSS_RCM_ICSSM0_IEP_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for ICSSM_IEP" "0,1,2,3,4,5,6,7" group.byte 0x3C0++0x0 line.byte 0x0 "MSS_RCM_ICSSM0_CORE_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for ICSSM_CORE" "0,1,2,3,4,5,6,7" group.byte 0x3C4++0x0 line.byte 0x0 "MSS_RCM_MSS_ICSSM_SYS_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for ICSSM_SYS" "0,1,2,3,4,5,6,7" group.byte 0x3C8++0x0 line.byte 0x0 "MSS_RCM_MSS_ELM_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for ELM" "0,1,2,3,4,5,6,7" group.byte 0x3CC++0x0 line.byte 0x0 "MSS_RCM_R5SS0_CORE0_GATE" bitfld.byte 0x0 0.--2. "CLKGATE,writing '111' will gate clock to CORE0 related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7" group.byte 0x3D0++0x0 line.byte 0x0 "MSS_RCM_R5SS1_CORE0_GATE" bitfld.byte 0x0 0.--2. "CLKGATE,writing '111' will gate clock to CORE0 related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7" group.byte 0x3D4++0x0 line.byte 0x0 "MSS_RCM_R5SS0_CORE1_GATE" bitfld.byte 0x0 0.--2. "CLKGATE,writing '111' will gate clock to CORE1 related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7" group.byte 0x3D8++0x0 line.byte 0x0 "MSS_RCM_R5SS1_CORE1_GATE" bitfld.byte 0x0 0.--2. "CLKGATE,writing '111' will gate clock to CORE1 related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7" rgroup.word 0x400++0x1 line.word 0x0 "MSS_RCM_MCAN0_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for corresponding MCAN" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for corresponding MCAN" rgroup.word 0x404++0x1 line.word 0x0 "MSS_RCM_MCAN1_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for corresponding MCAN" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for corresponding MCAN" rgroup.word 0x408++0x1 line.word 0x0 "MSS_RCM_MCAN2_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for corresponding MCAN" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for corresponding MCAN" rgroup.word 0x40C++0x1 line.word 0x0 "MSS_RCM_MCAN3_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for corresponding MCAN" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for corresponding MCAN" rgroup.word 0x410++0x1 line.word 0x0 "MSS_RCM_QSPI0_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for QSPI" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for QSPI" rgroup.word 0x414++0x1 line.word 0x0 "MSS_RCM_RTI0_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for Corresponding RTI" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for Corresponding RTI" rgroup.word 0x418++0x1 line.word 0x0 "MSS_RCM_RTI1_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for Corresponding RTI" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for Corresponding RTI" rgroup.word 0x41C++0x1 line.word 0x0 "MSS_RCM_RTI2_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for Corresponding RTI" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for Corresponding RTI" rgroup.word 0x420++0x1 line.word 0x0 "MSS_RCM_RTI3_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for Corresponding RTI" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for Corresponding RTI" rgroup.word 0x428++0x1 line.word 0x0 "MSS_RCM_WDT0_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for WDT" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for WDT" rgroup.word 0x42C++0x1 line.word 0x0 "MSS_RCM_WDT1_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for WDT" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for WDT" rgroup.word 0x430++0x1 line.word 0x0 "MSS_RCM_WDT2_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for WDT" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for WDT" rgroup.word 0x434++0x1 line.word 0x0 "MSS_RCM_WDT3_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for WDT" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for WDT" rgroup.word 0x43C++0x1 line.word 0x0 "MSS_RCM_MCSPI0_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for Corresponding SPI" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for Corresponding SPI" rgroup.word 0x440++0x1 line.word 0x0 "MSS_RCM_MCSPI1_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for Corresponding SPI" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for Corresponding SPI" rgroup.word 0x444++0x1 line.word 0x0 "MSS_RCM_MCSPI2_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for Corresponding SPI" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for Corresponding SPI" rgroup.word 0x448++0x1 line.word 0x0 "MSS_RCM_MCSPI3_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for Corresponding SPI" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for Corresponding SPI" rgroup.word 0x44C++0x1 line.word 0x0 "MSS_RCM_MCSPI4_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for Corresponding SPI" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for Corresponding SPI" rgroup.word 0x450++0x1 line.word 0x0 "MSS_RCM_MMC0_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for MMCSD" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for MMCSD" rgroup.word 0x454++0x1 line.word 0x0 "MSS_RCM_ICSSM0_UART_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for ICSSM_UCLK" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for ICSSM_UCLK" rgroup.word 0x458++0x1 line.word 0x0 "MSS_RCM_CPTS_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for CPTS" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for CPTS" rgroup.word 0x45C++0x1 line.word 0x0 "MSS_RCM_GPMC_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for GPMC" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for GPMC" rgroup.word 0x460++0x1 line.word 0x0 "MSS_RCM_CONTROLSS_PLL_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for CONTROLSS_PLL" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for CONTROLSS_PLL" rgroup.word 0x464++0x1 line.word 0x0 "MSS_RCM_I2C_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for I2C" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for I2C" rgroup.word 0x474++0x1 line.word 0x0 "MSS_RCM_LIN0_UART0_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for corresponding UART and LIN" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for corresponding UART and LIN" rgroup.word 0x478++0x1 line.word 0x0 "MSS_RCM_LIN1_UART1_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for corresponding UART and LIN" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for corresponding UART and LIN" rgroup.word 0x47C++0x1 line.word 0x0 "MSS_RCM_LIN2_UART2_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for corresponding UART and LIN" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for corresponding UART and LIN" rgroup.word 0x480++0x1 line.word 0x0 "MSS_RCM_LIN3_UART3_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for corresponding UART and LIN" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for corresponding UART and LIN" rgroup.word 0x484++0x1 line.word 0x0 "MSS_RCM_LIN4_UART4_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for corresponding UART and LIN" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for corresponding UART and LIN" rgroup.word 0x488++0x1 line.word 0x0 "MSS_RCM_LIN5_UART5_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for corresponding UART and LIN" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for corresponding UART and LIN" rgroup.word 0x48C++0x1 line.word 0x0 "MSS_RCM_RGMII_250_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for RGMII" rgroup.word 0x490++0x1 line.word 0x0 "MSS_RCM_RGMII_50_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for MII100" rgroup.word 0x494++0x1 line.word 0x0 "MSS_RCM_RGMII_5_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for MII10" rgroup.tbyte 0x49C++0x2 line.tbyte 0x0 "MSS_RCM_MMC0_32K_CLK_STATUS" hexmask.tbyte.word 0x0 8.--17. 1. "CURRDIVIDER,Status shows the current divider value choosen for XTAL_32K" rgroup.tbyte 0x4A0++0x2 line.tbyte 0x0 "MSS_RCM_TEMPSENSE_32K_CLK_STATUS" hexmask.tbyte.word 0x0 8.--17. 1. "CURRDIVIDER,Status shows the current divider value choosen for XTAL_32K" rgroup.word 0x4A4++0x1 line.word 0x0 "MSS_RCM_MSS_ELM_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for ELM" group.byte 0x500++0x0 line.byte 0x0 "MSS_RCM_R5SS0_POR_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:writing '111' will assert por reset to R5SS Read is always 000" "0,1,2,3,4,5,6,7" group.byte 0x504++0x0 line.byte 0x0 "MSS_RCM_R5SS1_POR_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:writing '111' will assert por reset to R5SS Read is always 000" "0,1,2,3,4,5,6,7" group.byte 0x508++0x0 line.byte 0x0 "MSS_RCM_R5SS0_CORE0_GRST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:writing '111' will reset CORE0 and MSS_CORE0_VIM" "0,1,2,3,4,5,6,7" group.byte 0x50C++0x0 line.byte 0x0 "MSS_RCM_R5SS1_CORE0_GRST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:writing '111' will reset CORE0 and MSS_CORE0_VIM" "0,1,2,3,4,5,6,7" group.byte 0x510++0x0 line.byte 0x0 "MSS_RCM_R5SS0_CORE1_GRST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:writing '111' will reset CORE1 and MSS_CORE1_VIM" "0,1,2,3,4,5,6,7" group.byte 0x514++0x0 line.byte 0x0 "MSS_RCM_R5SS1_CORE1_GRST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:writing '111' will reset CORE1 and MSS_CORE1_VIM" "0,1,2,3,4,5,6,7" group.byte 0x518++0x0 line.byte 0x0 "MSS_RCM_R5SS0_CORE0_LRST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:writing '111' will reset CORE0 only" "0,1,2,3,4,5,6,7" group.byte 0x51C++0x0 line.byte 0x0 "MSS_RCM_R5SS1_CORE0_LRST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:writing '111' will reset CORE0 only" "0,1,2,3,4,5,6,7" group.byte 0x520++0x0 line.byte 0x0 "MSS_RCM_R5SS0_CORE1_LRST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:writing '111' will reset CORE1 only" "0,1,2,3,4,5,6,7" group.byte 0x524++0x0 line.byte 0x0 "MSS_RCM_R5SS1_CORE1_LRST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring.write pulse bit field:writing '111' will reset CORE1 only" "0,1,2,3,4,5,6,7" group.byte 0x528++0x0 line.byte 0x0 "MSS_RCM_R5SS0_VIM0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS_CORE0_VIM Writing 000 will deassert the reset" "0,1,2,3,4,5,6,7" group.byte 0x52C++0x0 line.byte 0x0 "MSS_RCM_R5SS1_VIM0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS_CORE0_VIM Writing 000 will deassert the reset" "0,1,2,3,4,5,6,7" group.byte 0x530++0x0 line.byte 0x0 "MSS_RCM_R5SS0_VIM1_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS_CORE1_VIM" "0,1,2,3,4,5,6,7" group.byte 0x534++0x0 line.byte 0x0 "MSS_RCM_R5SS1_VIM1_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS_CORE1_VIM" "0,1,2,3,4,5,6,7" group.byte 0x538++0x0 line.byte 0x0 "MSS_RCM_MCRC0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MCRC" "0,1,2,3,4,5,6,7" group.byte 0x53C++0x0 line.byte 0x0 "MSS_RCM_RTI0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding RTI" "0,1,2,3,4,5,6,7" group.byte 0x540++0x0 line.byte 0x0 "MSS_RCM_RTI1_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding RTI" "0,1,2,3,4,5,6,7" group.byte 0x544++0x0 line.byte 0x0 "MSS_RCM_RTI2_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding RTI" "0,1,2,3,4,5,6,7" group.byte 0x548++0x0 line.byte 0x0 "MSS_RCM_RTI3_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding RTI" "0,1,2,3,4,5,6,7" group.byte 0x54C++0x0 line.byte 0x0 "MSS_RCM_WDT0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset WDT" "0,1,2,3,4,5,6,7" group.byte 0x550++0x0 line.byte 0x0 "MSS_RCM_WDT1_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset WDT" "0,1,2,3,4,5,6,7" group.byte 0x554++0x0 line.byte 0x0 "MSS_RCM_WDT2_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset WDT" "0,1,2,3,4,5,6,7" group.byte 0x558++0x0 line.byte 0x0 "MSS_RCM_WDT3_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset WDT" "0,1,2,3,4,5,6,7" group.byte 0x55C++0x0 line.byte 0x0 "MSS_RCM_TOP_ESM_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset ESM" "0,1,2,3,4,5,6,7" group.byte 0x560++0x0 line.byte 0x0 "MSS_RCM_DCC0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset DCCA" "0,1,2,3,4,5,6,7" group.byte 0x564++0x0 line.byte 0x0 "MSS_RCM_DCC1_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset DCCB" "0,1,2,3,4,5,6,7" group.byte 0x568++0x0 line.byte 0x0 "MSS_RCM_DCC2_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset DCCC" "0,1,2,3,4,5,6,7" group.byte 0x56C++0x0 line.byte 0x0 "MSS_RCM_DCC3_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset DCCD" "0,1,2,3,4,5,6,7" group.byte 0x570++0x0 line.byte 0x0 "MSS_RCM_MCSPI0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset Corresponding SPI" "0,1,2,3,4,5,6,7" group.byte 0x574++0x0 line.byte 0x0 "MSS_RCM_MCSPI1_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset Corresponding SPI" "0,1,2,3,4,5,6,7" group.byte 0x578++0x0 line.byte 0x0 "MSS_RCM_MCSPI2_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset Corresponding SPI" "0,1,2,3,4,5,6,7" group.byte 0x57C++0x0 line.byte 0x0 "MSS_RCM_MCSPI3_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset Corresponding SPI" "0,1,2,3,4,5,6,7" group.byte 0x580++0x0 line.byte 0x0 "MSS_RCM_MCSPI4_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset Corresponding SPI" "0,1,2,3,4,5,6,7" group.byte 0x584++0x0 line.byte 0x0 "MSS_RCM_QSPI0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset QSPI" "0,1,2,3,4,5,6,7" group.byte 0x588++0x0 line.byte 0x0 "MSS_RCM_MCAN0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding MCAN" "0,1,2,3,4,5,6,7" group.byte 0x58C++0x0 line.byte 0x0 "MSS_RCM_MCAN1_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding MCAN" "0,1,2,3,4,5,6,7" group.byte 0x590++0x0 line.byte 0x0 "MSS_RCM_MCAN2_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding MCAN" "0,1,2,3,4,5,6,7" group.byte 0x594++0x0 line.byte 0x0 "MSS_RCM_MCAN3_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding MCAN" "0,1,2,3,4,5,6,7" group.byte 0x598++0x0 line.byte 0x0 "MSS_RCM_I2C0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding I2C" "0,1,2,3,4,5,6,7" group.byte 0x59C++0x0 line.byte 0x0 "MSS_RCM_I2C1_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding I2C" "0,1,2,3,4,5,6,7" group.byte 0x5A0++0x0 line.byte 0x0 "MSS_RCM_I2C2_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding I2C" "0,1,2,3,4,5,6,7" group.byte 0x5A4++0x0 line.byte 0x0 "MSS_RCM_I2C3_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding I2C" "0,1,2,3,4,5,6,7" group.byte 0x5A8++0x0 line.byte 0x0 "MSS_RCM_UART0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding UART instance" "0,1,2,3,4,5,6,7" group.byte 0x5AC++0x0 line.byte 0x0 "MSS_RCM_UART1_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding UART instance" "0,1,2,3,4,5,6,7" group.byte 0x5B0++0x0 line.byte 0x0 "MSS_RCM_UART2_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding UART instance" "0,1,2,3,4,5,6,7" group.byte 0x5B4++0x0 line.byte 0x0 "MSS_RCM_UART3_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding UART instance" "0,1,2,3,4,5,6,7" group.byte 0x5B8++0x0 line.byte 0x0 "MSS_RCM_UART4_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding UART instance" "0,1,2,3,4,5,6,7" group.byte 0x5BC++0x0 line.byte 0x0 "MSS_RCM_UART5_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding UART instance" "0,1,2,3,4,5,6,7" group.byte 0x5C0++0x0 line.byte 0x0 "MSS_RCM_LIN0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset LIN" "0,1,2,3,4,5,6,7" group.byte 0x5C4++0x0 line.byte 0x0 "MSS_RCM_LIN1_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset LIN" "0,1,2,3,4,5,6,7" group.byte 0x5C8++0x0 line.byte 0x0 "MSS_RCM_LIN2_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset LIN" "0,1,2,3,4,5,6,7" group.byte 0x5CC++0x0 line.byte 0x0 "MSS_RCM_LIN3_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset LIN" "0,1,2,3,4,5,6,7" group.byte 0x5D0++0x0 line.byte 0x0 "MSS_RCM_LIN4_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset LIN" "0,1,2,3,4,5,6,7" group.word 0x5D8++0x1 line.word 0x0 "MSS_RCM_EDMA_RST_CTRL" bitfld.word 0x0 12.--14. "TPTCA1_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS_TPTCA1" "0,1,2,3,4,5,6,7" bitfld.word 0x0 8.--10. "TPTCA0_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS_TPTCA0" "0,1,2,3,4,5,6,7" bitfld.word 0x0 4.--6. "TPCCA_ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS_TPCCA" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset EDMA" "0,1,2,3,4,5,6,7" group.byte 0x5DC++0x0 line.byte 0x0 "MSS_RCM_INFRA_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS INFRA" "0,1,2,3,4,5,6,7" group.byte 0x5E0++0x0 line.byte 0x0 "MSS_RCM_CPSW_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS CPSW" "0,1,2,3,4,5,6,7" group.byte 0x5E4++0x0 line.byte 0x0 "MSS_RCM_ICSSM0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MSS ICSSM" "0,1,2,3,4,5,6,7" group.byte 0x5E8++0x0 line.byte 0x0 "MSS_RCM_MMC0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset MMCSD" "0,1,2,3,4,5,6,7" group.byte 0x5EC++0x0 line.byte 0x0 "MSS_RCM_GPIO0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding GPIO" "0,1,2,3,4,5,6,7" group.byte 0x5F0++0x0 line.byte 0x0 "MSS_RCM_GPIO1_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding GPIO" "0,1,2,3,4,5,6,7" group.byte 0x5F4++0x0 line.byte 0x0 "MSS_RCM_GPIO2_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding GPIO" "0,1,2,3,4,5,6,7" group.byte 0x5F8++0x0 line.byte 0x0 "MSS_RCM_GPIO3_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset corresponding GPIO" "0,1,2,3,4,5,6,7" group.byte 0x5FC++0x0 line.byte 0x0 "MSS_RCM_SPINLOCK0_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset SPINLOCK" "0,1,2,3,4,5,6,7" group.byte 0x600++0x0 line.byte 0x0 "MSS_RCM_GPMC_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset GPMC" "0,1,2,3,4,5,6,7" group.byte 0x604++0x0 line.byte 0x0 "MSS_RCM_TEMPSENSE_32K_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset TEMPSENSE" "0,1,2,3,4,5,6,7" group.byte 0x608++0x0 line.byte 0x0 "MSS_RCM_MSS_ELM_RST_CTRL" bitfld.byte 0x0 0.--2. "ASSERT,This feature is for debug purpose only. Software needs to ensure the state of the Device/IP before configuring. Writing '111' will reset ELM" "0,1,2,3,4,5,6,7" group.word 0x700++0x1 line.word 0x0 "MSS_RCM_L2OCRAM_BANK0_PD_CTRL" bitfld.word 0x0 8.--10. "AGOODIN,SW control for power signal 'AGOODIN' for MSS_L2_BANKA" "0,1,2,3,4,5,6,7" bitfld.word 0x0 4.--6. "AONIN,SW control for power signal 'AONIN' for MSS_L2_BANKA" "0,1,2,3,4,5,6,7" bitfld.word 0x0 0.--2. "ISO,SW control for power signal 'ISO' for MSS_L2_BANKA" "0,1,2,3,4,5,6,7" group.word 0x704++0x1 line.word 0x0 "MSS_RCM_L2OCRAM_BANK1_PD_CTRL" bitfld.word 0x0 8.--10. "AGOODIN,SW control for power signal 'AGOODIN' for MSS_L2_BANKB" "0,1,2,3,4,5,6,7" bitfld.word 0x0 4.--6. "AONIN,SW control for power signal 'AONIN' for MSS_L2_BANKB" "0,1,2,3,4,5,6,7" bitfld.word 0x0 0.--2. "ISO,SW control for power signal 'ISO' for MSS_L2_BANKB" "0,1,2,3,4,5,6,7" group.word 0x708++0x1 line.word 0x0 "MSS_RCM_L2OCRAM_BANK2_PD_CTRL" bitfld.word 0x0 8.--10. "AGOODIN,SW control for power signal 'AGOODIN' for MSS_L2_BANKC" "0,1,2,3,4,5,6,7" bitfld.word 0x0 4.--6. "AONIN,SW control for power signal 'AONIN' for MSS_L2_BANKC" "0,1,2,3,4,5,6,7" bitfld.word 0x0 0.--2. "ISO,SW control for power signal 'ISO' for MSS_L2_BANKC" "0,1,2,3,4,5,6,7" group.word 0x70C++0x1 line.word 0x0 "MSS_RCM_L2OCRAM_BANK3_PD_CTRL" bitfld.word 0x0 8.--10. "AGOODIN,SW control for power signal 'AGOODIN' for MSS_L2_BANKD" "0,1,2,3,4,5,6,7" bitfld.word 0x0 4.--6. "AONIN,SW control for power signal 'AONIN' for MSS_L2_BANKD" "0,1,2,3,4,5,6,7" bitfld.word 0x0 0.--2. "ISO,SW control for power signal 'ISO' for MSS_L2_BANKD" "0,1,2,3,4,5,6,7" rgroup.byte 0x710++0x0 line.byte 0x0 "MSS_RCM_L2OCRAM_BANK0_PD_STATUS" bitfld.byte 0x0 1. "AGOODOUT,SW status indicating the 'pgoodin' of MSS_L2_BANKA" "0,1" bitfld.byte 0x0 0. "AONOUT,SW status indicating the 'ponin' of MSS_L2_BANKA" "0,1" rgroup.byte 0x714++0x0 line.byte 0x0 "MSS_RCM_L2OCRAM_BANK1_PD_STATUS" bitfld.byte 0x0 1. "AGOODOUT,SW status indicating the 'pgoodin' of MSS_L2_BANKB" "0,1" bitfld.byte 0x0 0. "AONOUT,SW status indicating the 'ponin' of MSS_L2_BANKB" "0,1" rgroup.byte 0x718++0x0 line.byte 0x0 "MSS_RCM_L2OCRAM_BANK2_PD_STATUS" bitfld.byte 0x0 1. "AGOODOUT,SW status indicating the 'pgoodin' of MSS_L2_BANKC" "0,1" bitfld.byte 0x0 0. "AONOUT,SW status indicating the 'ponin' of MSS_L2_BANKC" "0,1" rgroup.byte 0x71C++0x0 line.byte 0x0 "MSS_RCM_L2OCRAM_BANK3_PD_STATUS" bitfld.byte 0x0 1. "AGOODOUT,SW status indicating the 'pgoodin' of MSS_L2_BANKD" "0,1" bitfld.byte 0x0 0. "AONOUT,SW status indicating the 'ponin' of MSS_L2_BANKD" "0,1" group.long 0x720++0xF line.long 0x0 "MSS_RCM_HW_REG0" hexmask.long 0x0 0.--31. 1. "HWREG,HW Reserved regiser" line.long 0x4 "MSS_RCM_HW_REG1" hexmask.long 0x4 0.--31. 1. "HWREG,HW Reserved regiser" line.long 0x8 "MSS_RCM_HW_REG2" hexmask.long 0x8 0.--31. 1. "HWREG,HW Reserved regiser" line.long 0xC "MSS_RCM_HW_REG3" hexmask.long 0xC 0.--31. 1. "HWREG,HW Reserved regiser" group.word 0x800++0x1 line.word 0x0 "MSS_RCM_HSM_RTIA_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "HSM_RTI0_CLK_SRC_SEL,Select line for selecting source clock for HSM_Corresponding RTI.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for.." group.word 0x804++0x1 line.word 0x0 "MSS_RCM_HSM_WDT_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "HSM_WDT0_CLK_SRC_SEL,Select line for selecting source clock for HSM_WDT.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock.." group.word 0x808++0x1 line.word 0x0 "MSS_RCM_HSM_RTC_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "HSM_RTC0_CLK_SRC_SEL,Select line for selecting source clock for HSM_RTC.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock.." group.word 0x80C++0x1 line.word 0x0 "MSS_RCM_HSM_DMTA_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "HSM_DTM0_CLK_SRC_SEL,Select line for selecting source clock for HSM_DMTA.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock.." group.word 0x810++0x1 line.word 0x0 "MSS_RCM_HSM_DMTB_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "HSM_DTM1_CLK_SRC_SEL,Select line for selecting source clock for HSM_DMTB.Data should be loaded as multibit. For example: if '0x5' should be selected then '0x555' should be configured to the register.Refer to AM602 clock spec for source clock.." group.word 0x814++0x1 line.word 0x0 "MSS_RCM_HSM_RTI_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value HSM RTI selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x818++0x1 line.word 0x0 "MSS_RCM_HSM_WDT_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value HSM WDT selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x81C++0x1 line.word 0x0 "MSS_RCM_HSM_RTC_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value HSM RTC selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x820++0x1 line.word 0x0 "MSS_RCM_HSM_DMTA_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value HSM DMTA selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.word 0x824++0x1 line.word 0x0 "MSS_RCM_HSM_DMTB_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIVR,Divider value HSM DMTB selected clock.Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register.Refer to AM602 clock spec for clock reference" group.byte 0x828++0x0 line.byte 0x0 "MSS_RCM_HSM_RTI_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for HSM RTI" "0,1,2,3,4,5,6,7" group.byte 0x82C++0x0 line.byte 0x0 "MSS_RCM_HSM_WDT_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for HSM WDT" "0,1,2,3,4,5,6,7" group.byte 0x830++0x0 line.byte 0x0 "MSS_RCM_HSM_RTC_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for HSM RTC" "0,1,2,3,4,5,6,7" group.byte 0x834++0x0 line.byte 0x0 "MSS_RCM_HSM_DMTA_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for HSM DMTA" "0,1,2,3,4,5,6,7" group.byte 0x838++0x0 line.byte 0x0 "MSS_RCM_HSM_DMTB_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,writing '111' will gate clock for HSM DMTB" "0,1,2,3,4,5,6,7" rgroup.word 0x83C++0x1 line.word 0x0 "MSS_RCM_HSM_RTI_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for HSM_RTI" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for HSM_RTI" rgroup.word 0x840++0x1 line.word 0x0 "MSS_RCM_HSM_WDT_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for HSM_WDT" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for HSM_WDT" rgroup.word 0x844++0x1 line.word 0x0 "MSS_RCM_HSM_RTC_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for HSM_RTC" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for HSM_RTC" rgroup.word 0x848++0x1 line.word 0x0 "MSS_RCM_HSM_DMTA_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for HSM_DMTA" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for HSM_DMTA" rgroup.word 0x84C++0x1 line.word 0x0 "MSS_RCM_HSM_DMTB_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for HSM_DMTB" hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for HSM_DMTB" group.long 0xFD0++0xF line.long 0x0 "MSS_RCM_HW_SPARE_RW0" hexmask.long 0x0 0.--31. 1. "HW_SPARE_RW0,Reserved for HW R&D" line.long 0x4 "MSS_RCM_HW_SPARE_RW1" hexmask.long 0x4 0.--31. 1. "HW_SPARE_RW1,Reserved for HW R&D" line.long 0x8 "MSS_RCM_HW_SPARE_RW2" hexmask.long 0x8 0.--31. 1. "HW_SPARE_RW2,Reserved for HW R&D" line.long 0xC "MSS_RCM_HW_SPARE_RW3" hexmask.long 0xC 0.--31. 1. "HW_SPARE_RW3,Reserved for HW R&D" rgroup.long 0xFE0++0xF line.long 0x0 "MSS_RCM_HW_SPARE_RO0" hexmask.long 0x0 0.--31. 1. "HW_SPARE_RO0,Reserved for HW R&D" line.long 0x4 "MSS_RCM_HW_SPARE_RO1" hexmask.long 0x4 0.--31. 1. "HW_SPARE_RO1,Reserved for HW R&D" line.long 0x8 "MSS_RCM_HW_SPARE_RO2" hexmask.long 0x8 0.--31. 1. "HW_SPARE_RO2,Reserved for HW R&D" line.long 0xC "MSS_RCM_HW_SPARE_RO3" hexmask.long 0xC 0.--31. 1. "HW_SPARE_RO3,Reserved for HW R&D" group.long 0xFF0++0x7 line.long 0x0 "MSS_RCM_HW_SPARE_WPH" hexmask.long 0x0 0.--31. 1. "HW_SPARE_WPH,Reserved for HW R&D" line.long 0x4 "MSS_RCM_HW_SPARE_REC" bitfld.long 0x4 31. "HW_SPARE_REC31,Reserved for HW R&D" "0,1" bitfld.long 0x4 30. "HW_SPARE_REC30,Reserved for HW R&D" "0,1" bitfld.long 0x4 29. "HW_SPARE_REC29,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 28. "HW_SPARE_REC28,Reserved for HW R&D" "0,1" bitfld.long 0x4 27. "HW_SPARE_REC27,Reserved for HW R&D" "0,1" bitfld.long 0x4 26. "HW_SPARE_REC26,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 25. "HW_SPARE_REC25,Reserved for HW R&D" "0,1" bitfld.long 0x4 24. "HW_SPARE_REC24,Reserved for HW R&D" "0,1" bitfld.long 0x4 23. "HW_SPARE_REC23,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 22. "HW_SPARE_REC22,Reserved for HW R&D" "0,1" bitfld.long 0x4 21. "HW_SPARE_REC21,Reserved for HW R&D" "0,1" bitfld.long 0x4 20. "HW_SPARE_REC20,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 19. "HW_SPARE_REC19,Reserved for HW R&D" "0,1" bitfld.long 0x4 18. "HW_SPARE_REC18,Reserved for HW R&D" "0,1" bitfld.long 0x4 17. "HW_SPARE_REC17,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 16. "HW_SPARE_REC16,Reserved for HW R&D" "0,1" bitfld.long 0x4 15. "HW_SPARE_REC15,Reserved for HW R&D" "0,1" bitfld.long 0x4 14. "HW_SPARE_REC14,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 13. "HW_SPARE_REC13,Reserved for HW R&D" "0,1" bitfld.long 0x4 12. "HW_SPARE_REC12,Reserved for HW R&D" "0,1" bitfld.long 0x4 11. "HW_SPARE_REC11,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 10. "HW_SPARE_REC10,Reserved for HW R&D" "0,1" bitfld.long 0x4 9. "HW_SPARE_REC9,Reserved for HW R&D" "0,1" bitfld.long 0x4 8. "HW_SPARE_REC8,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 7. "HW_SPARE_REC7,Reserved for HW R&D" "0,1" bitfld.long 0x4 6. "HW_SPARE_REC6,Reserved for HW R&D" "0,1" bitfld.long 0x4 5. "HW_SPARE_REC5,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 4. "HW_SPARE_REC4,Reserved for HW R&D" "0,1" bitfld.long 0x4 3. "HW_SPARE_REC3,Reserved for HW R&D" "0,1" bitfld.long 0x4 2. "HW_SPARE_REC2,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 1. "HW_SPARE_REC1,Reserved for HW R&D" "0,1" bitfld.long 0x4 0. "HW_SPARE_REC0,Reserved for HW R&D" "0,1" group.long 0x1008++0x7 line.long 0x0 "MSS_RCM_LOCK0_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "MSS_RCM_LOCK0_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" group.byte 0x1010++0x0 line.byte 0x0 "MSS_RCM_INTR_RAW_STATUS" bitfld.byte 0x0 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.byte 0x0 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" bitfld.byte 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" group.byte 0x1014++0x0 line.byte 0x0 "MSS_RCM_INTR_ENABLED_STATUS_CLEAR" bitfld.byte 0x0 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.byte 0x0 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" bitfld.byte 0x0 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" group.byte 0x1018++0x0 line.byte 0x0 "MSS_RCM_INTR_ENABLE" bitfld.byte 0x0 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.byte 0x0 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" bitfld.byte 0x0 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" group.byte 0x101C++0x0 line.byte 0x0 "MSS_RCM_INTR_ENABLE_CLEAR" bitfld.byte 0x0 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.byte 0x0 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" bitfld.byte 0x0 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.byte 0x1020++0x0 line.byte 0x0 "MSS_RCM_EOI" hexmask.byte 0x0 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0x3 line.long 0x0 "MSS_RCM_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." rgroup.byte 0x1028++0x0 line.byte 0x0 "MSS_RCM_FAULT_TYPE_STATUS" bitfld.byte 0x0 6. "FAULT_NS,Non-secure access." "0,1" hexmask.byte 0x0 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1.." rgroup.long 0x102C++0x3 line.long 0x0 "MSS_RCM_FAULT_ATTR_STATUS" hexmask.long.word 0x0 20.--31. 1. "FAULT_XID,XID." hexmask.long.word 0x0 8.--19. 1. "FAULT_ROUTEID,Route ID." hexmask.long.byte 0x0 0.--7. 1. "FAULT_PRIVID,Privilege ID." wgroup.long 0x1030++0x3 line.long 0x0 "MSS_RCM_FAULT_CLEAR" bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" tree.end tree.end tree "QSPI" base ad:0x48200000 rgroup.long 0x0++0x3 line.long 0x0 "QSPI0_PID" bitfld.long 0x0 30.--31. "SCHEME,The scheme of the register used. This indicates the PDR3.5 Method" "0,1,2,3" bitfld.long 0x0 28.--29. "RESERVED,Always read as 0" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,The function of the module being used" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Release Version The PDR release number of this IP" bitfld.long 0x0 8.--10. "MAJOR,Major Release Number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom IP" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Release Number" group.long 0x4++0x47 line.long 0x0 "QSPI0_MSS_QSPI_RESERVED1" line.long 0x4 "QSPI0_MSS_QSPI_RESERVED2" line.long 0x8 "QSPI0_MSS_QSPI_RESERVED3" line.long 0xC "QSPI0_SYSCONFIG" hexmask.long 0xC 6.--31. 1. "RESERVED3,Always read as 0" rbitfld.long 0xC 4.--5. "RESERVED2,Always read as 0" "0,1,2,3" bitfld.long 0xC 2.--3. "IDLEMODE,Configuration of the local target state management mode. By definition target can handle read/write transaction as long as it is out of IDLE state0x0 : Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests.." "0,1,2,3" newline rbitfld.long 0xC 0.--1. "RESERVED1,Always read as 0" "0,1,2,3" line.long 0x10 "QSPI0_MSS_QSPI_RESERVED4" line.long 0x14 "QSPI0_MSS_QSPI_RESERVED5" line.long 0x18 "QSPI0_MSS_QSPI_RESERVED6" line.long 0x1C "QSPI0_INTR_STATUS_RAW_SET" hexmask.long 0x1C 2.--31. 1. "RESERVED,Always read as 0" bitfld.long 0x1C 1. "WIRQ_RAW,Word Interrupt Status Read indicates raw status0 = inactive1 = activeWriting 1 will set statusWriting 0 has no effect" "0,1" bitfld.long 0x1C 0. "FIRQ_RAW,Frame Interrupt StatusRead indicates raw status0 = inactive1 = activeWriting 1 will set statusWriting 0 has no effect" "0,1" line.long 0x20 "QSPI0_INTR_STATUS_ENABLED_CLEAR" hexmask.long 0x20 2.--31. 1. "RESERVED,Always read as 0" bitfld.long 0x20 1. "WIRQ_ENA,Word Interrupt Enabled StatusRead indicates enabled status0 = inactive1 = activeWriting 1 will clear interruptWriting 0 has no effect" "0,1" bitfld.long 0x20 0. "FIRQ_ENA,Frame Interrupt Enabled StatusRead indicates enabled status0 = inactive1 = activeWriting 1 will clear interruptWriting 0 has no effect" "0,1" line.long 0x24 "QSPI0_INTR_ENABLE_SET" hexmask.long 0x24 2.--31. 1. "RESERVED,Always read as 0" bitfld.long 0x24 1. "WIRQ_ENA_SET,Word Interrupt Enable/SetRead indicates interrupt enable0 = disabled1 = enabledWriting 1 will set interrupt enabledWriting 0 has no effect" "0,1" bitfld.long 0x24 0. "FIRQ_ENA_SET,Frame Interrupt Enable/SetRead indicates interrupt enable0 = disabled1 = enabledWriting 1 will set interrupt enabledWriting 0 has no effect" "0,1" line.long 0x28 "QSPI0_INTR_ENABLE_CLEAR" hexmask.long 0x28 2.--31. 1. "RESERVED,Always read as 0" bitfld.long 0x28 1. "WIRQ_ENA_CLR,Word Interrupt Enable/ClearRead indicates interrupt enable0 = disabled1 = enabledWriting 1 will clear interrupt enabledWriting 0 has no effect" "0,1" bitfld.long 0x28 0. "FIRQ_ENA_CLR,Frame Interrupt Enable/ClearRead indicates interrupt enable0 = disabled1 = enabledWriting 1 will clear interrupt enabledWriting 0 has no effect" "0,1" line.long 0x2C "QSPI0_INTC_EOI" hexmask.long 0x2C 0.--31. 1. "EOI_VECTOR,Number associated with the ipgenericirq for intr output. There are 1 interrupt outputsWrite 0x0 : Write to intr IP GenericAny other write value is ignored." line.long 0x30 "QSPI0_MSS_QSPI_RESERVED7" line.long 0x34 "QSPI0_MSS_QSPI_RESERVED8" line.long 0x38 "QSPI0_MSS_QSPI_RESERVED9" line.long 0x3C "QSPI0_SPI_CLOCK_CNTRL" bitfld.long 0x3C 31. "CLKEN,Clock Enable. 0- Data clock is turned off1- Data clock is enabled" "0,1" hexmask.long.word 0x3C 16.--30. 1. "RESERVED,Always read as 0" hexmask.long.word 0x3C 0.--15. 1. "DCLK_DIV,Serial data clock divide by ratio" line.long 0x40 "QSPI0_SPI_DC" rbitfld.long 0x40 29.--31. "RESERVED4,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x40 27.--28. "DD3,Data delay for chip select 300- Data is output on the same cycle as the CS_N goes active01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active11- Data is output 3 DCLK cycles after.." "0,1,2,3" bitfld.long 0x40 26. "CKPH3,Clock phase for chip select 3 If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edgeIf CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted.." "0,1" newline bitfld.long 0x40 25. "CSP3,Chip select polarity for chip select 30- Active low1- Active high" "0,1" bitfld.long 0x40 24. "CKP3,Clock polarity for chip select 30- When data is not being transferred SCK = 01- When data is not being transferred SCK = 1" "0,1" rbitfld.long 0x40 21.--23. "RESERVED3,Always read as 0" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 19.--20. "DD2,Data delay for chip select 200- Data is output on the same cycle as the CS_N goes active01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active11- Data is output 3 DCLK cycles after.." "0,1,2,3" bitfld.long 0x40 18. "CKPH2,Clock phase for chip select 2. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edgeIf CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted.." "0,1" bitfld.long 0x40 17. "CSP2,Chip select polarity for chip select 20- Active low1- Active high" "0,1" newline bitfld.long 0x40 16. "CKP2,Clock polarity for chip select 20- When data is not being transferred SCK = 01- When data is not being transferred SCK = 1" "0,1" rbitfld.long 0x40 13.--15. "RESERVED2,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x40 11.--12. "DD1,Data delay for chip select 100- Data is output on the same cycle as the CS_N goes active01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active11- Data is output 3 DCLK cycles after.." "0,1,2,3" newline bitfld.long 0x40 10. "CKPH1,Clock phase for chip select 1. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edgeIf CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted.." "0,1" bitfld.long 0x40 9. "CSP1,Chip select polarity for chip select 10- Active low1- Active high" "0,1" bitfld.long 0x40 8. "CKP1,Clock polarity for chip select 10- When data is not being transferred SCK = 01- When data is not being transferred SCK = 1" "0,1" newline rbitfld.long 0x40 5.--7. "RESERVED1,Always read as 0" "0,1,2,3,4,5,6,7" bitfld.long 0x40 3.--4. "DD0,Data delay for chip select 000- Data is output on the same cycle as the CS_N goes active01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active11- Data is output 3 DCLK cycles after.." "0,1,2,3" bitfld.long 0x40 2. "CKPH0,Clock phase for chip select 0. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edgeIf CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted.." "0,1" newline bitfld.long 0x40 1. "CSP0,Chip select polarity for chip select 00- Active low1- Active high" "0,1" bitfld.long 0x40 0. "CKP0,Clock polarity for chip select 00- When data is not being transferred SCK = 01- When data is not being transferred SCK = 1" "0,1" line.long 0x44 "QSPI0_SPI_CMD" rbitfld.long 0x44 30.--31. "RESERVED3,Always read as 0" "0,1,2,3" bitfld.long 0x44 28.--29. "CSNUM,Device select. Sets the active chip select for the transfer00- Chip Select 0 active01- Chip Select 1 active10- Chip Select 2 active11- Chip Select 3 active" "0,1,2,3" rbitfld.long 0x44 26.--27. "RESERVED2,Always read as 0" "0,1,2,3" newline hexmask.long.byte 0x44 19.--25. 1. "WLEN,Word length. Sets the size of the individual transfers from 1 ? 128 bits0- 1 bit1- 2 bits?127 ? 128 bits" bitfld.long 0x44 16.--18. "CMD,Transfer command000- Reserved001- 4 pin Read Single 010- 4 pin Write Single011- 4 pin Read Dual100 ? Reserved101 ? 3 pin Read Single110 ? 3 pin Write Single 111 ? 6 pin Read Quad" "0,1,2,3,4,5,6,7" bitfld.long 0x44 15. "FIRQ,Frame count interrupt enable" "0,1" newline bitfld.long 0x44 14. "WIRQ,Word count interrupt enable" "0,1" rbitfld.long 0x44 12.--13. "RESERVED1,Always read as 0" "0,1,2,3" hexmask.long.word 0x44 0.--11. 1. "FLEN,Frame Length0- 1 word1- 2 words?4095 ? 4096 words" rgroup.long 0x4C++0x3 line.long 0x0 "QSPI0_SPI_STATUS" hexmask.long.byte 0x0 28.--31. 1. "RESERVED2,Always read as 0" hexmask.long.word 0x0 16.--27. 1. "WDCNT,Word count. This field will reflect the 1-4096 words transferred" hexmask.long.word 0x0 3.--15. 1. "RESERVED1,Always read as 0" newline bitfld.long 0x0 2. "FC,Frame complete. This bit is set after all of the requested words have been transmitted.0- Transfer is not complete1- Transfer is completeThis bit is reset when the SPI Status Register is read" "0,1" bitfld.long 0x0 1. "WC,Word complete. This bit is set after each word transfer is completed.0- Word transfer is not complete1- Word transfer is completeThis bit is reset when the SPI Status Register is read" "0,1" bitfld.long 0x0 0. "BUSY,Busy bit. Active transfer in progress. This bit is only set during an active word transfer. Between words the bit will clear to signal that it is ok to read/write the data registers.0- Idle1- Busy" "0,1" group.long 0x50++0x23 line.long 0x0 "QSPI0_SPI_DATA" hexmask.long 0x0 0.--31. 1. "DATA,Data register for read and write operations" line.long 0x4 "QSPI0_SPI_SETUP0" rbitfld.long 0x4 29.--31. "RESERVED2,Always read as 0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" hexmask.long.byte 0x4 16.--23. 1. "WCMD,Write Command" newline rbitfld.long 0x4 14.--15. "RESERVED1,Always read as 0" "0,1,2,3" bitfld.long 0x4 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command00 ? Normal read (all data input on spi_din)01 ? Dual read (odd bytes input on spi_din; even on spi_dout)10 ? Normal read (all data input on spi_din)11 ? Quad read (uses.." "0,1,2,3" bitfld.long 0x4 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits" "0: use the value in NUM_D_BITS1 = use 8 bits,?,2: use 16 bits,3: use 24 bits" newline bitfld.long 0x4 8.--9. "NUM_A_BYTES,Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes" hexmask.long.byte 0x4 0.--7. 1. "RCMD,Read Command" line.long 0x8 "QSPI0_SPI_SETUP1" rbitfld.long 0x8 29.--31. "RESERVED2,Always read as 0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 24.--28. 1. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" hexmask.long.byte 0x8 16.--23. 1. "WCMD,Write Command" newline rbitfld.long 0x8 14.--15. "RESERVED1,Always read as 0" "0,1,2,3" bitfld.long 0x8 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command00 ? Normal read (all data input on spi_din)01 ? Dual read (odd bytes input on spi_din; even on spi_dout)10 ? Normal read (all data input on spi_din)11 ? Quad read (uses.." "0,1,2,3" bitfld.long 0x8 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits" "0: use the value in NUM_D_BITS1 = use 8 bits,?,2: use 16 bits,3: use 24 bits" newline bitfld.long 0x8 8.--9. "NUM_A_BYTES,Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes" hexmask.long.byte 0x8 0.--7. 1. "RCMD,Read Command" line.long 0xC "QSPI0_SPI_SETUP2" rbitfld.long 0xC 29.--31. "RESERVED2,Always read as 0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--28. 1. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" hexmask.long.byte 0xC 16.--23. 1. "WCMD,Write Command" newline rbitfld.long 0xC 14.--15. "RESERVED1,Always read as 0" "0,1,2,3" bitfld.long 0xC 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command00 ? Normal read (all data input on spi_din)01 ? Dual read (odd bytes input on spi_din; even on spi_dout)10 ? Normal read (all data input on spi_din)11 ? Quad read (uses.." "0,1,2,3" bitfld.long 0xC 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits" "0: use the value in NUM_D_BITS1 = use 8 bits,?,2: use 16 bits,3: use 24 bits" newline bitfld.long 0xC 8.--9. "NUM_A_BYTES,Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes" hexmask.long.byte 0xC 0.--7. 1. "RCMD,Read Command" line.long 0x10 "QSPI0_SPI_SETUP3" rbitfld.long 0x10 29.--31. "RESERVED2,Always read as 0" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x10 24.--28. 1. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" hexmask.long.byte 0x10 16.--23. 1. "WCMD,Write Command" newline rbitfld.long 0x10 14.--15. "RESERVED1,Always read as 0" "0,1,2,3" bitfld.long 0x10 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command00 ? Normal read (all data input on spi_din)01 ? Dual read (odd bytes input on spi_din; even on spi_dout)10 ? Normal read (all data input on spi_din)11 ? Quad read (uses.." "0,1,2,3" bitfld.long 0x10 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits" "0: use the value in NUM_D_BITS1 = use 8 bits,?,2: use 16 bits,3: use 24 bits" newline bitfld.long 0x10 8.--9. "NUM_A_BYTES,Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes" "0: 1 byte,1: 2 bytes,2: 3 bytes,3: 4 bytes" hexmask.long.byte 0x10 0.--7. 1. "RCMD,Read Command" line.long 0x14 "QSPI0_SPI_SWITCH" hexmask.long 0x14 2.--31. 1. "RESERVED,Always read as 0" bitfld.long 0x14 1. "MM_INT_EN,Memory Mapped mode interrupt enable.0 ? Interrupts are disabled during memory mapped operations1 ? Word Count interrupt is enabled for memory mapped operations" "0,1" bitfld.long 0x14 0. "MMPT_S,MMPT select. If 0 (default) config port has is selected to control config of core SPI module. If 1 Memory Mapped Protocol Translator is selected to control config port of core SPI module." "0,1" line.long 0x18 "QSPI0_SPI_DATA1" hexmask.long 0x18 0.--31. 1. "DATA,Data register for read and write operations" line.long 0x1C "QSPI0_SPI_DATA2" hexmask.long 0x1C 0.--31. 1. "DATA,Data register for read and write operations" line.long 0x20 "QSPI0_SPI_DATA3" hexmask.long 0x20 0.--31. 1. "DATA,Data register for read and write operations" tree.end tree "R5SS" base ad:0x0 tree "R5SS0" sif (cpuis("AM263?-SS0")) tree "R5SS0_CORE0_TCMA_RAM" base ad:0x0 group.long 0x0++0x3 line.long 0x0 "R5SS0_CORE0_TCMA_RAM_RAM_START_TCMA" hexmask.long 0x0 0.--31. 1. "RAM_START,RAM start address of master sub system tcma" group.long 0x7FFC++0x3 line.long 0x0 "R5SS0_CORE0_TCMA_RAM_RAM_END_TCMA" hexmask.long 0x0 0.--31. 1. "RAM_END,RAM end address of master sub system tcma" tree.end endif sif (cpuis("AM263?-SS0")||cpuis("AM263?-SS1")) tree "R5SS0_CORE0_TCMB_RAM" base ad:0x80000 group.long 0x0++0x3 line.long 0x0 "R5SS0_CORE0_TCMB_RAM_RAM_START_TCMA" hexmask.long 0x0 0.--31. 1. "RAM_START,RAM start address of master sub system tcma" group.long 0x7FFC++0x3 line.long 0x0 "R5SS0_CORE0_TCMB_RAM_RAM_END_TCMA" hexmask.long 0x0 0.--31. 1. "RAM_END,RAM end address of master sub system tcma" tree.end endif tree "R5SS0_CCMR" base ad:0x53210000 group.long 0x0++0x17 line.long 0x0 "R5SS0_CCMR_CCMSR1" bitfld.long 0x0 16. "CMPE1,Compare Error0 = CPU signals are identical1= CPU signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x0 8. "STC1,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x0 1. "STET1,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" rbitfld.long 0x0 0. "STE1,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0x4 "R5SS0_CCMR_CCMKEYR1" hexmask.long.byte 0x4 0.--3. 1. "MKEY1,Mode Key0000 = lock step mode0110 = self test mode1001 = error forcing mode1111 = self test error forcing mode" line.long 0x8 "R5SS0_CCMR_CCMSR2" bitfld.long 0x8 16. "CMPE2,Compare Error0 = VIM signals are identical1= VIM signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x8 8. "STC2,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x8 1. "STET2,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" bitfld.long 0x8 0. "STE2,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0xC "R5SS0_CCMR_CCMKEYR2" hexmask.long.byte 0xC 0.--3. 1. "MKEY2,Mode Key0000 = lock step mode0110 = self test mode1001 = error forcing mode1111 = self test error forcing mode" line.long 0x10 "R5SS0_CCMR_CCMSR3" bitfld.long 0x10 16. "CMPE3,Compare Error0 = Inactivity monitor signals are identical1= Inactivity monitor signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x10 8. "STC3,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x10 1. "STET3,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" rbitfld.long 0x10 0. "STE3,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0x14 "R5SS0_CCMR_CCMKEYR3" hexmask.long.byte 0x14 0.--3. 1. "MKEY3,Mode Key0000 = lock step mode0110 = self test mode1001 = error forcing mode1111 = self test error forcing mode" rgroup.long 0x18++0x3 line.long 0x0 "R5SS0_CCMR_CCMPOLCNTRL" hexmask.long.byte 0x0 0.--7. 1. "POL_INV,This value is used to invert the 8 XOR of the CPU1 to create compare fail in functional active compare mode. User and privilege mode read = Returns current value of the POL INVPrivilege mode write = Update the values of POL INV" tree.end tree "R5SS0_CORE0_TCMA" base ad:0x78000000 group.long 0x0++0x3 line.long 0x0 "R5SS0_CORE0_TCMA_START" hexmask.long 0x0 0.--31. 1. "START,TCMA start address" group.long 0xFFFC++0x3 line.long 0x0 "R5SS0_CORE0_TCMA_END" hexmask.long 0x0 0.--31. 1. "END,TCMA end address" tree.end tree "R5SS0_CORE0_TCMB" base ad:0x78100000 group.long 0x0++0x3 line.long 0x0 "R5SS0_CORE0_TCMB_START" hexmask.long 0x0 0.--31. 1. "START,TCMB start address" group.long 0xFFFC++0x3 line.long 0x0 "R5SS0_CORE0_TCMB_END" hexmask.long 0x0 0.--31. 1. "END,TCMB end address" tree.end tree "R5SS0_CORE1_TCMA" base ad:0x78200000 group.long 0x0++0x3 line.long 0x0 "R5SS0_CORE1_TCMA_START" hexmask.long 0x0 0.--31. 1. "START,TCMA start address" group.long 0x7FFC++0x3 line.long 0x0 "R5SS0_CORE1_TCMA_END" hexmask.long 0x0 0.--31. 1. "END,TCMA end address" tree.end tree "R5SS0_CORE1_TCMB" base ad:0x78300000 group.long 0x0++0x3 line.long 0x0 "R5SS0_CORE1_TCMB_START" hexmask.long 0x0 0.--31. 1. "START,TCMB start address" group.long 0x7FFC++0x3 line.long 0x0 "R5SS0_CORE1_TCMB_END" hexmask.long 0x0 0.--31. 1. "END,TCMB end address" tree.end tree "R5SS0_STC" base ad:0x53500000 group.long 0x0++0xB line.long 0x0 "R5SS0_STC_STCGCR0" hexmask.long.word 0x0 16.--31. 1. "INTCOUNT_B16,Number of intervals of the self test run (RWP - Read Priviledge Mode Write only)Count of intervals that need to be covered for a specific selftest run.The selftest controller sends out ?complete? indication once it runs all of the intervals.." newline hexmask.long.byte 0x0 11.--15. 1. "NU0,Reserved bits" newline bitfld.long 0x0 8.--10. "CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only)Idle Cycles before and after capture clock. This value is used to insert that many idle cycles in the Capture phase. Programmable idle cycles allow.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5.--7. "SCANEN_HIGH_CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only). *NOT BYTE ACCESSIBLEIdle Cycles between scan_en going high to func_clk_en generation and scan_en going high to misr_log_en generation. This.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 2.--4. "NU1,Reserved bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--1. "RS_CNT_B1,Restart/Continue or preload (RWP - Read Priviledge Mode Write only)This bit specifies the selftest controller whether to continue the run from next interval onwards restart from ROM address 0 or preload from a prescribed interval. This bit.." "0: Continue NSTC run from previous interval01 =..,?,?,?" line.long 0x4 "R5SS0_STC_STCGCR1" hexmask.long.tbyte 0x4 12.--31. 1. "NU2,Reserved bits" newline hexmask.long.byte 0x4 8.--11. 1. "SEG0_CORE_SEL,Selects the Segment0 CORE for self test (RWP - Read Priviledge Mode Write only)Select the Segment0 CORE for Self -Test0001 = Select CORE for selftestOther = CORE not selected." newline rbitfld.long 0x4 7. "NU3,Reserved bits" "0,1" newline bitfld.long 0x4 6. "CODEC_SPREAD_MODE,Codec Spread Mode control signal (RWP - Read Priviledge Mode Write only)This bit is used to configure the codec in spread / X-OR mode.1 = Spread mode0 = XOR mode" "?,1: Spread mode0 = XOR mode" newline bitfld.long 0x4 5. "LP_SCAN_MODE,LP scan mode (RWP - Read Priviledge Mode Write only)This bit is used to decide the scan configuration:1 = Operates in Low Power Scan Mode. 0 = Operates in Normal Scan Mode." "0: Operates in Normal Scan Mode,1: Operates in Low Power Scan Mode" newline bitfld.long 0x4 4. "ROM_ACCESS_INV,Rom access inversion mode (RWP - Read Priviledge Mode Write only)- NOT SUPPORTED" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "ST_ENA_B4,Self test enable key (RWP - Read Priviledge Mode Write only)1010 = Self test run enabled All values other than 1010 = Self test run disabled" line.long 0x8 "R5SS0_STC_STCTPR" hexmask.long 0x8 0.--31. 1. "TO_PRELOAD,Self test time out preload (RWP - Read Priviledge Mode Write only)This register contains the total number of STC clock cycles it will take before a self-test timeout error will be triggered after the initiation of the self-test run. This is a.." rgroup.long 0xC++0xF line.long 0x0 "R5SS0_STC_STC_CADDR" hexmask.long 0x0 0.--31. 1. "ADDR,Current ROM Address for CORE1This register reflects the current ROM address (for micro code load) accessed during selftest for CORE1 in of case segment0 and all the remaining segmentsn where n = 1 to 3)." line.long 0x4 "R5SS0_STC_STCCICR" hexmask.long.word 0x4 16.--31. 1. "CORE2_ICOUNT,Specifies the last interval number for CORE2This specifies the Last executed Interval number for CORE2 of Segment0 if self test is being executed for secondary core as well. This field is applicable only for Segment 0." newline hexmask.long.word 0x4 0.--15. 1. "CORE1_ICOUNT,Specifies the last interval number for CORE1This specifies the Last executed Interval number of a self-test run." line.long 0x8 "R5SS0_STC_STCGSTAT" hexmask.long.tbyte 0x8 12.--31. 1. "NU4,Reserved bits" newline hexmask.long.byte 0x8 8.--11. 1. "ST_ACTIVE,Tells whether self test is currently active or not.1010 = Self test is activeOthers = SelfTest is not activeOnce the self-test completes and ST_ENA_B4 key is cleared this field will reflect the inactive value." newline hexmask.long.byte 0x8 2.--7. 1. "NU5,Reserved bits" newline bitfld.long 0x8 1. "TEST_FAIL,Test_fail flag (RCP - Read Clear on Writing in Priviledge Mode)0 = Self test run has not failed1 = SelfTest run has failed. Write Clear." "0: Self test run has not failed1 = SelfTest run has..,?" newline bitfld.long 0x8 0. "TEST_DONE,Test_done_flag (RCP - Read Clear on Writing in Priviledge Mode)0 = Not completed1 = SelfTest run Completed" "0: Not completed1 = SelfTest run Completed,?" line.long 0xC "R5SS0_STC_STCFSTAT" hexmask.long 0xC 5.--31. 1. "NU6,Reserved bits" newline bitfld.long 0xC 3.--4. "FSEG_ID,Failed Segment ID (RCP - Read Clear on Writing in Priviledge Mode)This field captures the Segment number for which any of the failures like TO_ER_B1 CPU1_FAIL_B1 and CPU2_FAIL_B1 occur.00 = Failure on Segment 001 = Failure on Segment 110.." "0: Failure on Segment,1: Failure on Segment,?,?" newline bitfld.long 0xC 2. "TO_ER_B1,Tells whether self test failed because of time out error (RCP - Read Clear on Writing in Priviledge Mode)0 = No time out error occurred1 = SelfTest run failed due to a timeout error" "0: No time out error occurred1 = SelfTest run..,?" newline bitfld.long 0xC 1. "CPU2_FAIL_B1,Tells whether MISR mismatch happenned in CORE2 when in Segment0 mode (RCP - Read Clear on Writing in Priviledge Mode)0 = No MISR mismatch for CORE21 = Self test run failed due to MISR mismatch for CORE2" "0: No MISR mismatch for CORE21 = Self test run..,?" newline bitfld.long 0xC 0. "CPU1_FAIL_B1,Tells whether MISR mismatch happenned in CORE1 (RCP - Read Clear on Writing in Priviledge Mode)Applicable to all segments.0 = No MISR mismatch for CORE11 = Self test run failed due to MISR mismatch for CORE1" "0: No MISR mismatch for CORE11 = Self test run..,?" group.long 0x1C++0x3 line.long 0x0 "R5SS0_STC_STCSCSCR" hexmask.long 0x0 5.--31. 1. "NU7,Reserved bits" newline bitfld.long 0x0 4. "FAULT_INS_B1,Fault Insertion bit (RWP - Read Priviledge Mode Write only)0 = No fault insertion.1 = Inserts fault in the logic unedr test which will make signature compare fail. This feature is used as diagnostic check of the STC IP." "0: No fault insertion,1: Inserts fault in the logic unedr test which will.." newline hexmask.long.byte 0x0 0.--3. 1. "SELF_CHECK_KEY_B4,Signature compare logic self check key enable/disable (RWP - Read Priviledge Mode Write only)1010 = Signature compare logic Self Check is enabledAll values other than 1010 = Signature compare logic Self Check is disabled" rgroup.long 0x20++0x3 line.long 0x0 "R5SS0_STC_STC_CADDR2" hexmask.long 0x0 0.--31. 1. "ADDR,Current ROM Address for CORE2This register reflects the current ROM address(for micro code load) accessed during selftest for CORE2 in of case segment0." group.long 0x24++0x17 line.long 0x0 "R5SS0_STC_STC_CLKDIV" hexmask.long.byte 0x0 27.--31. 1. "NU8,Reserved bits" newline bitfld.long 0x0 24.--26. "CLKDIV0,Clock division for Seg0 (RWP - Read Priviledge Mode Write only)*NOT SUPPORTEDX = Division ratio is X+1 for Segment 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 19.--23. 1. "NU9,Reserved bits" newline bitfld.long 0x0 16.--18. "CLKDIV1,Clock division for Seg1 (RWP - Read Priviledge Mode Write only)*NOT SUPPORTEDX = Division ratio is X+1 for Segment 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 11.--15. 1. "NU10,Reserved bits" newline bitfld.long 0x0 8.--10. "CLKDIV2,Clock division for Seg2 (RWP - Read Priviledge Mode Write only)*NOT SUPPORTEDX = Division ratio is X+1 for Segment 2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "NU11,Reserved bits" newline bitfld.long 0x0 0.--2. "CLKDIV3,Clock division for Seg3 (RWP - Read Priviledge Mode Write only)*NOT SUPPORTEDX = Division ratio is X+1 for Segment 3" "0,1,2,3,4,5,6,7" line.long 0x4 "R5SS0_STC_STC_SEGPLR" hexmask.long 0x4 2.--31. 1. "NU12,Reserved bits" newline bitfld.long 0x4 0.--1. "SEGID_PLOAD,Segment number for which preload is to be started (RWP - Read Priviledge Mode Write only)This specifies the segment for which the address of its First interval will be pre-loaded into the NSTC ROM address counter. The 1st address of each.." "?,1: Preload the address of the 1st interval of..,?,?" line.long 0x8 "R5SS0_STC_SEG0_START_ADDR" hexmask.long.word 0x8 20.--31. 1. "NU13,Reserved bits" newline hexmask.long.tbyte 0x8 0.--19. 1. "SEG_START_ADDR,Segment 0 Start Address (RWP - Read Priviledge Mode Write only)This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to (1x) ?PRELOAD? option this register is used to.." line.long 0xC "R5SS0_STC_SEG1_START_ADDR" hexmask.long.word 0xC 20.--31. 1. "NU14,Reserved bits" newline hexmask.long.tbyte 0xC 0.--19. 1. "SEG_START_ADDR,Segment 1 Start Address (RWP - Read Priviledge Mode Write only)This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to (1x) ?PRELOAD? option this register is used to.." line.long 0x10 "R5SS0_STC_SEG2_START_ADDR" hexmask.long.word 0x10 20.--31. 1. "NU15,Reserved bits" newline hexmask.long.tbyte 0x10 0.--19. 1. "SEG_START_ADDR,Segment 2 Start Address (RWP - Read Priviledge Mode Write only)This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to (1x) ?PRELOAD? option this register is used to.." line.long 0x14 "R5SS0_STC_SEG3_START_ADDR" hexmask.long.word 0x14 20.--31. 1. "NU16,Reserved bits" newline hexmask.long.tbyte 0x14 0.--19. 1. "SEG_START_ADDR,Segment 3 Start Address (RWP - Read Priviledge Mode Write only)This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to (1x) ?PRELOAD? option this register is used to.." rgroup.long 0x3C++0xDF line.long 0x0 "R5SS0_STC_CORE1_CURMISR_0" hexmask.long 0x0 0.--31. 1. "C1MISR0,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x4 "R5SS0_STC_CORE1_CURMISR_1" hexmask.long 0x4 0.--31. 1. "C1MISR1,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x8 "R5SS0_STC_CORE1_CURMISR_2" hexmask.long 0x8 0.--31. 1. "C1MISR2,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0xC "R5SS0_STC_CORE1_CURMISR_3" hexmask.long 0xC 0.--31. 1. "C1MISR3,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x10 "R5SS0_STC_CORE1_CURMISR_4" hexmask.long 0x10 0.--31. 1. "C1MISR4,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x14 "R5SS0_STC_CORE1_CURMISR_5" hexmask.long 0x14 0.--31. 1. "C1MISR5,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x18 "R5SS0_STC_CORE1_CURMISR_6" hexmask.long 0x18 0.--31. 1. "C1MISR6,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x1C "R5SS0_STC_CORE1_CURMISR_7" hexmask.long 0x1C 0.--31. 1. "C1MISR7,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x20 "R5SS0_STC_CORE1_CURMISR_8" hexmask.long 0x20 0.--31. 1. "C1MISR8,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x24 "R5SS0_STC_CORE1_CURMISR_9" hexmask.long 0x24 0.--31. 1. "C1MISR9,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x28 "R5SS0_STC_CORE1_CURMISR_10" hexmask.long 0x28 0.--31. 1. "C1MISR10,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x2C "R5SS0_STC_CORE1_CURMISR_11" hexmask.long 0x2C 0.--31. 1. "C1MISR11,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x30 "R5SS0_STC_CORE1_CURMISR_12" hexmask.long 0x30 0.--31. 1. "C1MISR12,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x34 "R5SS0_STC_CORE1_CURMISR_13" hexmask.long 0x34 0.--31. 1. "C1MISR13,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x38 "R5SS0_STC_CORE1_CURMISR_14" hexmask.long 0x38 0.--31. 1. "C1MISR14,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x3C "R5SS0_STC_CORE1_CURMISR_15" hexmask.long 0x3C 0.--31. 1. "C1MISR15,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x40 "R5SS0_STC_CORE1_CURMISR_16" hexmask.long 0x40 0.--31. 1. "C1MISR16,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x44 "R5SS0_STC_CORE1_CURMISR_17" hexmask.long 0x44 0.--31. 1. "C1MISR17,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x48 "R5SS0_STC_CORE1_CURMISR_18" hexmask.long 0x48 0.--31. 1. "C1MISR18,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x4C "R5SS0_STC_CORE1_CURMISR_19" hexmask.long 0x4C 0.--31. 1. "C1MISR19,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x50 "R5SS0_STC_CORE1_CURMISR_20" hexmask.long 0x50 0.--31. 1. "C1MISR20,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x54 "R5SS0_STC_CORE1_CURMISR_21" hexmask.long 0x54 0.--31. 1. "C1MISR21,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x58 "R5SS0_STC_CORE1_CURMISR_22" hexmask.long 0x58 0.--31. 1. "C1MISR22,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x5C "R5SS0_STC_CORE1_CURMISR_23" hexmask.long 0x5C 0.--31. 1. "C1MISR23,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x60 "R5SS0_STC_CORE1_CURMISR_24" hexmask.long 0x60 0.--31. 1. "C1MISR24,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x64 "R5SS0_STC_CORE1_CURMISR_25" hexmask.long 0x64 0.--31. 1. "C1MISR25,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x68 "R5SS0_STC_CORE1_CURMISR_26" hexmask.long 0x68 0.--31. 1. "C1MISR26,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x6C "R5SS0_STC_CORE1_CURMISR_27" hexmask.long 0x6C 0.--31. 1. "C1MISR27,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x70 "R5SS0_STC_CORE2_CURMISR_0" hexmask.long 0x70 0.--31. 1. "C2MISR0,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x74 "R5SS0_STC_CORE2_CURMISR_1" hexmask.long 0x74 0.--31. 1. "C2MISR1,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x78 "R5SS0_STC_CORE2_CURMISR_2" hexmask.long 0x78 0.--31. 1. "C2MISR2,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x7C "R5SS0_STC_CORE2_CURMISR_3" hexmask.long 0x7C 0.--31. 1. "C2MISR3,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x80 "R5SS0_STC_CORE2_CURMISR_4" hexmask.long 0x80 0.--31. 1. "C2MISR4,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x84 "R5SS0_STC_CORE2_CURMISR_5" hexmask.long 0x84 0.--31. 1. "C2MISR5,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x88 "R5SS0_STC_CORE2_CURMISR_6" hexmask.long 0x88 0.--31. 1. "C2MISR6,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x8C "R5SS0_STC_CORE2_CURMISR_7" hexmask.long 0x8C 0.--31. 1. "C2MISR7,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x90 "R5SS0_STC_CORE2_CURMISR_8" hexmask.long 0x90 0.--31. 1. "C2MISR8,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x94 "R5SS0_STC_CORE2_CURMISR_9" hexmask.long 0x94 0.--31. 1. "C2MISR9,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x98 "R5SS0_STC_CORE2_CURMISR_10" hexmask.long 0x98 0.--31. 1. "C2MISR10,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x9C "R5SS0_STC_CORE2_CURMISR_11" hexmask.long 0x9C 0.--31. 1. "C2MISR11,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xA0 "R5SS0_STC_CORE2_CURMISR_12" hexmask.long 0xA0 0.--31. 1. "C2MISR12,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xA4 "R5SS0_STC_CORE2_CURMISR_13" hexmask.long 0xA4 0.--31. 1. "C2MISR13,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xA8 "R5SS0_STC_CORE2_CURMISR_14" hexmask.long 0xA8 0.--31. 1. "C2MISR14,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xAC "R5SS0_STC_CORE2_CURMISR_15" hexmask.long 0xAC 0.--31. 1. "C2MISR15,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xB0 "R5SS0_STC_CORE2_CURMISR_16" hexmask.long 0xB0 0.--31. 1. "C2MISR16,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xB4 "R5SS0_STC_CORE2_CURMISR_17" hexmask.long 0xB4 0.--31. 1. "C2MISR17,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xB8 "R5SS0_STC_CORE2_CURMISR_18" hexmask.long 0xB8 0.--31. 1. "C2MISR18,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xBC "R5SS0_STC_CORE2_CURMISR_19" hexmask.long 0xBC 0.--31. 1. "C2MISR19,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xC0 "R5SS0_STC_CORE2_CURMISR_20" hexmask.long 0xC0 0.--31. 1. "C2MISR20,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xC4 "R5SS0_STC_CORE2_CURMISR_21" hexmask.long 0xC4 0.--31. 1. "C2MISR21,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xC8 "R5SS0_STC_CORE2_CURMISR_22" hexmask.long 0xC8 0.--31. 1. "C2MISR22,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xCC "R5SS0_STC_CORE2_CURMISR_23" hexmask.long 0xCC 0.--31. 1. "C2MISR23,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xD0 "R5SS0_STC_CORE2_CURMISR_24" hexmask.long 0xD0 0.--31. 1. "C2MISR24,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xD4 "R5SS0_STC_CORE2_CURMISR_25" hexmask.long 0xD4 0.--31. 1. "C2MISR25,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xD8 "R5SS0_STC_CORE2_CURMISR_26" hexmask.long 0xD8 0.--31. 1. "C2MISR26,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xDC "R5SS0_STC_CORE2_CURMISR_27" hexmask.long 0xDC 0.--31. 1. "C2MISR27,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." tree.end sif (cpuis("AM263?-SS0")||cpuis("AM263?-SS1")) tree "R5SS0_CORE0_TCMA_ROM" base ad:0x0 rgroup.long 0x0++0x3 line.long 0x0 "R5SS0_CORE0_TCMA_ROM_ROM_START_TCMA" hexmask.long 0x0 0.--31. 1. "ROM_START,ROM start address of master sub system tcma" rgroup.long 0x1FFFC++0x3 line.long 0x0 "R5SS0_CORE0_TCMA_ROM_ROM_END_TCMA" hexmask.long 0x0 0.--31. 1. "ROM_END,ROM end address of master sub system tcma" tree.end endif sif (cpuis("AM263?-SS0")||cpuis("AM263?-SS1")) tree "R5SS0_CORE0_TCMA_RAM" base ad:0x20000 group.long 0x0++0x3 line.long 0x0 "R5SS0_CORE0_TCMA_RAM_RAM_START_TCMA" hexmask.long 0x0 0.--31. 1. "RAM_START,RAM start address of master sub system tcma" group.long 0x7FFC++0x3 line.long 0x0 "R5SS0_CORE0_TCMA_RAM_RAM_END_TCMA" hexmask.long 0x0 0.--31. 1. "RAM_END,RAM end address of master sub system tcma" tree.end endif tree.end tree "R5SS1" tree "R5SS1_CCMR" base ad:0x53211000 group.long 0x0++0x17 line.long 0x0 "R5SS1_CCMR_CCMSR1" bitfld.long 0x0 16. "CMPE1,Compare Error0 = CPU signals are identical1= CPU signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x0 8. "STC1,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x0 1. "STET1,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" rbitfld.long 0x0 0. "STE1,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0x4 "R5SS1_CCMR_CCMKEYR1" hexmask.long.byte 0x4 0.--3. 1. "MKEY1,Mode Key0000 = lock step mode0110 = self test mode1001 = error forcing mode1111 = self test error forcing mode" line.long 0x8 "R5SS1_CCMR_CCMSR2" bitfld.long 0x8 16. "CMPE2,Compare Error0 = VIM signals are identical1= VIM signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x8 8. "STC2,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x8 1. "STET2,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" bitfld.long 0x8 0. "STE2,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0xC "R5SS1_CCMR_CCMKEYR2" hexmask.long.byte 0xC 0.--3. 1. "MKEY2,Mode Key0000 = lock step mode0110 = self test mode1001 = error forcing mode1111 = self test error forcing mode" line.long 0x10 "R5SS1_CCMR_CCMSR3" bitfld.long 0x10 16. "CMPE3,Compare Error0 = Inactivity monitor signals are identical1= Inactivity monitor signal compare mismatchWrites '1' to clear this bit" "0,1" bitfld.long 0x10 8. "STC3,Self Test Complete0 = self test on-going if self test mode asserted1 = self test is completeWrites have no effect" "0,1" bitfld.long 0x10 1. "STET3,Self Test Error Type0 = self test failed during Compare Match test1 = self test failed during Compare mismatch testWrites have no effect" "0,1" rbitfld.long 0x10 0. "STE3,Self Test Error0 = self test passed1 = self test failedWrites have no effect" "0,1" line.long 0x14 "R5SS1_CCMR_CCMKEYR3" hexmask.long.byte 0x14 0.--3. 1. "MKEY3,Mode Key0000 = lock step mode0110 = self test mode1001 = error forcing mode1111 = self test error forcing mode" rgroup.long 0x18++0x3 line.long 0x0 "R5SS1_CCMR_CCMPOLCNTRL" hexmask.long.byte 0x0 0.--7. 1. "POL_INV,This value is used to invert the 8 XOR of the CPU1 to create compare fail in functional active compare mode. User and privilege mode read = Returns current value of the POL INVPrivilege mode write = Update the values of POL INV" tree.end tree "R5SS1_CORE0_TCMA" base ad:0x78400000 group.long 0x0++0x3 line.long 0x0 "R5SS1_CORE0_TCMA_START" hexmask.long 0x0 0.--31. 1. "START,TCMA start address" group.long 0xFFFC++0x3 line.long 0x0 "R5SS1_CORE0_TCMA_END" hexmask.long 0x0 0.--31. 1. "END,TCMA end address" tree.end tree "R5SS1_CORE0_TCMB" base ad:0x78500000 group.long 0x0++0x3 line.long 0x0 "R5SS1_CORE0_TCMB_START" hexmask.long 0x0 0.--31. 1. "START,TCMB start address" group.long 0xFFFC++0x3 line.long 0x0 "R5SS1_CORE0_TCMB_END" hexmask.long 0x0 0.--31. 1. "END,TCMB end address" tree.end tree "R5SS1_CORE1_TCMA" base ad:0x78600000 group.long 0x0++0x3 line.long 0x0 "R5SS1_CORE1_TCMA_START" hexmask.long 0x0 0.--31. 1. "START,TCMA start address" group.long 0x7FFC++0x3 line.long 0x0 "R5SS1_CORE1_TCMA_END" hexmask.long 0x0 0.--31. 1. "END,TCMA end address" tree.end tree "R5SS1_CORE1_TCMB" base ad:0x78700000 group.long 0x0++0x3 line.long 0x0 "R5SS1_CORE1_TCMB_START" hexmask.long 0x0 0.--31. 1. "START,TCMB start address" group.long 0x7FFC++0x3 line.long 0x0 "R5SS1_CORE1_TCMB_END" hexmask.long 0x0 0.--31. 1. "END,TCMB end address" tree.end tree "R5SS1_STC" base ad:0x53510000 group.long 0x0++0xB line.long 0x0 "R5SS1_STC_STCGCR0" hexmask.long.word 0x0 16.--31. 1. "INTCOUNT_B16,Number of intervals of the self test run (RWP - Read Priviledge Mode Write only)Count of intervals that need to be covered for a specific selftest run.The selftest controller sends out ?complete? indication once it runs all of the intervals.." newline hexmask.long.byte 0x0 11.--15. 1. "NU0,Reserved bits" newline bitfld.long 0x0 8.--10. "CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only)Idle Cycles before and after capture clock. This value is used to insert that many idle cycles in the Capture phase. Programmable idle cycles allow.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5.--7. "SCANEN_HIGH_CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only). *NOT BYTE ACCESSIBLEIdle Cycles between scan_en going high to func_clk_en generation and scan_en going high to misr_log_en generation. This.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 2.--4. "NU1,Reserved bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--1. "RS_CNT_B1,Restart/Continue or preload (RWP - Read Priviledge Mode Write only)This bit specifies the selftest controller whether to continue the run from next interval onwards restart from ROM address 0 or preload from a prescribed interval. This bit.." "0: Continue NSTC run from previous interval01 =..,?,?,?" line.long 0x4 "R5SS1_STC_STCGCR1" hexmask.long.tbyte 0x4 12.--31. 1. "NU2,Reserved bits" newline hexmask.long.byte 0x4 8.--11. 1. "SEG0_CORE_SEL,Selects the Segment0 CORE for self test (RWP - Read Priviledge Mode Write only)Select the Segment0 CORE for Self -Test0001 = Select CORE for selftestOther = CORE not selected." newline rbitfld.long 0x4 7. "NU3,Reserved bits" "0,1" newline bitfld.long 0x4 6. "CODEC_SPREAD_MODE,Codec Spread Mode control signal (RWP - Read Priviledge Mode Write only)This bit is used to configure the codec in spread / X-OR mode.1 = Spread mode0 = XOR mode" "?,1: Spread mode0 = XOR mode" newline bitfld.long 0x4 5. "LP_SCAN_MODE,LP scan mode (RWP - Read Priviledge Mode Write only)This bit is used to decide the scan configuration:1 = Operates in Low Power Scan Mode. 0 = Operates in Normal Scan Mode." "0: Operates in Normal Scan Mode,1: Operates in Low Power Scan Mode" newline bitfld.long 0x4 4. "ROM_ACCESS_INV,Rom access inversion mode (RWP - Read Priviledge Mode Write only)- NOT SUPPORTED" "0,1" newline hexmask.long.byte 0x4 0.--3. 1. "ST_ENA_B4,Self test enable key (RWP - Read Priviledge Mode Write only)1010 = Self test run enabled All values other than 1010 = Self test run disabled" line.long 0x8 "R5SS1_STC_STCTPR" hexmask.long 0x8 0.--31. 1. "TO_PRELOAD,Self test time out preload (RWP - Read Priviledge Mode Write only)This register contains the total number of STC clock cycles it will take before a self-test timeout error will be triggered after the initiation of the self-test run. This is a.." rgroup.long 0xC++0xF line.long 0x0 "R5SS1_STC_STC_CADDR" hexmask.long 0x0 0.--31. 1. "ADDR,Current ROM Address for CORE1This register reflects the current ROM address (for micro code load) accessed during selftest for CORE1 in of case segment0 and all the remaining segmentsn where n = 1 to 3)." line.long 0x4 "R5SS1_STC_STCCICR" hexmask.long.word 0x4 16.--31. 1. "CORE2_ICOUNT,Specifies the last interval number for CORE2This specifies the Last executed Interval number for CORE2 of Segment0 if self test is being executed for secondary core as well. This field is applicable only for Segment 0." newline hexmask.long.word 0x4 0.--15. 1. "CORE1_ICOUNT,Specifies the last interval number for CORE1This specifies the Last executed Interval number of a self-test run." line.long 0x8 "R5SS1_STC_STCGSTAT" hexmask.long.tbyte 0x8 12.--31. 1. "NU4,Reserved bits" newline hexmask.long.byte 0x8 8.--11. 1. "ST_ACTIVE,Tells whether self test is currently active or not.1010 = Self test is activeOthers = SelfTest is not activeOnce the self-test completes and ST_ENA_B4 key is cleared this field will reflect the inactive value." newline hexmask.long.byte 0x8 2.--7. 1. "NU5,Reserved bits" newline bitfld.long 0x8 1. "TEST_FAIL,Test_fail flag (RCP - Read Clear on Writing in Priviledge Mode)0 = Self test run has not failed1 = SelfTest run has failed. Write Clear." "0: Self test run has not failed1 = SelfTest run has..,?" newline bitfld.long 0x8 0. "TEST_DONE,Test_done_flag (RCP - Read Clear on Writing in Priviledge Mode)0 = Not completed1 = SelfTest run Completed" "0: Not completed1 = SelfTest run Completed,?" line.long 0xC "R5SS1_STC_STCFSTAT" hexmask.long 0xC 5.--31. 1. "NU6,Reserved bits" newline bitfld.long 0xC 3.--4. "FSEG_ID,Failed Segment ID (RCP - Read Clear on Writing in Priviledge Mode)This field captures the Segment number for which any of the failures like TO_ER_B1 CPU1_FAIL_B1 and CPU2_FAIL_B1 occur.00 = Failure on Segment 001 = Failure on Segment 110.." "0: Failure on Segment,1: Failure on Segment,?,?" newline bitfld.long 0xC 2. "TO_ER_B1,Tells whether self test failed because of time out error (RCP - Read Clear on Writing in Priviledge Mode)0 = No time out error occurred1 = SelfTest run failed due to a timeout error" "0: No time out error occurred1 = SelfTest run..,?" newline bitfld.long 0xC 1. "CPU2_FAIL_B1,Tells whether MISR mismatch happenned in CORE2 when in Segment0 mode (RCP - Read Clear on Writing in Priviledge Mode)0 = No MISR mismatch for CORE21 = Self test run failed due to MISR mismatch for CORE2" "0: No MISR mismatch for CORE21 = Self test run..,?" newline bitfld.long 0xC 0. "CPU1_FAIL_B1,Tells whether MISR mismatch happenned in CORE1 (RCP - Read Clear on Writing in Priviledge Mode)Applicable to all segments.0 = No MISR mismatch for CORE11 = Self test run failed due to MISR mismatch for CORE1" "0: No MISR mismatch for CORE11 = Self test run..,?" group.long 0x1C++0x3 line.long 0x0 "R5SS1_STC_STCSCSCR" hexmask.long 0x0 5.--31. 1. "NU7,Reserved bits" newline bitfld.long 0x0 4. "FAULT_INS_B1,Fault Insertion bit (RWP - Read Priviledge Mode Write only)0 = No fault insertion.1 = Inserts fault in the logic unedr test which will make signature compare fail. This feature is used as diagnostic check of the STC IP." "0: No fault insertion,1: Inserts fault in the logic unedr test which will.." newline hexmask.long.byte 0x0 0.--3. 1. "SELF_CHECK_KEY_B4,Signature compare logic self check key enable/disable (RWP - Read Priviledge Mode Write only)1010 = Signature compare logic Self Check is enabledAll values other than 1010 = Signature compare logic Self Check is disabled" rgroup.long 0x20++0x3 line.long 0x0 "R5SS1_STC_STC_CADDR2" hexmask.long 0x0 0.--31. 1. "ADDR,Current ROM Address for CORE2This register reflects the current ROM address(for micro code load) accessed during selftest for CORE2 in of case segment0." group.long 0x24++0x17 line.long 0x0 "R5SS1_STC_STC_CLKDIV" hexmask.long.byte 0x0 27.--31. 1. "NU8,Reserved bits" newline bitfld.long 0x0 24.--26. "CLKDIV0,Clock division for Seg0 (RWP - Read Priviledge Mode Write only)*NOT SUPPORTEDX = Division ratio is X+1 for Segment 0" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 19.--23. 1. "NU9,Reserved bits" newline bitfld.long 0x0 16.--18. "CLKDIV1,Clock division for Seg1 (RWP - Read Priviledge Mode Write only)*NOT SUPPORTEDX = Division ratio is X+1 for Segment 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 11.--15. 1. "NU10,Reserved bits" newline bitfld.long 0x0 8.--10. "CLKDIV2,Clock division for Seg2 (RWP - Read Priviledge Mode Write only)*NOT SUPPORTEDX = Division ratio is X+1 for Segment 2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "NU11,Reserved bits" newline bitfld.long 0x0 0.--2. "CLKDIV3,Clock division for Seg3 (RWP - Read Priviledge Mode Write only)*NOT SUPPORTEDX = Division ratio is X+1 for Segment 3" "0,1,2,3,4,5,6,7" line.long 0x4 "R5SS1_STC_STC_SEGPLR" hexmask.long 0x4 2.--31. 1. "NU12,Reserved bits" newline bitfld.long 0x4 0.--1. "SEGID_PLOAD,Segment number for which preload is to be started (RWP - Read Priviledge Mode Write only)This specifies the segment for which the address of its First interval will be pre-loaded into the NSTC ROM address counter. The 1st address of each.." "?,1: Preload the address of the 1st interval of..,?,?" line.long 0x8 "R5SS1_STC_SEG0_START_ADDR" hexmask.long.word 0x8 20.--31. 1. "NU13,Reserved bits" newline hexmask.long.tbyte 0x8 0.--19. 1. "SEG_START_ADDR,Segment 0 Start Address (RWP - Read Priviledge Mode Write only)This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to (1x) ?PRELOAD? option this register is used to.." line.long 0xC "R5SS1_STC_SEG1_START_ADDR" hexmask.long.word 0xC 20.--31. 1. "NU14,Reserved bits" newline hexmask.long.tbyte 0xC 0.--19. 1. "SEG_START_ADDR,Segment 1 Start Address (RWP - Read Priviledge Mode Write only)This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to (1x) ?PRELOAD? option this register is used to.." line.long 0x10 "R5SS1_STC_SEG2_START_ADDR" hexmask.long.word 0x10 20.--31. 1. "NU15,Reserved bits" newline hexmask.long.tbyte 0x10 0.--19. 1. "SEG_START_ADDR,Segment 2 Start Address (RWP - Read Priviledge Mode Write only)This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to (1x) ?PRELOAD? option this register is used to.." line.long 0x14 "R5SS1_STC_SEG3_START_ADDR" hexmask.long.word 0x14 20.--31. 1. "NU16,Reserved bits" newline hexmask.long.tbyte 0x14 0.--19. 1. "SEG_START_ADDR,Segment 3 Start Address (RWP - Read Priviledge Mode Write only)This register holds the ROM address for the start of first interval of the segment.When STC_GCR0.RS_CNT_B1 field is set to (1x) ?PRELOAD? option this register is used to.." rgroup.long 0x3C++0xDF line.long 0x0 "R5SS1_STC_CORE1_CURMISR_0" hexmask.long 0x0 0.--31. 1. "C1MISR0,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x4 "R5SS1_STC_CORE1_CURMISR_1" hexmask.long 0x4 0.--31. 1. "C1MISR1,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x8 "R5SS1_STC_CORE1_CURMISR_2" hexmask.long 0x8 0.--31. 1. "C1MISR2,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0xC "R5SS1_STC_CORE1_CURMISR_3" hexmask.long 0xC 0.--31. 1. "C1MISR3,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x10 "R5SS1_STC_CORE1_CURMISR_4" hexmask.long 0x10 0.--31. 1. "C1MISR4,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x14 "R5SS1_STC_CORE1_CURMISR_5" hexmask.long 0x14 0.--31. 1. "C1MISR5,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x18 "R5SS1_STC_CORE1_CURMISR_6" hexmask.long 0x18 0.--31. 1. "C1MISR6,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x1C "R5SS1_STC_CORE1_CURMISR_7" hexmask.long 0x1C 0.--31. 1. "C1MISR7,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x20 "R5SS1_STC_CORE1_CURMISR_8" hexmask.long 0x20 0.--31. 1. "C1MISR8,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x24 "R5SS1_STC_CORE1_CURMISR_9" hexmask.long 0x24 0.--31. 1. "C1MISR9,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x28 "R5SS1_STC_CORE1_CURMISR_10" hexmask.long 0x28 0.--31. 1. "C1MISR10,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x2C "R5SS1_STC_CORE1_CURMISR_11" hexmask.long 0x2C 0.--31. 1. "C1MISR11,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x30 "R5SS1_STC_CORE1_CURMISR_12" hexmask.long 0x30 0.--31. 1. "C1MISR12,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x34 "R5SS1_STC_CORE1_CURMISR_13" hexmask.long 0x34 0.--31. 1. "C1MISR13,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x38 "R5SS1_STC_CORE1_CURMISR_14" hexmask.long 0x38 0.--31. 1. "C1MISR14,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x3C "R5SS1_STC_CORE1_CURMISR_15" hexmask.long 0x3C 0.--31. 1. "C1MISR15,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x40 "R5SS1_STC_CORE1_CURMISR_16" hexmask.long 0x40 0.--31. 1. "C1MISR16,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x44 "R5SS1_STC_CORE1_CURMISR_17" hexmask.long 0x44 0.--31. 1. "C1MISR17,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x48 "R5SS1_STC_CORE1_CURMISR_18" hexmask.long 0x48 0.--31. 1. "C1MISR18,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x4C "R5SS1_STC_CORE1_CURMISR_19" hexmask.long 0x4C 0.--31. 1. "C1MISR19,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x50 "R5SS1_STC_CORE1_CURMISR_20" hexmask.long 0x50 0.--31. 1. "C1MISR20,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x54 "R5SS1_STC_CORE1_CURMISR_21" hexmask.long 0x54 0.--31. 1. "C1MISR21,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x58 "R5SS1_STC_CORE1_CURMISR_22" hexmask.long 0x58 0.--31. 1. "C1MISR22,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x5C "R5SS1_STC_CORE1_CURMISR_23" hexmask.long 0x5C 0.--31. 1. "C1MISR23,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x60 "R5SS1_STC_CORE1_CURMISR_24" hexmask.long 0x60 0.--31. 1. "C1MISR24,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x64 "R5SS1_STC_CORE1_CURMISR_25" hexmask.long 0x64 0.--31. 1. "C1MISR25,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x68 "R5SS1_STC_CORE1_CURMISR_26" hexmask.long 0x68 0.--31. 1. "C1MISR26,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x6C "R5SS1_STC_CORE1_CURMISR_27" hexmask.long 0x6C 0.--31. 1. "C1MISR27,MISR Signature for CORE1This register contains the MISR data of the current interval for CORE1 in the case of segment0 and the remaining Segments 1 to 3. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets.." line.long 0x70 "R5SS1_STC_CORE2_CURMISR_0" hexmask.long 0x70 0.--31. 1. "C2MISR0,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x74 "R5SS1_STC_CORE2_CURMISR_1" hexmask.long 0x74 0.--31. 1. "C2MISR1,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x78 "R5SS1_STC_CORE2_CURMISR_2" hexmask.long 0x78 0.--31. 1. "C2MISR2,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x7C "R5SS1_STC_CORE2_CURMISR_3" hexmask.long 0x7C 0.--31. 1. "C2MISR3,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x80 "R5SS1_STC_CORE2_CURMISR_4" hexmask.long 0x80 0.--31. 1. "C2MISR4,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x84 "R5SS1_STC_CORE2_CURMISR_5" hexmask.long 0x84 0.--31. 1. "C2MISR5,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x88 "R5SS1_STC_CORE2_CURMISR_6" hexmask.long 0x88 0.--31. 1. "C2MISR6,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x8C "R5SS1_STC_CORE2_CURMISR_7" hexmask.long 0x8C 0.--31. 1. "C2MISR7,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x90 "R5SS1_STC_CORE2_CURMISR_8" hexmask.long 0x90 0.--31. 1. "C2MISR8,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x94 "R5SS1_STC_CORE2_CURMISR_9" hexmask.long 0x94 0.--31. 1. "C2MISR9,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x98 "R5SS1_STC_CORE2_CURMISR_10" hexmask.long 0x98 0.--31. 1. "C2MISR10,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0x9C "R5SS1_STC_CORE2_CURMISR_11" hexmask.long 0x9C 0.--31. 1. "C2MISR11,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xA0 "R5SS1_STC_CORE2_CURMISR_12" hexmask.long 0xA0 0.--31. 1. "C2MISR12,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xA4 "R5SS1_STC_CORE2_CURMISR_13" hexmask.long 0xA4 0.--31. 1. "C2MISR13,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xA8 "R5SS1_STC_CORE2_CURMISR_14" hexmask.long 0xA8 0.--31. 1. "C2MISR14,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xAC "R5SS1_STC_CORE2_CURMISR_15" hexmask.long 0xAC 0.--31. 1. "C2MISR15,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xB0 "R5SS1_STC_CORE2_CURMISR_16" hexmask.long 0xB0 0.--31. 1. "C2MISR16,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xB4 "R5SS1_STC_CORE2_CURMISR_17" hexmask.long 0xB4 0.--31. 1. "C2MISR17,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xB8 "R5SS1_STC_CORE2_CURMISR_18" hexmask.long 0xB8 0.--31. 1. "C2MISR18,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xBC "R5SS1_STC_CORE2_CURMISR_19" hexmask.long 0xBC 0.--31. 1. "C2MISR19,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xC0 "R5SS1_STC_CORE2_CURMISR_20" hexmask.long 0xC0 0.--31. 1. "C2MISR20,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xC4 "R5SS1_STC_CORE2_CURMISR_21" hexmask.long 0xC4 0.--31. 1. "C2MISR21,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xC8 "R5SS1_STC_CORE2_CURMISR_22" hexmask.long 0xC8 0.--31. 1. "C2MISR22,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xCC "R5SS1_STC_CORE2_CURMISR_23" hexmask.long 0xCC 0.--31. 1. "C2MISR23,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xD0 "R5SS1_STC_CORE2_CURMISR_24" hexmask.long 0xD0 0.--31. 1. "C2MISR24,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xD4 "R5SS1_STC_CORE2_CURMISR_25" hexmask.long 0xD4 0.--31. 1. "C2MISR25,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xD8 "R5SS1_STC_CORE2_CURMISR_26" hexmask.long 0xD8 0.--31. 1. "C2MISR26,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." line.long 0xDC "R5SS1_STC_CORE2_CURMISR_27" hexmask.long 0xDC 0.--31. 1. "C2MISR27,MISR Signature for CORE2This register contains the MISR data from the CORE2 for the current interval. This is applicable to Segment 0 alone. This value will be compared with the GOLDEN MISR value copied from ROM. This register gets reset to its.." tree.end tree.end tree.end tree "RTI" base ad:0x0 tree "RTI0" base ad:0x52180000 group.long 0x0++0x1B line.long 0x0 "RTI0_RTIGCTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode (read):0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "RTI0_RTITBCTRL" bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode (read):0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "RTI0_RTICAPCTRL" hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "RTI0_RTICOMPCTRL" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "RTI0_RTIFRC0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x14 "RTI0_RTIUC0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI0_RTICPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "RTI0_RTICAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 0 on.." line.long 0x4 "RTI0_RTICAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "RTI0_RTIFRC1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x4 "RTI0_RTIUC1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI0_RTICPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "RTI0_RTICAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 1 on.." line.long 0x4 "RTI0_RTICAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "RTI0_RTICOMP0" hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "RTI0_RTIUDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "RTI0_RTICOMP1" hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "RTI0_RTIUDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "RTI0_RTICOMP2" hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "RTI0_RTIUDCP2" hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "RTI0_RTICOMP3" hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "RTI0_RTIUDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "RTI0_RTITBLCOMP" hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode (read):current compare valuePrivilege mode (write when.." line.long 0x24 "RTI0_RTITBHCOMP" hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "RTI0_RTISETINT" hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "RTI0_RTICLEARINT" hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "RTI0_RTIINTFLAG" hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read):this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "RTI0_RTIDWDCTRL" hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode (read):0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged (enabled or disabled)Priviledge.." line.long 0x4 "RTI0_RTIDWDPRLD" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode (read):A read from this register in any CPU mode returns the current preload value.Priviledge mode (write):If the DWD is always enabled after reset is released:The DWD starts.." line.long 0x8 "RTI0_RTIWDSTATUS" hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode (read):0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode (read):0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode (read):0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode (read):0 = AWD pin 0 ?> 1 threshold not exceeded1 = AWD pin 0 ?> 1 threshold exceededPriviledge mode (write):0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "RTI0_RTIWDKEY" hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode (write):A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "RTI0_RTIDWDCNTR" hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "RTI0_RTIWWDRXNCTRL" hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode (read) privileged mode (write):0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "RTI0_RTIWWDSIZECTRL" hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode (read) privileged mode (write):Value written to WWDSIZE Window Size0x00000005 100% (Functionality same as the time-out digital.." line.long 0x1C "RTI0_RTIINTCLRENABLE" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "RTI0_RTICOMP0CLR" hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "RTI0_RTICOMP1CLR" hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "RTI0_RTICOMP2CLR" hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "RTI0_RTICOMP3CLR" hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "RTI1" base ad:0x52181000 group.long 0x0++0x1B line.long 0x0 "RTI1_RTIGCTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode (read):0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "RTI1_RTITBCTRL" bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode (read):0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "RTI1_RTICAPCTRL" hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "RTI1_RTICOMPCTRL" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "RTI1_RTIFRC0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x14 "RTI1_RTIUC0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI1_RTICPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "RTI1_RTICAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 0 on.." line.long 0x4 "RTI1_RTICAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "RTI1_RTIFRC1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x4 "RTI1_RTIUC1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI1_RTICPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "RTI1_RTICAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 1 on.." line.long 0x4 "RTI1_RTICAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "RTI1_RTICOMP0" hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "RTI1_RTIUDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "RTI1_RTICOMP1" hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "RTI1_RTIUDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "RTI1_RTICOMP2" hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "RTI1_RTIUDCP2" hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "RTI1_RTICOMP3" hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "RTI1_RTIUDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "RTI1_RTITBLCOMP" hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode (read):current compare valuePrivilege mode (write when.." line.long 0x24 "RTI1_RTITBHCOMP" hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "RTI1_RTISETINT" hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "RTI1_RTICLEARINT" hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "RTI1_RTIINTFLAG" hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read):this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "RTI1_RTIDWDCTRL" hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode (read):0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged (enabled or disabled)Priviledge.." line.long 0x4 "RTI1_RTIDWDPRLD" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode (read):A read from this register in any CPU mode returns the current preload value.Priviledge mode (write):If the DWD is always enabled after reset is released:The DWD starts.." line.long 0x8 "RTI1_RTIWDSTATUS" hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode (read):0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode (read):0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode (read):0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode (read):0 = AWD pin 0 ?> 1 threshold not exceeded1 = AWD pin 0 ?> 1 threshold exceededPriviledge mode (write):0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "RTI1_RTIWDKEY" hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode (write):A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "RTI1_RTIDWDCNTR" hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "RTI1_RTIWWDRXNCTRL" hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode (read) privileged mode (write):0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "RTI1_RTIWWDSIZECTRL" hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode (read) privileged mode (write):Value written to WWDSIZE Window Size0x00000005 100% (Functionality same as the time-out digital.." line.long 0x1C "RTI1_RTIINTCLRENABLE" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "RTI1_RTICOMP0CLR" hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "RTI1_RTICOMP1CLR" hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "RTI1_RTICOMP2CLR" hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "RTI1_RTICOMP3CLR" hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "RTI2" base ad:0x52182000 group.long 0x0++0x1B line.long 0x0 "RTI2_RTIGCTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode (read):0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "RTI2_RTITBCTRL" bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode (read):0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "RTI2_RTICAPCTRL" hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "RTI2_RTICOMPCTRL" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "RTI2_RTIFRC0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x14 "RTI2_RTIUC0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI2_RTICPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "RTI2_RTICAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 0 on.." line.long 0x4 "RTI2_RTICAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "RTI2_RTIFRC1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x4 "RTI2_RTIUC1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI2_RTICPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "RTI2_RTICAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 1 on.." line.long 0x4 "RTI2_RTICAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "RTI2_RTICOMP0" hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "RTI2_RTIUDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "RTI2_RTICOMP1" hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "RTI2_RTIUDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "RTI2_RTICOMP2" hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "RTI2_RTIUDCP2" hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "RTI2_RTICOMP3" hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "RTI2_RTIUDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "RTI2_RTITBLCOMP" hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode (read):current compare valuePrivilege mode (write when.." line.long 0x24 "RTI2_RTITBHCOMP" hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "RTI2_RTISETINT" hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "RTI2_RTICLEARINT" hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "RTI2_RTIINTFLAG" hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read):this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "RTI2_RTIDWDCTRL" hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode (read):0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged (enabled or disabled)Priviledge.." line.long 0x4 "RTI2_RTIDWDPRLD" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode (read):A read from this register in any CPU mode returns the current preload value.Priviledge mode (write):If the DWD is always enabled after reset is released:The DWD starts.." line.long 0x8 "RTI2_RTIWDSTATUS" hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode (read):0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode (read):0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode (read):0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode (read):0 = AWD pin 0 ?> 1 threshold not exceeded1 = AWD pin 0 ?> 1 threshold exceededPriviledge mode (write):0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "RTI2_RTIWDKEY" hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode (write):A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "RTI2_RTIDWDCNTR" hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "RTI2_RTIWWDRXNCTRL" hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode (read) privileged mode (write):0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "RTI2_RTIWWDSIZECTRL" hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode (read) privileged mode (write):Value written to WWDSIZE Window Size0x00000005 100% (Functionality same as the time-out digital.." line.long 0x1C "RTI2_RTIINTCLRENABLE" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "RTI2_RTICOMP0CLR" hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "RTI2_RTICOMP1CLR" hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "RTI2_RTICOMP2CLR" hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "RTI2_RTICOMP3CLR" hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "RTI3" base ad:0x52183000 group.long 0x0++0x1B line.long 0x0 "RTI3_RTIGCTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode (read):0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "RTI3_RTITBCTRL" bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode (read):0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "RTI3_RTICAPCTRL" hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "RTI3_RTICOMPCTRL" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "RTI3_RTIFRC0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x14 "RTI3_RTIUC0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "RTI3_RTICPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "RTI3_RTICAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 0 on.." line.long 0x4 "RTI3_RTICAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "RTI3_RTIFRC1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x4 "RTI3_RTIUC1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "RTI3_RTICPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "RTI3_RTICAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 1 on.." line.long 0x4 "RTI3_RTICAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "RTI3_RTICOMP0" hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "RTI3_RTIUDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "RTI3_RTICOMP1" hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "RTI3_RTIUDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "RTI3_RTICOMP2" hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "RTI3_RTIUDCP2" hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "RTI3_RTICOMP3" hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "RTI3_RTIUDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "RTI3_RTITBLCOMP" hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode (read):current compare valuePrivilege mode (write when.." line.long 0x24 "RTI3_RTITBHCOMP" hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "RTI3_RTISETINT" hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "RTI3_RTICLEARINT" hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "RTI3_RTIINTFLAG" hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read):this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "RTI3_RTIDWDCTRL" hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode (read):0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged (enabled or disabled)Priviledge.." line.long 0x4 "RTI3_RTIDWDPRLD" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode (read):A read from this register in any CPU mode returns the current preload value.Priviledge mode (write):If the DWD is always enabled after reset is released:The DWD starts.." line.long 0x8 "RTI3_RTIWDSTATUS" hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode (read):0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode (read):0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode (read):0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode (read):0 = AWD pin 0 ?> 1 threshold not exceeded1 = AWD pin 0 ?> 1 threshold exceededPriviledge mode (write):0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "RTI3_RTIWDKEY" hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode (write):A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "RTI3_RTIDWDCNTR" hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "RTI3_RTIWWDRXNCTRL" hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode (read) privileged mode (write):0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "RTI3_RTIWWDSIZECTRL" hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode (read) privileged mode (write):Value written to WWDSIZE Window Size0x00000005 100% (Functionality same as the time-out digital.." line.long 0x1C "RTI3_RTIINTCLRENABLE" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "RTI3_RTICOMP0CLR" hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "RTI3_RTICOMP1CLR" hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "RTI3_RTICOMP2CLR" hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "RTI3_RTICOMP3CLR" hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree.end tree "SOC_TIMESYNC_XBAR" base ad:0x0 tree "SOC_TIMESYNC_XBAR0" base ad:0x52E00000 rgroup.long 0x0++0x3 line.long 0x0 "SOC_TIMESYNC_XBAR0_PID" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "SOC_TIMESYNC_XBAR0_MUXCNTL" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.byte 0x0 0.--4. 1. "ENABLE,Mux control for interrupt N" tree.end tree "SOC_TIMESYNC_XBAR1" base ad:0x52E04000 rgroup.long 0x0++0x3 line.long 0x0 "SOC_TIMESYNC_XBAR1_PID" bitfld.long 0x0 30.--31. "SCHEME,scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,bu" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNCTION,function" hexmask.long.byte 0x0 11.--15. 1. "RTLVER,rtl version" bitfld.long 0x0 8.--10. "MAJREV,major version" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,custom id" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINREV,minor version" group.long 0x4++0x3 line.long 0x0 "SOC_TIMESYNC_XBAR1_MUXCNTL" bitfld.long 0x0 16. "INT_ENABLE,interrupt output enable for interrupt N" "0,1" hexmask.long.byte 0x0 0.--3. 1. "ENABLE,Mux control for interrupt N" tree.end tree.end tree "SPINLOCK" base ad:0x50E00000 rgroup.long 0x0++0x3 line.long 0x0 "SPINLOCK0_REVISION" bitfld.long 0x0 30.--31. "SCHEME,Used to distinguish which ID numbering scheme is used." "0,1,2,3" bitfld.long 0x0 28.--29. "BU,BU identifier" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Module family." hexmask.long.byte 0x0 11.--15. 1. "R_RTL,RTL version. R of X.Y.R.Z" newline bitfld.long 0x0 8.--10. "X_MAJOR,Major revision. X of X.Y.R.Z" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Special version number" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "Y_MINOR,Minor revision. Y of X.Y.R.Z" group.byte 0x10++0x0 line.byte 0x0 "SPINLOCK0_SYSCONFIG" bitfld.byte 0x0 1. "SOFTRESET,Module Software ResetThe bit is automatically reset by the hardware. During reads it always returns 0It has the same effect as the hardware resetWriting a 0 has no effect. Writing a 1 will start a soft reset sequence and free all of the locks" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "SPINLOCK0_SYSTATUS" hexmask.long.byte 0x0 24.--31. 1. "NUMLOCKS,Module configuration parameter n the total number of spinlocks divided by 32.e.g. For 256 spin locks this will return the number 0x08" bitfld.long 0x0 7. "IU7,In-Use flag 7 covering lock registers 224 - 255.If no lock registers are implemented in this range then this flag always reads as 0Read 0 : All lock registers 224 - 255 are in the Not Taken stateRead 1 : At least one of the lock registers 224 - 255.." "0: All lock registers 224,1: At least one of the lock registers 224" newline bitfld.long 0x0 6. "IU6,In-Use flag 6 covering lock registers 192 - 223.If no lock registers are implemented in this range then this flag always reads as 0Read 0 : All lock registers 192 - 223 are in the Not Taken stateRead 1 : At least one of the lock registers 192 - 223.." "0: All lock registers 192,1: At least one of the lock registers 192" bitfld.long 0x0 5. "IU5,In-Use flag 5 covering lock registers 160 - 191.If no lock registers are implemented in this range then this flag always reads as 0Read 0 : All lock registers 160 - 191 are in the Not Taken stateRead 1 : At least one of the lock registers 160 - 191.." "0: All lock registers 160,1: At least one of the lock registers 160" newline bitfld.long 0x0 4. "IU4,In-Use flag 4 covering lock registers 128 - 159.If no lock registers are implemented in this range then this flag always reads as 0Read 0 : All lock registers 128 - 159 are in the Not Taken stateRead 1 : At least one of the lock registers 128 - 159.." "0: All lock registers 128,1: At least one of the lock registers 128" bitfld.long 0x0 3. "IU3,In-Use flag 3 covering lock registers 96 - 127.If no lock registers are implemented in this range then this flag always reads as 0Read 0 : All lock registers 96 - 127 are in the Not Taken stateRead 1 : At least one of the lock registers 96 - 127 are.." "0: All lock registers 96,1: At least one of the lock registers 96" newline bitfld.long 0x0 2. "IU2,In-Use flag 2 covering lock registers 64 - 95.If no lock registers are implemented in this range then this flag always reads as 0Read 0 : All lock registers 64 - 95 are in the Not Taken stateRead 1 : At least one of the lock registers 64 - 95 are in.." "0: All lock registers 64,1: At least one of the lock registers 64" bitfld.long 0x0 1. "IU1,In-Use flag 1 covering lock registers 32 - 63.If no lock registers are implemented in this range then this flag always reads as 0Read 0 : All lock registers 32 - 63 are in the Not Taken stateRead 1 : At least one of the lock registers 32 - 63 are in.." "0: All lock registers 32,1: At least one of the lock registers 32" newline bitfld.long 0x0 0. "IU0,In-Use flag 0 covering lock registers 0 - 31.If no lock registers are implemented in this range then this flag always reads as 0Read 0 : All lock registers 0 - 31 are in the Not Taken stateRead 1 : At least one of the lock registers 0 - 31 are in.." "0: All lock registers 0,1: At least one of the lock registers 0" group.long 0x800++0x3 line.long 0x0 "SPINLOCK0_LOCK_REG" bitfld.long 0x0 0. "TAKEN,Lock StatusRead 0 : Lock was previously free. The reader now has been granted the lock.Read 1 : Lock was previously taken. The reader has not been granted the lock and must retry.Write 0 : Free the lock by setting TAKEN to zero.Write 1 : No effect" "0: Free the lock by setting TAKEN to zero,1: No effect" tree.end tree "TOP" base ad:0x0 tree "TOP_CTRL" base ad:0x50D80000 rgroup.long 0x0++0x3 line.long 0x0 "TOP_CTRL_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,Not Defined" newline hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,Not Defined" newline bitfld.long 0x0 8.--10. "PID_MAJOR,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM,Not Defined" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,Not Defined" rgroup.long 0x10++0x1B line.long 0x0 "TOP_CTRL_EFUSE_DIEID0" hexmask.long 0x0 0.--31. 1. "VAL,EFUSE DieID[31:0]" line.long 0x4 "TOP_CTRL_EFUSE_DIEID1" hexmask.long 0x4 0.--31. 1. "VAL,EFUSE DieID[63:32]" line.long 0x8 "TOP_CTRL_EFUSE_DIEID2" hexmask.long 0x8 0.--31. 1. "VAL,EFUSE DieID[95:64]" line.long 0xC "TOP_CTRL_EFUSE_DIEID3" hexmask.long 0xC 0.--31. 1. "VAL,EFUSE DieID[127:96]" line.long 0x10 "TOP_CTRL_EFUSE_UID0" hexmask.long 0x10 0.--31. 1. "VAL,EFUSE UID[31:0]" line.long 0x14 "TOP_CTRL_EFUSE_UID1" hexmask.long 0x14 0.--31. 1. "VAL,EFUSE UID[63:32]" line.long 0x18 "TOP_CTRL_EFUSE_UID2" hexmask.long 0x18 0.--31. 1. "VAL,EFUSE UID[95:64]" rgroup.tbyte 0x2C++0x2 line.tbyte 0x0 "TOP_CTRL_EFUSE_UID3" hexmask.tbyte 0x0 0.--23. 1. "VAL,EFUSE UID[120:96]" rgroup.word 0x30++0x1 line.word 0x0 "TOP_CTRL_EFUSE_DEVICE_TYPE" hexmask.word 0x0 0.--15. 1. "VAL,EFUSE Device Type" rgroup.long 0x34++0x7 line.long 0x0 "TOP_CTRL_EFUSE_FROM0_CHECKSUM" hexmask.long 0x0 0.--31. 1. "VAL,32 bit FROM0 Checksum" line.long 0x4 "TOP_CTRL_EFUSE_JTAG_USERCODE_ID" hexmask.long 0x4 0.--31. 1. "VAL,EFUSE JTAG_USER_CODE_ID[31:0];. Denotes part variant" rgroup.long 0x400++0x2B line.long 0x0 "TOP_CTRL_EFUSE0_ROW_61" hexmask.long 0x0 0.--25. 1. "EFUSE0_ROW_61,Captures the EFUSE Value." line.long 0x4 "TOP_CTRL_EFUSE0_ROW_62" hexmask.long 0x4 0.--25. 1. "EFUSE0_ROW_62,Captures the EFUSE Value." line.long 0x8 "TOP_CTRL_EFUSE0_ROW_63" hexmask.long 0x8 0.--25. 1. "EFUSE0_ROW_63,Captures the EFUSE Value." line.long 0xC "TOP_CTRL_EFUSE1_ROW_5" hexmask.long 0xC 0.--25. 1. "EFUSE1_ROW_5,Captures the EFUSE Value." line.long 0x10 "TOP_CTRL_EFUSE1_ROW_6" hexmask.long 0x10 0.--25. 1. "EFUSE1_ROW_6,Captures the EFUSE Value." line.long 0x14 "TOP_CTRL_EFUSE1_ROW_7" hexmask.long 0x14 0.--25. 1. "EFUSE1_ROW_7,Captures the EFUSE Value." line.long 0x18 "TOP_CTRL_EFUSE1_ROW_8" hexmask.long 0x18 0.--25. 1. "EFUSE1_ROW_8,Captures the EFUSE Value." line.long 0x1C "TOP_CTRL_EFUSE1_ROW_9" hexmask.long 0x1C 0.--25. 1. "EFUSE1_ROW_9,Captures the EFUSE Value." line.long 0x20 "TOP_CTRL_EFUSE1_ROW_10" hexmask.long 0x20 0.--25. 1. "EFUSE1_ROW_10,Captures the EFUSE Value." line.long 0x24 "TOP_CTRL_EFUSE1_ROW_11" hexmask.long 0x24 0.--25. 1. "EFUSE1_ROW_11,Captures the EFUSE Value." line.long 0x28 "TOP_CTRL_EFUSE1_ROW_12" bitfld.long 0x28 25. "CUSTOMER_IP_DISABLE,Customer IP set control0 - All IPs enabled1 - Customer IP set disabled (PWM24-31 CMPSSA6-9 CMPSSB6-9 disabled)" "0,1" newline bitfld.long 0x28 24. "EPWM_FEATURE_DISABLE,Customer protected features inside PWM IP 0 - All features enabled1 - Customer defined features are protected" "0,1" newline hexmask.long.byte 0x28 20.--23. 1. "CANFD_DIS,CANFD disables. Bit positions correspond to CAN instance. 0 - CAN is enabled1 - CAN is disabled" newline hexmask.long.byte 0x28 12.--19. 1. "ICSSM_HW_DIS,See ICSSM Spec for features" newline bitfld.long 0x28 11. "ICSSM_DIS,ICSSM IP disable0 - ICSSM enabled1 - ICSSM disabled" "0,1" newline bitfld.long 0x28 10. "TWOX_CTRL_PERIP_DISABLE,2x control IPs enabled0 - 1x control IPs (refer to PRD for the IP counts)1 - 2x control IPs (refer to PRD for the IP counts)" "0,1" newline bitfld.long 0x28 9. "R5SS_FREQ,R5SS Freq0 - 400 MHz1 - 200 MHz" "0,1" newline bitfld.long 0x28 8. "R5SS1_DISABLE,R5SS1 Disabled" "0,1" newline bitfld.long 0x28 7. "R5SS1_DUAL_CORE_DISABLE,Force Lock step" "0,1" newline bitfld.long 0x28 6. "R5SS1_FORCE_DUAL_CORE,Force Dual core" "0,1" newline bitfld.long 0x28 5. "R5SS0_DUAL_CORE_DISABLE,Force Lock step" "0,1" newline bitfld.long 0x28 4. "R5SS0_FORCE_DUAL_CORE,Force Dual core" "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "L2_MEM_SIZE,Captures the EFUSE Value." rgroup.byte 0x42C++0x0 line.byte 0x0 "TOP_CTRL_EFUSE1_ROW_13" bitfld.byte 0x0 1. "ROM_PBIST_EN,ROM PBIST ENABLE C ONTROL0 - PBIST DISABLE1 - PBIST ENABLE" "0,1" newline bitfld.byte 0x0 0. "HSM_HALT_ON_ROM_ECC_ERR_EN,Enabling halting of the HSM operation on a ROM ECC error that is detected." "0,1" rgroup.long 0x430++0xAB line.long 0x0 "TOP_CTRL_EFUSE1_ROW_14" hexmask.long 0x0 0.--25. 1. "EFUSE1_ROW_14,Captures the EFUSE Value." line.long 0x4 "TOP_CTRL_EFUSE1_ROW_15" hexmask.long 0x4 0.--25. 1. "EFUSE1_ROW_15,Captures the EFUSE Value." line.long 0x8 "TOP_CTRL_EFUSE1_ROW_16" hexmask.long 0x8 0.--25. 1. "EFUSE1_ROW_16,Captures the EFUSE Value." line.long 0xC "TOP_CTRL_EFUSE1_ROW_17" hexmask.long 0xC 0.--25. 1. "EFUSE1_ROW_17,Captures the EFUSE Value." line.long 0x10 "TOP_CTRL_EFUSE1_ROW_18" hexmask.long 0x10 0.--25. 1. "EFUSE1_ROW_18,Captures the EFUSE Value." line.long 0x14 "TOP_CTRL_EFUSE1_ROW_19" hexmask.long 0x14 0.--25. 1. "EFUSE1_ROW_19,Captures the EFUSE Value." line.long 0x18 "TOP_CTRL_EFUSE1_ROW_20" hexmask.long 0x18 0.--25. 1. "EFUSE1_ROW_20,Captures the EFUSE Value." line.long 0x1C "TOP_CTRL_EFUSE1_ROW_21" hexmask.long 0x1C 0.--25. 1. "EFUSE1_ROW_21,Captures the EFUSE Value." line.long 0x20 "TOP_CTRL_EFUSE1_ROW_22" hexmask.long 0x20 0.--25. 1. "EFUSE1_ROW_22,Captures the EFUSE Value." line.long 0x24 "TOP_CTRL_EFUSE1_ROW_23" hexmask.long 0x24 0.--25. 1. "EFUSE1_ROW_23,Captures the EFUSE Value." line.long 0x28 "TOP_CTRL_EFUSE1_ROW_24" hexmask.long 0x28 0.--25. 1. "EFUSE1_ROW_24,Captures the EFUSE Value." line.long 0x2C "TOP_CTRL_EFUSE1_ROW_25" hexmask.long 0x2C 0.--25. 1. "EFUSE1_ROW_25,Captures the EFUSE Value." line.long 0x30 "TOP_CTRL_EFUSE1_ROW_26" hexmask.long 0x30 0.--25. 1. "EFUSE1_ROW_26,Captures the EFUSE Value." line.long 0x34 "TOP_CTRL_EFUSE1_ROW_27" hexmask.long 0x34 0.--25. 1. "EFUSE1_ROW_27,Captures the EFUSE Value." line.long 0x38 "TOP_CTRL_EFUSE1_ROW_28" hexmask.long 0x38 0.--25. 1. "EFUSE1_ROW_28,Captures the EFUSE Value." line.long 0x3C "TOP_CTRL_EFUSE1_ROW_29" hexmask.long 0x3C 0.--25. 1. "EFUSE1_ROW_29,Captures the EFUSE Value." line.long 0x40 "TOP_CTRL_EFUSE1_ROW_30" hexmask.long 0x40 0.--25. 1. "EFUSE1_ROW_30,Captures the EFUSE Value." line.long 0x44 "TOP_CTRL_EFUSE1_ROW_31" hexmask.long 0x44 0.--25. 1. "EFUSE1_ROW_31,Captures the EFUSE Value." line.long 0x48 "TOP_CTRL_EFUSE1_ROW_32" hexmask.long 0x48 0.--25. 1. "EFUSE1_ROW_32,Captures the EFUSE Value." line.long 0x4C "TOP_CTRL_EFUSE1_ROW_33" hexmask.long 0x4C 0.--25. 1. "EFUSE1_ROW_33,Captures the EFUSE Value." line.long 0x50 "TOP_CTRL_EFUSE1_ROW_34" hexmask.long 0x50 0.--25. 1. "EFUSE1_ROW_34,Captures the EFUSE Value." line.long 0x54 "TOP_CTRL_EFUSE1_ROW_35" hexmask.long 0x54 0.--25. 1. "EFUSE1_ROW_35,Captures the EFUSE Value." line.long 0x58 "TOP_CTRL_EFUSE1_ROW_36" hexmask.long 0x58 0.--25. 1. "EFUSE1_ROW_36,Captures the EFUSE Value." line.long 0x5C "TOP_CTRL_EFUSE1_ROW_37" hexmask.long 0x5C 0.--25. 1. "EFUSE1_ROW_37,Captures the EFUSE Value." line.long 0x60 "TOP_CTRL_EFUSE1_ROW_38" hexmask.long 0x60 0.--25. 1. "EFUSE1_ROW_38,Captures the EFUSE Value." line.long 0x64 "TOP_CTRL_EFUSE1_ROW_39" hexmask.long 0x64 0.--25. 1. "EFUSE1_ROW_39,Captures the EFUSE Value." line.long 0x68 "TOP_CTRL_EFUSE1_ROW_40" hexmask.long 0x68 0.--25. 1. "EFUSE1_ROW_40,Captures the EFUSE Value." line.long 0x6C "TOP_CTRL_EFUSE1_ROW_41" hexmask.long 0x6C 0.--25. 1. "EFUSE1_ROW_41,Captures the EFUSE Value." line.long 0x70 "TOP_CTRL_EFUSE1_ROW_42" hexmask.long 0x70 0.--25. 1. "EFUSE1_ROW_42,Captures the EFUSE Value." line.long 0x74 "TOP_CTRL_EFUSE1_ROW_43" hexmask.long 0x74 0.--25. 1. "EFUSE1_ROW_43,Captures the EFUSE Value." line.long 0x78 "TOP_CTRL_EFUSE1_ROW_44" hexmask.long 0x78 0.--25. 1. "EFUSE1_ROW_44,Captures the EFUSE Value." line.long 0x7C "TOP_CTRL_EFUSE1_ROW_45" hexmask.long 0x7C 0.--25. 1. "EFUSE1_ROW_45,Captures the EFUSE Value." line.long 0x80 "TOP_CTRL_EFUSE1_ROW_46" hexmask.long 0x80 0.--25. 1. "EFUSE1_ROW_46,Captures the EFUSE Value." line.long 0x84 "TOP_CTRL_EFUSE1_ROW_47" hexmask.long 0x84 0.--25. 1. "EFUSE1_ROW_47,Captures the EFUSE Value." line.long 0x88 "TOP_CTRL_EFUSE1_ROW_48" hexmask.long 0x88 0.--25. 1. "EFUSE1_ROW_48,Captures the EFUSE Value." line.long 0x8C "TOP_CTRL_EFUSE1_ROW_49" hexmask.long 0x8C 0.--25. 1. "EFUSE1_ROW_49,Captures the EFUSE Value." line.long 0x90 "TOP_CTRL_EFUSE1_ROW_50" hexmask.long 0x90 0.--25. 1. "EFUSE1_ROW_50,Captures the EFUSE Value." line.long 0x94 "TOP_CTRL_EFUSE1_ROW_51" hexmask.long 0x94 0.--25. 1. "EFUSE1_ROW_51,Captures the EFUSE Value." line.long 0x98 "TOP_CTRL_EFUSE1_ROW_52" hexmask.long 0x98 0.--25. 1. "EFUSE1_ROW_52,Captures the EFUSE Value." line.long 0x9C "TOP_CTRL_EFUSE1_ROW_53" hexmask.long 0x9C 0.--25. 1. "EFUSE1_ROW_53,Captures the EFUSE Value." line.long 0xA0 "TOP_CTRL_EFUSE1_ROW_54" hexmask.long 0xA0 0.--25. 1. "EFUSE1_ROW_54,Captures the EFUSE Value." line.long 0xA4 "TOP_CTRL_EFUSE1_ROW_55" hexmask.long 0xA4 0.--25. 1. "EFUSE1_ROW_55,Captures the EFUSE Value." line.long 0xA8 "TOP_CTRL_EFUSE1_ROW_56" hexmask.long 0xA8 0.--25. 1. "EFUSE1_ROW_56,Captures the EFUSE Value." rgroup.long 0x500++0x3 line.long 0x0 "TOP_CTRL_MAC_ID0" hexmask.long 0x0 0.--31. 1. "MACID_LO,MAC ID low [32bits]" rgroup.word 0x504++0x1 line.word 0x0 "TOP_CTRL_MAC_ID1" hexmask.word 0x0 0.--15. 1. "MACID_HI,MAC ID high [16bits]" rgroup.word 0x510++0x1 line.word 0x0 "TOP_CTRL_TRIM_TEMP_M40C" hexmask.word 0x0 0.--10. 1. "TEMP,Record the temperature at which the temp sensor trims were performed" rgroup.long 0x514++0x7 line.long 0x0 "TOP_CTRL_TRIM_TEMPSENSE_M40C0" hexmask.long 0x0 0.--31. 1. "TRIM,Trim for temperature sensor calibration [Lower 32bits]" line.long 0x4 "TOP_CTRL_TRIM_TEMPSENSE_M40C1" hexmask.long.word 0x4 0.--8. 1. "TRIM,Trim for temperature sensor calibration [Upper 9bits]" rgroup.word 0x51C++0x1 line.word 0x0 "TOP_CTRL_TRIM_TEMP_150C" hexmask.word 0x0 0.--10. 1. "TEMP,Record the temperature at which the temp sensor trims were performed" rgroup.long 0x520++0x7 line.long 0x0 "TOP_CTRL_TRIM_TEMPSENSE_150C0" hexmask.long 0x0 0.--31. 1. "TRIM,Trim for temperature sensor calibration [Lower 32bits]" line.long 0x4 "TOP_CTRL_TRIM_TEMPSENSE_150C1" hexmask.long.word 0x4 0.--8. 1. "TRIM,Trim for temperature sensor calibration [Upper 9bits]" rgroup.word 0x528++0x1 line.word 0x0 "TOP_CTRL_TRIM_TEMP_30C" hexmask.word 0x0 0.--10. 1. "TEMP,Record the temperature at which the temp sensor trims were performed" rgroup.long 0x52C++0x7 line.long 0x0 "TOP_CTRL_TRIM_TEMPSENSE_30C0" hexmask.long 0x0 0.--31. 1. "TRIM,Trim for temperature sensor calibration [Lower 32bits]" line.long 0x4 "TOP_CTRL_TRIM_TEMPSENSE_30C1" hexmask.long.word 0x4 0.--8. 1. "TRIM,Trim for temperature sensor calibration [Upper 9bits]" rgroup.word 0x534++0x1 line.word 0x0 "TOP_CTRL_N_FACTOR_TEMPSENSE" hexmask.word 0x0 0.--13. 1. "VAL,Temp Sensor N factor" group.byte 0x800++0x0 line.byte 0x0 "TOP_CTRL_EFUSE_OVERRIDE_HSM_HALT_ON_ROM_ECC_ERR_EN" bitfld.byte 0x0 4. "OVERRIDE_VAL,Override MMR value" "0,1" newline bitfld.byte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.long 0x804++0x17 line.long 0x0 "TOP_CTRL_EFUSE_OVERRIDE_MEM_MARGINCTRL" bitfld.long 0x0 28.--29. "BRG_MARGIN,Override MMR value" "0,1,2,3" newline bitfld.long 0x0 24.--26. "BRG_MARGIN_OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" newline bitfld.long 0x0 20.--21. "BYG_MARGIN,Override MMR value" "0,1,2,3" newline bitfld.long 0x0 16.--18. "BYG_MARGIN_OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" newline hexmask.long.byte 0x0 12.--15. 1. "GWG_MARGIN,Override MMR value" newline bitfld.long 0x0 8.--10. "GWG_MARGIN_OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" newline bitfld.long 0x0 4.--5. "GLG_MARGIN,Override MMR value" "0,1,2,3" newline bitfld.long 0x0 0.--2. "GLG_MARGIN_OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" line.long 0x4 "TOP_CTRL_EFUSE_OVERRIDE_ADC0_TRIM" hexmask.long.word 0x4 16.--30. 1. "ADC0_TRIM,offset trim of the ADC (3 values each 5 bit for SE-p SE-m & Diff)" newline bitfld.long 0x4 0.--2. "OVERRIDE,Override EFUSE Value with SW Value Write 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" line.long 0x8 "TOP_CTRL_EFUSE_OVERRIDE_ADC1_TRIM" hexmask.long.word 0x8 16.--30. 1. "ADC1_TRIM,offset trim of the ADC (3 values each 5 bit for SE-p SE-m & Diff)" newline bitfld.long 0x8 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" line.long 0xC "TOP_CTRL_EFUSE_OVERRIDE_ADC2_TRIM" hexmask.long.word 0xC 16.--30. 1. "ADC2_TRIM,offset trim of the ADC (3 values each 5 bit for SE-p SE-m & Diff)" newline bitfld.long 0xC 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" line.long 0x10 "TOP_CTRL_EFUSE_OVERRIDE_ADC3_TRIM" hexmask.long.word 0x10 16.--30. 1. "ADC3_TRIM,offset trim of the ADC (3 values each 5 bit for SE-p SE-m & Diff)" newline bitfld.long 0x10 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" line.long 0x14 "TOP_CTRL_EFUSE_OVERRIDE_ADC4_TRIM" hexmask.long.word 0x14 16.--30. 1. "ADC4_TRIM,offset trim of the ADC (3 values each 5 bit for SE-p SE-m & Diff)" newline bitfld.long 0x14 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.byte 0x81C++0x0 line.byte 0x0 "TOP_CTRL_EFUSE_OVERRIDE_ADC_CFG_CTRL" bitfld.byte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.long 0x820++0x7 line.long 0x0 "TOP_CTRL_EFUSE_OVERRIDE_ADC_CFG0" hexmask.long 0x0 0.--31. 1. "ADC_CFG_31_0,Family Trim. Will be same for all ADC's. Finalized during Bench/ATE char" line.long 0x4 "TOP_CTRL_EFUSE_OVERRIDE_ADC_CFG1" hexmask.long 0x4 0.--31. 1. "ADC_CFG_63_32,Family Trim. Will be same for all ADC's. Finalized during Bench/ATE char" group.tbyte 0x828++0x2 line.tbyte 0x0 "TOP_CTRL_EFUSE_OVERRIDE_ADC_CFG2" hexmask.tbyte 0x0 0.--23. 1. "ADC_CFG_87_64,Family Trim. Will be same for all ADC's. Finalized during Bench/ATE char" group.byte 0x82C++0x0 line.byte 0x0 "TOP_CTRL_EFUSE_OVERRIDE_CSS01_TRIM_CTRL" bitfld.byte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.long 0x830++0x3 line.long 0x0 "TOP_CTRL_EFUSE_OVERRIDE_CSS01_TRIM" hexmask.long 0x0 0.--31. 1. "CSS01_TRIM,CSS Trim signal" group.byte 0x834++0x0 line.byte 0x0 "TOP_CTRL_EFUSE_OVERRIDE_CSS23_TRIM_CTRL" bitfld.byte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.long 0x838++0x3 line.long 0x0 "TOP_CTRL_EFUSE_OVERRIDE_CSS23_TRIM" hexmask.long 0x0 0.--31. 1. "CSS23_TRIM,CSS Trim signal" group.byte 0x83C++0x0 line.byte 0x0 "TOP_CTRL_EFUSE_OVERRIDE_CSS45_TRIM_CTRL" bitfld.byte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.long 0x840++0x3 line.long 0x0 "TOP_CTRL_EFUSE_OVERRIDE_CSS45_TRIM" hexmask.long 0x0 0.--31. 1. "CSS45_TRIM,CSS Trim signal" group.byte 0x844++0x0 line.byte 0x0 "TOP_CTRL_EFUSE_OVERRIDE_CSS67_TRIM_CTRL" bitfld.byte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.long 0x848++0x3 line.long 0x0 "TOP_CTRL_EFUSE_OVERRIDE_CSS67_TRIM" hexmask.long 0x0 0.--31. 1. "CSS67_TRIM,CSS Trim signal" group.byte 0x84C++0x0 line.byte 0x0 "TOP_CTRL_EFUSE_OVERRIDE_CSS89_TRIM_CTRL" bitfld.byte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.long 0x850++0x3 line.long 0x0 "TOP_CTRL_EFUSE_OVERRIDE_CSS89_TRIM" hexmask.long 0x0 0.--31. 1. "CSS89_TRIM,CSS Trim signal" group.byte 0x854++0x0 line.byte 0x0 "TOP_CTRL_EFUSE_OVERRIDE_CSS_CFG_CTRL" bitfld.byte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.long 0x858++0x17 line.long 0x0 "TOP_CTRL_EFUSE_OVERRIDE_CSS_CFG0" hexmask.long 0x0 0.--31. 1. "CSS_CFG_31_0,Compdac Family trim (all CMPSS a & b)" line.long 0x4 "TOP_CTRL_EFUSE_OVERRIDE_CSS_CFG1" hexmask.long 0x4 0.--31. 1. "CSS_CFG_0_63_32,Compdac Family trim (all CMPSS a & b)" line.long 0x8 "TOP_CTRL_EFUSE_OVERRIDE_DAC_TRIM" hexmask.long.word 0x8 16.--28. 1. "DAC_TRIM,DAC Trim28:24 : [12:8] gain trim; 23:16 : [7:0] offset trim" newline bitfld.long 0x8 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" line.long 0xC "TOP_CTRL_EFUSE_OVERRIDE_DAC_CFG" bitfld.long 0xC 24. "ASYNC_MODE_EN,async_mode_en" "0,1" newline bitfld.long 0xC 16.--17. "IBIAS_CFG,ibias_cfg[1:0]" "0,1,2,3" newline bitfld.long 0xC 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" line.long 0x10 "TOP_CTRL_EFUSE_OVERRIDE_REFBUF0_TRIM" hexmask.long.byte 0x10 28.--31. 1. "ROK0B_UV_TRIM,ROK0B Under voltage threshold trim" newline hexmask.long.byte 0x10 24.--27. 1. "ROK0B_OV_TRIM,ROK0B Over voltage threshold trim" newline hexmask.long.byte 0x10 20.--23. 1. "ROK0A_UV_TRIM,ROK0A Under voltage threshold trim" newline hexmask.long.byte 0x10 16.--19. 1. "ROK0A_OV_TRIM,ROK0A Over voltage threshold trim" newline hexmask.long.byte 0x10 8.--15. 1. "REF_TRIM,Trims output voltage with 1mV steps +/-30mV default 0V" newline bitfld.long 0x10 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" line.long 0x14 "TOP_CTRL_EFUSE_OVERRIDE_REFBUF0_CFG" hexmask.long.byte 0x14 24.--27. 1. "ROK0B_VSEL,Voltage selection for reference OK comp (1.46V to 1.86V) (ROK0B)" newline hexmask.long.byte 0x14 20.--23. 1. "ROK0A_VSEL,Voltage selection for reference OK comp (1.46V to 1.86V)" newline hexmask.long.byte 0x14 16.--19. 1. "ADCREF_VSEL,Selects output voltage level from 1.46V to 1.86V; default code is 1.8V" newline hexmask.long.byte 0x14 8.--14. 1. "REFBUF0_CFG,Bit0: Debug feature doubles the current of the 2nd stage. enfbres_pwdBit6-1: adjust current bias for the 1st 2nd and 3rd stages.trim_ampbias[5:0]" newline bitfld.long 0x14 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.tbyte 0x870++0x2 line.tbyte 0x0 "TOP_CTRL_EFUSE_OVERRIDE_REFBUF1_TRIM" hexmask.tbyte.byte 0x0 20.--23. 1. "ROK1_UV_TRIM,ROK0A Under voltage threshold trim" newline hexmask.tbyte.byte 0x0 16.--19. 1. "ROK1_OV_TRIM,ROK0A Over voltage threshold trim" newline hexmask.tbyte.byte 0x0 8.--15. 1. "REF_TRIM,Trims output voltage with 1mV steps +/-30mV default 0V" newline bitfld.tbyte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.tbyte 0x874++0x2 line.tbyte 0x0 "TOP_CTRL_EFUSE_OVERRIDE_REFBUF1_CFG" hexmask.tbyte.byte 0x0 20.--23. 1. "ROK1_VSEL,Voltage selection for reference OK comp (1.46V to 1.86V)" newline hexmask.tbyte.byte 0x0 16.--19. 1. "ADCREF_VSEL,Selects output voltage level from 1.46V to 1.86V; default code is 1.8V" newline hexmask.tbyte.byte 0x0 8.--14. 1. "REFBUF1_CFG,Bit0: Debug feature doubles the current of the 2nd stage. enfbres_pwdBit6-1: adjust current bias for the 1st 2nd and 3rd stages.trim_ampbias[5:0]" newline bitfld.tbyte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.long 0x878++0xF line.long 0x0 "TOP_CTRL_EFUSE_OVERRIDE_PMU_CFG" hexmask.long.byte 0x0 24.--30. 1. "LDO_DFTC,Main LDO(1.8v) Config signals.Bit15: Not UsedBit14: 1 Double current in clampBit13: 1 Local ~200uA load resistor connected to ldooutBit12: 1 Amplifier ok bypassedBit 11-10: Adjust master current mirror in amplifier 2'b11 = 0.67x current.." newline hexmask.long.byte 0x0 16.--20. 1. "BG_DFTC,Bandgap DFT controls for debug purposes.Bit7: 1 To short large BJT base resistor to GNDBit6: 1 To short small BJT base resistor to GNDBit5: 1 To turn OFF startup pull NMOSBit4: 1 To turn OFF startup currentBit3: 1 to adjust(increase) BGAMP biasing" newline bitfld.long 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" line.long 0x4 "TOP_CTRL_EFUSE_OVERRIDE_PMU_SPARE_TRIM" hexmask.long.word 0x4 16.--25. 1. "TRIM,PMU spare trim override value{pmu_trim_1p1v<7:6> pmu_trim_1p1v<19:18> pmu_trim_1p1v<35:30>}" newline bitfld.long 0x4 0.--2. "OVERRIDE,Override EFUSE Value for PMU SPARE trimWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" line.long 0x8 "TOP_CTRL_EFUSE_OVERRIDE_LDO_TRIM" hexmask.long.byte 0x8 24.--29. 1. "LDO_TRIM_OFFSET,LDO Fine trim around program point" newline hexmask.long.byte 0x8 16.--19. 1. "LDO_PROG,LDO programming controls. Adjusts nominal LDO output voltage" newline bitfld.long 0x8 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" line.long 0xC "TOP_CTRL_EFUSE_OVERRIDE_BG_TRIM" hexmask.long.byte 0xC 24.--29. 1. "BG_TRIMC,Bandgap curvture/slope trim bits" newline hexmask.long.byte 0xC 16.--19. 1. "BG_TRIMMAG,Bandgap magnitude trim bits" newline hexmask.long.byte 0xC 8.--15. 1. "BG_TRIMI,[19:18] = Unused[17:12] = Bandgap current trim bits" newline bitfld.long 0xC 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.byte 0x888++0x0 line.byte 0x0 "TOP_CTRL_EFUSE_OVERRIDE_SFTYMON_THRHLD_TRIM_CTRL" bitfld.byte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.long 0x88C++0x3 line.long 0x0 "TOP_CTRL_EFUSE_OVERRIDE_SFTYMON_THRHLD_TRIM0" hexmask.long.byte 0x0 28.--31. 1. "C5_LOW_TRIM,C5 low side threshold trim setting" newline hexmask.long.byte 0x0 24.--27. 1. "C5_HIGH_TRIM,C5 high side threshold trim setting" newline hexmask.long.byte 0x0 20.--23. 1. "C3_LOW_TRIM,C3 low side threshold trim setting" newline hexmask.long.byte 0x0 16.--19. 1. "C3_HIGH_TRIM,C3 high side threshold trim setting" newline hexmask.long.byte 0x0 12.--15. 1. "C2_LOW_TRIM,C2 low side threshold trim setting" newline hexmask.long.byte 0x0 8.--11. 1. "C2_HIGH_TRIM,C2 high side threshold trim setting" newline hexmask.long.byte 0x0 4.--7. 1. "C1_LOW_TRIM,C1 low side threshold trim setting" newline hexmask.long.byte 0x0 0.--3. 1. "C1_HIGH_TRIM,C1 high side threshold trim setting;" group.byte 0x890++0x0 line.byte 0x0 "TOP_CTRL_EFUSE_OVERRIDE_SFTYMON_THRHLD_TRIM1" hexmask.byte 0x0 0.--3. 1. "C8_LOW_TRIM,C8 low side threshold trim setting" group.tbyte 0x894++0x2 line.tbyte 0x0 "TOP_CTRL_EFUSE_OVERRIDE_RCOSC_TRIM" hexmask.tbyte.byte 0x0 16.--22. 1. "FREQ_TRIM,RC oscillator frequency trim" newline bitfld.tbyte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.tbyte 0x898++0x2 line.tbyte 0x0 "TOP_CTRL_EFUSE_SAFETYMON_SPARE" hexmask.tbyte.byte 0x0 16.--23. 1. "VAL,SAFETYMON_SPARE trim override value" newline bitfld.tbyte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.tbyte 0x89C++0x2 line.tbyte 0x0 "TOP_CTRL_EFUSE_SPARE_1" hexmask.tbyte.byte 0x0 16.--20. 1. "VAL,SPARE_1 trim override value" newline bitfld.tbyte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.tbyte 0x8A0++0x2 line.tbyte 0x0 "TOP_CTRL_EFUSE_SPARE_2" hexmask.tbyte.byte 0x0 16.--20. 1. "VAL,SPARE_2 trim override value" newline bitfld.tbyte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.tbyte 0x8A4++0x2 line.tbyte 0x0 "TOP_CTRL_EFUSE_SPARE_3" hexmask.tbyte.byte 0x0 16.--20. 1. "VAL,SPARE_3 trim override value" newline bitfld.tbyte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.tbyte 0x8A8++0x2 line.tbyte 0x0 "TOP_CTRL_EFUSE_SPARE_4" hexmask.tbyte.byte 0x0 16.--20. 1. "VAL,SPARE_4 trim override value" newline bitfld.tbyte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.tbyte 0x8AC++0x2 line.tbyte 0x0 "TOP_CTRL_EFUSE_SPARE_5" hexmask.tbyte.byte 0x0 16.--20. 1. "VAL,SPARE_5 trim override value" newline bitfld.tbyte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.tbyte 0x8B0++0x2 line.tbyte 0x0 "TOP_CTRL_EFUSE_SPARE_6" hexmask.tbyte.byte 0x0 16.--20. 1. "VAL,SPARE_6 trim override value" newline bitfld.tbyte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.tbyte 0x8B4++0x2 line.tbyte 0x0 "TOP_CTRL_EFUSE_SPARE_7" hexmask.tbyte.byte 0x0 16.--20. 1. "VAL,SPARE_6 trim override value" newline bitfld.tbyte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.byte 0x8B8++0x0 line.byte 0x0 "TOP_CTRL_EFUSE_OVERRIDE_TSENSE_TRIM_CTRL" bitfld.byte 0x0 0.--2. "OVERRIDE,Override EFUSE Value with SW ValueWrite 3'b000 : EFUSE ValueWrite 3'b111 : MMR Value" "0: EFUSE ValueWrite,?,?,?,?,?,?,7: MMR Value" group.long 0x8BC++0x7 line.long 0x0 "TOP_CTRL_EFUSE_OVERRIDE_TSENSE_TRIM" bitfld.long 0x0 30.--31. "VPTAT_RTRIM,TS: Vptat R trim (PTAT voltage resistor trim)" "0,1,2,3" newline hexmask.long.byte 0x0 24.--29. 1. "TSHUT_TRIM,Tshut Temperature C (Shutdown temperature trim)" newline hexmask.long.byte 0x0 16.--23. 1. "DTRTEMPS,RDAC offset trim" newline hexmask.long.byte 0x0 8.--15. 1. "DTRBGAPV,TS Bandgap magnitude trim" newline hexmask.long.byte 0x0 0.--7. 1. "DTRBGAPC,TS Bandgap curvature trim" line.long 0x4 "TOP_CTRL_EFUSE_OVERRIDE_PLL_TRIM" hexmask.long.byte 0x4 24.--28. 1. "PER_NWELLTRIM_OVERRIDE_VAL,Peripheral ADPLL trim override value when per_adpll_trim_override is programmed" newline bitfld.long 0x4 16.--18. "PER_NWELLTRIM_OVERRIDE,Peripheral ADPLL trim value is overridden by per_adpll_trim_override_val when this bit is programmed 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--12. 1. "CORE_NWELLTRIM_OVERRIDE_VAL,Core ADPLL trim override value when core_adpll_trim_override is programmed" newline bitfld.long 0x4 0.--2. "CORE_NWELLTRIM_OVERRIDE,Core ADPLL trim value is overridden by core_adpll_trim_override_val when this bit is programmed 1" "0,1,2,3,4,5,6,7" group.byte 0xC00++0x0 line.byte 0x0 "TOP_CTRL_ADC_REFBUF0_CTRL" bitfld.byte 0x0 0.--2. "ENABLE,Enables adc reference 0 mask hhv before enable000: Disable111 : Enable" "0,1,2,3,4,5,6,7" group.byte 0xC04++0x0 line.byte 0x0 "TOP_CTRL_ADC_REFBUF1_CTRL" bitfld.byte 0x0 0.--2. "ENABLE,Enables adc reference 0 mask hhv before enable000: Disable111 : Enable" "0,1,2,3,4,5,6,7" group.word 0xC08++0x1 line.word 0x0 "TOP_CTRL_ADC_REF_COMP_CTRL" bitfld.word 0x0 8.--10. "ADC34_REFOK_EN,enables reference comparators (ROK1). This monitors adc3 & adc4 refernc" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4.--6. "ADC12_REFOK_EN,enables reference comparators (ROK0B). This monitors adc1 & adc2 refernce" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "ADC0_REFOK_EN,enables reference comparators (ROK0). This monitors adc0 refernce" "0,1,2,3,4,5,6,7" rgroup.byte 0xC0C++0x0 line.byte 0x0 "TOP_CTRL_ADC_REF_GOOD_STATUS" bitfld.byte 0x0 5. "ADC34_REF_UV_GOOD,Under Voltage check OK" "0,1" newline bitfld.byte 0x0 4. "ADC34_REF_OV_GOOD,Over voltage check OK" "0,1" newline bitfld.byte 0x0 3. "ADC12_REF_UV_GOOD,Under Voltage check OK" "0,1" newline bitfld.byte 0x0 2. "ADC12_REF_OV_GOOD,Over voltage check OK" "0,1" newline bitfld.byte 0x0 1. "ADC0_REF_UV_GOOD,Under Voltage check OK" "0,1" newline bitfld.byte 0x0 0. "ADC0_REF_OV_GOOD,Over voltage check OK" "0,1" group.long 0xC10++0x3 line.long 0x0 "TOP_CTRL_VMON_CTRL" bitfld.long 0x0 24.--26. "CMP8_EN,VMON EN" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "CMP7_EN,VMON EN" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "CMP5_EN,VMON EN" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "CMP3_EN,VMON EN" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "CMP2_EN,VMON EN" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "CMP1_EN,VMON EN" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "CMP0_EN,VMON EN" "0,1,2,3,4,5,6,7" rgroup.word 0xC14++0x1 line.word 0x0 "TOP_CTRL_VMON_STAT" bitfld.word 0x0 10. "CMP8_UV_OK,VMON OK" "0,1" newline bitfld.word 0x0 9. "CMP7_UV_OK,VMON OK" "0,1" newline bitfld.word 0x0 8. "CMP5_UV_OK,VMON OK" "0,1" newline bitfld.word 0x0 7. "CMP5_OV_OK,VMON OK" "0,1" newline bitfld.word 0x0 6. "CMP3_UV_OK,VMON OK" "0,1" newline bitfld.word 0x0 5. "CMP3_OV_OK,VMON OK" "0,1" newline bitfld.word 0x0 4. "CMP2_UV_OK,VMON OK" "0,1" newline bitfld.word 0x0 3. "CMP2_OV_OK,VMON OK" "0,1" newline bitfld.word 0x0 2. "CMP1_UV_OK,VMON OK" "0,1" newline bitfld.word 0x0 1. "CMP1_OV_OK,VMON OK" "0,1" newline bitfld.word 0x0 0. "CMP0_UV_OK,VMON OK" "0,1" rgroup.byte 0xC18++0x0 line.byte 0x0 "TOP_CTRL_PMU_COARSE_STAT" bitfld.byte 0x0 3. "VSUP18_RDY,Coarse VMON OK" "0,1" newline bitfld.byte 0x0 2. "VCORE_RDY,Coarse VMON OK" "0,1" newline bitfld.byte 0x0 1. "LDO_RDY,Coarse VMON OK" "0,1" newline bitfld.byte 0x0 0. "BG_RDY,Coarse VMON OK" "0,1" group.long 0xC20++0x7 line.long 0x0 "TOP_CTRL_MASK_VMON_ERROR_ESM_H" bitfld.long 0x0 16. "ADC34_REF_UV_MASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 15. "ADC34_REF_OV_MASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 14. "ADC12_REF_UV_MASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 13. "ADC12_REF_OV_MASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 12. "ADC0_REF_UV_MASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 11. "ADC0_REF_OV_MASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 10. "CMP8_UV_ERR_MASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 9. "CMP7_UV_ERR_MASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 8. "CMP5_UV_ERR_MASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 7. "CMP5_OV_ERR_MASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 6. "CMP3_UV_ERR_MASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 5. "CMP3_OV_ERR_MASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 4. "CMP2_UV_ERR_MASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 3. "CMP2_OV_ERR_MASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 2. "CMP1_UV_ERR_NASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 1. "CMP1_OV_ERR_MASK,VMON Error Mask to ESM" "0,1" newline bitfld.long 0x0 0. "CMP0_UV_ERR_MASK,VMON Error Mask to ESM" "0,1" line.long 0x4 "TOP_CTRL_MASK_VMON_ERROR_ESM_L" bitfld.long 0x4 16. "ADC34_REF_UV_MASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 15. "ADC34_REF_OV_MASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 14. "ADC12_REF_UV_MASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 13. "ADC12_REF_OV_MASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 12. "ADC0_REF_UV_MASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 11. "ADC0_REF_OV_MASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 10. "CMP8_UV_ERR_MASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 9. "CMP7_UV_ERR_MASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 8. "CMP5_UV_ERR_MASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 7. "CMP5_OV_ERR_MASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 6. "CMP3_UV_ERR_MASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 5. "CMP3_OV_ERR_MASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 4. "CMP2_UV_ERR_MASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 3. "CMP2_OV_ERR_MASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 2. "CMP1_UV_ERR_NASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 1. "CMP1_OV_ERR_MASK,VMON Error Mask to INTR" "0,1" newline bitfld.long 0x4 0. "CMP0_UV_ERR_MASK,VMON Error Mask to INTR" "0,1" group.byte 0xC30++0x0 line.byte 0x0 "TOP_CTRL_MASK_ANA_ISO" bitfld.byte 0x0 0.--2. "MASK,Mask the Ana ISO generating SOC reset due to a glitch on VDD OK.Used during Trim updates to the analog or during ADC Refbuf enable" "0,1,2,3,4,5,6,7" group.byte 0xC34++0x0 line.byte 0x0 "TOP_CTRL_VMON_FILTER_CTRL" bitfld.byte 0x0 0.--1. "SELECT_VALUE,VMON FILTER control select00 : no filtering (default)01 : filtering for 4.8us10 : filtering for 9.6us11 : filtering for 14.4us" "?,1: filtering for 4,?,?" group.long 0xD00++0x3 line.long 0x0 "TOP_CTRL_TSENSE_CFG" bitfld.long 0x0 28. "TMPSOFF,Temperature sensor off0 : on1 : off" "0,1" newline bitfld.long 0x0 24. "BGROFF,BandGap on/off control 1 : off 0 : on" "0: on,1: off" newline bitfld.long 0x0 20. "AIPOFF,1 : iddq mode select 0 : normal mode" "0: normal mode,1: iddq mode select" newline bitfld.long 0x0 16. "SNSR_MX_HIZ,sensor mux hiz control0 : normal operation. Mux will select either one of the anlaog sensor 1 : mux will be high impedence" "?,1: mux will be high impedence" newline hexmask.long.byte 0x0 8.--13. 1. "DELAY,number of wait clock cycles between each TMPS Readout. Configure a Non zero value as delay value since configuring 0 is not allowed" newline hexmask.long.byte 0x0 4.--7. 1. "SENSOR_SEL,Sensor Selection sensor enable bits for each sensor 0 : sensor disable 1 : sensor enablebit 3: temp_sensor3bit 2: temp_sensor2bit 1: temp_sensor1bit 0: temp_sensor0" newline bitfld.long 0x0 0. "ENABLE,Temperature controller enable" "0,1" rgroup.byte 0xD04++0x0 line.byte 0x0 "TOP_CTRL_TSENSE_STATUS" bitfld.byte 0x0 6. "S1_COLD,temperature Sensor 1 cold event detect0 : event not occured1 : event occurred" "0,1" newline bitfld.byte 0x0 5. "S1_HOT,temperature Sensor 1 hot event detect0 : event not occured1 : event occurred" "0,1" newline bitfld.byte 0x0 4. "S1_LOW_THRHLD,temperature Sensor 1 low threshold event detect0 : event not occured1 : event occurred" "0,1" newline bitfld.byte 0x0 2. "S0_COLD,temperature Sensor 0 cold event detect0 : event not occured1 : event occurred" "0,1" newline bitfld.byte 0x0 1. "S0_HOT,temperature Sensor 0 hot event detect0 : event not occured1 : event occurred" "0,1" newline bitfld.byte 0x0 0. "S0_LOW_THRHLD,temperature Sensor 0 low threshold event detect0 : event not occured1 : event occurred" "0,1" rgroup.byte 0xD08++0x0 line.byte 0x0 "TOP_CTRL_TSENSE_STATUS_RAW" bitfld.byte 0x0 6. "S1_COLD,temperature Sensor 1 cold event detect0 : event not occured1 : event occurred" "0,1" newline bitfld.byte 0x0 5. "S1_HOT,temperature Sensor 1 hot event detect0 : event not occured1 : event occurred" "0,1" newline bitfld.byte 0x0 4. "S1_LOW_THRHLD,temperature Sensor 1 low threshold event detect0 : event not occured1 : event occurred" "0,1" newline bitfld.byte 0x0 2. "S0_COLD,temperature Sensor 0 cold event detect0 : event not occured1 : event occurred" "0,1" newline bitfld.byte 0x0 1. "S0_HOT,temperature Sensor 0 hot event detect0 : event not occured1 : event occurred" "0,1" newline bitfld.byte 0x0 0. "S0_LOW_THRHLD,temperature Sensor 0 low threshold event detect0 : event not occured1 : event occurred" "0,1" group.long 0xD10++0x3 line.long 0x0 "TOP_CTRL_TSENSE0_TSHUT" bitfld.long 0x0 29.--31. "EFUSE_OVERRIDE,Efuse override000 -- Value from EFUSE is used as tshut hot and tshut cold thresholds111 - Overide value takes effect" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--23. 1. "TSHUT_THRHLD_HOT,tshut hot threshold. Reads efuse value untill overwritten with override = 111" newline hexmask.long.byte 0x0 0.--7. 1. "TSHUT_THRSHLD_COLD,tshut cold threshold. Reads efuse value untill overwritten with override = 111" group.tbyte 0xD14++0x2 line.tbyte 0x0 "TOP_CTRL_TSENSE0_ALERT" hexmask.tbyte.byte 0x0 16.--23. 1. "ALERT_THRHLD_HOT,hot threshold/high temp threshold" newline hexmask.tbyte.byte 0x0 0.--7. 1. "ALERT_THRHLD_COLD,cold threshold/low temp threshold" group.long 0xD18++0x3 line.long 0x0 "TOP_CTRL_TSENSE0_CNTL" bitfld.long 0x0 24. "MASK_LOW_THRHLD,mask low threshold comparator output" "0,1" newline bitfld.long 0x0 20. "MASK_COLD,mask cold comparator output" "0,1" newline bitfld.long 0x0 16. "MASK_HOT,Mask hot comparator output" "0,1" newline bitfld.long 0x0 8. "ACCU_CLEAR,accumulator clear" "0,1" newline bitfld.long 0x0 4. "FIFO_FREEZE,fifo freeze" "0,1" newline bitfld.long 0x0 0. "FIFO_CLEAR,fifo clear" "0,1" rgroup.long 0xD1C++0x17 line.long 0x0 "TOP_CTRL_TSENSE0_RESULT" bitfld.long 0x0 16. "ECOZ,Conversion in Progress.1 : Conversion on going0 : conversion completed" "?,1: Conversion on going0 : conversion completed" newline hexmask.long.byte 0x0 0.--7. 1. "DTEMP,Temp Code readout" line.long 0x4 "TOP_CTRL_TSENSE0_DATA0" hexmask.long.tbyte 0x4 8.--31. 1. "TAG,tag 0" newline hexmask.long.byte 0x4 0.--7. 1. "DATA,fifo data 0" line.long 0x8 "TOP_CTRL_TSENSE0_DATA1" hexmask.long.tbyte 0x8 8.--31. 1. "TAG,tag 1" newline hexmask.long.byte 0x8 0.--7. 1. "DATA,fifo data 1" line.long 0xC "TOP_CTRL_TSENSE0_DATA2" hexmask.long.tbyte 0xC 8.--31. 1. "TAG,tag 2" newline hexmask.long.byte 0xC 0.--7. 1. "DATA,fifo data 2" line.long 0x10 "TOP_CTRL_TSENSE0_DATA3" hexmask.long.tbyte 0x10 8.--31. 1. "TAG,tag 3" newline hexmask.long.byte 0x10 0.--7. 1. "DATA,fifo data 3" line.long 0x14 "TOP_CTRL_TSENSE0_ACCU" hexmask.long 0x14 0.--31. 1. "CUMUL,cumulative sum of past DTEMPs" group.long 0xD40++0x3 line.long 0x0 "TOP_CTRL_TSENSE1_TSHUT" bitfld.long 0x0 29.--31. "EFUSE_OVERRIDE,Efuse override000 -- Value from EFUSE is used as tshut hot and tshut cold thresholds111 - Overide value takes effect" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--23. 1. "TSHUT_THRHLD_HOT,tshut hot threshold. Reads efuse value untill overwritten with override = 111" newline hexmask.long.byte 0x0 0.--7. 1. "TSHUT_THRSHLD_COLD,tshut cold threshold. Reads efuse value untill overwritten with override = 111" group.tbyte 0xD44++0x2 line.tbyte 0x0 "TOP_CTRL_TSENSE1_ALERT" hexmask.tbyte.byte 0x0 16.--23. 1. "ALERT_THRHLD_HOT,hot threshold/high temp threshold" newline hexmask.tbyte.byte 0x0 0.--7. 1. "ALERT_THRHLD_COLD,cold threshold/low temp threshold" group.long 0xD48++0x3 line.long 0x0 "TOP_CTRL_TSENSE1_CNTL" bitfld.long 0x0 24. "MASK_LOW_THRHLD,mask low threshold comparator output" "0,1" newline bitfld.long 0x0 20. "MASK_COLD,mask cold comparator output" "0,1" newline bitfld.long 0x0 16. "MASK_HOT,Mask hot comparator output" "0,1" newline bitfld.long 0x0 8. "ACCU_CLEAR,accumulator clear" "0,1" newline bitfld.long 0x0 4. "FIFO_FREEZE,fifo freeze" "0,1" newline bitfld.long 0x0 0. "FIFO_CLEAR,fifo clear" "0,1" rgroup.long 0xD4C++0x17 line.long 0x0 "TOP_CTRL_TSENSE1_RESULT" bitfld.long 0x0 16. "ECOZ,Conversion in Progress.1 : Conversion on going0 : conversion completed" "?,1: Conversion on going0 : conversion completed" newline hexmask.long.byte 0x0 0.--7. 1. "DTEMP,Temp Code readout" line.long 0x4 "TOP_CTRL_TSENSE1_DATA0" hexmask.long.tbyte 0x4 8.--31. 1. "TAG,tag 0" newline hexmask.long.byte 0x4 0.--7. 1. "DATA,fifo data 0" line.long 0x8 "TOP_CTRL_TSENSE1_DATA1" hexmask.long.tbyte 0x8 8.--31. 1. "TAG,tag 1" newline hexmask.long.byte 0x8 0.--7. 1. "DATA,fifo data 1" line.long 0xC "TOP_CTRL_TSENSE1_DATA2" hexmask.long.tbyte 0xC 8.--31. 1. "TAG,tag 2" newline hexmask.long.byte 0xC 0.--7. 1. "DATA,fifo data 2" line.long 0x10 "TOP_CTRL_TSENSE1_DATA3" hexmask.long.tbyte 0x10 8.--31. 1. "TAG,tag 3" newline hexmask.long.byte 0x10 0.--7. 1. "DATA,fifo data 3" line.long 0x14 "TOP_CTRL_TSENSE1_ACCU" hexmask.long 0x14 0.--31. 1. "CUMUL,cumulative sum of past DTEMPs" rgroup.long 0xD7C++0x3 line.long 0x0 "TOP_CTRL_TSENSE2_RESULT" bitfld.long 0x0 16. "ECOZ,Conversion in Progress.1 : Conversion on going0 : conversion completed" "?,1: Conversion on going0 : conversion completed" newline hexmask.long.byte 0x0 0.--7. 1. "DTEMP,Temp Code readout" rgroup.long 0xDAC++0x3 line.long 0x0 "TOP_CTRL_TSENSE3_RESULT" bitfld.long 0x0 16. "ECOZ,Conversion in Progress.1 : Conversion on going0 : conversion completed" "?,1: Conversion on going0 : conversion completed" newline hexmask.long.byte 0x0 0.--7. 1. "DTEMP,Temp Code readout" group.byte 0xE00++0x0 line.byte 0x0 "TOP_CTRL_DFT_ATB_GLOBALEN_ADC_CSS" bitfld.byte 0x0 4. "ATB_GLOBALEN_ADC4_CSS,ADC does not use 3V ATB This signal is used to enable master 3V & 1.8V switch (gates all cmpss 3V ATB access and cmpss+adc 1.8V atb access)" "0,1" newline bitfld.byte 0x0 3. "ATB_GLOBALEN_ADC3_CSS,ADC does not use 3V ATB This signal is used to enable master 3V & 1.8V switch (gates all cmpss 3V ATB access and cmpss+adc 1.8V atb access)" "0,1" newline bitfld.byte 0x0 2. "ATB_GLOBALEN_ADC2_CSS,ADC does not use 3V ATB This signal is used to enable master 3V & 1.8V switch (gates all cmpss 3V ATB access and cmpss+adc 1.8V atb access)" "0,1" newline bitfld.byte 0x0 1. "ATB_GLOBALEN_ADC1_CSS,ADC does not use 3V ATB This signal is used to enable master 3V & 1.8V switch (gates all cmpss 3V ATB access and cmpss+adc 1.8V atb access)" "0,1" newline bitfld.byte 0x0 0. "ATB_GLOBALEN_ADC0_CSS,ADC does not use 3V ATB This signal is used to enable master 3V & 1.8V switch (gates all cmpss 3V ATB access and cmpss+adc 1.8V atb access)" "0,1" group.long 0xE04++0x7 line.long 0x0 "TOP_CTRL_DFT_ATB0_MASTEREN_ADC_CSS_DAC" bitfld.long 0x0 25. "DAC_ATB0_MASTEREN,Master Enable : atb0 of dac12" "0,1" newline bitfld.long 0x0 24. "CSS4B1_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b1" "0,1" newline bitfld.long 0x0 23. "CSS3B1_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b1" "0,1" newline bitfld.long 0x0 22. "CSS2B1_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b1" "0,1" newline bitfld.long 0x0 21. "CSS1B1_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b1" "0,1" newline bitfld.long 0x0 20. "CSS0B1_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b1" "0,1" newline bitfld.long 0x0 19. "CSS4B0_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b0" "0,1" newline bitfld.long 0x0 18. "CSS3B0_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b0" "0,1" newline bitfld.long 0x0 17. "CSS2B0_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b0" "0,1" newline bitfld.long 0x0 16. "CSS1B0_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b0" "0,1" newline bitfld.long 0x0 15. "CSS0B0_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b0" "0,1" newline bitfld.long 0x0 14. "CSS4A1_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a1" "0,1" newline bitfld.long 0x0 13. "CSS3A1_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a1" "0,1" newline bitfld.long 0x0 12. "CSS2A1_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a1" "0,1" newline bitfld.long 0x0 11. "CSS1A1_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a1" "0,1" newline bitfld.long 0x0 10. "CSS0A1_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a1" "0,1" newline bitfld.long 0x0 9. "CSS4A0_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a0" "0,1" newline bitfld.long 0x0 8. "CSS3A0_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a0" "0,1" newline bitfld.long 0x0 7. "CSS2A0_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a0" "0,1" newline bitfld.long 0x0 6. "CSS1A0_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a0" "0,1" newline bitfld.long 0x0 5. "CSS0A0_ATB0_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a0" "0,1" newline bitfld.long 0x0 4. "ADC4_ATB0_MASTEREN,Master Enable : atb0 of corresponding adc" "0,1" newline bitfld.long 0x0 3. "ADC3_ATB0_MASTEREN,Master Enable : atb0 of corresponding adc" "0,1" newline bitfld.long 0x0 2. "ADC2_ATB0_MASTEREN,Master Enable : atb0 of corresponding adc" "0,1" newline bitfld.long 0x0 1. "ADC1_ATB0_MASTEREN,Master Enable : atb0 of corresponding adc" "0,1" newline bitfld.long 0x0 0. "ADC0_ATB0_MASTEREN,Master Enable : atb0 of corresponding adc" "0,1" line.long 0x4 "TOP_CTRL_DFT_ATB1_MASTEREN_ADC_CSS_DAC" bitfld.long 0x4 25. "DAC_ATB1_MASTEREN,Master Enable : atb0 of dac12" "0,1" newline bitfld.long 0x4 24. "CSS4B1_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b1" "0,1" newline bitfld.long 0x4 23. "CSS3B1_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b1" "0,1" newline bitfld.long 0x4 22. "CSS2B1_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b1" "0,1" newline bitfld.long 0x4 21. "CSS1B1_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b1" "0,1" newline bitfld.long 0x4 20. "CSS0B1_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b1" "0,1" newline bitfld.long 0x4 19. "CSS4B0_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b0" "0,1" newline bitfld.long 0x4 18. "CSS3B0_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b0" "0,1" newline bitfld.long 0x4 17. "CSS2B0_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b0" "0,1" newline bitfld.long 0x4 16. "CSS1B0_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b0" "0,1" newline bitfld.long 0x4 15. "CSS0B0_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-b0" "0,1" newline bitfld.long 0x4 14. "CSS4A1_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a1" "0,1" newline bitfld.long 0x4 13. "CSS3A1_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a1" "0,1" newline bitfld.long 0x4 12. "CSS2A1_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a1" "0,1" newline bitfld.long 0x4 11. "CSS1A1_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a1" "0,1" newline bitfld.long 0x4 10. "CSS0A1_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a1" "0,1" newline bitfld.long 0x4 9. "CSS4A0_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a0" "0,1" newline bitfld.long 0x4 8. "CSS3A0_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a0" "0,1" newline bitfld.long 0x4 7. "CSS2A0_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a0" "0,1" newline bitfld.long 0x4 6. "CSS1A0_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a0" "0,1" newline bitfld.long 0x4 5. "CSS0A0_ATB1_MASTEREN,Master Enable : atb0 of corresponding subsystems cmpss-a0" "0,1" group.word 0xE0C++0x1 line.word 0x0 "TOP_CTRL_DFT_PMU_REFSYS_SAFETY" bitfld.word 0x0 15. "RCOSC_STOP,0:rc enabled 1: stops rcosc clock" "0: rc enabled,1: stops rcosc clock" newline bitfld.word 0x0 14. "BG_DIS,Bandgap disable signal.1'b0 = Bandgap enabled. 1'b1 = Badgap disabled" "0: Bandgap enabled,1: Badgap disabled" newline bitfld.word 0x0 13. "BG_FLIPEN_CTRL,Bandgap flipen control for amplifier offset correction during trimming.1'b0 => normal operation; 1'b1 => AMP inputs flipped." "0: normal operation,1: AMP inputs flipped" newline bitfld.word 0x0 12. "LDO_DIS,Disables LDO if set '1'" "0,1" newline bitfld.word 0x0 9.--11. "ATB_MUX_SEL_SAFETYCOMP,Selects analog signals for atestoutput for each of the test modes of the safety comparators according to test mode controlled by tb_ctrl_1p1v<83:82> : Test Mode 1 (tb_ctrl_1p1v<83:82>='b01): C5 & C20: HIZ 1: vssa of C5; 2:vth_lo of.." "?,1: vssa of C1,2: vth_lo of C1,3: vth_hi of C1,4: vssa of C0,5: vmon of C0,6: vref of C0,7: HIZSelects Analog Test Signals for Temperature.." newline bitfld.word 0x0 7.--8. "ATB_EN_SAFETYCOMP,Enables three different test modes for safety comparators: 00: HIZ01: Test Mode1 enable10: Test Mode 2 enable11: Test Mode 3 enable" "0: HIZ01: Test Mode1 enable10: Test Mode 2..,?,?,?" newline bitfld.word 0x0 6. "ATB_EN_TS,Analog test mode enable for temperature sesnsor" "0,1" newline bitfld.word 0x0 5. "ATB_EN_BG,Bandgap atest enabled" "0,1" newline bitfld.word 0x0 4. "ATB_EN_LDO,LDO atest enabled." "0,1" newline bitfld.word 0x0 3. "ATB_EN_SYSBOOT,atest enable pins for PMU. Only one bit should be high at a time.system boot logic atest enabled." "0,1" newline bitfld.word 0x0 0.--2. "ATB_MUX_SEL_PMU_REFSYS,Common atest channel selection bits for bandgap sysboot and LDO.Decoded to enable 8 channels of each module." "0,1,2,3,4,5,6,7" group.long 0xE10++0x3 line.long 0x0 "TOP_CTRL_DFT_ANA_DTB_ENABLES" bitfld.long 0x0 25. "DAC_DTB_MASTEREN,Master Enable : dtb0 of dac12" "0,1" newline bitfld.long 0x0 24. "CSS4B1_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-b1" "0,1" newline bitfld.long 0x0 23. "CSS3B1_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-b1" "0,1" newline bitfld.long 0x0 22. "CSS2B1_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-b1" "0,1" newline bitfld.long 0x0 21. "CSS1B1_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-b1" "0,1" newline bitfld.long 0x0 20. "CSS0B1_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-b1" "0,1" newline bitfld.long 0x0 19. "CSS4B0_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-b0" "0,1" newline bitfld.long 0x0 18. "CSS3B0_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-b0" "0,1" newline bitfld.long 0x0 17. "CSS2B0_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-b0" "0,1" newline bitfld.long 0x0 16. "CSS1B0_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-b0" "0,1" newline bitfld.long 0x0 15. "CSS0B0_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-b0" "0,1" newline bitfld.long 0x0 14. "CSS4A1_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-a1" "0,1" newline bitfld.long 0x0 13. "CSS3A1_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-a1" "0,1" newline bitfld.long 0x0 12. "CSS2A1_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-a1" "0,1" newline bitfld.long 0x0 11. "CSS1A1_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-a1" "0,1" newline bitfld.long 0x0 10. "CSS0A1_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-a1" "0,1" newline bitfld.long 0x0 9. "CSS4A0_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-a0" "0,1" newline bitfld.long 0x0 8. "CSS3A0_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-a0" "0,1" newline bitfld.long 0x0 7. "CSS2A0_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-a0" "0,1" newline bitfld.long 0x0 6. "CSS1A0_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-a0" "0,1" newline bitfld.long 0x0 5. "CSS0A0_DTB_MASTEREN,Master Enable : dtb0 of corresponding subsystems cmpss-a0" "0,1" newline bitfld.long 0x0 4. "ADC4_DTB_MASTEREN,Master Enable : dtb0 of corresponding adc" "0,1" newline bitfld.long 0x0 3. "ADC3_DTB_MASTEREN,Master Enable : dtb0 of corresponding adc" "0,1" newline bitfld.long 0x0 2. "ADC2_DTB_MASTEREN,Master Enable : dtb0 of corresponding adc" "0,1" newline bitfld.long 0x0 1. "ADC1_DTB_MASTEREN,Master Enable : dtb0 of corresponding adc" "0,1" newline bitfld.long 0x0 0. "ADC0_DTB_MASTEREN,Master Enable : dtb0 of corresponding adc" "0,1" group.word 0xE14++0x1 line.word 0x0 "TOP_CTRL_DFT_ADC_CHSEL_OV_CTRL_VALUE" bitfld.word 0x0 10. "ADC_CHSEL_OV_CTRL,1 bit as the override control" "0,1" newline hexmask.word 0x0 0.--9. 1. "ADC_CHSEL,ADC Channel select overrides adcX_ctrl_1p1v signal" group.long 0xE18++0x17 line.long 0x0 "TOP_CTRL_DFT_DAC_CTRL" bitfld.long 0x0 8. "DFT_LOAD_HIGH_EN,Connects 5k resistor between Vout and vdd_3p3v" "0,1" newline bitfld.long 0x0 7. "DFT_LOAD_LOW_EN,Connects 5k resistor between Vout and VSS" "0,1" newline bitfld.long 0x0 6. "IBIAS_20UA_ATB,connects ibias_20uA current sink to test bus" "0,1" newline bitfld.long 0x0 5. "RDAC_VREF_HI_ATB,Connects RDAC VREF_HI to test bus" "0,1" newline bitfld.long 0x0 4. "RDAC_VREF_LOW_ATB,Connects RDAC VREF_LOW to test bus" "0,1" newline bitfld.long 0x0 3. "VSS_ATB,Connects VSS to test bus" "0,1" newline bitfld.long 0x0 2. "VFEEDBACK_ATB,Connects Vfeedback node to test bus" "0,1" newline bitfld.long 0x0 1. "RDAC_VBOT_ATB,Connects RDAC VBOT node to test bus" "0,1" newline bitfld.long 0x0 0. "RDAC_VTOP_ATB,Connects RDAC VTOP node to test bus" "0,1" line.long 0x4 "TOP_CTRL_DFT_CSS01_CTRL" bitfld.long 0x4 24.--25. "CSS1_DTB_MUX_CONFIG,2 b00 = MSB (default)2 b01 = LSB2 b10 = Enable2 b11 = compout" "0: MSB,1: LSB2,2: Enable2,3: compout" newline bitfld.long 0x4 23. "CSS1_DTB_SELECT,1 b0 = dtb connected for compL (default)1 b1 = dtb connected for compH" "0: dtb connected for compL,1: dtb connected for compH" newline bitfld.long 0x4 21.--22. "CSS1_ATB_SELECT,2 b00 = atb off (default)2 b01 = atb enable for compL2 b10 = atb enable for compH2 b11 = both ATB active" "0: atb off,1: atb enable for compL2,2: atb enable for compH2,3: both ATB active" newline hexmask.long.byte 0x4 17.--20. 1. "CSS1_TESTANA_L_ANA_MUX_CONTROL,4 b0000 = 1p8v testana isolated (default)4 b0001 = vref_int4 b0010 = vref_low4 b0011 = vdac<0>4 b0100 = vdac<1>4 b0101 = vss4 b0110 = ibias 10uA ( atleast 1.25v at the pad)4 b0111 = por_ibias 10uA (atleast.." newline bitfld.long 0x4 15.--16. "CSS1_TESTANA_L_SUP_MUX_CONTROL,For: compssa_L POS IN // NEG IN2 b00 = POS Mux control // DAC (default)2 b01 = ATB // DAC (tb_ctrl_1p1v<1> = 1'b1)2 b10 = POS Mux control // ATB (tb_ctrl_1p1v<1> = 1'b1)2 b11 = POS Mux control.." "0: inh // NEG Mux control,1: ATB,2: inh // ATB,3: inh // DAC" newline bitfld.long 0x4 14. "CSS1_COMPOUT_BYPASS_VAL,comparator bypass value" "0,1" newline bitfld.long 0x4 13. "CSS1_COMPOUT_BYPASS_EN,1 b0 = compout is connected to internal comparator (default)1 b1 = compout is equal to compout_bypass_val" "0: compout is connected to internal comparator,1: compout is equal to compout_bypass_val" newline bitfld.long 0x4 11.--12. "CSS0_DTB_MUX_CONFIG,2 b00 = MSB (default)2 b01 = LSB2 b10 = Enable2 b11 = compout" "0: MSB,1: LSB2,2: Enable2,3: compout" newline bitfld.long 0x4 10. "CSS0_DTB_SELECT,1 b0 = dtb connected for compL (default)1 b1 = dtb connected for compH" "0: dtb connected for compL,1: dtb connected for compH" newline bitfld.long 0x4 8.--9. "CSS0_ATB_SELECT,2 b00 = atb off (default)2 b01 = atb enable for compL2 b10 = atb enable for compH2 b11 = both ATB active" "0: atb off,1: atb enable for compL2,2: atb enable for compH2,3: both ATB active" newline hexmask.long.byte 0x4 4.--7. 1. "CSS0_TESTANA_L_ANA_MUX_CONTROL,4 b0000 = 1p8v testana isolated (default)4 b0001 = vref_int4 b0010 = vref_low4 b0011 = vdac<0>4 b0100 = vdac<1>4 b0101 = vss4 b0110 = ibias 10uA ( atleast 1.25v at the pad)4 b0111 = por_ibias 10uA (atleast.." newline bitfld.long 0x4 2.--3. "CSS0_TESTANA_L_SUP_MUX_CONTROL,For: compssa_L POS IN // NEG IN2 b00 = POS Mux control // DAC (default)2 b01 = ATB // DAC (tb_ctrl_1p1v<1> = 1'b1)2 b10 = POS Mux control // ATB (tb_ctrl_1p1v<1> = 1'b1)2 b11 = POS Mux control.." "0: inh // NEG Mux control,1: ATB,2: inh // ATB,3: inh // DAC" newline bitfld.long 0x4 1. "CSS0_COMPOUT_BYPASS_VAL,comparator bypass value" "0,1" newline bitfld.long 0x4 0. "CSS0_COMPOUT_BYPASS_EN,1 b0 = compout is connected to internal comparator (default)1 b1 = compout is equal to compout_bypass_val" "0: compout is connected to internal comparator,1: compout is equal to compout_bypass_val" line.long 0x8 "TOP_CTRL_DFT_CSS23_CTRL" bitfld.long 0x8 24.--25. "CSS3_DTB_MUX_CONFIG,2 b00 = MSB (default)2 b01 = LSB2 b10 = Enable2 b11 = compout" "0: MSB,1: LSB2,2: Enable2,3: compout" newline bitfld.long 0x8 23. "CSS3_DTB_SELECT,1 b0 = dtb connected for compL (default)1 b1 = dtb connected for compH" "0: dtb connected for compL,1: dtb connected for compH" newline bitfld.long 0x8 21.--22. "CSS3_ATB_SELECT,2 b00 = atb off (default)2 b01 = atb enable for compL2 b10 = atb enable for compH2 b11 = both ATB active" "0: atb off,1: atb enable for compL2,2: atb enable for compH2,3: both ATB active" newline hexmask.long.byte 0x8 17.--20. 1. "CSS3_TESTANA_L_ANA_MUX_CONTROL,4 b0000 = 1p8v testana isolated (default)4 b0001 = vref_int4 b0010 = vref_low4 b0011 = vdac<0>4 b0100 = vdac<1>4 b0101 = vss4 b0110 = ibias 10uA ( atleast 1.25v at the pad)4 b0111 = por_ibias 10uA (atleast.." newline bitfld.long 0x8 15.--16. "CSS3_TESTANA_L_SUP_MUX_CONTROL,For: compssa_L POS IN // NEG IN2 b00 = POS Mux control // DAC (default)2 b01 = ATB // DAC (tb_ctrl_1p1v<1> = 1'b1)2 b10 = POS Mux control // ATB (tb_ctrl_1p1v<1> = 1'b1)2 b11 = POS Mux control.." "0: inh // NEG Mux control,1: ATB,2: inh // ATB,3: inh // DAC" newline bitfld.long 0x8 14. "CSS3_COMPOUT_BYPASS_VAL,comparator bypass value" "0,1" newline bitfld.long 0x8 13. "CSS3_COMPOUT_BYPASS_EN,1 b0 = compout is connected to internal comparator (default)1 b1 = compout is equal to compout_bypass_val" "0: compout is connected to internal comparator,1: compout is equal to compout_bypass_val" newline bitfld.long 0x8 11.--12. "CSS2_DTB_MUX_CONFIG,2 b00 = MSB (default)2 b01 = LSB2 b10 = Enable2 b11 = compout" "0: MSB,1: LSB2,2: Enable2,3: compout" newline bitfld.long 0x8 10. "CSS2_DTB_SELECT,1 b0 = dtb connected for compL (default)1 b1 = dtb connected for compH" "0: dtb connected for compL,1: dtb connected for compH" newline bitfld.long 0x8 8.--9. "CSS2_ATB_SELECT,2 b00 = atb off (default)2 b01 = atb enable for compL2 b10 = atb enable for compH2 b11 = both ATB active" "0: atb off,1: atb enable for compL2,2: atb enable for compH2,3: both ATB active" newline hexmask.long.byte 0x8 4.--7. 1. "CSS2_TESTANA_L_ANA_MUX_CONTROL,4 b0000 = 1p8v testana isolated (default)4 b0001 = vref_int4 b0010 = vref_low4 b0011 = vdac<0>4 b0100 = vdac<1>4 b0101 = vss4 b0110 = ibias 10uA ( atleast 1.25v at the pad)4 b0111 = por_ibias 10uA (atleast.." newline bitfld.long 0x8 2.--3. "CSS2_TESTANA_L_SUP_MUX_CONTROL,For: compssa_L POS IN // NEG IN2 b00 = POS Mux control // DAC (default)2 b01 = ATB // DAC (tb_ctrl_1p1v<1> = 1'b1)2 b10 = POS Mux control // ATB (tb_ctrl_1p1v<1> = 1'b1)2 b11 = POS Mux control.." "0: inh // NEG Mux control,1: ATB,2: inh // ATB,3: inh // DAC" newline bitfld.long 0x8 1. "CSS2_COMPOUT_BYPASS_VAL,comparator bypass value" "0,1" newline bitfld.long 0x8 0. "CSS2_COMPOUT_BYPASS_EN,1 b0 = compout is connected to internal comparator (default)1 b1 = compout is equal to compout_bypass_val" "0: compout is connected to internal comparator,1: compout is equal to compout_bypass_val" line.long 0xC "TOP_CTRL_DFT_CSS45_CTRL" bitfld.long 0xC 24.--25. "CSS5_DTB_MUX_CONFIG,2 b00 = MSB (default)2 b01 = LSB2 b10 = Enable2 b11 = compout" "0: MSB,1: LSB2,2: Enable2,3: compout" newline bitfld.long 0xC 23. "CSS5_DTB_SELECT,1 b0 = dtb connected for compL (default)1 b1 = dtb connected for compH" "0: dtb connected for compL,1: dtb connected for compH" newline bitfld.long 0xC 21.--22. "CSS5_ATB_SELECT,2 b00 = atb off (default)2 b01 = atb enable for compL2 b10 = atb enable for compH2 b11 = both ATB active" "0: atb off,1: atb enable for compL2,2: atb enable for compH2,3: both ATB active" newline hexmask.long.byte 0xC 17.--20. 1. "CSS5_TESTANA_L_ANA_MUX_CONTROL,4 b0000 = 1p8v testana isolated (default)4 b0001 = vref_int4 b0010 = vref_low4 b0011 = vdac<0>4 b0100 = vdac<1>4 b0101 = vss4 b0110 = ibias 10uA ( atleast 1.25v at the pad)4 b0111 = por_ibias 10uA (atleast.." newline bitfld.long 0xC 15.--16. "CSS5_TESTANA_L_SUP_MUX_CONTROL,For: compssa_L POS IN // NEG IN2 b00 = POS Mux control // DAC (default)2 b01 = ATB // DAC (tb_ctrl_1p1v<1> = 1'b1)2 b10 = POS Mux control // ATB (tb_ctrl_1p1v<1> = 1'b1)2 b11 = POS Mux control.." "0: inh // NEG Mux control,1: ATB,2: inh // ATB,3: inh // DAC" newline bitfld.long 0xC 14. "CSS5_COMPOUT_BYPASS_VAL,comparator bypass value" "0,1" newline bitfld.long 0xC 13. "CSS5_COMPOUT_BYPASS_EN,1 b0 = compout is connected to internal comparator (default)1 b1 = compout is equal to compout_bypass_val" "0: compout is connected to internal comparator,1: compout is equal to compout_bypass_val" newline bitfld.long 0xC 11.--12. "CSS4_DTB_MUX_CONFIG,2 b00 = MSB (default)2 b01 = LSB2 b10 = Enable2 b11 = compout" "0: MSB,1: LSB2,2: Enable2,3: compout" newline bitfld.long 0xC 10. "CSS4_DTB_SELECT,1 b0 = dtb connected for compL (default)1 b1 = dtb connected for compH" "0: dtb connected for compL,1: dtb connected for compH" newline bitfld.long 0xC 8.--9. "CSS4_ATB_SELECT,2 b00 = atb off (default)2 b01 = atb enable for compL2 b10 = atb enable for compH2 b11 = both ATB active" "0: atb off,1: atb enable for compL2,2: atb enable for compH2,3: both ATB active" newline hexmask.long.byte 0xC 4.--7. 1. "CSS4_TESTANA_L_ANA_MUX_CONTROL,4 b0000 = 1p8v testana isolated (default)4 b0001 = vref_int4 b0010 = vref_low4 b0011 = vdac<0>4 b0100 = vdac<1>4 b0101 = vss4 b0110 = ibias 10uA ( atleast 1.25v at the pad)4 b0111 = por_ibias 10uA (atleast.." newline bitfld.long 0xC 2.--3. "CSS4_TESTANA_L_SUP_MUX_CONTROL,For: compssa_L POS IN // NEG IN2 b00 = POS Mux control // DAC (default)2 b01 = ATB // DAC (tb_ctrl_1p1v<1> = 1'b1)2 b10 = POS Mux control // ATB (tb_ctrl_1p1v<1> = 1'b1)2 b11 = POS Mux control.." "0: inh // NEG Mux control,1: ATB,2: inh // ATB,3: inh // DAC" newline bitfld.long 0xC 1. "CSS4_COMPOUT_BYPASS_VAL,comparator bypass value" "0,1" newline bitfld.long 0xC 0. "CSS4_COMPOUT_BYPASS_EN,1 b0 = compout is connected to internal comparator (default)1 b1 = compout is equal to compout_bypass_val" "0: compout is connected to internal comparator,1: compout is equal to compout_bypass_val" line.long 0x10 "TOP_CTRL_DFT_CSS67_CTRL" bitfld.long 0x10 24.--25. "CSS7_DTB_MUX_CONFIG,2 b00 = MSB (default)2 b01 = LSB2 b10 = Enable2 b11 = compout" "0: MSB,1: LSB2,2: Enable2,3: compout" newline bitfld.long 0x10 23. "CSS7_DTB_SELECT,1 b0 = dtb connected for compL (default)1 b1 = dtb connected for compH" "0: dtb connected for compL,1: dtb connected for compH" newline bitfld.long 0x10 21.--22. "CSS7_ATB_SELECT,2 b00 = atb off (default)2 b01 = atb enable for compL2 b10 = atb enable for compH2 b11 = both ATB active" "0: atb off,1: atb enable for compL2,2: atb enable for compH2,3: both ATB active" newline hexmask.long.byte 0x10 17.--20. 1. "CSS7_TESTANA_L_ANA_MUX_CONTROL,4 b0000 = 1p8v testana isolated (default)4 b0001 = vref_int4 b0010 = vref_low4 b0011 = vdac<0>4 b0100 = vdac<1>4 b0101 = vss4 b0110 = ibias 10uA ( atleast 1.25v at the pad)4 b0111 = por_ibias 10uA (atleast.." newline bitfld.long 0x10 15.--16. "CSS7_TESTANA_L_SUP_MUX_CONTROL,For: compssa_L POS IN // NEG IN2 b00 = POS Mux control // DAC (default)2 b01 = ATB // DAC (tb_ctrl_1p1v<1> = 1'b1)2 b10 = POS Mux control // ATB (tb_ctrl_1p1v<1> = 1'b1)2 b11 = POS Mux control.." "0: inh // NEG Mux control,1: ATB,2: inh // ATB,3: inh // DAC" newline bitfld.long 0x10 14. "CSS7_COMPOUT_BYPASS_VAL,comparator bypass value" "0,1" newline bitfld.long 0x10 13. "CSS7_COMPOUT_BYPASS_EN,1 b0 = compout is connected to internal comparator (default)1 b1 = compout is equal to compout_bypass_val" "0: compout is connected to internal comparator,1: compout is equal to compout_bypass_val" newline bitfld.long 0x10 11.--12. "CSS6_DTB_MUX_CONFIG,2 b00 = MSB (default)2 b01 = LSB2 b10 = Enable2 b11 = compout" "0: MSB,1: LSB2,2: Enable2,3: compout" newline bitfld.long 0x10 10. "CSS6_DTB_SELECT,1 b0 = dtb connected for compL (default)1 b1 = dtb connected for compH" "0: dtb connected for compL,1: dtb connected for compH" newline bitfld.long 0x10 8.--9. "CSS6_ATB_SELECT,2 b00 = atb off (default)2 b01 = atb enable for compL2 b10 = atb enable for compH2 b11 = both ATB active" "0: atb off,1: atb enable for compL2,2: atb enable for compH2,3: both ATB active" newline hexmask.long.byte 0x10 4.--7. 1. "CSS6_TESTANA_L_ANA_MUX_CONTROL,4 b0000 = 1p8v testana isolated (default)4 b0001 = vref_int4 b0010 = vref_low4 b0011 = vdac<0>4 b0100 = vdac<1>4 b0101 = vss4 b0110 = ibias 10uA ( atleast 1.25v at the pad)4 b0111 = por_ibias 10uA (atleast.." newline bitfld.long 0x10 2.--3. "CSS6_TESTANA_L_SUP_MUX_CONTROL,For: compssa_L POS IN // NEG IN2 b00 = POS Mux control // DAC (default)2 b01 = ATB // DAC (tb_ctrl_1p1v<1> = 1'b1)2 b10 = POS Mux control // ATB (tb_ctrl_1p1v<1> = 1'b1)2 b11 = POS Mux control.." "0: inh // NEG Mux control,1: ATB,2: inh // ATB,3: inh // DAC" newline bitfld.long 0x10 1. "CSS6_COMPOUT_BYPASS_VAL,comparator bypass value" "0,1" newline bitfld.long 0x10 0. "CSS6_COMPOUT_BYPASS_EN,1 b0 = compout is connected to internal comparator (default)1 b1 = compout is equal to compout_bypass_val" "0: compout is connected to internal comparator,1: compout is equal to compout_bypass_val" line.long 0x14 "TOP_CTRL_DFT_CSS89_CTRL" bitfld.long 0x14 24.--25. "CSS9_DTB_MUX_CONFIG,2 b00 = MSB (default)2 b01 = LSB2 b10 = Enable2 b11 = compout" "0: MSB,1: LSB2,2: Enable2,3: compout" newline bitfld.long 0x14 23. "CSS9_DTB_SELECT,1 b0 = dtb connected for compL (default)1 b1 = dtb connected for compH" "0: dtb connected for compL,1: dtb connected for compH" newline bitfld.long 0x14 21.--22. "CSS9_ATB_SELECT,2 b00 = atb off (default)2 b01 = atb enable for compL2 b10 = atb enable for compH2 b11 = both ATB active" "0: atb off,1: atb enable for compL2,2: atb enable for compH2,3: both ATB active" newline hexmask.long.byte 0x14 17.--20. 1. "CSS9_TESTANA_L_ANA_MUX_CONTROL,4 b0000 = 1p8v testana isolated (default)4 b0001 = vref_int4 b0010 = vref_low4 b0011 = vdac<0>4 b0100 = vdac<1>4 b0101 = vss4 b0110 = ibias 10uA ( atleast 1.25v at the pad)4 b0111 = por_ibias 10uA (atleast.." newline bitfld.long 0x14 15.--16. "CSS9_TESTANA_L_SUP_MUX_CONTROL,For: compssa_L POS IN // NEG IN2 b00 = POS Mux control // DAC (default)2 b01 = ATB // DAC (tb_ctrl_1p1v<1> = 1'b1)2 b10 = POS Mux control // ATB (tb_ctrl_1p1v<1> = 1'b1)2 b11 = POS Mux control.." "0: inh // NEG Mux control,1: ATB,2: inh // ATB,3: inh // DAC" newline bitfld.long 0x14 14. "CSS9_COMPOUT_BYPASS_VAL,comparator bypass value" "0,1" newline bitfld.long 0x14 13. "CSS9_COMPOUT_BYPASS_EN,1 b0 = compout is connected to internal comparator (default)1 b1 = compout is equal to compout_bypass_val" "0: compout is connected to internal comparator,1: compout is equal to compout_bypass_val" newline bitfld.long 0x14 11.--12. "CSS8_DTB_MUX_CONFIG,2 b00 = MSB (default)2 b01 = LSB2 b10 = Enable2 b11 = compout" "0: MSB,1: LSB2,2: Enable2,3: compout" newline bitfld.long 0x14 10. "CSS8_DTB_SELECT,1 b0 = dtb connected for compL (default)1 b1 = dtb connected for compH" "0: dtb connected for compL,1: dtb connected for compH" newline bitfld.long 0x14 8.--9. "CSS8_ATB_SELECT,2 b00 = atb off (default)2 b01 = atb enable for compL2 b10 = atb enable for compH2 b11 = both ATB active" "0: atb off,1: atb enable for compL2,2: atb enable for compH2,3: both ATB active" newline hexmask.long.byte 0x14 4.--7. 1. "CSS8_TESTANA_L_ANA_MUX_CONTROL,4 b0000 = 1p8v testana isolated (default)4 b0001 = vref_int4 b0010 = vref_low4 b0011 = vdac<0>4 b0100 = vdac<1>4 b0101 = vss4 b0110 = ibias 10uA ( atleast 1.25v at the pad)4 b0111 = por_ibias 10uA (atleast.." newline bitfld.long 0x14 2.--3. "CSS8_TESTANA_L_SUP_MUX_CONTROL,For: compssa_L POS IN // NEG IN2 b00 = POS Mux control // DAC (default)2 b01 = ATB // DAC (tb_ctrl_1p1v<1> = 1'b1)2 b10 = POS Mux control // ATB (tb_ctrl_1p1v<1> = 1'b1)2 b11 = POS Mux control.." "0: inh // NEG Mux control,1: ATB,2: inh // ATB,3: inh // DAC" newline bitfld.long 0x14 1. "CSS8_COMPOUT_BYPASS_VAL,comparator bypass value" "0,1" newline bitfld.long 0x14 0. "CSS8_COMPOUT_BYPASS_EN,1 b0 = compout is connected to internal comparator (default)1 b1 = compout is equal to compout_bypass_val" "0: compout is connected to internal comparator,1: compout is equal to compout_bypass_val" group.tbyte 0xE30++0x2 line.tbyte 0x0 "TOP_CTRL_DFT_RAMP_DACL" hexmask.tbyte 0x0 0.--19. 1. "RAMP_DACL,Fanout internal ramp to DACL of the CMPSS (currently reserved)" group.word 0xE34++0x1 line.word 0x0 "TOP_CTRL_DFT_REFBUF_CTRL" bitfld.word 0x0 7.--8. "REFBUF1_ATB_MUX_SEL,Analog test select controls for reference buffer and comparators" "0,1,2,3" newline bitfld.word 0x0 5.--6. "REFBUF0_ATB_MUX_SEL,Analog test select controls for reference buffer and comparators" "0,1,2,3" newline bitfld.word 0x0 4. "REFBUF1_ATBEN,Atest enable REFBUF1" "0,1" newline bitfld.word 0x0 3. "REFBUF1_ATBEN_ROK1,analog test enable for the comparators ROK1" "0,1" newline bitfld.word 0x0 2. "REFBUF0_ATBEN,Atest enable REFBUF0" "0,1" newline bitfld.word 0x0 1. "REFBUF0_ATBEN_ROK0,analog test enable for the comparators ROK0" "0,1" newline bitfld.word 0x0 0. "REFBUF0_ATBEN_ROK0B,analog test enable for the comparators ROK0B" "0,1" group.long 0xE38++0x3 line.long 0x0 "TOP_CTRL_DFT_ODP_ATB_LOOPBACK_CTRL" hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved bits" newline bitfld.long 0x0 2. "ATB1_ADCCAL1_LB,if '1' connects atestv1 to adc_cal1" "0,1" newline bitfld.long 0x0 1. "ATB0_ADCCAL0_LB,if '1' connects atestv0 to adc_cal0 (must ensure adc_cal0 is not driven)" "0,1" newline bitfld.long 0x0 0. "ODP_EN,must set '1' to test odp module" "0,1" group.byte 0xE3C++0x0 line.byte 0x0 "TOP_CTRL_DFT_SOC_DTB_MUX_SEL" hexmask.byte 0x0 0.--7. 1. "DTB_MUX_SEL,Mux selection controls for selecting the DTB lines going out of SOC for debug purpose and for testing." group.byte 0xE40++0x0 line.byte 0x0 "TOP_CTRL_DFT_TEMPSENSE_CTRL" bitfld.byte 0x0 0. "SENSOR5_SEL,Sensor control for 5th local sensor" "0,1" group.long 0xE44++0xF line.long 0x0 "TOP_CTRL_DFT_CTRL_1" hexmask.long 0x0 0.--31. 1. "RESERVED,Reserved bits" line.long 0x4 "TOP_CTRL_DFT_CTRL_2" hexmask.long 0x4 0.--31. 1. "RESERVED,Reserved bits" line.long 0x8 "TOP_CTRL_DFT_CTRL_3" hexmask.long 0x8 0.--31. 1. "RESERVED,Reserved bits" line.long 0xC "TOP_CTRL_DFT_CTRL_4" hexmask.long 0xC 0.--31. 1. "RESERVED,Reserved bits" group.long 0xF04++0x7 line.long 0x0 "TOP_CTRL_PROBE_BUS_SEL0" hexmask.long 0x0 0.--31. 1. "SEL,Probe Bus 0 Mux Select" line.long 0x4 "TOP_CTRL_PROBE_BUS_SEL1" hexmask.long 0x4 0.--31. 1. "SEL,Probe Bus 1 Mux Select" group.long 0xFD0++0xF line.long 0x0 "TOP_CTRL_HW_SPARE_RW0" hexmask.long 0x0 0.--31. 1. "HW_SPARE_RW0,Reserved for HW R&D" line.long 0x4 "TOP_CTRL_HW_SPARE_RW1" hexmask.long 0x4 0.--31. 1. "HW_SPARE_RW1,Reserved for HW R&D" line.long 0x8 "TOP_CTRL_HW_SPARE_RW2" hexmask.long 0x8 0.--31. 1. "HW_SPARE_RW2,Reserved for HW R&D" line.long 0xC "TOP_CTRL_HW_SPARE_RW3" hexmask.long 0xC 0.--31. 1. "HW_SPARE_RW3,Reserved for HW R&D" rgroup.long 0xFE0++0xF line.long 0x0 "TOP_CTRL_HW_SPARE_RO0" hexmask.long 0x0 0.--31. 1. "HW_SPARE_RO0,Reserved for HW R&D" line.long 0x4 "TOP_CTRL_HW_SPARE_RO1" hexmask.long 0x4 0.--31. 1. "HW_SPARE_RO1,Reserved for HW R&D" line.long 0x8 "TOP_CTRL_HW_SPARE_RO2" hexmask.long 0x8 0.--31. 1. "HW_SPARE_RO2,Reserved for HW R&D" line.long 0xC "TOP_CTRL_HW_SPARE_RO3" hexmask.long 0xC 0.--31. 1. "HW_SPARE_RO3,Reserved for HW R&D" group.long 0xFF0++0xF line.long 0x0 "TOP_CTRL_HW_SPARE_WPH" hexmask.long 0x0 0.--31. 1. "HW_SPARE_WPH,Reserved for HW R&D" line.long 0x4 "TOP_CTRL_HW_SPARE_REC" bitfld.long 0x4 31. "HW_SPARE_REC31,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 30. "HW_SPARE_REC30,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 29. "HW_SPARE_REC29,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 28. "HW_SPARE_REC28,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 27. "HW_SPARE_REC27,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 26. "HW_SPARE_REC26,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 25. "HW_SPARE_REC25,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 24. "HW_SPARE_REC24,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 23. "HW_SPARE_REC23,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 22. "HW_SPARE_REC22,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 21. "HW_SPARE_REC21,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 20. "HW_SPARE_REC20,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 19. "HW_SPARE_REC19,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 18. "HW_SPARE_REC18,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 17. "HW_SPARE_REC17,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 16. "HW_SPARE_REC16,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 15. "HW_SPARE_REC15,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 14. "HW_SPARE_REC14,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 13. "HW_SPARE_REC13,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 12. "HW_SPARE_REC12,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 11. "HW_SPARE_REC11,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 10. "HW_SPARE_REC10,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 9. "HW_SPARE_REC9,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 8. "HW_SPARE_REC8,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 7. "HW_SPARE_REC7,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 6. "HW_SPARE_REC6,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 5. "HW_SPARE_REC5,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 4. "HW_SPARE_REC4,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 3. "HW_SPARE_REC3,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 2. "HW_SPARE_REC2,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 1. "HW_SPARE_REC1,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 0. "HW_SPARE_REC0,Reserved for HW R&D" "0,1" line.long 0x8 "TOP_CTRL_HW_SPARE_REC0" hexmask.long 0x8 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0xC "TOP_CTRL_HW_SPARE_REC1" hexmask.long 0xC 0.--31. 1. "LOCK0_KICK1,- KICK1 component" group.byte 0x1008++0x0 line.byte 0x0 "TOP_CTRL_LOCK0_KICK0" bitfld.byte 0x0 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" group.byte 0x100C++0x0 line.byte 0x0 "TOP_CTRL_LOCK0_KICK1" bitfld.byte 0x0 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" group.byte 0x1010++0x0 line.byte 0x0 "TOP_CTRL_INTR_RAW_STATUS" bitfld.byte 0x0 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" group.byte 0x1014++0x0 line.byte 0x0 "TOP_CTRL_INTR_ENABLED_STATUS_CLEAR" bitfld.byte 0x0 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.byte 0x1018++0x0 line.byte 0x0 "TOP_CTRL_INTR_ENABLE" hexmask.byte 0x0 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x101C++0x3 line.long 0x0 "TOP_CTRL_INTR_ENABLE_CLEAR" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." rgroup.byte 0x1020++0x0 line.byte 0x0 "TOP_CTRL_EOI" bitfld.byte 0x0 6. "FAULT_NS,Non-secure access." "0,1" newline hexmask.byte 0x0 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1.." rgroup.long 0x1024++0x3 line.long 0x0 "TOP_CTRL_FAULT_ADDRESS" hexmask.long.word 0x0 20.--31. 1. "FAULT_XID,XID." newline hexmask.long.word 0x0 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x0 0.--7. 1. "FAULT_PRIVID,Privilege ID." wgroup.word 0x1028++0x1 line.word 0x0 "TOP_CTRL_FAULT_TYPE_STATUS" bitfld.word 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" tree.end tree "TOP_EFUSE_FARM" base ad:0x53600000 group.long 0x0++0x3F line.long 0x0 "TOP_EFUSE_FARM_INSTRUCTION" hexmask.long.byte 0x0 24.--28. 1. "HOLDECI,Holds the eFuse controller instruction." hexmask.long.word 0x0 0.--15. 1. "ADDHOLDDWI,Holds the address to use for the DumpWord instruction. All other instructions ignore these bits." line.long 0x4 "TOP_EFUSE_FARM_ADDRESS" hexmask.long.word 0x4 16.--31. 1. "NU1,Not used" hexmask.long.byte 0x4 11.--15. 1. "BLOCKSEL,FuseROM block select. These five bits select which of the 32 possible FuseROMs is used in the following instruction." hexmask.long.word 0x4 0.--10. 1. "ROW,FuseROM row address. Given the FuseROM selected by the FuseROM block select these 11 bits select which row of the FuseROM is used in the following instruction. Since the maximum number of rows for a FuseROM is 64 only bits [5:0] of the FuseROM row.." line.long 0x8 "TOP_EFUSE_FARM_DATAREGISTERUPPER" hexmask.long 0x8 3.--31. 1. "NU1,Not used" bitfld.long 0x8 2. "WRITEPROTECT,Write protect (WP). Once this bit is set high ('1') in any FuseROM row the other bits in that FuseROM row can no longer be programmed." "0,1" bitfld.long 0x8 1. "READPROTECT,Read protect (RP). Once this bit is set high ('1') in any FuseROM row a DumpWord instruction returns all zeros (00000000H). The actual data in bits [31:0] of that row will still be loaded into the fuse scan chain during an autoload operation." "0,1" newline bitfld.long 0x8 0. "REDUNDANTROW,row 0 - Not used row 1 - 63 Redundant (R). Once this bit is set high (?1?) the row is marked as having a failure and is replaced by a redundant row." "0,1" line.long 0xC "TOP_EFUSE_FARM_DATAREGISTERLOWER" bitfld.long 0xC 31. "DISABLELOADFUSESCAN,Disable LoadFuseScanChain. If this bit is programmed the LoadFuseScanChain operation (also called soft load operation) is disabled." "0,1" hexmask.long.tbyte 0xC 7.--29. 1. "NU1,Not used" bitfld.long 0xC 6. "REDUNDANCYENABLE,Redundancy enable. If a redundant row address is programmed in bits[5:0] this bit must be programmed." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "REDUNDANTROW,Redundant row address. These six bits contain the address of a failing row that will be replaced by the native redundant row physically located at the bottom of FuseROM array." line.long 0x10 "TOP_EFUSE_FARM_SYSTEMCONFIG" bitfld.long 0x10 12.--13. "PWRMGMTCTRL,Master interface power management control" "0,1,2,3" hexmask.long.byte 0x10 8.--11. 1. "CLKCTL,Control of clock internal gating while module is idle. There is one bit per clock. The actual register width depends on the number of functional clocks controlled." bitfld.long 0x10 6. "REACTION,Reaction to module suspend assertion (for emulation). There is no effect if bit[5]=1." "0,1" newline bitfld.long 0x10 5. "SENSITIVITY,Sensitivity to module suspend (for emulation)." "0,1" bitfld.long 0x10 3.--4. "IDLEREQACK,Slave interface power management control. Idle request/acknowledge control." "0,1,2,3" bitfld.long 0x10 2. "WAKEUPGENCTL,Asynchronous wake-up generation control" "0,1" newline bitfld.long 0x10 1. "SWRESET,Module software reset" "0,1" bitfld.long 0x10 0. "INTAUTOGATECTL,Internal autogating control." "0,1" line.long 0x14 "TOP_EFUSE_FARM_SYSTEMSTATUS" bitfld.long 0x14 0. "RESETDONE,Reset done." "0,1" line.long 0x18 "TOP_EFUSE_FARM_ACCUMULATOR" hexmask.long.byte 0x18 24.--31. 1. "NU1,Not used" hexmask.long.tbyte 0x18 0.--23. 1. "ACCUMULATOR,Accumulator. These bits hold data after the execution of various instructions." line.long 0x1C "TOP_EFUSE_FARM_BOUNDARY" hexmask.long.word 0x1C 22.--31. 1. "NU2,Not used" bitfld.long 0x1C 21. "DSIABLERDROW,Disable read row 0. When high disables read of row 0 during initial access of FuseROM." "0,1" hexmask.long.word 0x1C 9.--20. 1. "NU1,Not used" newline bitfld.long 0x1C 8. "EFCFDI,EFC_FDI. This bit drives the EFC_FDI input when enable is set." "0,1" bitfld.long 0x1C 7. "SYSDIEDAUTOLOADEN,SYS_DIEID_AUTOLOAD_EN. This bit drives the SYS_DIEID_AUTOLOAD_EN input when enable is set." "0,1" bitfld.long 0x1C 5.--6. "SYSREPAIREN,SYS_REPAIR_EN[1:0]. This bus sets the SYS_REPAIR_EN inputs when enable is set." "0,1,2,3" newline hexmask.long.byte 0x1C 1.--4. 1. "SYSWSREADSTATES,SYS_WS_READ_STATES[3:0]. These bits drive the SYS_WS_READ_STATES inputs when enable is set." bitfld.long 0x1C 0. "ENABLE,Enable. This bit is used to control whether the input ports or the boundary register drives the inputs. If set high (?1?) the inputs to the controller are driven by the values of the boundary register." "0,1" line.long 0x20 "TOP_EFUSE_FARM_KEYFLAG" hexmask.long 0x20 1.--31. 1. "NU1,Not used" bitfld.long 0x20 0. "KEYFLAG,Key flag. If the proper key is loaded into the key code bits this bit will read a 1." "0,1" line.long 0x24 "TOP_EFUSE_FARM_KEY" hexmask.long 0x24 0.--31. 1. "KEYCODE,Key code. These 32 bits are used to set the key (96969696h) for the program instruction." line.long 0x28 "TOP_EFUSE_FARM_RELEASE" hexmask.long.byte 0x28 25.--31. 1. "YEARODP,Release code indicating year of ODP controller macro release." hexmask.long.byte 0x28 21.--24. 1. "MONTHODP,Release code indicating month of ODP controller macro release." hexmask.long.byte 0x28 16.--20. 1. "DAYODP,Release code indicating day of ODP controller macro release." newline hexmask.long.byte 0x28 9.--15. 1. "YEAREFUSE,Release code indicating year of eFuse controller macro release." hexmask.long.byte 0x28 5.--8. 1. "MONTHEFUSE,Release code indicating month of eFuse controller macro release." hexmask.long.byte 0x28 0.--4. 1. "DAYEFUSE,Release code indicating day of eFuse controller macro release." line.long 0x2C "TOP_EFUSE_FARM_PINS" hexmask.long.tbyte 0x2C 9.--31. 1. "NU1,Not used" bitfld.long 0x2C 8. "EFCREADY,EFC_READY. Output pin." "0,1" bitfld.long 0x2C 7. "EFCFCLRZ,EFC_FCLRZ. Output pin." "0,1" newline bitfld.long 0x2C 6. "SYSDIEDAUTOLOADEN,SYS_DIEID_AUTOLOAD_EN. Input pin." "0,1" bitfld.long 0x2C 4.--5. "SYSREPAIREN,SYS_REPAIR_EN[1:0]. Input pins." "0,1,2,3" hexmask.long.byte 0x2C 0.--3. 1. "SYSWSREADSTATES,SYS_WS_READ_STATES[3:0]. Input pin." line.long 0x30 "TOP_EFUSE_FARM_CRA" hexmask.long 0x30 6.--31. 1. "NU1,Not used" hexmask.long.byte 0x30 0.--5. 1. "DATA,Data bits to be programmed into the CRA bits of the addressed row" line.long 0x34 "TOP_EFUSE_FARM_READ" hexmask.long.tbyte 0x34 8.--31. 1. "NU2,Not used" hexmask.long.byte 0x34 4.--7. 1. "READCLKPULSEWIDTH,ROM clock read pulse width. Active high. Specifies the number of internal clock cycles that the FuseROM clock (pin FROM_CLK) is high ('1'). These bits override the SYS_WS_READ_STATE[3:0] ports. Values are: Bit Width (4b'0000) 1 *.." rbitfld.long 0x34 3. "NU1,Reserved for FuseROM testing and debugging." "0,1" newline bitfld.long 0x34 2. "READDATABIT,Read data bit. If the read protect (RP) bit is set in any row only RP and the write protect (WP) bit are reported during a read and the other bits are zero. If the RP bit is not set and the repair (R) bit is set: If read register[2] = 0.." "0,1" bitfld.long 0x34 0.--1. "COMBINEDMARGIN,Combined margin. The bits set the sense amp margin limits according to the following table. The FuseROM Compiler section in the GS60 Customer In-field Programmable FuseROM specification shows more information on combined margin." "?,1: 0,?,?" line.long 0x38 "TOP_EFUSE_FARM_PROGRAM" rbitfld.long 0x38 31. "NU1,Not used" "0,1" bitfld.long 0x38 30. "CMPDISABLE,Compare disable. Before any FuseROM bit is actually blown the value of the data register is compared to the FuseROM data bits in the row selected by the address register. If the data register is already equal to the FuseROM row data the row.." "0,1" hexmask.long.word 0x38 14.--29. 1. "CLKSTALLPULSEWIDTH,16-bit FuseROM clock stall pulse width. Active low. After the controller attempts to program the data register value into the FuseROM row selected by the address register the FROM_CLK signal is held low (?0?) for a specified number of.." newline bitfld.long 0x38 13. "SHORTSWITCH,Program signal for FuseROM VPP-to-VDD shorting switch. This bit must be set high before executing the program instruction and low after program is completed. The eFuse controller output FROM_ENSW is created from this signal. The FROM_ENSW.." "0,1" hexmask.long.byte 0x38 9.--12. 1. "WRITEITERATION,4-bit maximum write iterations. This register sets the maximum number of sweeps that the program instruction uses to make the FuseROM row equal to the value in the data register. If the eFuse controller sweeps the number of times set in.." hexmask.long.word 0x38 0.--8. 1. "WRITECLKPULSEWIDTH,9-bit FuseROM clock write pulse width. Active low. These bits determine the width of the write phase (i.e. FROM_CLK = '0') of the FROM_CLK signal. In most instances the width of the FROM_CLK write phase relative to the internal clock.." line.long 0x3C "TOP_EFUSE_FARM_ERROR" hexmask.long 0x3C 6.--31. 1. "NU1,Not used" bitfld.long 0x3C 5. "INSTRUCTIONDONE,Instruction done. Set after each instruction is done. Should be cleared by the interfaces." "0,1" hexmask.long.byte 0x3C 0.--4. 1. "STATUSCODE,Error/Status code. These five bits hold the error or status code that was returned by the instruction that was executed." tree.end tree "TOP_ESM" base ad:0x52D00000 rgroup.long 0x0++0x7 line.long 0x0 "TOP_ESM_PID" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "TOP_ESM_INFO" bitfld.long 0x4 31. "LAST_RESET,Indicates the Source of the last Reset" "0,1" hexmask.long.byte 0x4 8.--15. 1. "PULSE_GROUPS,Number of Pulse Error Groups" hexmask.long.byte 0x4 0.--7. 1. "GROUPS,Total number of Error Groups" group.byte 0x8++0x0 line.byte 0x0 "TOP_ESM_EN" hexmask.byte 0x0 0.--3. 1. "KEY,Global Enable" wgroup.byte 0xC++0x0 line.byte 0x0 "TOP_ESM_SFT_RST" hexmask.byte 0x0 0.--3. 1. "KEY,Global Soft Reset" group.byte 0x10++0x0 line.byte 0x0 "TOP_ESM_ERR_RAW" bitfld.byte 0x0 0.--2. "STS,This is the raw status for config errors" "0,1,2,3,4,5,6,7" group.byte 0x14++0x0 line.byte 0x0 "TOP_ESM_ERR_STS" bitfld.byte 0x0 0.--2. "MSK,This is the masked status/clear for config errors" "0,1,2,3,4,5,6,7" group.byte 0x18++0x0 line.byte 0x0 "TOP_ESM_ERR_EN_SET" bitfld.byte 0x0 0.--2. "MSK,This is the mask enable set for config errors" "0,1,2,3,4,5,6,7" group.byte 0x1C++0x0 line.byte 0x0 "TOP_ESM_ERR_EN_CLR" bitfld.byte 0x0 0.--2. "MSK,This is the mask enable clear for config errors" "0,1,2,3,4,5,6,7" rgroup.long 0x20++0xF line.long 0x0 "TOP_ESM_LOW_PRI" hexmask.long.word 0x0 16.--31. 1. "PLS,This is the highest priority outstanding low priority pulse interrupt" hexmask.long.word 0x0 0.--15. 1. "LVL,This is the highest priority outstanding low priority level interrupt" line.long 0x4 "TOP_ESM_HI_PRI" hexmask.long.word 0x4 16.--31. 1. "PLS,This is the highest priority outstanding high priority pulse interrupt" hexmask.long.word 0x4 0.--15. 1. "LVL,This is the highest priority outstanding high priority level interrupt" line.long 0x8 "TOP_ESM_LOW" hexmask.long 0x8 0.--31. 1. "STS,This is the raw status for config errors" line.long 0xC "TOP_ESM_HI" hexmask.long 0xC 0.--31. 1. "STS,This is the raw status for config errors" wgroup.word 0x30++0x1 line.word 0x0 "TOP_ESM_EOI" hexmask.word 0x0 0.--10. 1. "KEY,This is the interrupt being serviced" group.byte 0x40++0x0 line.byte 0x0 "TOP_ESM_PIN_CTRL" hexmask.byte 0x0 4.--7. 1. "PWM_EN,PWM enable" hexmask.byte 0x0 0.--3. 1. "KEY,Pin Control Key" rgroup.long 0x44++0x3 line.long 0x0 "TOP_ESM_PIN_STS" bitfld.long 0x0 0. "VAL,Value of the error_pin_n" "0,1" rgroup.tbyte 0x48++0x2 line.tbyte 0x0 "TOP_ESM_PIN_CNTR" hexmask.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value" group.tbyte 0x4C++0x2 line.tbyte 0x0 "TOP_ESM_PIN_CNTR_PRE" hexmask.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" rgroup.tbyte 0x50++0x2 line.tbyte 0x0 "TOP_ESM_PWMH_PIN_CNTR" hexmask.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value" group.tbyte 0x54++0x2 line.tbyte 0x0 "TOP_ESM_PWMH_PIN_CNTR_PRE" hexmask.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" rgroup.tbyte 0x58++0x2 line.tbyte 0x0 "TOP_ESM_PWML_PIN_CNTR" hexmask.tbyte 0x0 0.--23. 1. "COUNT,Current Counter Value" group.tbyte 0x5C++0x2 line.tbyte 0x0 "TOP_ESM_PWML_PIN_CNTR_PRE" hexmask.tbyte 0x0 0.--23. 1. "COUNT,Counter Pre-Load Value" tree.end tree "TOP_PBIST" base ad:0x53300000 group.word 0x100++0x1 line.word 0x0 "TOP_PBIST_PBIST_A0" hexmask.word 0x0 0.--15. 1. "PBIST_CI2,TI Internal Register.Reserved for HW RnD" group.word 0x104++0x1 line.word 0x0 "TOP_PBIST_PBIST_A1" hexmask.word 0x0 0.--15. 1. "PBIST_CI3,TI Internal Register.Reserved for HW RnD" group.long 0x108++0x3 line.long 0x0 "TOP_PBIST_PBIST_A2" hexmask.long.byte 0x0 24.--31. 1. "RGS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset." hexmask.long.byte 0x0 16.--23. 1. "RDS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset." hexmask.long.byte 0x0 8.--15. 1. "DWR,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset." hexmask.long.byte 0x0 0.--7. 1. "RAM,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset." group.word 0x10C++0x1 line.word 0x0 "TOP_PBIST_PBIST_A3" hexmask.word.byte 0x0 8.--15. 1. "DLR1,Datalogger Register[8] : Reserevd[9] : Default Testing Mode. When in this mode ROM-based testing is kicked off. If the intention is to perform go/no-go testing via config write to both this bit and bit [2] ofthe Datalogger Register.." hexmask.word.byte 0x0 0.--7. 1. "DLR0,Datalogger Register[1:0] : Reserved[2] : ROM-based testing mode. Setting this bit to 1 enables the PBIST controller to execute test algorithms that arestored in the PBIST ROM[3] : Do not change this bit from its default value of 1[4] : Config access.." group.byte 0x110++0x0 line.byte 0x0 "TOP_PBIST_PBIST_L0" hexmask.byte 0x0 0.--3. 1. "PBIST_CMS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset." group.byte 0x114++0x0 line.byte 0x0 "TOP_PBIST_PBIST_L1" hexmask.byte 0x0 0.--4. 1. "PBIST_PC,TI Internal Register.Reserved for HW RnD" group.long 0x118++0xB line.long 0x0 "TOP_PBIST_PBIST_L2" hexmask.long.byte 0x0 24.--31. 1. "SCR3,TI Internal Register.Reserved for HW RnD" hexmask.long.byte 0x0 16.--23. 1. "SCR2,TI Internal Register.Reserved for HW RnD" hexmask.long.byte 0x0 8.--15. 1. "SCR1,TI Internal Register.Reserved for HW RnD" hexmask.long.byte 0x0 0.--7. 1. "SCR0,TI Internal Register.Reserved for HW RnD" line.long 0x4 "TOP_PBIST_PBIST_L3" hexmask.long.byte 0x4 24.--31. 1. "SCR7,TI Internal Register.Reserved for HW RnD" hexmask.long.byte 0x4 16.--23. 1. "SCR6,TI Internal Register.Reserved for HW RnD" hexmask.long.byte 0x4 8.--15. 1. "SCR5,TI Internal Register.Reserved for HW RnD" hexmask.long.byte 0x4 0.--7. 1. "SCR4,TI Internal Register.Reserved for HW RnD" line.long 0x8 "TOP_PBIST_PBIST_DD10" hexmask.long.byte 0x8 24.--31. 1. "CS3,TI Internal Register.Reserved for HW RnD" hexmask.long.byte 0x8 16.--23. 1. "CS2,TI Internal Register.Reserved for HW RnD" hexmask.long.byte 0x8 8.--15. 1. "CS1,TI Internal Register.Reserved for HW RnD" hexmask.long.byte 0x8 0.--7. 1. "CS0,TI Internal Register.Reserved for HW RnD" group.byte 0x124++0x0 line.byte 0x0 "TOP_PBIST_PBIST_DE10" hexmask.byte 0x0 0.--7. 1. "PBIST_FDLY,TI Internal Register.Reserved for HW RnD" group.long 0x130++0x3 line.long 0x0 "TOP_PBIST_PBIST_CA0" bitfld.long 0x0 0. "PBIST_PACT,Pbist Active/ROM Clock Enable Register[0]: This bit must be set to turn on internal PBIST clocks. Setting this bit asserts an internal signal that is usedas the clock gate enable. As long as this bit is 0 any access to PBIST will not go.." "0: Disable internal PBIST clocksValue,1: Enable internal PBIST clocks" group.byte 0x134++0x0 line.byte 0x0 "TOP_PBIST_PBIST_CA1" hexmask.byte 0x0 0.--4. 1. "PBIST_ID,PBIST ID.This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. The value of this register does not affect the functionality of the CPU interface." rgroup.long 0x138++0x7 line.long 0x0 "TOP_PBIST_PBIST_CA2" bitfld.long 0x0 0. "PBIST_FSFR0,Fail Status Fail Register- Port 0 This register indicates if a failure occurred during a memory self-test.Value 0 = No failure occurredValue 1 = Indicates a failure" "0: No failure occurredValue,1: Indicates a failure" line.long 0x4 "TOP_PBIST_PBIST_CA3" bitfld.long 0x4 0. "PBIST_FSFR1,Fail Status Fail Register- Port 1 This register indicates if a failure occurred during a memory self-test.Value 0 = No failure occurredValue 1 = Indicates a failure" "0: No failure occurredValue,1: Indicates a failure" rgroup.byte 0x140++0x0 line.byte 0x0 "TOP_PBIST_PBIST_CL0" hexmask.byte 0x0 0.--3. 1. "PBIST_FSRCR0,Fail Status Count - Port 0 These registers keep count of the number of failures observed during the memory self-test. The PBISTcontroller stops executing the memory self-test whenever a failure occurs in any memory instance for anyof the.." rgroup.byte 0x144++0x0 line.byte 0x0 "TOP_PBIST_PBIST_CL1" hexmask.byte 0x0 0.--3. 1. "PBIST_FSRCR1,Fail Status Count - Port 1These registers keep count of the number of failures observed during the memory self-test. The PBISTcontroller stops executing the memory self-test whenever a failure occurs in any memory instance for anyof the test.." rgroup.word 0x148++0x1 line.word 0x0 "TOP_PBIST_PBIST_CL2" hexmask.word 0x0 0.--15. 1. "PBIST_FSRA1,TI Internal Register.Reserved for HW RnD" rgroup.long 0x14C++0x7 line.long 0x0 "TOP_PBIST_PBIST_CL3" hexmask.long 0x0 0.--31. 1. "PBIST_FSRDL0,TI Internal Register.Reserved for HW RnD" line.long 0x4 "TOP_PBIST_PBIST_CI0" hexmask.long 0x4 0.--31. 1. "PBIST_FSRDL1,TI Internal Register.Reserved for HW RnD" group.byte 0x154++0x0 line.byte 0x0 "TOP_PBIST_PBIST_CI1" bitfld.byte 0x0 0.--1. "PBIST_ROM,Rom Mask .This two-bit register sets appropriate ROM access modes for the PBIST controller.Value 0h = No information is used from ROMValue 1h = Only RAM Group information from ROMVaule 2h = Only Algorithm information from ROMValue 3h = Both.." "0,1,2,3" group.long 0x158++0xB line.long 0x0 "TOP_PBIST_PBIST_CI2" hexmask.long.byte 0x0 24.--31. 1. "ALGO3,This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm.Writing a value 1 to the particular bit enables the corresponding algorithm.Writing a value 0 to the.." hexmask.long.byte 0x0 16.--23. 1. "ALGO2,This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm.Writing a value 1 to the particular bit enables the corresponding algorithm.Writing a value 0 to the.." hexmask.long.byte 0x0 8.--15. 1. "ALGO1,This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm.Writing a value 1 to the particular bit enables the corresponding algorithm.Writing a value 0 to the.." hexmask.long.byte 0x0 0.--7. 1. "ALGO0,This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm.Writing a value 1 to the particular bit enables the corresponding algorithm.Writing a value 0 to the.." line.long 0x4 "TOP_PBIST_PBIST_CI3" hexmask.long.byte 0x4 24.--31. 1. "RINFOL3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." hexmask.long.byte 0x4 16.--23. 1. "RINFOL2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." hexmask.long.byte 0x4 8.--15. 1. "RINFOL1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." hexmask.long.byte 0x4 0.--7. 1. "RINFOL0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." line.long 0x8 "TOP_PBIST_PBIST_RAMT" hexmask.long.byte 0x8 24.--31. 1. "RINFOU3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." hexmask.long.byte 0x8 16.--23. 1. "RINFOU2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." hexmask.long.byte 0x8 8.--15. 1. "RINFOU1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." hexmask.long.byte 0x8 0.--7. 1. "RINFOU0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group the corresponding bit in this register must be set to 1. The default value of this.." tree.end tree "TOP_RCM" base ad:0x53200000 rgroup.long 0x0++0x3 line.long 0x0 "TOP_RCM_PID" hexmask.long.word 0x0 16.--31. 1. "PID_MSB16,Not Defined" newline hexmask.long.byte 0x0 11.--15. 1. "PID_MISC,Not Defined" newline bitfld.long 0x0 8.--10. "PID_MAJOR,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "PID_CUSTOM,Not Defined" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "PID_MINOR,Not Defined" group.long 0x4++0x3 line.long 0x0 "TOP_RCM_WARM_RESET_CONFIG" bitfld.long 0x0 28.--30. "WDOG3_RST_EN,Data should be loaded as multibit. Write 3'b000 to disable corresponding Watchdog control on Warm reset Write 3'b111 enable corresponding Watchdog to control Warm reset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "WDOG2_RST_EN,Data should be loaded as multibit. Write 3'b000 to disable corresponding Watchdog control on Warm reset Write 3'b111 enable corresponding Watchdog to control Warm reset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "WDOG1_RST_EN,Data should be loaded as multibit. Write 3'b000 to disable corresponding Watchdog control on Warm reset Write 3'b111 enable corresponding Watchdog to control Warm reset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16.--18. "WDOG0_RST_EN,Data should be loaded as multibit. Write 3'b000 to disable corresponding Watchdog control on Warm reset Write 3'b111 enable corresponding Watchdog to control Warm reset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12.--14. "TSENSE1_RST_EN,Data should be loaded as multibit. Write 3'b000 to disable temperature sensor 1 on Warm reset Write 3'b111 to enable temperature sensor 1l on Warm reset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8.--10. "TSENSE0_RST_EN,Data should be loaded as multibit. Write 3'b000 to disable temperature sensor 0 control on Warm reset Write 3'b111 to enable temperature sensor 0 control on Warm reset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4.--6. "DEBUGSS_RST_EN,Data should be loaded as multibit. Write 3'b000 to disable debugger control on Warm reset Write 3'b111 enable debugger to control Warm reset" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "PAD_BYPASS,Bypass the Warm reset from Pad InputData should be loaded as multibit. Write 3'b000 : Pad Warm Reset pin has control over warm resetWrite 3'b111 : Pad warm reset pin has no control on warm reset" "0: Pad Warm Reset pin has control over warm..,?,?,?,?,?,?,7: Pad warm reset pin has no control on warm reset" group.byte 0x8++0x0 line.byte 0x0 "TOP_RCM_WARM_RESET_REQ" bitfld.byte 0x0 0.--2. "SW_RST,Data should be loaded as multibit. Write 3'b000 to assert warm reset from SWWrite 3'b111 to deassert warm reset from SW if this is the only source of warm reset" "0,1,2,3,4,5,6,7" rgroup.word 0xC++0x1 line.word 0x0 "TOP_RCM_WARM_RST_CAUSE" hexmask.word 0x0 0.--11. 1. "CAUSE,System Reset Cause register12'b0000_0100_0001 - POR reset12'b0000_0100_0010 - Warm reset due to MSS_WDT012'b0000_0100_0100 - Warm reset due to MSS_WDT112'b0000_0100_1000 - Warm reset due to MSS_WDT212'b0000_0101_0000 - Warm reset due to.." group.byte 0x10++0x0 line.byte 0x0 "TOP_RCM_WARM_RST_CAUSE_CLR" bitfld.byte 0x0 0.--2. "CLEAR,Write pulse bit field: Data should be loaded as multibit. System Reset Cause register Clear" "0,1,2,3,4,5,6,7" group.byte 0x14++0x0 line.byte 0x0 "TOP_RCM_RCOSC32K_CTRL" bitfld.byte 0x0 0.--2. "STOPOSC,Stop 32KHz RCOSC. Write 3'b111 to stop clock" "0,1,2,3,4,5,6,7" group.word 0x18++0x1 line.word 0x0 "TOP_RCM_LIMP_MODE_EN" bitfld.word 0x0 8.--10. "COREPLL_LOSS_EN,Enable for core pll phase lock loss to generate Limp mode3'b000: will not generate Limp mode (multibit 000)3'b111 : will generate Limp mode (multibit 111)" "?,?,?,?,?,?,?,7: will generate Limp mode" newline bitfld.word 0x0 4.--6. "XTALCLK_LOSS_EN,Enable for crystal_clock_loss to generate Limp mode3'b000: will not generate Limp mode (multibit 000)3'b111 : will generate Limp mode (multibit 111)" "?,?,?,?,?,?,?,7: will generate Limp mode" newline bitfld.word 0x0 0.--2. "DCC0_ERROR_EN,Enable DCC0 Error to generate Limp mode 3'b000: DCC0 Error will not generate Limp mode (multibit 000)3'b111 : DCC0 Error will generate Limp mode (multibit 111)" "0: DCC0 Error will not generate Limp mode,?,?,?,?,?,?,7: DCC0 Error will generate Limp mode" group.byte 0x1C++0x0 line.byte 0x0 "TOP_RCM_PLL_REF_CLK_SRC_SEL" bitfld.byte 0x0 4.--6. "PLL_PERI_REF_CLK_SRC_SEL,Mux selct for PERI PLL REF clockWrite 3'b111 : to select external reference clock as PLL reference clockWrite 3'b000 : to select on-die clock as PLL reference clock" "0: to select on-die clock as PLL reference clock,?,?,?,?,?,?,7: to select external reference clock as PLL.." newline bitfld.byte 0x0 0.--2. "PLL_CORE_REF_CLK_SRC_SEL,Mux selct for CORE PLL REF clockWrite 3'b111 : to select external reference clock as PLL reference clockWrite 3'b000 : to select on-die clock as PLL reference clock" "0: to select on-die clock as PLL reference clock,?,?,?,?,?,?,7: to select external reference clock as PLL.." group.byte 0x20++0x0 line.byte 0x0 "TOP_RCM_PAD_XTAL_CTRL" bitfld.byte 0x0 3. "XTAL_XI_OE_N,When gz is low the padxo output is enabled padxi to padxo is a single stage inverter and the oscillator can oscillate with an external crystal plus capacitors/resistor. When gz is high padxo is in high impedance mode padxi and Y are.." "0,1" newline bitfld.byte 0x0 2. "XTAL_XO_RESSELECT,When resselect is low an internal 1Meg Ohm resistor is connected between padxi and padxo for oscillator bias. When resselect is asserted (high) the internal resistor is disconnected. For oscillation with a crystal while.." "0,1" newline bitfld.byte 0x0 1. "XTAL_XO_SW2,XTAL pad control bit frequency selection pin SW2 Based on table belowsw2 sw1 Freq of operation0 0 5 20 MHz0 1 15 35 MHz1 0 30 40 MHz1 1 40 55 MHz" "0,1" newline bitfld.byte 0x0 0. "XTAL_XO_SW1,XTAL pad control bit frequency selection pin SW1 Based on table belowsw2 sw1 Freq of operation0 0 5 20 MHz0 1 15 35 MHz1 0 30 40 MHz1 1 40 55 MHz" "0,1" rgroup.long 0x24++0x3 line.long 0x0 "TOP_RCM_SOP_MODE_VALUE" hexmask.long 0x0 0.--31. 1. "VAL,See below table SOP_MODE values and its corresponding mappingSOP_PAD3 SOP_PAD2 SOP_PAD1 SOP_PAD0 bootmode 0 0 0 0 QSPI Functional mode(4S) 0.." rgroup.word 0x28++0x1 line.word 0x0 "TOP_RCM_CLK_LOSS_STATUS" bitfld.word 0x0 8. "RC_GOOD_BOOT,Clock status of RC clock at boot. Reset value will reflect the actual status1 --> clock present at boot0 --> clock not present at boot" "0,1" newline bitfld.word 0x0 4. "RC_CLOCK_LOSS,Coarse detection clock loss status for RC clock. Reset value will reflect the actual status1 --> clock lost0 --> clock good" "0,1" newline bitfld.word 0x0 0. "CRYSTAL_CLOCK_LOSS,Coarse detection clock loss status for Crystal clock. Reset value will reflect the actual status1 --> clock lost0 --> clock good" "0,1" group.word 0x30++0x1 line.word 0x0 "TOP_RCM_WARM_RSTTIME1" hexmask.word 0x0 0.--11. 1. "DELAY,programing Output delay Data should be loaded as multibit. For example: if value of 0x5 should be selected then 0x555 should be configured to the register." group.word 0x34++0x1 line.word 0x0 "TOP_RCM_WARM_RSTTIME2" hexmask.word 0x0 0.--11. 1. "DELAY,programing input Rise delay Data should be loaded as multibit. For example: if value of 0x5 should be selected then 0x555 should be configured to the register." group.word 0x38++0x1 line.word 0x0 "TOP_RCM_WARM_RSTTIME3" hexmask.word 0x0 0.--11. 1. "DELAY,programing Input Fall delay Data should be loaded as multibit. For example: if value of 0x5 should be selected then 0x555 should be configured to the register." group.byte 0x400++0x0 line.byte 0x0 "TOP_RCM_PLL_CORE_PWRCTRL" bitfld.byte 0x0 5. "PONIN,ON/OFF control of the weak power switch digital. For functionalmode it should be 1" "0,1" newline bitfld.byte 0x0 4. "PGOODIN,ON/OFF control of the strong power switch digital. For functional mode it should be 1" "0,1" newline bitfld.byte 0x0 3. "RET,Save/Restore control for Retention mode. For functional mode itshould be 0" "0,1" newline bitfld.byte 0x0 2. "ISORET,Save/Restore control for Isolation of output pins For functional modeit should be 0" "0,1" newline bitfld.byte 0x0 1. "ISOSCAN,Save/Restore control for Isolation of the Scanout pins. For functionalmode it should be 0" "0,1" newline bitfld.byte 0x0 0. "OFFMODE,Used to switch OFF the logic on VDDA. For functional mode itshould be 0" "0,1" group.long 0x404++0xB line.long 0x0 "TOP_RCM_PLL_CORE_CLKCTRL" bitfld.long 0x0 31. "CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK." "0,1" newline bitfld.long 0x0 30. "ENSSC,Controls Clock Spreading. SSC is not supported. Should be set to 0x0 to disable clock spreading." "0,1" newline bitfld.long 0x0 29. "CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO0x0 : synchronously disables CLKDCOLDO0x1 : synchronously enables CLKDCOLDO" "0,1" newline bitfld.long 0x0 23. "IDLE,Sets PLL to Idle mode0x0 : When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL will go toActive and Locked0x1 : When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL will go toIdle Bypass low powe" "0,1" newline bitfld.long 0x0 22. "BYPASSACKZ,BYPASSACKZ is a special purpose input to the module. In generalthis input is expected to be tied to static low. For the output clocks ofthe module that do not have an internal bypass mux viz.CLKDCOLDO and CLKOUTLDO a bypass mux could.." "0,1" newline bitfld.long 0x0 21. "STBYRET,Standby retention control0x0 : prepares ADPLLLJ for relock when out of retention byremoving the gating on all internal clocks.0x1 : prepares ADPLLLJ for retention by gating all the internalclocks." "?,1: prepares ADPLLLJ for retention by gating all the.." newline bitfld.long 0x0 20. "CLKOUTEN,CLKOUT enable or disable0x0 : synchronously disables CLKOUT0x1 : synchronously enables CLKOUT" "0,1" newline bitfld.long 0x0 19. "CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO 0x0 : synchronously disables CLKOUTLDO 0x1 : synchronously enables CLKOUTLDO" "0: synchronously disables CLKOUTLDO,1: synchronously enables CLKOUTLDO" newline bitfld.long 0x0 18. "ULOWCLKEN,Select CLKOUT source in bypass0x0: When ADPLLLJ in bypass mode CLKOUT = CLKINP/(N2+1)0x1: When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW." "?,1: When ADPLLLJ in bypass mode" newline bitfld.long 0x0 17. "CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p." "0,1" newline bitfld.long 0x0 16. "M2PWDNZ,M2 divider power down mode0x0: Asynchronous power down for M2 divider0x1 : M2 divider is functional" "0,1" newline bitfld.long 0x0 14. "STOPMODE,When in Lossclk/Stbyret 0x0 : Limp mode 0x1 : Stopmode" "0: Limp mode,1: Stopmode" newline bitfld.long 0x0 10.--12. "SELFREQDCO,DCO Clock (DCOCLK = CLKINP * [M/(N+1)]) frequency rangeselector.0x0: Reserved0x2: HS2 : DCOCLK range is from 500 MHz to 1000 MHz0x3: Reserved0x4: HS1: DCOCLK range is from 1000 MHz to 2000 MHz0x5: Reserved" "0: Reserved0x2: HS2 : DCOCLK range is from 500 MHz..,?,?,?,?,?,?,?" newline bitfld.long 0x0 8. "RELAXED_LOCK,Decides when FREQLOCK asserted0x0: FREQLOCK asserted when DC frequency error less than 1%0x1: FREQLOCK asserted when DC frequency error less than 2%" "0,1" newline bitfld.long 0x0 1. "SSCTYPE,SSC Type" "0,1" newline bitfld.long 0x0 0. "TINTZ,PLL core soft reset" "0,1" line.long 0x4 "TOP_RCM_PLL_CORE_TENABLE" bitfld.long 0x4 0. "TENABLE,M N. SD and SELFREQDCO latch (active rise edge)" "0,1" line.long 0x8 "TOP_RCM_PLL_CORE_TENABLEDIV" bitfld.long 0x8 0. "TENABLEDIV,M2 and N2 latch (active rise edge)" "0,1" group.tbyte 0x410++0x2 line.tbyte 0x0 "TOP_RCM_PLL_CORE_M2NDIV" hexmask.tbyte.byte 0x0 16.--22. 1. "M2,Post-divider is REGM2" newline hexmask.tbyte.byte 0x0 0.--7. 1. "N,Pre-divider is REGN+1" group.tbyte 0x414++0x2 line.tbyte 0x0 "TOP_RCM_PLL_CORE_MN2DIV" hexmask.tbyte.byte 0x0 16.--19. 1. "N2,Bypass divider is REGN2+1" newline hexmask.tbyte.word 0x0 0.--11. 1. "M,Feedback Multiplier is REGM" group.long 0x418++0x3 line.long 0x0 "TOP_RCM_PLL_CORE_FRACDIV" hexmask.long.byte 0x0 24.--31. 1. "REGSD,Sigma-Delta DividerShould be set by s/w to provide optimum jitter performance.DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)] * CLKINP/ 250) where CLKINP is the input clock of the DPLL in MHz" newline hexmask.long.tbyte 0x0 0.--17. 1. "FRACTIONALM,Fractional part of the M divider." group.byte 0x41C++0x0 line.byte 0x0 "TOP_RCM_PLL_CORE_BWCTRL" bitfld.byte 0x0 1.--2. "BWCONTROL,Change Loop Bandwidth" "0,1,2,3" newline bitfld.byte 0x0 0. "BW_INCR_DECRZ,Direction of Loop Bandwidth0x0 : decrease BW0x1 : increase BW" "0,1" group.long 0x420++0x3 line.long 0x0 "TOP_RCM_PLL_CORE_FRACCTRL" bitfld.long 0x0 31. "DOWNSPREAD,Controls frequency spread0x0 : enables both side frequency spread about the programmed frequency.0x1 : enables low frequency spread only" "?,1: enables low frequency spread only" newline bitfld.long 0x0 28.--30. "MODFREQDIVIDEREXPONENT,Exponent of the REFCLK divider to define the modulation frequency." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 21.--27. 1. "MODFREQDIVIDERMANTISSA,Mantissa of the REFCLK divider to define the modulation frequency" newline bitfld.long 0x0 18.--20. "DELTAMSTEPINTEGER,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x0 0.--17. 1. "DELTAMSTEPFRACTION,The fraction part of Frequency Spread control" rgroup.long 0x424++0x3 line.long 0x0 "TOP_RCM_PLL_CORE_STATUS" bitfld.long 0x0 31. "PONOUT,Status of the weak power-switch0x0 : indicates the/OFF status of the weak power-switch in digital toSOC.0x1 : ndicates the ON status of the weak power-switch in digital toSOC." "?,1: ndicates the ON status of the weak power-switch.." newline bitfld.long 0x0 30. "PGOODOUT,Status of the strong power-switch0x0 : indicates the/OFF status of the strong power-switch in digital toSOC.0x1 : ndicates the ON status of the strong power-switch in digital toSOC." "?,1: ndicates the ON status of the strong.." newline bitfld.long 0x0 29. "LDOPWDN,1 indicates ADPLLLJ internal LDO is power down. VDDLDOOUT willbe un-defined in this condition" "0,1" newline bitfld.long 0x0 28. "RECAL_BSTATUS3,Recalibration status flag. 1 ADPLLLJ requires recalibration" "0,1" newline bitfld.long 0x0 27. "RECAL_OPPIN,Recalibration status flag. 1 ADPLLLJ requires recalibration" "0,1" newline bitfld.long 0x0 12. "CLKOUTLDOENACK,Indicates the enable/disable condition of CLKOUTLDOEN0x0 = CLKOUTLDO gating completed0x1 = CLKOUTLDO enabling completed" "0,1" newline bitfld.long 0x0 11. "CLKDCOLDOACK,Indicates the enable/disable condition of CLKDCOLDOEN0x0 = CLKDCOLDO gating completed0x1 = CLKDCOLOD enabling completed" "0,1" newline bitfld.long 0x0 10. "PHASELOCK,Status on PHASELOCK output pin" "0,1" newline bitfld.long 0x0 9. "FREQLOCK,Status on FREQLOCK output pin" "0,1" newline bitfld.long 0x0 8. "BYPASSACK,Status of BYPASSACK output pin" "0,1" newline bitfld.long 0x0 7. "STBYRETACK,Standby and retention status0x0: indicates to SOC that all internal clocks in ADPLLLJ are activeand it is starting the relock process.0x1: indicates to SOC that all internal clocks in ADPLLLJ are gatedand it is ready for retention." "?,1: indicates to SOC that all internal clocks in.." newline bitfld.long 0x0 6. "LOSSREF,Reference input loss" "0,1" newline bitfld.long 0x0 5. "CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN0x0 = CLKOUT gating completed0x1 = CLKOUT enabling completed" "0,1" newline bitfld.long 0x0 4. "LOCK2,ADPLL internal loop lock status" "0,1" newline bitfld.long 0x0 3. "M2CHANGEACK,Acknowledge for change to M2 divider. Toggles from 1-0 or 0-1(depending on current value) once CLKOUT frequency change hascompleted." "0,1" newline bitfld.long 0x0 2. "SSCACK,Spread Spectrum status0x0 : Spread-spectrum Clocking is disabled on output clocks0x1 : Spread-spectrum Clocking is enabled on output clocks" "0,1" newline bitfld.long 0x0 1. "HIGHJITTER,1 indicates jitter. After PHASELOCK is asserted high theHIGHJITTER flag is asserted high if phase error between REFCLKand FBCLK greater than 24%." "0,1" newline bitfld.long 0x0 0. "BYPASS,Bypass status signal. 1 CLKOUT in bypass" "0,1" group.tbyte 0x428++0x2 line.tbyte 0x0 "TOP_RCM_PLL_CORE_HSDIVIDER" rbitfld.tbyte 0x0 17. "LDOPWDNACK,LDO Power Down Ack" "0,1" newline rbitfld.tbyte 0x0 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1" newline bitfld.tbyte 0x0 2. "TENABLEDIV,Tenable Div" "0,1" newline bitfld.tbyte 0x0 1. "LDOPWDN,LDO Power Down" "0,1" newline bitfld.tbyte 0x0 0. "BYPASS,HSDIVIDER Bypass" "0,1" group.word 0x42C++0x1 line.word 0x0 "TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT0" bitfld.word 0x0 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output0h (R/W) = CLKOUT0 divider active1h (R/W) = CLKOUT0 divider is powered down" "0,1" newline rbitfld.word 0x0 9. "STATUS,HSDIVIDER CLKOUT0 status0h (R) = The clock output is gated1h (R) = The clock output is enabled" "0,1" newline bitfld.word 0x0 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT00h (R/W) = Automatically gate this clock when there is nodependency for it1h (R/W) = Force this clock to stay enabled even if there is norequest" "0,1" newline rbitfld.word 0x0 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIVindicates that the change in divider value has taken effect" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "DIV,DPLL post-divider factor M4 for internal clock generation.Divide values from 1 to 31.0h (R/W) = Reserved" group.word 0x430++0x1 line.word 0x0 "TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT1" bitfld.word 0x0 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output0h (R/W) = CLKOUT1 divider active1h (R/W) = CLKOUT1 divider is powered down" "0,1" newline rbitfld.word 0x0 9. "STATUS,HSDIVIDER CLKOUT1 status0h (R) = The clock output is gated1h (R) = The clock output is enabled" "0,1" newline bitfld.word 0x0 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT10h (R/W) = Automatically gate this clock when there is nodependency for it1h (R/W) = Force this clock to stay enabled even if there is norequest" "0,1" newline rbitfld.word 0x0 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIVindicates that the change in divider value has taken effect" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "DIV,DPLL post-divider factor M5 for internal clock generation.Divide values from 1 to 31.0h (R/W) = Reserved" group.word 0x434++0x1 line.word 0x0 "TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT2" bitfld.word 0x0 12. "PWDN,Power down for HSDIVIDER M6 divider and hence CLKOUT2 output0h (R/W) = CLKOUT2 divider active1h (R/W) = CLKOUT2 divider is powered down" "0,1" newline rbitfld.word 0x0 9. "STATUS,HSDIVIDER CLKOUT2 status0h (R) = The clock output is gated1h (R) = The clock output is enabled" "0,1" newline bitfld.word 0x0 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT20h (R/W) = Automatically gate this clock when there is nodependency for it1h (R/W) = Force this clock to stay enabled even if there is norequest" "0,1" newline rbitfld.word 0x0 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIVindicates that the change in divider value has taken effect" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "DIV,DPLL post-divider factor M6 for internal clock generation.Divide values from 1 to 31.0h (R/W) = Reserved" group.byte 0x43C++0x0 line.byte 0x0 "TOP_RCM_PLL_CORE_RSTCTRL" bitfld.byte 0x0 0.--2. "ASSERT,SW Reset override for the PLLWrite 3'b111 : Override is enabled and Reset is asserted" "?,?,?,?,?,?,?,7: Override is enabled and Reset is asserted" group.byte 0x440++0x0 line.byte 0x0 "TOP_RCM_PLL_CORE_HSDIVIDER_RSTCTRL" bitfld.byte 0x0 0.--2. "ASSERT,SW Reset override for the HSDIVIDERWrite 3'b111 : Override is enabled and Reset is asserted" "?,?,?,?,?,?,?,7: Override is enabled and Reset is asserted" group.word 0x500++0x1 line.word 0x0 "TOP_RCM_R5SS_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for MSS Coretex R5 and System bus Clock.Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register.Refer to AM602 clock spec for.." rgroup.byte 0x504++0x0 line.byte 0x0 "TOP_RCM_R5SS_CLK_STATUS" hexmask.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for Root clock for CortexR5 and Sysclk" group.byte 0x510++0x0 line.byte 0x0 "TOP_RCM_R5SS0_CLK_DIV_SEL" bitfld.byte 0x0 0.--2. "CLKDIVSEL,writing 3'b000 Sets R5 clock = R5SS Root clockWriting 3'b111 Sets R5 Clock = SYSCLK" "0,1,2,3,4,5,6,7" group.byte 0x514++0x0 line.byte 0x0 "TOP_RCM_R5SS1_CLK_DIV_SEL" bitfld.byte 0x0 0.--2. "CLKDIVSEL,writing 3'b000 Sets R5 clock = R5SS Root clockWriting 3'b111 Sets R5 Clock = SYSCLK" "0,1,2,3,4,5,6,7" group.byte 0x518++0x0 line.byte 0x0 "TOP_RCM_R5SS0_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,Only for debug- Functionality not guaranteed Clock gating config for MSS Coretex R5.Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000)Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated" group.byte 0x51C++0x0 line.byte 0x0 "TOP_RCM_R5SS1_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,Only for debug- Functionality not guaranteed Clock gating config for MSS Coretex R5.Data should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000)Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated" group.word 0x520++0x1 line.word 0x0 "TOP_RCM_SYS_CLK_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIV,Divider value for System Clock selected clock.Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register." group.byte 0x524++0x0 line.byte 0x0 "TOP_RCM_SYS_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,Only for debug- Functionality not guaranteed Clock gating config for System ClockData should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000)Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated" rgroup.word 0x528++0x1 line.word 0x0 "TOP_RCM_SYS_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for Sys Clock" group.byte 0x800++0x0 line.byte 0x0 "TOP_RCM_PLL_PER_PWRCTRL" bitfld.byte 0x0 5. "PONIN,ON/OFF control of the weak power switch digital. For functionalmode it should be 1" "0,1" newline bitfld.byte 0x0 4. "PGOODIN,ON/OFF control of the strong power switch digital. For functional mode it should be 1" "0,1" newline bitfld.byte 0x0 3. "RET,Save/Restore control for Retention mode. For functional mode itshould be 0" "0,1" newline bitfld.byte 0x0 2. "ISORET,Save/Restore control for Isolation of output pins For functional modeit should be 0" "0,1" newline bitfld.byte 0x0 1. "ISOSCAN,Save/Restore control for Isolation of the Scanout pins. For functionalmode it should be 0" "0,1" newline bitfld.byte 0x0 0. "OFFMODE,Used to switch OFF the logic on VDDA. For functional mode itshould be 0" "0,1" group.long 0x804++0xB line.long 0x0 "TOP_RCM_PLL_PER_CLKCTRL" bitfld.long 0x0 31. "CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK." "0,1" newline bitfld.long 0x0 30. "ENSSC,Controls Clock Spreading. SSC is not supported. Should be set to 0x0 to disable clock spreading." "0,1" newline bitfld.long 0x0 29. "CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO0x0 : synchronously disables CLKDCOLDO0x1 : synchronously enables CLKDCOLDO" "0,1" newline bitfld.long 0x0 23. "IDLE,Sets PLL to Idle mode0x0 : When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL will go toActive and Locked0x1 : When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL will go toIdle Bypass low powe" "0,1" newline bitfld.long 0x0 22. "BYPASSACKZ,BYPASSACKZ is a special purpose input to the module. In generalthis input is expected to be tied to static low. For the output clocks ofthe module that do not have an internal bypass mux viz.CLKDCOLDO and CLKOUTLDO a bypass mux could.." "0,1" newline bitfld.long 0x0 21. "STBYRET,Standby retention control0x0 : prepares ADPLLLJ for relock when out of retention byremoving the gating on all internal clocks.0x1 : prepares ADPLLLJ for retention by gating all the internalclocks." "?,1: prepares ADPLLLJ for retention by gating all the.." newline bitfld.long 0x0 20. "CLKOUTEN,CLKOUT enable or disable0x0 : synchronously disables CLKOUT0x1 : synchronously enables CLKOUT" "0,1" newline bitfld.long 0x0 19. "CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO 0x0 : synchronously disables CLKOUTLDO 0x1 : synchronously enables CLKOUTLDO" "0: synchronously disables CLKOUTLDO,1: synchronously enables CLKOUTLDO" newline bitfld.long 0x0 18. "ULOWCLKEN,Select CLKOUT source in bypass0x0: When ADPLLLJ in bypass mode CLKOUT = CLKINP/(N2+1)0x1: When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW." "?,1: When ADPLLLJ in bypass mode" newline bitfld.long 0x0 17. "CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p." "0,1" newline bitfld.long 0x0 16. "M2PWDNZ,M2 divider power down mode0x0: Asynchronous power down for M2 divider0x1 : M2 divider is functional" "0,1" newline bitfld.long 0x0 14. "STOPMODE,When in Lossclk/Stbyret 0x0 : Limp mode 0x1 : Stopmode" "0: Limp mode,1: Stopmode" newline bitfld.long 0x0 10.--12. "SELFREQDCO,DCO Clock (DCOCLK = CLKINP * [M/(N+1)]) frequency rangeselector.0x0: Reserved0x2: HS2 : DCOCLK range is from 500 MHz to 1000 MHz0x3: Reserved0x4: HS1: DCOCLK range is from 1000 MHz to 2000 MHz0x5: Reserved" "0: Reserved0x2: HS2 : DCOCLK range is from 500 MHz..,?,?,?,?,?,?,?" newline bitfld.long 0x0 8. "RELAXED_LOCK,Decides when FREQLOCK asserted0x0: FREQLOCK asserted when DC frequency error less than 1%0x1: FREQLOCK asserted when DC frequency error less than 2%" "0,1" newline bitfld.long 0x0 1. "SSCTYPE,SSC Type" "0,1" newline bitfld.long 0x0 0. "TINTZ,PLL core soft reset" "0,1" line.long 0x4 "TOP_RCM_PLL_PER_TENABLE" bitfld.long 0x4 0. "TENABLE,M N. SD and SELFREQDCO latch (active rise edge)" "0,1" line.long 0x8 "TOP_RCM_PLL_PER_TENABLEDIV" bitfld.long 0x8 0. "TENABLEDIV,M2 and N2 latch (active rise edge)" "0,1" group.tbyte 0x810++0x2 line.tbyte 0x0 "TOP_RCM_PLL_PER_M2NDIV" hexmask.tbyte.byte 0x0 16.--22. 1. "M2,Post-divider is REGM2" newline hexmask.tbyte.byte 0x0 0.--7. 1. "N,Pre-divider is REGN+1" group.tbyte 0x814++0x2 line.tbyte 0x0 "TOP_RCM_PLL_PER_MN2DIV" hexmask.tbyte.byte 0x0 16.--19. 1. "N2,Bypass divider is REGN2+1" newline hexmask.tbyte.word 0x0 0.--11. 1. "M,Feedback Multiplier is REGM" group.long 0x818++0x3 line.long 0x0 "TOP_RCM_PLL_PER_FRACDIV" hexmask.long.byte 0x0 24.--31. 1. "REGSD,Sigma-Delta DividerShould be set by s/w to provide optimum jitter performance.DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)] * CLKINP/ 250) where CLKINP is the input clock of the DPLL in MHz" newline hexmask.long.tbyte 0x0 0.--17. 1. "FRACTIONALM,Fractional part of the M divider." group.byte 0x81C++0x0 line.byte 0x0 "TOP_RCM_PLL_PER_BWCTRL" bitfld.byte 0x0 1.--2. "BWCONTROL,Change Loop Bandwidth" "0,1,2,3" newline bitfld.byte 0x0 0. "BW_INCR_DECRZ,Direction of Loop Bandwidth0x0 : decrease BW0x1 : increase BW" "0,1" group.long 0x820++0x3 line.long 0x0 "TOP_RCM_PLL_PER_FRACCTRL" bitfld.long 0x0 31. "DOWNSPREAD,Controls frequency spread0x0 : enables both side frequency spread about the programmed frequency.0x1 : enables low frequency spread only" "?,1: enables low frequency spread only" newline bitfld.long 0x0 28.--30. "MODFREQDIVIDEREXPONENT,Exponent of the REFCLK divider to define the modulation frequency." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 21.--27. 1. "MODFREQDIVIDERMANTISSA,Mantissa of the REFCLK divider to define the modulation frequency" newline bitfld.long 0x0 18.--20. "DELTAMSTEPINTEGER,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7" newline hexmask.long.tbyte 0x0 0.--17. 1. "DELTAMSTEPFRACTION,The fraction part of Frequency Spread control" rgroup.long 0x824++0x3 line.long 0x0 "TOP_RCM_PLL_PER_STATUS" bitfld.long 0x0 31. "PONOUT,Status of the weak power-switch0x0 : indicates the/OFF status of the weak power-switch in digital toSOC.0x1 : ndicates the ON status of the weak power-switch in digital toSOC." "?,1: ndicates the ON status of the weak power-switch.." newline bitfld.long 0x0 30. "PGOODOUT,Status of the strong power-switch0x0 : indicates the/OFF status of the strong power-switch in digital toSOC.0x1 : ndicates the ON status of the strong power-switch in digital toSOC." "?,1: ndicates the ON status of the strong.." newline bitfld.long 0x0 29. "LDOPWDN,1 indicates ADPLLLJ internal LDO is power down. VDDLDOOUT willbe un-defined in this condition" "0,1" newline bitfld.long 0x0 28. "RECAL_BSTATUS3,Recalibration status flag. 1 ADPLLLJ requires recalibration" "0,1" newline bitfld.long 0x0 27. "RECAL_OPPIN,Recalibration status flag. 1 ADPLLLJ requires recalibration" "0,1" newline bitfld.long 0x0 12. "CLKOUTLDOENACK,Indicates the enable/disable condition of CLKOUTLDOEN0x0 = CLKOUTLDO gating completed0x1 = CLKOUTLDO enabling completed" "0,1" newline bitfld.long 0x0 11. "CLKDCOLDOACK,Indicates the enable/disable condition of CLKDCOLDOEN0x0 = CLKDCOLDO gating completed0x1 = CLKDCOLDO enabling completed" "0,1" newline bitfld.long 0x0 10. "PHASELOCK,Status on PHASELOCK output pin" "0,1" newline bitfld.long 0x0 9. "FREQLOCK,Status on FREQLOCK output pin" "0,1" newline bitfld.long 0x0 8. "BYPASSACK,Status of BYPASSACK output pin" "0,1" newline bitfld.long 0x0 7. "STBYRETACK,Standby and retention status0x0: indicates to SOC that all internal clocks in ADPLLLJ are activeand it is starting the relock process.0x1: indicates to SOC that all internal clocks in ADPLLLJ are gatedand it is ready for retention." "?,1: indicates to SOC that all internal clocks in.." newline bitfld.long 0x0 6. "LOSSREF,Reference input loss" "0,1" newline bitfld.long 0x0 5. "CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN0x0 = CLKOUT gating completed0x1 = CLKOUT enabling completed" "0,1" newline bitfld.long 0x0 4. "LOCK2,ADPLL internal loop lock status" "0,1" newline bitfld.long 0x0 3. "M2CHANGEACK,Acknowledge for change to M2 divider. Toggles from 1-0 or 0-1(depending on current value) once CLKOUT frequency change hascompleted." "0,1" newline bitfld.long 0x0 2. "SSCACK,Spread Spectrum status0x0 : Spread-spectrum Clocking is disabled on output clocks0x1 : Spread-spectrum Clocking is enabled on output clocks" "0,1" newline bitfld.long 0x0 1. "HIGHJITTER,1 indicates jitter. After PHASELOCK is asserted high theHIGHJITTER flag is asserted high if phase error between REFCLKand FBCLK greater than 24%." "0,1" newline bitfld.long 0x0 0. "BYPASS,Bypass status signal. 1 CLKOUT in bypass" "0,1" group.tbyte 0x828++0x2 line.tbyte 0x0 "TOP_RCM_PLL_PER_HSDIVIDER" rbitfld.tbyte 0x0 17. "LDOPWDNACK,LDO Power Down Ack" "0,1" newline rbitfld.tbyte 0x0 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1" newline bitfld.tbyte 0x0 2. "TENABLEDIV,Tenable Div" "0,1" newline bitfld.tbyte 0x0 1. "LDOPWDN,LDO Power Down" "0,1" newline bitfld.tbyte 0x0 0. "BYPASS,HSDIVIDER Bypass" "0,1" group.word 0x82C++0x1 line.word 0x0 "TOP_RCM_PLL_PER_HSDIVIDER_CLKOUT0" bitfld.word 0x0 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output0h (R/W) = CLKOUT0 divider active1h (R/W) = CLKOUT0 divider is powered down" "0,1" newline rbitfld.word 0x0 9. "STATUS,HSDIVIDER CLKOUT0 status0h (R) = The clock output is gated1h (R) = The clock output is enabled" "0,1" newline bitfld.word 0x0 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT00h (R/W) = Automatically gate this clock when there is nodependency for it1h (R/W) = Force this clock to stay enabled even if there is norequest" "0,1" newline rbitfld.word 0x0 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIVindicates that the change in divider value has taken effect" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "DIV,DPLL post-divider factor M4 for internal clock generation.Divide values from 1 to 31.0h (R/W) = Reserved" group.word 0x830++0x1 line.word 0x0 "TOP_RCM_PLL_PER_HSDIVIDER_CLKOUT1" bitfld.word 0x0 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output0h (R/W) = CLKOUT1 divider active1h (R/W) = CLKOUT1 divider is powered down" "0,1" newline rbitfld.word 0x0 9. "STATUS,HSDIVIDER CLKOUT1 status0h (R) = The clock output is gated1h (R) = The clock output is enabled" "0,1" newline bitfld.word 0x0 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT10h (R/W) = Automatically gate this clock when there is nodependency for it1h (R/W) = Force this clock to stay enabled even if there is norequest" "0,1" newline rbitfld.word 0x0 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIVindicates that the change in divider value has taken effect" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "DIV,DPLL post-divider factor M5 for internal clock generation.Divide values from 1 to 31.0h (R/W) = Reserved" group.byte 0x83C++0x0 line.byte 0x0 "TOP_RCM_PLL_PER_RSTCTRL" bitfld.byte 0x0 0.--2. "ASSERT,SW Reset override for the PLLWrite 3'b111 : Override is enabled and Reset is asserted" "?,?,?,?,?,?,?,7: Override is enabled and Reset is asserted" group.byte 0x840++0x0 line.byte 0x0 "TOP_RCM_PLL_PER_HSDIVIDER_RSTCTRL" bitfld.byte 0x0 0.--2. "ASSERT,SW Reset override for the HSDIVIDERWrite 3'b111 : Override is enabled and Reset is asserted" "?,?,?,?,?,?,?,7: Override is enabled and Reset is asserted" group.word 0xC00++0x1 line.word 0x0 "TOP_RCM_CLKOUT0_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for MSS CLKOUT .Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0xC04++0x1 line.word 0x0 "TOP_RCM_CLKOUT1_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for MSS CLKOUT .Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0xC08++0x1 line.word 0x0 "TOP_RCM_CLKOUT0_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIV,Divider value for CLKOUT selected clock.Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register." group.word 0xC0C++0x1 line.word 0x0 "TOP_RCM_CLKOUT1_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIV,Divider value for CLKOUT selected clock.Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register." group.byte 0xC10++0x0 line.byte 0x0 "TOP_RCM_CLKOUT0_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,Only for debug- Functionality not guaranteed Clock gating config for MSS CLKOUTData should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000)Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated" group.byte 0xC14++0x0 line.byte 0x0 "TOP_RCM_CLKOUT1_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,Only for debug- Functionality not guaranteed Clock gating config for MSS CLKOUTData should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000)Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated" rgroup.word 0xC18++0x1 line.word 0x0 "TOP_RCM_CLKOUT0_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for CLKOUT Clock" newline hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for CLKOUT Clock" rgroup.word 0xC1C++0x1 line.word 0x0 "TOP_RCM_CLKOUT1_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for CLKOUT Clock" newline hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for CLKOUT Clock" group.word 0xC20++0x1 line.word 0x0 "TOP_RCM_TRCCLKOUT_CLK_SRC_SEL" hexmask.word 0x0 0.--11. 1. "CLKSRCSEL,Select line for selecting source clock for TRC ClkoutData should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register.Refer to AM602 clock spec for source clock reference" group.word 0xC24++0x1 line.word 0x0 "TOP_RCM_TRCCLKOUT_DIV_VAL" hexmask.word 0x0 0.--11. 1. "CLKDIV,Divider value for TRC Clkout selected clock.Data should be loaded as multibit. For example: if divider value of 0x5 should be selected then 0x555 should be configured to the register." group.byte 0xC28++0x0 line.byte 0x0 "TOP_RCM_TRCCLKOUT_CLK_GATE" bitfld.byte 0x0 0.--2. "GATED,Clock gatring config for TRC ClkoutData should be loaded as multibit. Write 3'b000 : Clock is ungated (multibit 000)Write 3'b111 : Clock is gated (multibit 111)" "0: Clock is ungated,?,?,?,?,?,?,7: Clock is gated" rgroup.word 0xC2C++0x1 line.word 0x0 "TOP_RCM_TRCCLKOUT_CLK_STATUS" hexmask.word.byte 0x0 8.--15. 1. "CURRDIVIDER,Status shows the current divider value choosen for PMIC Clkout Clock" newline hexmask.word.byte 0x0 0.--7. 1. "CLKINUSE,Status shows the source clock slected for PMIC Clkout Clock" group.long 0xD00++0x7 line.long 0x0 "TOP_RCM_DFT_DMLED_EXEC" hexmask.long 0x0 0.--31. 1. "VAL,SW mapping for DMLED ExecutionBit 0 : HSM CM4 Execution Bit 1 : HWA CM4 Execution Bit 2 : MSS CR5undefined Execution" line.long 0x4 "TOP_RCM_DFT_DMLED_STATUS" hexmask.long 0x4 0.--31. 1. "VAL,SW mapping for DMLED StatusBit 0 : HSM CM4 Status Bit 1 : HWA CM4 Status Bit 2 : MSS CR5undefined Status" group.long 0xE00++0xF line.long 0x0 "TOP_RCM_HW_REG0" hexmask.long 0x0 0.--31. 1. "HWREG,HW Reserved regiser. Reserved for HW RnD" line.long 0x4 "TOP_RCM_HW_REG1" hexmask.long 0x4 0.--31. 1. "HWREG,HW Reserved regiser. Reserved for HW RnD" line.long 0x8 "TOP_RCM_HW_REG2" hexmask.long 0x8 0.--31. 1. "HWREG,HW Reserved regiser. Reserved for HW RnD" line.long 0xC "TOP_RCM_HW_REG3" hexmask.long 0xC 0.--31. 1. "HWREG,HW Reserved regiser. Reserved for HW RnD" group.long 0xFD0++0xF line.long 0x0 "TOP_RCM_HW_SPARE_RW0" hexmask.long 0x0 0.--31. 1. "HW_SPARE_RW0,Reserved for HW R&D" line.long 0x4 "TOP_RCM_HW_SPARE_RW1" hexmask.long 0x4 0.--31. 1. "HW_SPARE_RW1,Reserved for HW R&D" line.long 0x8 "TOP_RCM_HW_SPARE_RW2" hexmask.long 0x8 0.--31. 1. "HW_SPARE_RW2,Reserved for HW R&D" line.long 0xC "TOP_RCM_HW_SPARE_RW3" hexmask.long 0xC 0.--31. 1. "HW_SPARE_RW3,Reserved for HW R&D" rgroup.long 0xFE0++0xF line.long 0x0 "TOP_RCM_HW_SPARE_RO0" hexmask.long 0x0 0.--31. 1. "HW_SPARE_RO0,Reserved for HW R&D" line.long 0x4 "TOP_RCM_HW_SPARE_RO1" hexmask.long 0x4 0.--31. 1. "HW_SPARE_RO1,Reserved for HW R&D" line.long 0x8 "TOP_RCM_HW_SPARE_RO2" hexmask.long 0x8 0.--31. 1. "HW_SPARE_RO2,Reserved for HW R&D" line.long 0xC "TOP_RCM_HW_SPARE_RO3" hexmask.long 0xC 0.--31. 1. "HW_SPARE_RO3,Reserved for HW R&D" group.long 0xFF0++0x7 line.long 0x0 "TOP_RCM_HW_SPARE_WPH" hexmask.long 0x0 0.--31. 1. "HW_SPARE_WPH,Reserved for HW R&D" line.long 0x4 "TOP_RCM_HW_SPARE_REC" bitfld.long 0x4 31. "HW_SPARE_REC31,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 30. "HW_SPARE_REC30,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 29. "HW_SPARE_REC29,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 28. "HW_SPARE_REC28,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 27. "HW_SPARE_REC27,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 26. "HW_SPARE_REC26,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 25. "HW_SPARE_REC25,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 24. "HW_SPARE_REC24,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 23. "HW_SPARE_REC23,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 22. "HW_SPARE_REC22,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 21. "HW_SPARE_REC21,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 20. "HW_SPARE_REC20,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 19. "HW_SPARE_REC19,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 18. "HW_SPARE_REC18,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 17. "HW_SPARE_REC17,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 16. "HW_SPARE_REC16,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 15. "HW_SPARE_REC15,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 14. "HW_SPARE_REC14,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 13. "HW_SPARE_REC13,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 12. "HW_SPARE_REC12,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 11. "HW_SPARE_REC11,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 10. "HW_SPARE_REC10,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 9. "HW_SPARE_REC9,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 8. "HW_SPARE_REC8,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 7. "HW_SPARE_REC7,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 6. "HW_SPARE_REC6,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 5. "HW_SPARE_REC5,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 4. "HW_SPARE_REC4,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 3. "HW_SPARE_REC3,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 2. "HW_SPARE_REC2,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 1. "HW_SPARE_REC1,Reserved for HW R&D" "0,1" newline bitfld.long 0x4 0. "HW_SPARE_REC0,Reserved for HW R&D" "0,1" group.long 0x1008++0x7 line.long 0x0 "TOP_RCM_LOCK0_KICK0" hexmask.long 0x0 0.--31. 1. "LOCK0_KICK0,- KICK0 component" line.long 0x4 "TOP_RCM_LOCK0_KICK1" hexmask.long 0x4 0.--31. 1. "LOCK0_KICK1,- KICK1 component" group.byte 0x1010++0x0 line.byte 0x0 "TOP_RCM_INTR_RAW_STATUS" bitfld.byte 0x0 3. "PROXY_ERR,Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "KICK_ERR,Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ADDR_ERR,Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "PROT_ERR,Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect." "0,1" group.byte 0x1014++0x0 line.byte 0x0 "TOP_RCM_INTR_ENABLED_STATUS_CLEAR" bitfld.byte 0x0 3. "ENABLED_PROXY_ERR,Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "ENABLED_KICK_ERR,Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ENABLED_ADDR_ERR,Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "ENABLED_PROT_ERR,Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect." "0,1" group.byte 0x1018++0x0 line.byte 0x0 "TOP_RCM_INTR_ENABLE" bitfld.byte 0x0 3. "PROXY_ERR_EN,Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "KICK_ERR_EN,Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ADDR_ERR_EN,Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "PROT_ERR_EN,Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect." "0,1" group.byte 0x101C++0x0 line.byte 0x0 "TOP_RCM_INTR_ENABLE_CLEAR" bitfld.byte 0x0 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" newline bitfld.byte 0x0 0. "PROT_ERR_EN_CLR,Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect." "0,1" group.byte 0x1020++0x0 line.byte 0x0 "TOP_RCM_EOI" hexmask.byte 0x0 0.--7. 1. "EOI_VECTOR,EOI vector value. Write this with interrupt distribution value in the chip." rgroup.long 0x1024++0x3 line.long 0x0 "TOP_RCM_FAULT_ADDRESS" hexmask.long 0x0 0.--31. 1. "FAULT_ADDR,Fault Address." rgroup.byte 0x1028++0x0 line.byte 0x0 "TOP_RCM_FAULT_TYPE_STATUS" bitfld.byte 0x0 6. "FAULT_NS,Non-secure access." "0,1" newline hexmask.byte 0x0 0.--5. 1. "FAULT_TYPE,Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1.." rgroup.long 0x102C++0x3 line.long 0x0 "TOP_RCM_FAULT_ATTR_STATUS" hexmask.long.word 0x0 20.--31. 1. "FAULT_XID,XID." newline hexmask.long.word 0x0 8.--19. 1. "FAULT_ROUTEID,Route ID." newline hexmask.long.byte 0x0 0.--7. 1. "FAULT_PRIVID,Privilege ID." wgroup.long 0x1030++0x3 line.long 0x0 "TOP_RCM_FAULT_CLEAR" bitfld.long 0x0 0. "FAULT_CLR,Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect." "0,1" tree.end tree.end tree "TPCC" base ad:0x52A00000 rgroup.long 0x0++0x7 line.long 0x0 "TPCC0_PID" bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3" bitfld.long 0x0 28.--29. "RES1,RESERVE FIELD" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family." hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version" newline bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" line.long 0x4 "TPCC0_CCCFG" hexmask.long.byte 0x4 26.--31. 1. "RES2,RESERVE FIELD" bitfld.long 0x4 25. "MPEXIST,Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included." "0: No memory protection,1: Memory Protection logic included" newline bitfld.long 0x4 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included." "0: No Channel mapping,1: Channel mapping logic included" bitfld.long 0x4 22.--23. "RES3,RESERVE FIELD" "0,1,2,3" newline bitfld.long 0x4 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x4 19. "RES4,RESERVE FIELD" "0,1" newline bitfld.long 0x4 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x4 15. "RES5,RESERVE FIELD" "0,1" newline bitfld.long 0x4 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x4 11. "RES6,RESERVE FIELD" "0,1" newline bitfld.long 0x4 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x4 7. "RES7,RESERVE FIELD" "0,1" newline bitfld.long 0x4 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x4 3. "RES8,RESERVE FIELD" "0,1" newline bitfld.long 0x4 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7" group.long 0x200++0x3 line.long 0x0 "TPCC0_QCHMAPN" hexmask.long.tbyte 0x0 14.--31. 1. "RES10,RESERVE FIELD" hexmask.long.word 0x0 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N." newline bitfld.long 0x0 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" group.long 0x240++0x3 line.long 0x0 "TPCC0_DMAQNUMN" rbitfld.long 0x0 31. "RES11,RESERVE FIELD" "0,1" bitfld.long 0x0 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 27. "RES12,RESERVE FIELD" "0,1" bitfld.long 0x0 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 23. "RES13,RESERVE FIELD" "0,1" bitfld.long 0x0 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 19. "RES14,RESERVE FIELD" "0,1" bitfld.long 0x0 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 15. "RES15,RESERVE FIELD" "0,1" bitfld.long 0x0 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 11. "RES16,RESERVE FIELD" "0,1" bitfld.long 0x0 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 7. "RES17,RESERVE FIELD" "0,1" bitfld.long 0x0 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 3. "RES18,RESERVE FIELD" "0,1" bitfld.long 0x0 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x260++0x3 line.long 0x0 "TPCC0_QDMAQNUM" rbitfld.long 0x0 31. "RES19,RESERVE FIELD" "0,1" bitfld.long 0x0 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 27. "RES20,RESERVE FIELD" "0,1" bitfld.long 0x0 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 23. "RES21,RESERVE FIELD" "0,1" bitfld.long 0x0 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 19. "RES22,RESERVE FIELD" "0,1" bitfld.long 0x0 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 15. "RES23,RESERVE FIELD" "0,1" bitfld.long 0x0 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 11. "RES24,RESERVE FIELD" "0,1" bitfld.long 0x0 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 7. "RES25,RESERVE FIELD" "0,1" bitfld.long 0x0 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 3. "RES26,RESERVE FIELD" "0,1" bitfld.long 0x0 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" group.long 0x280++0x7 line.long 0x0 "TPCC0_QUETCMAP" hexmask.long 0x0 7.--31. 1. "RES27,RESERVE FIELD" bitfld.long 0x0 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 3. "RES28,RESERVE FIELD" "0,1" bitfld.long 0x0 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" line.long 0x4 "TPCC0_QUEPRI" hexmask.long 0x4 7.--31. 1. "RES29,RESERVE FIELD" bitfld.long 0x4 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 3. "RES30,RESERVE FIELD" "0,1" bitfld.long 0x4 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" rgroup.long 0x300++0x7 line.long 0x0 "TPCC0_EMR" bitfld.long 0x0 31. "E31,Event Missed #31" "0,1" bitfld.long 0x0 30. "E30,Event Missed #30" "0,1" newline bitfld.long 0x0 29. "E29,Event Missed #29" "0,1" bitfld.long 0x0 28. "E28,Event Missed #28" "0,1" newline bitfld.long 0x0 27. "E27,Event Missed #27" "0,1" bitfld.long 0x0 26. "E26,Event Missed #26" "0,1" newline bitfld.long 0x0 25. "E25,Event Missed #25" "0,1" bitfld.long 0x0 24. "E24,Event Missed #24" "0,1" newline bitfld.long 0x0 23. "E23,Event Missed #23" "0,1" bitfld.long 0x0 22. "E22,Event Missed #22" "0,1" newline bitfld.long 0x0 21. "E21,Event Missed #21" "0,1" bitfld.long 0x0 20. "E20,Event Missed #20" "0,1" newline bitfld.long 0x0 19. "E19,Event Missed #19" "0,1" bitfld.long 0x0 18. "E18,Event Missed #18" "0,1" newline bitfld.long 0x0 17. "E17,Event Missed #17" "0,1" bitfld.long 0x0 16. "E16,Event Missed #16" "0,1" newline bitfld.long 0x0 15. "E15,Event Missed #15" "0,1" bitfld.long 0x0 14. "E14,Event Missed #14" "0,1" newline bitfld.long 0x0 13. "E13,Event Missed #13" "0,1" bitfld.long 0x0 12. "E12,Event Missed #12" "0,1" newline bitfld.long 0x0 11. "E11,Event Missed #11" "0,1" bitfld.long 0x0 10. "E10,Event Missed #10" "0,1" newline bitfld.long 0x0 9. "E9,Event Missed #9" "0,1" bitfld.long 0x0 8. "E8,Event Missed #8" "0,1" newline bitfld.long 0x0 7. "E7,Event Missed #7" "0,1" bitfld.long 0x0 6. "E6,Event Missed #6" "0,1" newline bitfld.long 0x0 5. "E5,Event Missed #5" "0,1" bitfld.long 0x0 4. "E4,Event Missed #4" "0,1" newline bitfld.long 0x0 3. "E3,Event Missed #3" "0,1" bitfld.long 0x0 2. "E2,Event Missed #2" "0,1" newline bitfld.long 0x0 1. "E1,Event Missed #1" "0,1" bitfld.long 0x0 0. "E0,Event Missed #0" "0,1" line.long 0x4 "TPCC0_EMRH" bitfld.long 0x4 31. "E63,Event Missed #63" "0,1" bitfld.long 0x4 30. "E62,Event Missed #62" "0,1" newline bitfld.long 0x4 29. "E61,Event Missed #61" "0,1" bitfld.long 0x4 28. "E60,Event Missed #60" "0,1" newline bitfld.long 0x4 27. "E59,Event Missed #59" "0,1" bitfld.long 0x4 26. "E58,Event Missed #58" "0,1" newline bitfld.long 0x4 25. "E57,Event Missed #57" "0,1" bitfld.long 0x4 24. "E56,Event Missed #56" "0,1" newline bitfld.long 0x4 23. "E55,Event Missed #55" "0,1" bitfld.long 0x4 22. "E54,Event Missed #54" "0,1" newline bitfld.long 0x4 21. "E53,Event Missed #53" "0,1" bitfld.long 0x4 20. "E52,Event Missed #52" "0,1" newline bitfld.long 0x4 19. "E51,Event Missed #51" "0,1" bitfld.long 0x4 18. "E50,Event Missed #50" "0,1" newline bitfld.long 0x4 17. "E49,Event Missed #49" "0,1" bitfld.long 0x4 16. "E48,Event Missed #48" "0,1" newline bitfld.long 0x4 15. "E47,Event Missed #47" "0,1" bitfld.long 0x4 14. "E46,Event Missed #46" "0,1" newline bitfld.long 0x4 13. "E45,Event Missed #45" "0,1" bitfld.long 0x4 12. "E44,Event Missed #44" "0,1" newline bitfld.long 0x4 11. "E43,Event Missed #43" "0,1" bitfld.long 0x4 10. "E42,Event Missed #42" "0,1" newline bitfld.long 0x4 9. "E41,Event Missed #41" "0,1" bitfld.long 0x4 8. "E40,Event Missed #40" "0,1" newline bitfld.long 0x4 7. "E39,Event Missed #39" "0,1" bitfld.long 0x4 6. "E38,Event Missed #38" "0,1" newline bitfld.long 0x4 5. "E37,Event Missed #37" "0,1" bitfld.long 0x4 4. "E36,Event Missed #36" "0,1" newline bitfld.long 0x4 3. "E35,Event Missed #35" "0,1" bitfld.long 0x4 2. "E34,Event Missed #34" "0,1" newline bitfld.long 0x4 1. "E33,Event Missed #33" "0,1" bitfld.long 0x4 0. "E32,Event Missed #32" "0,1" wgroup.long 0x308++0x7 line.long 0x0 "TPCC0_EMCR" bitfld.long 0x0 31. "E31,Event Missed Clear #31" "0,1" bitfld.long 0x0 30. "E30,Event Missed Clear #30" "0,1" newline bitfld.long 0x0 29. "E29,Event Missed Clear #29" "0,1" bitfld.long 0x0 28. "E28,Event Missed Clear #28" "0,1" newline bitfld.long 0x0 27. "E27,Event Missed Clear #27" "0,1" bitfld.long 0x0 26. "E26,Event Missed Clear #26" "0,1" newline bitfld.long 0x0 25. "E25,Event Missed Clear #25" "0,1" bitfld.long 0x0 24. "E24,Event Missed Clear #24" "0,1" newline bitfld.long 0x0 23. "E23,Event Missed Clear #23" "0,1" bitfld.long 0x0 22. "E22,Event Missed Clear #22" "0,1" newline bitfld.long 0x0 21. "E21,Event Missed Clear #21" "0,1" bitfld.long 0x0 20. "E20,Event Missed Clear #20" "0,1" newline bitfld.long 0x0 19. "E19,Event Missed Clear #19" "0,1" bitfld.long 0x0 18. "E18,Event Missed Clear #18" "0,1" newline bitfld.long 0x0 17. "E17,Event Missed Clear #17" "0,1" bitfld.long 0x0 16. "E16,Event Missed Clear #16" "0,1" newline bitfld.long 0x0 15. "E15,Event Missed Clear #15" "0,1" bitfld.long 0x0 14. "E14,Event Missed Clear #14" "0,1" newline bitfld.long 0x0 13. "E13,Event Missed Clear #13" "0,1" bitfld.long 0x0 12. "E12,Event Missed Clear #12" "0,1" newline bitfld.long 0x0 11. "E11,Event Missed Clear #11" "0,1" bitfld.long 0x0 10. "E10,Event Missed Clear #10" "0,1" newline bitfld.long 0x0 9. "E9,Event Missed Clear #9" "0,1" bitfld.long 0x0 8. "E8,Event Missed Clear #8" "0,1" newline bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1" bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1" newline bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1" bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1" newline bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1" bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1" newline bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1" bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1" line.long 0x4 "TPCC0_EMCRH" bitfld.long 0x4 31. "E63,Event Missed Clear #63" "0,1" bitfld.long 0x4 30. "E62,Event Missed Clear #62" "0,1" newline bitfld.long 0x4 29. "E61,Event Missed Clear #61" "0,1" bitfld.long 0x4 28. "E60,Event Missed Clear #60" "0,1" newline bitfld.long 0x4 27. "E59,Event Missed Clear #59" "0,1" bitfld.long 0x4 26. "E58,Event Missed Clear #58" "0,1" newline bitfld.long 0x4 25. "E57,Event Missed Clear #57" "0,1" bitfld.long 0x4 24. "E56,Event Missed Clear #56" "0,1" newline bitfld.long 0x4 23. "E55,Event Missed Clear #55" "0,1" bitfld.long 0x4 22. "E54,Event Missed Clear #54" "0,1" newline bitfld.long 0x4 21. "E53,Event Missed Clear #53" "0,1" bitfld.long 0x4 20. "E52,Event Missed Clear #52" "0,1" newline bitfld.long 0x4 19. "E51,Event Missed Clear #51" "0,1" bitfld.long 0x4 18. "E50,Event Missed Clear #50" "0,1" newline bitfld.long 0x4 17. "E49,Event Missed Clear #49" "0,1" bitfld.long 0x4 16. "E48,Event Missed Clear #48" "0,1" newline bitfld.long 0x4 15. "E47,Event Missed Clear #47" "0,1" bitfld.long 0x4 14. "E46,Event Missed Clear #46" "0,1" newline bitfld.long 0x4 13. "E45,Event Missed Clear #45" "0,1" bitfld.long 0x4 12. "E44,Event Missed Clear #44" "0,1" newline bitfld.long 0x4 11. "E43,Event Missed Clear #43" "0,1" bitfld.long 0x4 10. "E42,Event Missed Clear #42" "0,1" newline bitfld.long 0x4 9. "E41,Event Missed Clear #41" "0,1" bitfld.long 0x4 8. "E40,Event Missed Clear #40" "0,1" newline bitfld.long 0x4 7. "E39,Event Missed Clear #39" "0,1" bitfld.long 0x4 6. "E38,Event Missed Clear #38" "0,1" newline bitfld.long 0x4 5. "E37,Event Missed Clear #37" "0,1" bitfld.long 0x4 4. "E36,Event Missed Clear #36" "0,1" newline bitfld.long 0x4 3. "E35,Event Missed Clear #35" "0,1" bitfld.long 0x4 2. "E34,Event Missed Clear #34" "0,1" newline bitfld.long 0x4 1. "E33,Event Missed Clear #33" "0,1" bitfld.long 0x4 0. "E32,Event Missed Clear #32" "0,1" rgroup.long 0x310++0x3 line.long 0x0 "TPCC0_QEMR" hexmask.long.tbyte 0x0 8.--31. 1. "RES31,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event Missed #7" "0,1" newline bitfld.long 0x0 6. "E6,Event Missed #6" "0,1" bitfld.long 0x0 5. "E5,Event Missed #5" "0,1" newline bitfld.long 0x0 4. "E4,Event Missed #4" "0,1" bitfld.long 0x0 3. "E3,Event Missed #3" "0,1" newline bitfld.long 0x0 2. "E2,Event Missed #2" "0,1" bitfld.long 0x0 1. "E1,Event Missed #1" "0,1" newline bitfld.long 0x0 0. "E0,Event Missed #0" "0,1" group.long 0x314++0x3 line.long 0x0 "TPCC0_QEMCR" hexmask.long.tbyte 0x0 8.--31. 1. "RES32,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event Missed Clear #7" "0,1" newline bitfld.long 0x0 6. "E6,Event Missed Clear #6" "0,1" bitfld.long 0x0 5. "E5,Event Missed Clear #5" "0,1" newline bitfld.long 0x0 4. "E4,Event Missed Clear #4" "0,1" bitfld.long 0x0 3. "E3,Event Missed Clear #3" "0,1" newline bitfld.long 0x0 2. "E2,Event Missed Clear #2" "0,1" bitfld.long 0x0 1. "E1,Event Missed Clear #1" "0,1" newline bitfld.long 0x0 0. "E0,Event Missed Clear #0" "0,1" rgroup.long 0x318++0x3 line.long 0x0 "TPCC0_CCERR" hexmask.long.word 0x0 17.--31. 1. "RES33,RESERVE FIELD" bitfld.long 0x0 16. "TCERR,Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR.." "0: Total number of allowed TCCs outstanding has not..,1: Total number of allowed TCCs has been reached" newline hexmask.long.byte 0x0 8.--15. 1. "RES34,RESERVE FIELD" bitfld.long 0x0 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" newline bitfld.long 0x0 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" bitfld.long 0x0 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" newline bitfld.long 0x0 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" bitfld.long 0x0 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" newline bitfld.long 0x0 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" bitfld.long 0x0 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" newline bitfld.long 0x0 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any.." "0: Watermark/threshold has not been exceeded,1: Watermark/threshold has been exceeded" group.long 0x31C++0x7 line.long 0x0 "TPCC0_CCERRCLR" hexmask.long.word 0x0 17.--31. 1. "RES35,RESERVE FIELD" bitfld.long 0x0 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RES36,RESERVE FIELD" bitfld.long 0x0 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect." "0,1" newline bitfld.long 0x0 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect." "0,1" bitfld.long 0x0 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect." "0,1" newline bitfld.long 0x0 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect." "0,1" bitfld.long 0x0 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect." "0,1" newline bitfld.long 0x0 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect." "0,1" bitfld.long 0x0 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect." "0,1" newline bitfld.long 0x0 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect." "0,1" line.long 0x4 "TPCC0_EEVAL" hexmask.long 0x4 2.--31. 1. "RES37,RESERVE FIELD" bitfld.long 0x4 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect." "0,1" newline bitfld.long 0x4 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect." "0,1" group.long 0x340++0x7 line.long 0x0 "TPCC0_DRAEM" bitfld.long 0x0 31. "E31,DMA Region Access enable for Region M bit #31" "0,1" bitfld.long 0x0 30. "E30,DMA Region Access enable for Region M bit #30" "0,1" newline bitfld.long 0x0 29. "E29,DMA Region Access enable for Region M bit #29" "0,1" bitfld.long 0x0 28. "E28,DMA Region Access enable for Region M bit #28" "0,1" newline bitfld.long 0x0 27. "E27,DMA Region Access enable for Region M bit #27" "0,1" bitfld.long 0x0 26. "E26,DMA Region Access enable for Region M bit #26" "0,1" newline bitfld.long 0x0 25. "E25,DMA Region Access enable for Region M bit #25" "0,1" bitfld.long 0x0 24. "E24,DMA Region Access enable for Region M bit #24" "0,1" newline bitfld.long 0x0 23. "E23,DMA Region Access enable for Region M bit #23" "0,1" bitfld.long 0x0 22. "E22,DMA Region Access enable for Region M bit #22" "0,1" newline bitfld.long 0x0 21. "E21,DMA Region Access enable for Region M bit #21" "0,1" bitfld.long 0x0 20. "E20,DMA Region Access enable for Region M bit #20" "0,1" newline bitfld.long 0x0 19. "E19,DMA Region Access enable for Region M bit #19" "0,1" bitfld.long 0x0 18. "E18,DMA Region Access enable for Region M bit #18" "0,1" newline bitfld.long 0x0 17. "E17,DMA Region Access enable for Region M bit #17" "0,1" bitfld.long 0x0 16. "E16,DMA Region Access enable for Region M bit #16" "0,1" newline bitfld.long 0x0 15. "E15,DMA Region Access enable for Region M bit #15" "0,1" bitfld.long 0x0 14. "E14,DMA Region Access enable for Region M bit #14" "0,1" newline bitfld.long 0x0 13. "E13,DMA Region Access enable for Region M bit #13" "0,1" bitfld.long 0x0 12. "E12,DMA Region Access enable for Region M bit #12" "0,1" newline bitfld.long 0x0 11. "E11,DMA Region Access enable for Region M bit #11" "0,1" bitfld.long 0x0 10. "E10,DMA Region Access enable for Region M bit #10" "0,1" newline bitfld.long 0x0 9. "E9,DMA Region Access enable for Region M bit #9" "0,1" bitfld.long 0x0 8. "E8,DMA Region Access enable for Region M bit #8" "0,1" newline bitfld.long 0x0 7. "E7,DMA Region Access enable for Region M bit #7" "0,1" bitfld.long 0x0 6. "E6,DMA Region Access enable for Region M bit #6" "0,1" newline bitfld.long 0x0 5. "E5,DMA Region Access enable for Region M bit #5" "0,1" bitfld.long 0x0 4. "E4,DMA Region Access enable for Region M bit #4" "0,1" newline bitfld.long 0x0 3. "E3,DMA Region Access enable for Region M bit #3" "0,1" bitfld.long 0x0 2. "E2,DMA Region Access enable for Region M bit #2" "0,1" newline bitfld.long 0x0 1. "E1,DMA Region Access enable for Region M bit #1" "0,1" bitfld.long 0x0 0. "E0,DMA Region Access enable for Region M bit #0" "0,1" line.long 0x4 "TPCC0_DRAEHM" bitfld.long 0x4 31. "E63,DMA Region Access enable for Region M bit #63" "0,1" bitfld.long 0x4 30. "E62,DMA Region Access enable for Region M bit #62" "0,1" newline bitfld.long 0x4 29. "E61,DMA Region Access enable for Region M bit #61" "0,1" bitfld.long 0x4 28. "E60,DMA Region Access enable for Region M bit #60" "0,1" newline bitfld.long 0x4 27. "E59,DMA Region Access enable for Region M bit #59" "0,1" bitfld.long 0x4 26. "E58,DMA Region Access enable for Region M bit #58" "0,1" newline bitfld.long 0x4 25. "E57,DMA Region Access enable for Region M bit #57" "0,1" bitfld.long 0x4 24. "E56,DMA Region Access enable for Region M bit #56" "0,1" newline bitfld.long 0x4 23. "E55,DMA Region Access enable for Region M bit #55" "0,1" bitfld.long 0x4 22. "E54,DMA Region Access enable for Region M bit #54" "0,1" newline bitfld.long 0x4 21. "E53,DMA Region Access enable for Region M bit #53" "0,1" bitfld.long 0x4 20. "E52,DMA Region Access enable for Region M bit #52" "0,1" newline bitfld.long 0x4 19. "E51,DMA Region Access enable for Region M bit #51" "0,1" bitfld.long 0x4 18. "E50,DMA Region Access enable for Region M bit #50" "0,1" newline bitfld.long 0x4 17. "E49,DMA Region Access enable for Region M bit #49" "0,1" bitfld.long 0x4 16. "E48,DMA Region Access enable for Region M bit #48" "0,1" newline bitfld.long 0x4 15. "E47,DMA Region Access enable for Region M bit #47" "0,1" bitfld.long 0x4 14. "E46,DMA Region Access enable for Region M bit #46" "0,1" newline bitfld.long 0x4 13. "E45,DMA Region Access enable for Region M bit #45" "0,1" bitfld.long 0x4 12. "E44,DMA Region Access enable for Region M bit #44" "0,1" newline bitfld.long 0x4 11. "E43,DMA Region Access enable for Region M bit #43" "0,1" bitfld.long 0x4 10. "E42,DMA Region Access enable for Region M bit #42" "0,1" newline bitfld.long 0x4 9. "E41,DMA Region Access enable for Region M bit #41" "0,1" bitfld.long 0x4 8. "E40,DMA Region Access enable for Region M bit #40" "0,1" newline bitfld.long 0x4 7. "E39,DMA Region Access enable for Region M bit #39" "0,1" bitfld.long 0x4 6. "E38,DMA Region Access enable for Region M bit #38" "0,1" newline bitfld.long 0x4 5. "E37,DMA Region Access enable for Region M bit #37" "0,1" bitfld.long 0x4 4. "E36,DMA Region Access enable for Region M bit #36" "0,1" newline bitfld.long 0x4 3. "E35,DMA Region Access enable for Region M bit #35" "0,1" bitfld.long 0x4 2. "E34,DMA Region Access enable for Region M bit #34" "0,1" newline bitfld.long 0x4 1. "E33,DMA Region Access enable for Region M bit #33" "0,1" bitfld.long 0x4 0. "E32,DMA Region Access enable for Region M bit #32" "0,1" group.long 0x380++0x3 line.long 0x0 "TPCC0_QRAEN" hexmask.long.tbyte 0x0 8.--31. 1. "RES38,RESERVE FIELD" bitfld.long 0x0 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1" newline bitfld.long 0x0 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1" bitfld.long 0x0 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1" newline bitfld.long 0x0 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1" bitfld.long 0x0 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1" newline bitfld.long 0x0 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1" bitfld.long 0x0 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1" newline bitfld.long 0x0 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1" rgroup.long 0x400++0x3F line.long 0x0 "TPCC0_QNE0" hexmask.long.tbyte 0x0 8.--31. 1. "RES39,RESERVE FIELD" bitfld.long 0x0 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." line.long 0x4 "TPCC0_QNE1" hexmask.long.tbyte 0x4 8.--31. 1. "RES40,RESERVE FIELD" bitfld.long 0x4 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." line.long 0x8 "TPCC0_QNE2" hexmask.long.tbyte 0x8 8.--31. 1. "RES41,RESERVE FIELD" bitfld.long 0x8 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x8 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." line.long 0xC "TPCC0_QNE3" hexmask.long.tbyte 0xC 8.--31. 1. "RES42,RESERVE FIELD" bitfld.long 0xC 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0xC 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." line.long 0x10 "TPCC0_QNE4" hexmask.long.tbyte 0x10 8.--31. 1. "RES43,RESERVE FIELD" bitfld.long 0x10 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x10 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." line.long 0x14 "TPCC0_QNE5" hexmask.long.tbyte 0x14 8.--31. 1. "RES44,RESERVE FIELD" bitfld.long 0x14 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x14 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." line.long 0x18 "TPCC0_QNE6" hexmask.long.tbyte 0x18 8.--31. 1. "RES45,RESERVE FIELD" bitfld.long 0x18 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x18 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." line.long 0x1C "TPCC0_QNE7" hexmask.long.tbyte 0x1C 8.--31. 1. "RES46,RESERVE FIELD" bitfld.long 0x1C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x1C 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." line.long 0x20 "TPCC0_QNE8" hexmask.long.tbyte 0x20 8.--31. 1. "RES47,RESERVE FIELD" bitfld.long 0x20 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x20 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." line.long 0x24 "TPCC0_QNE9" hexmask.long.tbyte 0x24 8.--31. 1. "RES48,RESERVE FIELD" bitfld.long 0x24 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x24 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." line.long 0x28 "TPCC0_QNE10" hexmask.long.tbyte 0x28 8.--31. 1. "RES49,RESERVE FIELD" bitfld.long 0x28 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x28 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." line.long 0x2C "TPCC0_QNE11" hexmask.long.tbyte 0x2C 8.--31. 1. "RES50,RESERVE FIELD" bitfld.long 0x2C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." line.long 0x30 "TPCC0_QNE12" hexmask.long.tbyte 0x30 8.--31. 1. "RES51,RESERVE FIELD" bitfld.long 0x30 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x30 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." line.long 0x34 "TPCC0_QNE13" hexmask.long.tbyte 0x34 8.--31. 1. "RES52,RESERVE FIELD" bitfld.long 0x34 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x34 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." line.long 0x38 "TPCC0_QNE14" hexmask.long.tbyte 0x38 8.--31. 1. "RES53,RESERVE FIELD" bitfld.long 0x38 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x38 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." line.long 0x3C "TPCC0_QNE15" hexmask.long.tbyte 0x3C 8.--31. 1. "RES54,RESERVE FIELD" bitfld.long 0x3C 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" newline hexmask.long.byte 0x3C 0.--5. 1. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and.." rgroup.long 0x600++0x3 line.long 0x0 "TPCC0_QSTATN" hexmask.long.byte 0x0 25.--31. 1. "RES55,RESERVE FIELD" bitfld.long 0x0 24. "THRXCD,Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit." "0: Threshold specified by QWMTHR,1: Threshold specified by QWMTHR" newline bitfld.long 0x0 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10.." newline bitfld.long 0x0 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full)" newline hexmask.long.byte 0x0 4.--7. 1. "RES58,RESERVE FIELD" hexmask.long.byte 0x0 0.--3. 1. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry)" group.long 0x620++0x3 line.long 0x0 "TPCC0_QWMTHRA" hexmask.long.tbyte 0x0 13.--31. 1. "RES59,RESERVE FIELD" hexmask.long.byte 0x0 8.--12. 1. "Q1,Queue Threshold for Q1 value" newline rbitfld.long 0x0 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "Q0,Queue Threshold for Q0 value" rgroup.long 0x640++0x3 line.long 0x0 "TPCC0_CCSTAT" hexmask.long.byte 0x0 24.--31. 1. "RES61,RESERVE FIELD" bitfld.long 0x0 23. "QUEACTV7,Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7." "0: No Evts are queued in Q7,1: At least one TR is queued in Q7" newline bitfld.long 0x0 22. "QUEACTV6,Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6." "0: No Evts are queued in Q6,1: At least one TR is queued in Q6" bitfld.long 0x0 21. "QUEACTV5,Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5." "0: No Evts are queued in Q5,1: At least one TR is queued in Q5" newline bitfld.long 0x0 20. "QUEACTV4,Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4." "0: No Evts are queued in Q4,1: At least one TR is queued in Q4" bitfld.long 0x0 19. "QUEACTV3,Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3." "0: No Evts are queued in Q3,1: At least one TR is queued in Q3" newline bitfld.long 0x0 18. "QUEACTV2,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0: No Evts are queued in Q2,1: At least one TR is queued in Q2" bitfld.long 0x0 17. "QUEACTV1,Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1." "0: No Evts are queued in Q1,1: At least one TR is queued in Q1" newline bitfld.long 0x0 16. "QUEACTV0,Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0." "0: No Evts are queued in Q0,1: At least one TR is queued in Q0" bitfld.long 0x0 14.--15. "RES62,RESERVE FIELD" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion.." bitfld.long 0x0 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy." "0: Channel is idle,1: Channel is busy" bitfld.long 0x0 3. "RES64,RESERVE FIELD" "0,1" newline bitfld.long 0x0 2. "TRACTV,Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0: Transfer Request processing/submission logic is..,1: Transfer Request processing/submission logic is.." bitfld.long 0x0 1. "QEVTACTV,QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC." "0: No enabled QDMA Events are active within the CC,1: At least one enabled DMA Event" newline bitfld.long 0x0 0. "EVTACTV,DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC." "0: No enabled DMA Events are active within the CC,1: At least one enabled DMA Event" group.long 0x700++0x3 line.long 0x0 "TPCC0_AETCTL" bitfld.long 0x0 31. "EN,AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled." "0: AET event generation is disabled,1: AET event generation is enabled" hexmask.long.tbyte 0x0 14.--30. 1. "RES65,RESERVE FIELD" newline hexmask.long.byte 0x0 8.--13. 1. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" rbitfld.long 0x0 7. "RES66,RESERVE FIELD" "0,1" newline bitfld.long 0x0 6. "TYPE,AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events" "0: Event specified by STARTEVT applies to DMA Events,1: Event specified by STARTEVT applies to QDMA Events" hexmask.long.byte 0x0 0.--5. 1. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" rgroup.long 0x704++0x3 line.long 0x0 "TPCC0_AETSTAT" hexmask.long 0x0 1.--31. 1. "RES67,RESERVE FIELD" bitfld.long 0x0 0. "STAT,AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high." "0: tpcc_aet is currently low,1: tpcc_aet is currently high" group.long 0x708++0x3 line.long 0x0 "TPCC0_AETCMD" hexmask.long 0x0 1.--31. 1. "RES68,RESERVE FIELD" bitfld.long 0x0 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.." "0,1" rgroup.long 0x1000++0x7 line.long 0x0 "TPCC0_ER" bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_ERH" bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" wgroup.long 0x1008++0xF line.long 0x0 "TPCC0_ECR" bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_ECRH" bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" line.long 0x8 "TPCC0_ESR" bitfld.long 0x8 31. "E31,Event #31" "0,1" bitfld.long 0x8 30. "E30,Event #30" "0,1" newline bitfld.long 0x8 29. "E29,Event #29" "0,1" bitfld.long 0x8 28. "E28,Event #28" "0,1" newline bitfld.long 0x8 27. "E27,Event #27" "0,1" bitfld.long 0x8 26. "E26,Event #26" "0,1" newline bitfld.long 0x8 25. "E25,Event #25" "0,1" bitfld.long 0x8 24. "E24,Event #24" "0,1" newline bitfld.long 0x8 23. "E23,Event #23" "0,1" bitfld.long 0x8 22. "E22,Event #22" "0,1" newline bitfld.long 0x8 21. "E21,Event #21" "0,1" bitfld.long 0x8 20. "E20,Event #20" "0,1" newline bitfld.long 0x8 19. "E19,Event #19" "0,1" bitfld.long 0x8 18. "E18,Event #18" "0,1" newline bitfld.long 0x8 17. "E17,Event #17" "0,1" bitfld.long 0x8 16. "E16,Event #16" "0,1" newline bitfld.long 0x8 15. "E15,Event #15" "0,1" bitfld.long 0x8 14. "E14,Event #14" "0,1" newline bitfld.long 0x8 13. "E13,Event #13" "0,1" bitfld.long 0x8 12. "E12,Event #12" "0,1" newline bitfld.long 0x8 11. "E11,Event #11" "0,1" bitfld.long 0x8 10. "E10,Event #10" "0,1" newline bitfld.long 0x8 9. "E9,Event #9" "0,1" bitfld.long 0x8 8. "E8,Event #8" "0,1" newline bitfld.long 0x8 7. "E7,Event #7" "0,1" bitfld.long 0x8 6. "E6,Event #6" "0,1" newline bitfld.long 0x8 5. "E5,Event #5" "0,1" bitfld.long 0x8 4. "E4,Event #4" "0,1" newline bitfld.long 0x8 3. "E3,Event #3" "0,1" bitfld.long 0x8 2. "E2,Event #2" "0,1" newline bitfld.long 0x8 1. "E1,Event #1" "0,1" bitfld.long 0x8 0. "E0,Event #0" "0,1" line.long 0xC "TPCC0_ESRH" bitfld.long 0xC 31. "E63,Event #63" "0,1" bitfld.long 0xC 30. "E62,Event #62" "0,1" newline bitfld.long 0xC 29. "E61,Event #61" "0,1" bitfld.long 0xC 28. "E60,Event #60" "0,1" newline bitfld.long 0xC 27. "E59,Event #59" "0,1" bitfld.long 0xC 26. "E58,Event #58" "0,1" newline bitfld.long 0xC 25. "E57,Event #57" "0,1" bitfld.long 0xC 24. "E56,Event #56" "0,1" newline bitfld.long 0xC 23. "E55,Event #55" "0,1" bitfld.long 0xC 22. "E54,Event #54" "0,1" newline bitfld.long 0xC 21. "E53,Event #53" "0,1" bitfld.long 0xC 20. "E52,Event #52" "0,1" newline bitfld.long 0xC 19. "E51,Event #51" "0,1" bitfld.long 0xC 18. "E50,Event #50" "0,1" newline bitfld.long 0xC 17. "E49,Event #49" "0,1" bitfld.long 0xC 16. "E48,Event #48" "0,1" newline bitfld.long 0xC 15. "E47,Event #47" "0,1" bitfld.long 0xC 14. "E46,Event #46" "0,1" newline bitfld.long 0xC 13. "E45,Event #45" "0,1" bitfld.long 0xC 12. "E44,Event #44" "0,1" newline bitfld.long 0xC 11. "E43,Event #43" "0,1" bitfld.long 0xC 10. "E42,Event #42" "0,1" newline bitfld.long 0xC 9. "E41,Event #41" "0,1" bitfld.long 0xC 8. "E40,Event #40" "0,1" newline bitfld.long 0xC 7. "E39,Event #39" "0,1" bitfld.long 0xC 6. "E38,Event #38" "0,1" newline bitfld.long 0xC 5. "E37,Event #37" "0,1" bitfld.long 0xC 4. "E36,Event #36" "0,1" newline bitfld.long 0xC 3. "E35,Event #35" "0,1" bitfld.long 0xC 2. "E34,Event #34" "0,1" newline bitfld.long 0xC 1. "E33,Event #33" "0,1" bitfld.long 0xC 0. "E32,Event #32" "0,1" rgroup.long 0x1018++0xF line.long 0x0 "TPCC0_CER" bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_CERH" bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" line.long 0x8 "TPCC0_EER" bitfld.long 0x8 31. "E31,Event #31" "0,1" bitfld.long 0x8 30. "E30,Event #30" "0,1" newline bitfld.long 0x8 29. "E29,Event #29" "0,1" bitfld.long 0x8 28. "E28,Event #28" "0,1" newline bitfld.long 0x8 27. "E27,Event #27" "0,1" bitfld.long 0x8 26. "E26,Event #26" "0,1" newline bitfld.long 0x8 25. "E25,Event #25" "0,1" bitfld.long 0x8 24. "E24,Event #24" "0,1" newline bitfld.long 0x8 23. "E23,Event #23" "0,1" bitfld.long 0x8 22. "E22,Event #22" "0,1" newline bitfld.long 0x8 21. "E21,Event #21" "0,1" bitfld.long 0x8 20. "E20,Event #20" "0,1" newline bitfld.long 0x8 19. "E19,Event #19" "0,1" bitfld.long 0x8 18. "E18,Event #18" "0,1" newline bitfld.long 0x8 17. "E17,Event #17" "0,1" bitfld.long 0x8 16. "E16,Event #16" "0,1" newline bitfld.long 0x8 15. "E15,Event #15" "0,1" bitfld.long 0x8 14. "E14,Event #14" "0,1" newline bitfld.long 0x8 13. "E13,Event #13" "0,1" bitfld.long 0x8 12. "E12,Event #12" "0,1" newline bitfld.long 0x8 11. "E11,Event #11" "0,1" bitfld.long 0x8 10. "E10,Event #10" "0,1" newline bitfld.long 0x8 9. "E9,Event #9" "0,1" bitfld.long 0x8 8. "E8,Event #8" "0,1" newline bitfld.long 0x8 7. "E7,Event #7" "0,1" bitfld.long 0x8 6. "E6,Event #6" "0,1" newline bitfld.long 0x8 5. "E5,Event #5" "0,1" bitfld.long 0x8 4. "E4,Event #4" "0,1" newline bitfld.long 0x8 3. "E3,Event #3" "0,1" bitfld.long 0x8 2. "E2,Event #2" "0,1" newline bitfld.long 0x8 1. "E1,Event #1" "0,1" bitfld.long 0x8 0. "E0,Event #0" "0,1" line.long 0xC "TPCC0_EERH" bitfld.long 0xC 31. "E63,Event #63" "0,1" bitfld.long 0xC 30. "E62,Event #62" "0,1" newline bitfld.long 0xC 29. "E61,Event #61" "0,1" bitfld.long 0xC 28. "E60,Event #60" "0,1" newline bitfld.long 0xC 27. "E59,Event #59" "0,1" bitfld.long 0xC 26. "E58,Event #58" "0,1" newline bitfld.long 0xC 25. "E57,Event #57" "0,1" bitfld.long 0xC 24. "E56,Event #56" "0,1" newline bitfld.long 0xC 23. "E55,Event #55" "0,1" bitfld.long 0xC 22. "E54,Event #54" "0,1" newline bitfld.long 0xC 21. "E53,Event #53" "0,1" bitfld.long 0xC 20. "E52,Event #52" "0,1" newline bitfld.long 0xC 19. "E51,Event #51" "0,1" bitfld.long 0xC 18. "E50,Event #50" "0,1" newline bitfld.long 0xC 17. "E49,Event #49" "0,1" bitfld.long 0xC 16. "E48,Event #48" "0,1" newline bitfld.long 0xC 15. "E47,Event #47" "0,1" bitfld.long 0xC 14. "E46,Event #46" "0,1" newline bitfld.long 0xC 13. "E45,Event #45" "0,1" bitfld.long 0xC 12. "E44,Event #44" "0,1" newline bitfld.long 0xC 11. "E43,Event #43" "0,1" bitfld.long 0xC 10. "E42,Event #42" "0,1" newline bitfld.long 0xC 9. "E41,Event #41" "0,1" bitfld.long 0xC 8. "E40,Event #40" "0,1" newline bitfld.long 0xC 7. "E39,Event #39" "0,1" bitfld.long 0xC 6. "E38,Event #38" "0,1" newline bitfld.long 0xC 5. "E37,Event #37" "0,1" bitfld.long 0xC 4. "E36,Event #36" "0,1" newline bitfld.long 0xC 3. "E35,Event #35" "0,1" bitfld.long 0xC 2. "E34,Event #34" "0,1" newline bitfld.long 0xC 1. "E33,Event #33" "0,1" bitfld.long 0xC 0. "E32,Event #32" "0,1" wgroup.long 0x1028++0xF line.long 0x0 "TPCC0_EECR" bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_EECRH" bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" line.long 0x8 "TPCC0_EESR" bitfld.long 0x8 31. "E31,Event #31" "0,1" bitfld.long 0x8 30. "E30,Event #30" "0,1" newline bitfld.long 0x8 29. "E29,Event #29" "0,1" bitfld.long 0x8 28. "E28,Event #28" "0,1" newline bitfld.long 0x8 27. "E27,Event #27" "0,1" bitfld.long 0x8 26. "E26,Event #26" "0,1" newline bitfld.long 0x8 25. "E25,Event #25" "0,1" bitfld.long 0x8 24. "E24,Event #24" "0,1" newline bitfld.long 0x8 23. "E23,Event #23" "0,1" bitfld.long 0x8 22. "E22,Event #22" "0,1" newline bitfld.long 0x8 21. "E21,Event #21" "0,1" bitfld.long 0x8 20. "E20,Event #20" "0,1" newline bitfld.long 0x8 19. "E19,Event #19" "0,1" bitfld.long 0x8 18. "E18,Event #18" "0,1" newline bitfld.long 0x8 17. "E17,Event #17" "0,1" bitfld.long 0x8 16. "E16,Event #16" "0,1" newline bitfld.long 0x8 15. "E15,Event #15" "0,1" bitfld.long 0x8 14. "E14,Event #14" "0,1" newline bitfld.long 0x8 13. "E13,Event #13" "0,1" bitfld.long 0x8 12. "E12,Event #12" "0,1" newline bitfld.long 0x8 11. "E11,Event #11" "0,1" bitfld.long 0x8 10. "E10,Event #10" "0,1" newline bitfld.long 0x8 9. "E9,Event #9" "0,1" bitfld.long 0x8 8. "E8,Event #8" "0,1" newline bitfld.long 0x8 7. "E7,Event #7" "0,1" bitfld.long 0x8 6. "E6,Event #6" "0,1" newline bitfld.long 0x8 5. "E5,Event #5" "0,1" bitfld.long 0x8 4. "E4,Event #4" "0,1" newline bitfld.long 0x8 3. "E3,Event #3" "0,1" bitfld.long 0x8 2. "E2,Event #2" "0,1" newline bitfld.long 0x8 1. "E1,Event #1" "0,1" bitfld.long 0x8 0. "E0,Event #0" "0,1" line.long 0xC "TPCC0_EESRH" bitfld.long 0xC 31. "E63,Event #63" "0,1" bitfld.long 0xC 30. "E62,Event #62" "0,1" newline bitfld.long 0xC 29. "E61,Event #61" "0,1" bitfld.long 0xC 28. "E60,Event #60" "0,1" newline bitfld.long 0xC 27. "E59,Event #59" "0,1" bitfld.long 0xC 26. "E58,Event #58" "0,1" newline bitfld.long 0xC 25. "E57,Event #57" "0,1" bitfld.long 0xC 24. "E56,Event #56" "0,1" newline bitfld.long 0xC 23. "E55,Event #55" "0,1" bitfld.long 0xC 22. "E54,Event #54" "0,1" newline bitfld.long 0xC 21. "E53,Event #53" "0,1" bitfld.long 0xC 20. "E52,Event #52" "0,1" newline bitfld.long 0xC 19. "E51,Event #51" "0,1" bitfld.long 0xC 18. "E50,Event #50" "0,1" newline bitfld.long 0xC 17. "E49,Event #49" "0,1" bitfld.long 0xC 16. "E48,Event #48" "0,1" newline bitfld.long 0xC 15. "E47,Event #47" "0,1" bitfld.long 0xC 14. "E46,Event #46" "0,1" newline bitfld.long 0xC 13. "E45,Event #45" "0,1" bitfld.long 0xC 12. "E44,Event #44" "0,1" newline bitfld.long 0xC 11. "E43,Event #43" "0,1" bitfld.long 0xC 10. "E42,Event #42" "0,1" newline bitfld.long 0xC 9. "E41,Event #41" "0,1" bitfld.long 0xC 8. "E40,Event #40" "0,1" newline bitfld.long 0xC 7. "E39,Event #39" "0,1" bitfld.long 0xC 6. "E38,Event #38" "0,1" newline bitfld.long 0xC 5. "E37,Event #37" "0,1" bitfld.long 0xC 4. "E36,Event #36" "0,1" newline bitfld.long 0xC 3. "E35,Event #35" "0,1" bitfld.long 0xC 2. "E34,Event #34" "0,1" newline bitfld.long 0xC 1. "E33,Event #33" "0,1" bitfld.long 0xC 0. "E32,Event #32" "0,1" rgroup.long 0x1038++0x7 line.long 0x0 "TPCC0_SER" bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_SERH" bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" wgroup.long 0x1040++0x7 line.long 0x0 "TPCC0_SECR" bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_SECRH" bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" rgroup.long 0x1050++0x7 line.long 0x0 "TPCC0_IER" bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC0_IERH" bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" wgroup.long 0x1058++0xF line.long 0x0 "TPCC0_IECR" bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC0_IECRH" bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x8 "TPCC0_IESR" bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0xC "TPCC0_IESRH" bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x1068++0x7 line.long 0x0 "TPCC0_IPR" bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC0_IPRH" bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" wgroup.long 0x1070++0x7 line.long 0x0 "TPCC0_ICR" bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC0_ICRH" bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x1078++0x3 line.long 0x0 "TPCC0_IEVAL" hexmask.long 0x0 2.--31. 1. "RES69,RESERVE FIELD" bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect." "0,1" newline bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.." "0,1" rgroup.long 0x1080++0x7 line.long 0x0 "TPCC0_QER" hexmask.long.tbyte 0x0 8.--31. 1. "RES70,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_QEER" hexmask.long.tbyte 0x4 8.--31. 1. "RES71,RESERVE FIELD" bitfld.long 0x4 7. "E7,Event #7" "0,1" newline bitfld.long 0x4 6. "E6,Event #6" "0,1" bitfld.long 0x4 5. "E5,Event #5" "0,1" newline bitfld.long 0x4 4. "E4,Event #4" "0,1" bitfld.long 0x4 3. "E3,Event #3" "0,1" newline bitfld.long 0x4 2. "E2,Event #2" "0,1" bitfld.long 0x4 1. "E1,Event #1" "0,1" newline bitfld.long 0x4 0. "E0,Event #0" "0,1" group.long 0x1088++0x7 line.long 0x0 "TPCC0_QEECR" hexmask.long.tbyte 0x0 8.--31. 1. "RES72,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_QEESR" hexmask.long.tbyte 0x4 8.--31. 1. "RES73,RESERVE FIELD" bitfld.long 0x4 7. "E7,Event #7" "0,1" newline bitfld.long 0x4 6. "E6,Event #6" "0,1" bitfld.long 0x4 5. "E5,Event #5" "0,1" newline bitfld.long 0x4 4. "E4,Event #4" "0,1" bitfld.long 0x4 3. "E3,Event #3" "0,1" newline bitfld.long 0x4 2. "E2,Event #2" "0,1" bitfld.long 0x4 1. "E1,Event #1" "0,1" newline bitfld.long 0x4 0. "E0,Event #0" "0,1" rgroup.long 0x1090++0x3 line.long 0x0 "TPCC0_QSER" hexmask.long.tbyte 0x0 8.--31. 1. "RES74,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" group.long 0x1094++0x3 line.long 0x0 "TPCC0_QSECR" hexmask.long.tbyte 0x0 8.--31. 1. "RES75,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" rgroup.long 0x2000++0x7 line.long 0x0 "TPCC0_ER_RN" bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_ERH_RN" bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" wgroup.long 0x2008++0xF line.long 0x0 "TPCC0_ECR_RN" bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_ECRH_RN" bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" line.long 0x8 "TPCC0_ESR_RN" bitfld.long 0x8 31. "E31,Event #31" "0,1" bitfld.long 0x8 30. "E30,Event #30" "0,1" newline bitfld.long 0x8 29. "E29,Event #29" "0,1" bitfld.long 0x8 28. "E28,Event #28" "0,1" newline bitfld.long 0x8 27. "E27,Event #27" "0,1" bitfld.long 0x8 26. "E26,Event #26" "0,1" newline bitfld.long 0x8 25. "E25,Event #25" "0,1" bitfld.long 0x8 24. "E24,Event #24" "0,1" newline bitfld.long 0x8 23. "E23,Event #23" "0,1" bitfld.long 0x8 22. "E22,Event #22" "0,1" newline bitfld.long 0x8 21. "E21,Event #21" "0,1" bitfld.long 0x8 20. "E20,Event #20" "0,1" newline bitfld.long 0x8 19. "E19,Event #19" "0,1" bitfld.long 0x8 18. "E18,Event #18" "0,1" newline bitfld.long 0x8 17. "E17,Event #17" "0,1" bitfld.long 0x8 16. "E16,Event #16" "0,1" newline bitfld.long 0x8 15. "E15,Event #15" "0,1" bitfld.long 0x8 14. "E14,Event #14" "0,1" newline bitfld.long 0x8 13. "E13,Event #13" "0,1" bitfld.long 0x8 12. "E12,Event #12" "0,1" newline bitfld.long 0x8 11. "E11,Event #11" "0,1" bitfld.long 0x8 10. "E10,Event #10" "0,1" newline bitfld.long 0x8 9. "E9,Event #9" "0,1" bitfld.long 0x8 8. "E8,Event #8" "0,1" newline bitfld.long 0x8 7. "E7,Event #7" "0,1" bitfld.long 0x8 6. "E6,Event #6" "0,1" newline bitfld.long 0x8 5. "E5,Event #5" "0,1" bitfld.long 0x8 4. "E4,Event #4" "0,1" newline bitfld.long 0x8 3. "E3,Event #3" "0,1" bitfld.long 0x8 2. "E2,Event #2" "0,1" newline bitfld.long 0x8 1. "E1,Event #1" "0,1" bitfld.long 0x8 0. "E0,Event #0" "0,1" line.long 0xC "TPCC0_ESRH_RN" bitfld.long 0xC 31. "E63,Event #63" "0,1" bitfld.long 0xC 30. "E62,Event #62" "0,1" newline bitfld.long 0xC 29. "E61,Event #61" "0,1" bitfld.long 0xC 28. "E60,Event #60" "0,1" newline bitfld.long 0xC 27. "E59,Event #59" "0,1" bitfld.long 0xC 26. "E58,Event #58" "0,1" newline bitfld.long 0xC 25. "E57,Event #57" "0,1" bitfld.long 0xC 24. "E56,Event #56" "0,1" newline bitfld.long 0xC 23. "E55,Event #55" "0,1" bitfld.long 0xC 22. "E54,Event #54" "0,1" newline bitfld.long 0xC 21. "E53,Event #53" "0,1" bitfld.long 0xC 20. "E52,Event #52" "0,1" newline bitfld.long 0xC 19. "E51,Event #51" "0,1" bitfld.long 0xC 18. "E50,Event #50" "0,1" newline bitfld.long 0xC 17. "E49,Event #49" "0,1" bitfld.long 0xC 16. "E48,Event #48" "0,1" newline bitfld.long 0xC 15. "E47,Event #47" "0,1" bitfld.long 0xC 14. "E46,Event #46" "0,1" newline bitfld.long 0xC 13. "E45,Event #45" "0,1" bitfld.long 0xC 12. "E44,Event #44" "0,1" newline bitfld.long 0xC 11. "E43,Event #43" "0,1" bitfld.long 0xC 10. "E42,Event #42" "0,1" newline bitfld.long 0xC 9. "E41,Event #41" "0,1" bitfld.long 0xC 8. "E40,Event #40" "0,1" newline bitfld.long 0xC 7. "E39,Event #39" "0,1" bitfld.long 0xC 6. "E38,Event #38" "0,1" newline bitfld.long 0xC 5. "E37,Event #37" "0,1" bitfld.long 0xC 4. "E36,Event #36" "0,1" newline bitfld.long 0xC 3. "E35,Event #35" "0,1" bitfld.long 0xC 2. "E34,Event #34" "0,1" newline bitfld.long 0xC 1. "E33,Event #33" "0,1" bitfld.long 0xC 0. "E32,Event #32" "0,1" rgroup.long 0x2018++0xF line.long 0x0 "TPCC0_CER_RN" bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_CERH_RN" bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" line.long 0x8 "TPCC0_EER_RN" bitfld.long 0x8 31. "E31,Event #31" "0,1" bitfld.long 0x8 30. "E30,Event #30" "0,1" newline bitfld.long 0x8 29. "E29,Event #29" "0,1" bitfld.long 0x8 28. "E28,Event #28" "0,1" newline bitfld.long 0x8 27. "E27,Event #27" "0,1" bitfld.long 0x8 26. "E26,Event #26" "0,1" newline bitfld.long 0x8 25. "E25,Event #25" "0,1" bitfld.long 0x8 24. "E24,Event #24" "0,1" newline bitfld.long 0x8 23. "E23,Event #23" "0,1" bitfld.long 0x8 22. "E22,Event #22" "0,1" newline bitfld.long 0x8 21. "E21,Event #21" "0,1" bitfld.long 0x8 20. "E20,Event #20" "0,1" newline bitfld.long 0x8 19. "E19,Event #19" "0,1" bitfld.long 0x8 18. "E18,Event #18" "0,1" newline bitfld.long 0x8 17. "E17,Event #17" "0,1" bitfld.long 0x8 16. "E16,Event #16" "0,1" newline bitfld.long 0x8 15. "E15,Event #15" "0,1" bitfld.long 0x8 14. "E14,Event #14" "0,1" newline bitfld.long 0x8 13. "E13,Event #13" "0,1" bitfld.long 0x8 12. "E12,Event #12" "0,1" newline bitfld.long 0x8 11. "E11,Event #11" "0,1" bitfld.long 0x8 10. "E10,Event #10" "0,1" newline bitfld.long 0x8 9. "E9,Event #9" "0,1" bitfld.long 0x8 8. "E8,Event #8" "0,1" newline bitfld.long 0x8 7. "E7,Event #7" "0,1" bitfld.long 0x8 6. "E6,Event #6" "0,1" newline bitfld.long 0x8 5. "E5,Event #5" "0,1" bitfld.long 0x8 4. "E4,Event #4" "0,1" newline bitfld.long 0x8 3. "E3,Event #3" "0,1" bitfld.long 0x8 2. "E2,Event #2" "0,1" newline bitfld.long 0x8 1. "E1,Event #1" "0,1" bitfld.long 0x8 0. "E0,Event #0" "0,1" line.long 0xC "TPCC0_EERH_RN" bitfld.long 0xC 31. "E63,Event #63" "0,1" bitfld.long 0xC 30. "E62,Event #62" "0,1" newline bitfld.long 0xC 29. "E61,Event #61" "0,1" bitfld.long 0xC 28. "E60,Event #60" "0,1" newline bitfld.long 0xC 27. "E59,Event #59" "0,1" bitfld.long 0xC 26. "E58,Event #58" "0,1" newline bitfld.long 0xC 25. "E57,Event #57" "0,1" bitfld.long 0xC 24. "E56,Event #56" "0,1" newline bitfld.long 0xC 23. "E55,Event #55" "0,1" bitfld.long 0xC 22. "E54,Event #54" "0,1" newline bitfld.long 0xC 21. "E53,Event #53" "0,1" bitfld.long 0xC 20. "E52,Event #52" "0,1" newline bitfld.long 0xC 19. "E51,Event #51" "0,1" bitfld.long 0xC 18. "E50,Event #50" "0,1" newline bitfld.long 0xC 17. "E49,Event #49" "0,1" bitfld.long 0xC 16. "E48,Event #48" "0,1" newline bitfld.long 0xC 15. "E47,Event #47" "0,1" bitfld.long 0xC 14. "E46,Event #46" "0,1" newline bitfld.long 0xC 13. "E45,Event #45" "0,1" bitfld.long 0xC 12. "E44,Event #44" "0,1" newline bitfld.long 0xC 11. "E43,Event #43" "0,1" bitfld.long 0xC 10. "E42,Event #42" "0,1" newline bitfld.long 0xC 9. "E41,Event #41" "0,1" bitfld.long 0xC 8. "E40,Event #40" "0,1" newline bitfld.long 0xC 7. "E39,Event #39" "0,1" bitfld.long 0xC 6. "E38,Event #38" "0,1" newline bitfld.long 0xC 5. "E37,Event #37" "0,1" bitfld.long 0xC 4. "E36,Event #36" "0,1" newline bitfld.long 0xC 3. "E35,Event #35" "0,1" bitfld.long 0xC 2. "E34,Event #34" "0,1" newline bitfld.long 0xC 1. "E33,Event #33" "0,1" bitfld.long 0xC 0. "E32,Event #32" "0,1" wgroup.long 0x2028++0xF line.long 0x0 "TPCC0_EECR_RN" bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_EECRH_RN" bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" line.long 0x8 "TPCC0_EESR_RN" bitfld.long 0x8 31. "E31,Event #31" "0,1" bitfld.long 0x8 30. "E30,Event #30" "0,1" newline bitfld.long 0x8 29. "E29,Event #29" "0,1" bitfld.long 0x8 28. "E28,Event #28" "0,1" newline bitfld.long 0x8 27. "E27,Event #27" "0,1" bitfld.long 0x8 26. "E26,Event #26" "0,1" newline bitfld.long 0x8 25. "E25,Event #25" "0,1" bitfld.long 0x8 24. "E24,Event #24" "0,1" newline bitfld.long 0x8 23. "E23,Event #23" "0,1" bitfld.long 0x8 22. "E22,Event #22" "0,1" newline bitfld.long 0x8 21. "E21,Event #21" "0,1" bitfld.long 0x8 20. "E20,Event #20" "0,1" newline bitfld.long 0x8 19. "E19,Event #19" "0,1" bitfld.long 0x8 18. "E18,Event #18" "0,1" newline bitfld.long 0x8 17. "E17,Event #17" "0,1" bitfld.long 0x8 16. "E16,Event #16" "0,1" newline bitfld.long 0x8 15. "E15,Event #15" "0,1" bitfld.long 0x8 14. "E14,Event #14" "0,1" newline bitfld.long 0x8 13. "E13,Event #13" "0,1" bitfld.long 0x8 12. "E12,Event #12" "0,1" newline bitfld.long 0x8 11. "E11,Event #11" "0,1" bitfld.long 0x8 10. "E10,Event #10" "0,1" newline bitfld.long 0x8 9. "E9,Event #9" "0,1" bitfld.long 0x8 8. "E8,Event #8" "0,1" newline bitfld.long 0x8 7. "E7,Event #7" "0,1" bitfld.long 0x8 6. "E6,Event #6" "0,1" newline bitfld.long 0x8 5. "E5,Event #5" "0,1" bitfld.long 0x8 4. "E4,Event #4" "0,1" newline bitfld.long 0x8 3. "E3,Event #3" "0,1" bitfld.long 0x8 2. "E2,Event #2" "0,1" newline bitfld.long 0x8 1. "E1,Event #1" "0,1" bitfld.long 0x8 0. "E0,Event #0" "0,1" line.long 0xC "TPCC0_EESRH_RN" bitfld.long 0xC 31. "E63,Event #63" "0,1" bitfld.long 0xC 30. "E62,Event #62" "0,1" newline bitfld.long 0xC 29. "E61,Event #61" "0,1" bitfld.long 0xC 28. "E60,Event #60" "0,1" newline bitfld.long 0xC 27. "E59,Event #59" "0,1" bitfld.long 0xC 26. "E58,Event #58" "0,1" newline bitfld.long 0xC 25. "E57,Event #57" "0,1" bitfld.long 0xC 24. "E56,Event #56" "0,1" newline bitfld.long 0xC 23. "E55,Event #55" "0,1" bitfld.long 0xC 22. "E54,Event #54" "0,1" newline bitfld.long 0xC 21. "E53,Event #53" "0,1" bitfld.long 0xC 20. "E52,Event #52" "0,1" newline bitfld.long 0xC 19. "E51,Event #51" "0,1" bitfld.long 0xC 18. "E50,Event #50" "0,1" newline bitfld.long 0xC 17. "E49,Event #49" "0,1" bitfld.long 0xC 16. "E48,Event #48" "0,1" newline bitfld.long 0xC 15. "E47,Event #47" "0,1" bitfld.long 0xC 14. "E46,Event #46" "0,1" newline bitfld.long 0xC 13. "E45,Event #45" "0,1" bitfld.long 0xC 12. "E44,Event #44" "0,1" newline bitfld.long 0xC 11. "E43,Event #43" "0,1" bitfld.long 0xC 10. "E42,Event #42" "0,1" newline bitfld.long 0xC 9. "E41,Event #41" "0,1" bitfld.long 0xC 8. "E40,Event #40" "0,1" newline bitfld.long 0xC 7. "E39,Event #39" "0,1" bitfld.long 0xC 6. "E38,Event #38" "0,1" newline bitfld.long 0xC 5. "E37,Event #37" "0,1" bitfld.long 0xC 4. "E36,Event #36" "0,1" newline bitfld.long 0xC 3. "E35,Event #35" "0,1" bitfld.long 0xC 2. "E34,Event #34" "0,1" newline bitfld.long 0xC 1. "E33,Event #33" "0,1" bitfld.long 0xC 0. "E32,Event #32" "0,1" rgroup.long 0x2038++0x7 line.long 0x0 "TPCC0_SER_RN" bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_SERH_RN" bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" wgroup.long 0x2040++0x7 line.long 0x0 "TPCC0_SECR_RN" bitfld.long 0x0 31. "E31,Event #31" "0,1" bitfld.long 0x0 30. "E30,Event #30" "0,1" newline bitfld.long 0x0 29. "E29,Event #29" "0,1" bitfld.long 0x0 28. "E28,Event #28" "0,1" newline bitfld.long 0x0 27. "E27,Event #27" "0,1" bitfld.long 0x0 26. "E26,Event #26" "0,1" newline bitfld.long 0x0 25. "E25,Event #25" "0,1" bitfld.long 0x0 24. "E24,Event #24" "0,1" newline bitfld.long 0x0 23. "E23,Event #23" "0,1" bitfld.long 0x0 22. "E22,Event #22" "0,1" newline bitfld.long 0x0 21. "E21,Event #21" "0,1" bitfld.long 0x0 20. "E20,Event #20" "0,1" newline bitfld.long 0x0 19. "E19,Event #19" "0,1" bitfld.long 0x0 18. "E18,Event #18" "0,1" newline bitfld.long 0x0 17. "E17,Event #17" "0,1" bitfld.long 0x0 16. "E16,Event #16" "0,1" newline bitfld.long 0x0 15. "E15,Event #15" "0,1" bitfld.long 0x0 14. "E14,Event #14" "0,1" newline bitfld.long 0x0 13. "E13,Event #13" "0,1" bitfld.long 0x0 12. "E12,Event #12" "0,1" newline bitfld.long 0x0 11. "E11,Event #11" "0,1" bitfld.long 0x0 10. "E10,Event #10" "0,1" newline bitfld.long 0x0 9. "E9,Event #9" "0,1" bitfld.long 0x0 8. "E8,Event #8" "0,1" newline bitfld.long 0x0 7. "E7,Event #7" "0,1" bitfld.long 0x0 6. "E6,Event #6" "0,1" newline bitfld.long 0x0 5. "E5,Event #5" "0,1" bitfld.long 0x0 4. "E4,Event #4" "0,1" newline bitfld.long 0x0 3. "E3,Event #3" "0,1" bitfld.long 0x0 2. "E2,Event #2" "0,1" newline bitfld.long 0x0 1. "E1,Event #1" "0,1" bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_SECRH_RN" bitfld.long 0x4 31. "E63,Event #63" "0,1" bitfld.long 0x4 30. "E62,Event #62" "0,1" newline bitfld.long 0x4 29. "E61,Event #61" "0,1" bitfld.long 0x4 28. "E60,Event #60" "0,1" newline bitfld.long 0x4 27. "E59,Event #59" "0,1" bitfld.long 0x4 26. "E58,Event #58" "0,1" newline bitfld.long 0x4 25. "E57,Event #57" "0,1" bitfld.long 0x4 24. "E56,Event #56" "0,1" newline bitfld.long 0x4 23. "E55,Event #55" "0,1" bitfld.long 0x4 22. "E54,Event #54" "0,1" newline bitfld.long 0x4 21. "E53,Event #53" "0,1" bitfld.long 0x4 20. "E52,Event #52" "0,1" newline bitfld.long 0x4 19. "E51,Event #51" "0,1" bitfld.long 0x4 18. "E50,Event #50" "0,1" newline bitfld.long 0x4 17. "E49,Event #49" "0,1" bitfld.long 0x4 16. "E48,Event #48" "0,1" newline bitfld.long 0x4 15. "E47,Event #47" "0,1" bitfld.long 0x4 14. "E46,Event #46" "0,1" newline bitfld.long 0x4 13. "E45,Event #45" "0,1" bitfld.long 0x4 12. "E44,Event #44" "0,1" newline bitfld.long 0x4 11. "E43,Event #43" "0,1" bitfld.long 0x4 10. "E42,Event #42" "0,1" newline bitfld.long 0x4 9. "E41,Event #41" "0,1" bitfld.long 0x4 8. "E40,Event #40" "0,1" newline bitfld.long 0x4 7. "E39,Event #39" "0,1" bitfld.long 0x4 6. "E38,Event #38" "0,1" newline bitfld.long 0x4 5. "E37,Event #37" "0,1" bitfld.long 0x4 4. "E36,Event #36" "0,1" newline bitfld.long 0x4 3. "E35,Event #35" "0,1" bitfld.long 0x4 2. "E34,Event #34" "0,1" newline bitfld.long 0x4 1. "E33,Event #33" "0,1" bitfld.long 0x4 0. "E32,Event #32" "0,1" rgroup.long 0x2050++0x7 line.long 0x0 "TPCC0_IER_RN" bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC0_IERH_RN" bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" wgroup.long 0x2058++0xF line.long 0x0 "TPCC0_IECR_RN" bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC0_IECRH_RN" bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" line.long 0x8 "TPCC0_IESR_RN" bitfld.long 0x8 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x8 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x8 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x8 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x8 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x8 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x8 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x8 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x8 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x8 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x8 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x8 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x8 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x8 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x8 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x8 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x8 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x8 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x8 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x8 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x8 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x8 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x8 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x8 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x8 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x8 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x8 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x8 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x8 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x8 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x8 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x8 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0xC "TPCC0_IESRH_RN" bitfld.long 0xC 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0xC 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0xC 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0xC 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0xC 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0xC 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0xC 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0xC 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0xC 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0xC 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0xC 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0xC 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0xC 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0xC 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0xC 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0xC 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0xC 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0xC 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0xC 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0xC 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0xC 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0xC 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0xC 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0xC 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0xC 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0xC 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0xC 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0xC 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0xC 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0xC 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0xC 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0xC 0. "I32,Interrupt associated with TCC #32" "0,1" rgroup.long 0x2068++0x7 line.long 0x0 "TPCC0_IPR_RN" bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC0_IPRH_RN" bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" wgroup.long 0x2070++0x7 line.long 0x0 "TPCC0_ICR_RN" bitfld.long 0x0 31. "I31,Interrupt associated with TCC #31" "0,1" bitfld.long 0x0 30. "I30,Interrupt associated with TCC #30" "0,1" newline bitfld.long 0x0 29. "I29,Interrupt associated with TCC #29" "0,1" bitfld.long 0x0 28. "I28,Interrupt associated with TCC #28" "0,1" newline bitfld.long 0x0 27. "I27,Interrupt associated with TCC #27" "0,1" bitfld.long 0x0 26. "I26,Interrupt associated with TCC #26" "0,1" newline bitfld.long 0x0 25. "I25,Interrupt associated with TCC #25" "0,1" bitfld.long 0x0 24. "I24,Interrupt associated with TCC #24" "0,1" newline bitfld.long 0x0 23. "I23,Interrupt associated with TCC #23" "0,1" bitfld.long 0x0 22. "I22,Interrupt associated with TCC #22" "0,1" newline bitfld.long 0x0 21. "I21,Interrupt associated with TCC #21" "0,1" bitfld.long 0x0 20. "I20,Interrupt associated with TCC #20" "0,1" newline bitfld.long 0x0 19. "I19,Interrupt associated with TCC #19" "0,1" bitfld.long 0x0 18. "I18,Interrupt associated with TCC #18" "0,1" newline bitfld.long 0x0 17. "I17,Interrupt associated with TCC #17" "0,1" bitfld.long 0x0 16. "I16,Interrupt associated with TCC #16" "0,1" newline bitfld.long 0x0 15. "I15,Interrupt associated with TCC #15" "0,1" bitfld.long 0x0 14. "I14,Interrupt associated with TCC #14" "0,1" newline bitfld.long 0x0 13. "I13,Interrupt associated with TCC #13" "0,1" bitfld.long 0x0 12. "I12,Interrupt associated with TCC #12" "0,1" newline bitfld.long 0x0 11. "I11,Interrupt associated with TCC #11" "0,1" bitfld.long 0x0 10. "I10,Interrupt associated with TCC #10" "0,1" newline bitfld.long 0x0 9. "I9,Interrupt associated with TCC #9" "0,1" bitfld.long 0x0 8. "I8,Interrupt associated with TCC #8" "0,1" newline bitfld.long 0x0 7. "I7,Interrupt associated with TCC #7" "0,1" bitfld.long 0x0 6. "I6,Interrupt associated with TCC #6" "0,1" newline bitfld.long 0x0 5. "I5,Interrupt associated with TCC #5" "0,1" bitfld.long 0x0 4. "I4,Interrupt associated with TCC #4" "0,1" newline bitfld.long 0x0 3. "I3,Interrupt associated with TCC #3" "0,1" bitfld.long 0x0 2. "I2,Interrupt associated with TCC #2" "0,1" newline bitfld.long 0x0 1. "I1,Interrupt associated with TCC #1" "0,1" bitfld.long 0x0 0. "I0,Interrupt associated with TCC #0" "0,1" line.long 0x4 "TPCC0_ICRH_RN" bitfld.long 0x4 31. "I63,Interrupt associated with TCC #63" "0,1" bitfld.long 0x4 30. "I62,Interrupt associated with TCC #62" "0,1" newline bitfld.long 0x4 29. "I61,Interrupt associated with TCC #61" "0,1" bitfld.long 0x4 28. "I60,Interrupt associated with TCC #60" "0,1" newline bitfld.long 0x4 27. "I59,Interrupt associated with TCC #59" "0,1" bitfld.long 0x4 26. "I58,Interrupt associated with TCC #58" "0,1" newline bitfld.long 0x4 25. "I57,Interrupt associated with TCC #57" "0,1" bitfld.long 0x4 24. "I56,Interrupt associated with TCC #56" "0,1" newline bitfld.long 0x4 23. "I55,Interrupt associated with TCC #55" "0,1" bitfld.long 0x4 22. "I54,Interrupt associated with TCC #54" "0,1" newline bitfld.long 0x4 21. "I53,Interrupt associated with TCC #53" "0,1" bitfld.long 0x4 20. "I52,Interrupt associated with TCC #52" "0,1" newline bitfld.long 0x4 19. "I51,Interrupt associated with TCC #51" "0,1" bitfld.long 0x4 18. "I50,Interrupt associated with TCC #50" "0,1" newline bitfld.long 0x4 17. "I49,Interrupt associated with TCC #49" "0,1" bitfld.long 0x4 16. "I48,Interrupt associated with TCC #48" "0,1" newline bitfld.long 0x4 15. "I47,Interrupt associated with TCC #47" "0,1" bitfld.long 0x4 14. "I46,Interrupt associated with TCC #46" "0,1" newline bitfld.long 0x4 13. "I45,Interrupt associated with TCC #45" "0,1" bitfld.long 0x4 12. "I44,Interrupt associated with TCC #44" "0,1" newline bitfld.long 0x4 11. "I43,Interrupt associated with TCC #43" "0,1" bitfld.long 0x4 10. "I42,Interrupt associated with TCC #42" "0,1" newline bitfld.long 0x4 9. "I41,Interrupt associated with TCC #41" "0,1" bitfld.long 0x4 8. "I40,Interrupt associated with TCC #40" "0,1" newline bitfld.long 0x4 7. "I39,Interrupt associated with TCC #39" "0,1" bitfld.long 0x4 6. "I38,Interrupt associated with TCC #38" "0,1" newline bitfld.long 0x4 5. "I37,Interrupt associated with TCC #37" "0,1" bitfld.long 0x4 4. "I36,Interrupt associated with TCC #36" "0,1" newline bitfld.long 0x4 3. "I35,Interrupt associated with TCC #35" "0,1" bitfld.long 0x4 2. "I34,Interrupt associated with TCC #34" "0,1" newline bitfld.long 0x4 1. "I33,Interrupt associated with TCC #33" "0,1" bitfld.long 0x4 0. "I32,Interrupt associated with TCC #32" "0,1" group.long 0x2078++0x3 line.long 0x0 "TPCC0_IEVAL_RN" hexmask.long 0x0 2.--31. 1. "RES76,RESERVE FIELD" bitfld.long 0x0 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect." "0,1" newline bitfld.long 0x0 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.." "0,1" rgroup.long 0x2080++0x7 line.long 0x0 "TPCC0_QER_RN" hexmask.long.tbyte 0x0 8.--31. 1. "RES77,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_QEER_RN" hexmask.long.tbyte 0x4 8.--31. 1. "RES78,RESERVE FIELD" bitfld.long 0x4 7. "E7,Event #7" "0,1" newline bitfld.long 0x4 6. "E6,Event #6" "0,1" bitfld.long 0x4 5. "E5,Event #5" "0,1" newline bitfld.long 0x4 4. "E4,Event #4" "0,1" bitfld.long 0x4 3. "E3,Event #3" "0,1" newline bitfld.long 0x4 2. "E2,Event #2" "0,1" bitfld.long 0x4 1. "E1,Event #1" "0,1" newline bitfld.long 0x4 0. "E0,Event #0" "0,1" group.long 0x2088++0x7 line.long 0x0 "TPCC0_QEECR_RN" hexmask.long.tbyte 0x0 8.--31. 1. "RES79,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" line.long 0x4 "TPCC0_QEESR_RN" hexmask.long.tbyte 0x4 8.--31. 1. "RES80,RESERVE FIELD" bitfld.long 0x4 7. "E7,Event #7" "0,1" newline bitfld.long 0x4 6. "E6,Event #6" "0,1" bitfld.long 0x4 5. "E5,Event #5" "0,1" newline bitfld.long 0x4 4. "E4,Event #4" "0,1" bitfld.long 0x4 3. "E3,Event #3" "0,1" newline bitfld.long 0x4 2. "E2,Event #2" "0,1" bitfld.long 0x4 1. "E1,Event #1" "0,1" newline bitfld.long 0x4 0. "E0,Event #0" "0,1" rgroup.long 0x2090++0x3 line.long 0x0 "TPCC0_QSER_RN" hexmask.long.tbyte 0x0 8.--31. 1. "RES81,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" group.long 0x2094++0x3 line.long 0x0 "TPCC0_QSECR_RN" hexmask.long.tbyte 0x0 8.--31. 1. "RES82,RESERVE FIELD" bitfld.long 0x0 7. "E7,Event #7" "0,1" newline bitfld.long 0x0 6. "E6,Event #6" "0,1" bitfld.long 0x0 5. "E5,Event #5" "0,1" newline bitfld.long 0x0 4. "E4,Event #4" "0,1" bitfld.long 0x0 3. "E3,Event #3" "0,1" newline bitfld.long 0x0 2. "E2,Event #2" "0,1" bitfld.long 0x0 1. "E1,Event #1" "0,1" newline bitfld.long 0x0 0. "E0,Event #0" "0,1" group.long 0x4000++0x1F line.long 0x0 "TPCC0_OPT" rbitfld.long 0x0 31. "PRIV,Privilege level: privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via.." "0: User level privilege PRIV =,1: Supervisor level privilege" rbitfld.long 0x0 28.--30. "RES83,RESERVE FIELD" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--27. 1. "PRIVID,Privilege ID: Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata.." bitfld.long 0x0 23. "ITCCHEN,Intermediate transfer completion chaining enable: 0: Intermediate transfer complete chaining is disabled. 1: Intermediate transfer complete chaining is enabled." "0: Intermediate transfer complete chaining is..,1: Intermediate transfer complete chaining is enabled" newline bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" bitfld.long 0x0 21. "ITCINTEN,Intermediate transfer completion interrupt enable: 0: Intermediate transfer complete interrupt is disabled. 1: Intermediate transfer complete interrupt is enabled (corresponding IER[TCC] bit must be set to 1 to generate interrupt)" "0: Intermediate transfer complete interrupt is..,1: Intermediate transfer complete interrupt is.." newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled (corresponding IER[TCC] bit must be set to 1 to generate interrupt)" "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" bitfld.long 0x0 19. "WIMODE,Backward compatibility mode: 0: Normal operation 1 : WI Backwards Compatibility mode forces BCNT to be adjusted by '1' upon TR submission (0 means 1 1 means 2 ... ) and forces ACNT to be treated as a word-count (left shifted by 2 by hardware.." "0: Normal operation,1: WI Backwards Compatibility mode forces BCNT to.." newline rbitfld.long 0x0 18. "RES84,RESERVE FIELD" "0,1" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER (bit CER[TCC]) for chaining or in IER (bit IER[TCC]) for interrupts." newline bitfld.long 0x0 11. "TCCMODE,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt. 0: Normal Completion A transfer is considered completed after the transfer parameters are returned to the.." "0: Normal Completion A transfer is considered..,1: Early Completion A transfer is considered.." bitfld.long 0x0 8.--10. "FWID,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 4.--7. 1. "RES85,RESERVE FIELD" bitfld.long 0x0 3. "STATIC,Static Entry: 0: Entry is updated as normal 1: Entry is static Count and Address updates are not updated after TRP is submitted. Linking is not performed." "0: Entry is updated as normal,1: Entry is static Count and Address updates are.." newline bitfld.long 0x0 2. "SYNCDIM,Transfer Synchronization Dimension: 0: A-Sync Each event triggers the transfer of ACNT elements. 1: AB-Sync Each event triggers the transfer of BCNT arrays of ACNT elements" "0: A-Sync Each event triggers the transfer of ACNT..,1: AB-Sync Each event triggers the transfer of BCNT.." bitfld.long 0x0 1. "DAM,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC. 0: INCR Dst addressing within an array increments. Dst is not a FIFO. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." newline bitfld.long 0x0 0. "SAM,Source Address Mode: Source Address Mode within an array. Pass-thru to TC. 0: INCR Src addressing within an array increments. Source is not a FIFO. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." line.long 0x4 "TPCC0_SRC" hexmask.long 0x4 0.--31. 1. "SRC,Source Address: The 32-bit source address parameters specify the starting byte address of the source . If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the OPT.FWID field. No.." line.long 0x8 "TPCC0_ABCNT" hexmask.long.word 0x8 16.--31. 1. "BCNT,BCNT : Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation valid values for BCNT can be anywhere between 1 and 65535. Therefore the maximum number of arrays in a.." hexmask.long.word 0x8 0.--15. 1. "ACNT,ACNT : number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore the maximum number of bytes in an array is.." line.long 0xC "TPCC0_DST" hexmask.long 0xC 0.--31. 1. "DST,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by the.." line.long 0x10 "TPCC0_BIDX" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address.." hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from.." line.long 0x14 "TPCC0_LNK" hexmask.long.word 0x14 16.--31. 1. "BCNTRLD,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case the CC decrements the BCNT value by one on.." hexmask.long.word 0x14 0.--15. 1. "LINK,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the.." line.long 0x18 "TPCC0_CIDX" hexmask.long.word 0x18 16.--31. 1. "DCIDX,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of.." hexmask.long.word 0x18 0.--15. 1. "SCIDX,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current.." line.long 0x1C "TPCC0_CCNT" hexmask.long.word 0x1C 16.--31. 1. "RES86,RESERVE FIELD" hexmask.long.word 0x1C 0.--15. 1. "CCNT,CCNT : Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore the maximum number of frames in a block is 65535 (64K-1.." tree.end tree "TPTC" base ad:0x0 tree "TPTC00" base ad:0x52A40000 rgroup.long 0x0++0x3 line.long 0x0 "TPTC00_PID" bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version" bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" rgroup.word 0x4++0x1 line.word 0x0 "TPTC00_TCCFG" bitfld.word 0x0 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3" bitfld.word 0x0 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3" newline bitfld.word 0x0 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" rgroup.word 0x100++0x1 line.word 0x0 "TPTC00_TCSTAT" bitfld.word 0x0 12.--13. "DFSTRTPTR,Dst FIFO Start PointerRepresents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3" "0,1,2,3" bitfld.word 0x0 8. "ACTV,Channel ActiveChannel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.ACTV = 0 : Channel is idle.ACTV = 1 : Channel is busy." "0: Channel is idle,1: Channel is busy" newline bitfld.word 0x0 4.--6. "DSTACTV,Destination Active StateSpecifies the number of TRs that are resident in the Dst Register FIFO at a given instant.Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.word 0x0 2. "WSACTV,Write Status ActiveWSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands." "0: Write status is not pending,1: Write Status is pending" newline bitfld.word 0x0 1. "SRCACTV,Source Active StateSRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full [DSTFULL == 1].SRCACTV = 1 : Source Active set is busy either.." "0: Source Active set is idle,1: Source Active set is busy either performing read.." bitfld.word 0x0 0. "PROGBUSY,Program Register Set BusyPROGBUSY = 0 : Prog set idle and is available for programming.PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set." "0: Prog set idle and is available for programming,1: Prog set busy" rgroup.byte 0x104++0x0 line.byte 0x0 "TPTC00_INTSTAT" bitfld.byte 0x0 1. "TRDONE,TR Done Event Status:TRDONE = 0 : Condition not detected.TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE.." "0: Condition not detected,1: Set when TC has completed a Transfer Request" bitfld.byte 0x0 0. "PROGEMPTY,Program Set Empty Event Status:PROGEMPTY = 0 : Condition not detected.PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit." "0: Condition not detected,1: Set when Program Register set transitions to.." group.byte 0x108++0x0 line.byte 0x0 "TPTC00_INTEN" bitfld.byte 0x0 1. "TRDONE,TR Done Event Enable:INTEN.TRDONE = 0 : TRDONE Event is disabled.INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation" "0: TRDONE Event is disabled,1: TRDONE Event is enabled and contributes to.." bitfld.byte 0x0 0. "PROGEMPTY,Program Set Empty Event Enable:INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation" "0: PROGEMPTY Event is disabled,1: PROGEMPTY Event is enabled and contributes to.." wgroup.byte 0x10C++0x0 line.byte 0x0 "TPTC00_INTCLR" bitfld.byte 0x0 1. "TRDONE,TR Done Event Clear:INTCLR.TRDONE = 0 : Writes of '0' have no effect.INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT" bitfld.byte 0x0 0. "PROGEMPTY,Program Set Empty Event Clear:INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT" wgroup.byte 0x110++0x0 line.byte 0x0 "TPTC00_INTCMD" bitfld.byte 0x0 1. "SET,Set TPTC interrupt:Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.Writes of '0' have no affect." "0,1" bitfld.byte 0x0 0. "EVAL,Evaluate state of TPTC interruptWrite of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.Writes of '0' have no affect." "0,1" rgroup.byte 0x120++0x0 line.byte 0x0 "TPTC00_ERRSTAT" bitfld.byte 0x0 3. "MMRAERR,MMR Address Error:MMRAERR = 0 : Condition not detected.MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. [Is only be set for non-emulation accesses]. No additional error information is recorded." "0: Condition not detected,1: User attempted to read or write to invalid.." bitfld.byte 0x0 2. "TRERR,TR Error:TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" newline bitfld.byte 0x0 0. "BUSERR,Bus Error Event:BUSERR = 0: Condition not detected.BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register [ERRDET]." "0: Condition not detected,1: TC has detected an error code on the write.." group.byte 0x124++0x0 line.byte 0x0 "TPTC00_ERREN" bitfld.byte 0x0 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR:ERREN.MMRAERR = 0 : BUSERR is disabled.ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: MMRAERR is enabled and contributes to the TPTC.." bitfld.byte 0x0 2. "TRERR,Interrupt enable for ERRSTAT.TRERR:ERREN.TRERR = 0 : BUSERR is disabled.ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: TRERR is enabled and contributes to the TPTC.." newline bitfld.byte 0x0 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR:ERREN.BUSERR = 0 : BUSERR is disabled.ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: BUSERR is enabled and contributes to the TPTC.." wgroup.byte 0x128++0x0 line.byte 0x0 "TPTC00_ERRCLR" bitfld.byte 0x0 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR:ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT" bitfld.byte 0x0 2. "TRERR,Interrupt clear for ERRSTAT.TRERR:ERRCLR.TRERR = 0 : Writes of '0' have no effect.ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT" newline bitfld.byte 0x0 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR:ERRCLR.BUSERR = 0 : Writes of '0' have no effect.ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT" rgroup.tbyte 0x12C++0x2 line.tbyte 0x0 "TPTC00_ERRDET" bitfld.tbyte 0x0 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.tbyte 0x0 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" newline hexmask.tbyte.byte 0x0 8.--13. 1. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error." hexmask.tbyte.byte 0x0 0.--3. 1. "STAT,Transaction Status:Stores the non-zero status/error code that was detected on the read status or write status bus.MS-bit effectively serves as the read vs. write error code.If read status and write status are returned on the same cycle then the TC.." wgroup.byte 0x130++0x0 line.byte 0x0 "TPTC00_ERRCMD" bitfld.byte 0x0 1. "SET,Set TPTC error interrupt:Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.Writes of '0' have no affect." "0,1" bitfld.byte 0x0 0. "EVAL,Evaluate state of TPTC error interruptWrite of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.Writes of '0' have no affect." "0,1" group.byte 0x140++0x0 line.byte 0x0 "TPTC00_RDRATE" bitfld.byte 0x0 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" group.long 0x200++0x13 line.long 0x0 "TPTC00_POPT" bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0: Transfer complete chaining is disabled.1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0: Transfer complete interrupt is disabled.1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0: Priority 0 - Highest priority1: Priority 1 ...7: Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0: INCR Dst addressing within an array increments.1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0: INCR Src addressing within an array increments.1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." line.long 0x4 "TPTC00_PSRC" hexmask.long 0x4 0.--31. 1. "SADDR,Source address for Program Register Set" line.long 0x8 "TPTC00_PCNT" hexmask.long.word 0x8 16.--31. 1. "BCNT,B-Dimension count. Number of arrays to be transferred where each array is ACNT in length." hexmask.long.word 0x8 0.--15. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension." line.long 0xC "TPTC00_PDST" hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Program Register Set" line.long 0x10 "TPTC00_PBIDX" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set:B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used regardless.." hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set:B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of.." rgroup.word 0x214++0x1 line.word 0x0 "TPTC00_PMPPRXY" bitfld.word 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.word 0x0 8. "PRIV,Privilege Level:PRIV = 0 : User level privilegePRIV = 1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.word.byte 0x0 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." group.long 0x240++0x3 line.long 0x0 "TPTC00_SAOPT" bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0: Transfer complete chaining is disabled.1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0: Transfer complete interrupt is disabled.1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0: Priority 0 - Highest priority1: Priority 1 ...7: Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0: INCR Dst addressing within an array increments.1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0: INCR Src addressing within an array increments.1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." rgroup.long 0x244++0x3 line.long 0x0 "TPTC00_SASRC" hexmask.long 0x0 0.--31. 1. "SADDR,Source address for Source Active Register Set" rgroup.tbyte 0x248++0x2 line.tbyte 0x0 "TPTC00_SACNT" hexmask.tbyte 0x0 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension." rgroup.long 0x24C++0x7 line.long 0x0 "TPTC00_SADST" hexmask.long 0x0 0.--31. 1. "DADDR,Destination address for Source Active Register Set" line.long 0x4 "TPTC00_SABIDX" hexmask.long.word 0x4 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set:B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.." hexmask.long.word 0x4 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set:B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless.." rgroup.word 0x254++0x1 line.word 0x0 "TPTC00_SAMPPRXY" bitfld.word 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.word 0x0 8. "PRIV,Privilege Level:PRIV = 0 : User level privilegePRIV = 1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.word.byte 0x0 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." rgroup.word 0x258++0x1 line.word 0x0 "TPTC00_SACNTRLD" hexmask.word 0x0 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the Src.." rgroup.long 0x25C++0x7 line.long 0x0 "TPTC00_SASRCBREF" hexmask.long 0x0 0.--31. 1. "SADDRBREF,Source address reference for Source Active Register Set:Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." line.long 0x4 "TPTC00_SADSTBREF" hexmask.long 0x4 0.--31. 1. "DADDRBREF,Dst address reference is not applicable for Src Active Register Set. Reads return 0x0." rgroup.word 0x264++0x1 line.word 0x0 "TPTC00_SABCNT" hexmask.word 0x0 0.--15. 1. "BCNT,B-Dimension count:Number of arrays to be transferred where each array is ACNT in length.Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT.." rgroup.word 0x280++0x1 line.word 0x0 "TPTC00_DFCNTRLD" hexmask.word 0x0 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the.." rgroup.long 0x284++0x3 line.long 0x0 "TPTC00_DFSRCBREF" hexmask.long 0x0 0.--31. 1. "SADDRBREF,Source address reference for Destination FIFO Register Set:Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.long 0x300++0x3 line.long 0x0 "TPTC00_DFOPT0" bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0: Transfer complete chaining is disabled.1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0: Transfer complete interrupt is disabled.1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0: Priority 0 - Highest priority1: Priority 1 ...7: Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0: INCR Dst addressing within an array increments.1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0: INCR Src addressing within an array increments.1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." rgroup.long 0x304++0x3 line.long 0x0 "TPTC00_DFSRC0" hexmask.long 0x0 0.--31. 1. "SADDR,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." rgroup.tbyte 0x308++0x2 line.tbyte 0x0 "TPTC00_DFACNT0" hexmask.tbyte 0x0 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred infirst dimension." rgroup.long 0x30C++0x7 line.long 0x0 "TPTC00_DFDST0" hexmask.long 0x0 0.--31. 1. "DADDR,Destination address for Dst FIFO Register Set:Initial value is copied from PDST.DADDR.TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.When a TR is complete.." line.long 0x4 "TPTC00_DFBIDX0" hexmask.long.word 0x4 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].DBIDX.." hexmask.long.word 0x4 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].SBIDX is always.." rgroup.word 0x314++0x1 line.word 0x0 "TPTC00_DFMPPRXY0" bitfld.word 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.word 0x0 8. "PRIV,Privilege Level:PRIV = 0 : User level privilegePRIV = 1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.word.byte 0x0 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." rgroup.word 0x318++0x1 line.word 0x0 "TPTC00_DFBCNT0" hexmask.word 0x0 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set:Number of arrays to be transferred where each array is ACNT in length.Represents the amount of data remaining to be written.Initial value is copied from PCNT.TC decrements ACNT and BCNT as necessary after each.." group.long 0x340++0x3 line.long 0x0 "TPTC00_DFOPT1" bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0: Transfer complete chaining is disabled.1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0: Transfer complete interrupt is disabled.1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0: Priority 0 - Highest priority1: Priority 1 ...7: Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0: INCR Dst addressing within an array increments.1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0: INCR Src addressing within an array increments.1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." rgroup.long 0x344++0x3 line.long 0x0 "TPTC00_DFSRC1" hexmask.long 0x0 0.--31. 1. "SADDR,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." rgroup.tbyte 0x348++0x2 line.tbyte 0x0 "TPTC00_DFACNT1" hexmask.tbyte 0x0 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred infirst dimension." rgroup.long 0x34C++0x7 line.long 0x0 "TPTC00_DFDST1" hexmask.long 0x0 0.--31. 1. "DADDR,Destination address for Dst FIFO Register Set:Initial value is copied from PDST.DADDR.TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.When a TR is complete.." line.long 0x4 "TPTC00_DFBIDX1" hexmask.long.word 0x4 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].DBIDX.." hexmask.long.word 0x4 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].SBIDX is always.." rgroup.word 0x354++0x1 line.word 0x0 "TPTC00_DFMPPRXY1" bitfld.word 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.word 0x0 8. "PRIV,Privilege Level:PRIV = 0 : User level privilegePRIV = 1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.word.byte 0x0 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." rgroup.word 0x358++0x1 line.word 0x0 "TPTC00_DFBCNT1" hexmask.word 0x0 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set:Number of arrays to be transferred where each array is ACNT in length.Represents the amount of data remaining to be written.Initial value is copied from PCNT.TC decrements ACNT and BCNT as necessary after each.." tree.end tree "TPTC01" base ad:0x52A60000 rgroup.long 0x0++0x3 line.long 0x0 "TPTC01_PID" bitfld.long 0x0 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1." "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Function indicates a software compatible module family." newline hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL Version" bitfld.long 0x0 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor Revision" rgroup.word 0x4++0x1 line.word 0x0 "TPTC01_TCCFG" bitfld.word 0x0 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3" bitfld.word 0x0 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3" newline bitfld.word 0x0 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" rgroup.word 0x100++0x1 line.word 0x0 "TPTC01_TCSTAT" bitfld.word 0x0 12.--13. "DFSTRTPTR,Dst FIFO Start PointerRepresents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3" "0,1,2,3" bitfld.word 0x0 8. "ACTV,Channel ActiveChannel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.ACTV = 0 : Channel is idle.ACTV = 1 : Channel is busy." "0: Channel is idle,1: Channel is busy" newline bitfld.word 0x0 4.--6. "DSTACTV,Destination Active StateSpecifies the number of TRs that are resident in the Dst Register FIFO at a given instant.Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.word 0x0 2. "WSACTV,Write Status ActiveWSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands." "0: Write status is not pending,1: Write Status is pending" newline bitfld.word 0x0 1. "SRCACTV,Source Active StateSRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full [DSTFULL == 1].SRCACTV = 1 : Source Active set is busy either.." "0: Source Active set is idle,1: Source Active set is busy either performing read.." bitfld.word 0x0 0. "PROGBUSY,Program Register Set BusyPROGBUSY = 0 : Prog set idle and is available for programming.PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set." "0: Prog set idle and is available for programming,1: Prog set busy" rgroup.byte 0x104++0x0 line.byte 0x0 "TPTC01_INTSTAT" bitfld.byte 0x0 1. "TRDONE,TR Done Event Status:TRDONE = 0 : Condition not detected.TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE.." "0: Condition not detected,1: Set when TC has completed a Transfer Request" bitfld.byte 0x0 0. "PROGEMPTY,Program Set Empty Event Status:PROGEMPTY = 0 : Condition not detected.PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit." "0: Condition not detected,1: Set when Program Register set transitions to.." group.byte 0x108++0x0 line.byte 0x0 "TPTC01_INTEN" bitfld.byte 0x0 1. "TRDONE,TR Done Event Enable:INTEN.TRDONE = 0 : TRDONE Event is disabled.INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation" "0: TRDONE Event is disabled,1: TRDONE Event is enabled and contributes to.." bitfld.byte 0x0 0. "PROGEMPTY,Program Set Empty Event Enable:INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation" "0: PROGEMPTY Event is disabled,1: PROGEMPTY Event is enabled and contributes to.." wgroup.byte 0x10C++0x0 line.byte 0x0 "TPTC01_INTCLR" bitfld.byte 0x0 1. "TRDONE,TR Done Event Clear:INTCLR.TRDONE = 0 : Writes of '0' have no effect.INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT" bitfld.byte 0x0 0. "PROGEMPTY,Program Set Empty Event Clear:INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit" "0: Writes of '0' have no effect,1: Write of '1' clears INTSTAT" wgroup.byte 0x110++0x0 line.byte 0x0 "TPTC01_INTCMD" bitfld.byte 0x0 1. "SET,Set TPTC interrupt:Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.Writes of '0' have no affect." "0,1" bitfld.byte 0x0 0. "EVAL,Evaluate state of TPTC interruptWrite of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.Writes of '0' have no affect." "0,1" rgroup.byte 0x120++0x0 line.byte 0x0 "TPTC01_ERRSTAT" bitfld.byte 0x0 3. "MMRAERR,MMR Address Error:MMRAERR = 0 : Condition not detected.MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. [Is only be set for non-emulation accesses]. No additional error information is recorded." "0: Condition not detected,1: User attempted to read or write to invalid.." bitfld.byte 0x0 2. "TRERR,TR Error:TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" newline bitfld.byte 0x0 0. "BUSERR,Bus Error Event:BUSERR = 0: Condition not detected.BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register [ERRDET]." "0: Condition not detected,1: TC has detected an error code on the write.." group.byte 0x124++0x0 line.byte 0x0 "TPTC01_ERREN" bitfld.byte 0x0 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR:ERREN.MMRAERR = 0 : BUSERR is disabled.ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: MMRAERR is enabled and contributes to the TPTC.." bitfld.byte 0x0 2. "TRERR,Interrupt enable for ERRSTAT.TRERR:ERREN.TRERR = 0 : BUSERR is disabled.ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: TRERR is enabled and contributes to the TPTC.." newline bitfld.byte 0x0 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR:ERREN.BUSERR = 0 : BUSERR is disabled.ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation." "0: BUSERR is disabled,1: BUSERR is enabled and contributes to the TPTC.." wgroup.byte 0x128++0x0 line.byte 0x0 "TPTC01_ERRCLR" bitfld.byte 0x0 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR:ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT" bitfld.byte 0x0 2. "TRERR,Interrupt clear for ERRSTAT.TRERR:ERRCLR.TRERR = 0 : Writes of '0' have no effect.ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT" newline bitfld.byte 0x0 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR:ERRCLR.BUSERR = 0 : Writes of '0' have no effect.ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register." "0: Writes of '0' have no effect,1: Write of '1' clears ERRSTAT" rgroup.tbyte 0x12C++0x2 line.tbyte 0x0 "TPTC01_ERRDET" bitfld.tbyte 0x0 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.tbyte 0x0 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" newline hexmask.tbyte.byte 0x0 8.--13. 1. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error." hexmask.tbyte.byte 0x0 0.--3. 1. "STAT,Transaction Status:Stores the non-zero status/error code that was detected on the read status or write status bus.MS-bit effectively serves as the read vs. write error code.If read status and write status are returned on the same cycle then the TC.." wgroup.byte 0x130++0x0 line.byte 0x0 "TPTC01_ERRCMD" bitfld.byte 0x0 1. "SET,Set TPTC error interrupt:Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.Writes of '0' have no affect." "0,1" bitfld.byte 0x0 0. "EVAL,Evaluate state of TPTC error interruptWrite of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.Writes of '0' have no affect." "0,1" group.byte 0x140++0x0 line.byte 0x0 "TPTC01_RDRATE" bitfld.byte 0x0 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" group.long 0x200++0x13 line.long 0x0 "TPTC01_POPT" bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0: Transfer complete chaining is disabled.1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0: Transfer complete interrupt is disabled.1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0: Priority 0 - Highest priority1: Priority 1 ...7: Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0: INCR Dst addressing within an array increments.1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0: INCR Src addressing within an array increments.1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." line.long 0x4 "TPTC01_PSRC" hexmask.long 0x4 0.--31. 1. "SADDR,Source address for Program Register Set" line.long 0x8 "TPTC01_PCNT" hexmask.long.word 0x8 16.--31. 1. "BCNT,B-Dimension count. Number of arrays to be transferred where each array is ACNT in length." hexmask.long.word 0x8 0.--15. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension." line.long 0xC "TPTC01_PDST" hexmask.long 0xC 0.--31. 1. "DADDR,Destination address for Program Register Set" line.long 0x10 "TPTC01_PBIDX" hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set:B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used regardless.." hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set:B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of.." rgroup.word 0x214++0x1 line.word 0x0 "TPTC01_PMPPRXY" bitfld.word 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.word 0x0 8. "PRIV,Privilege Level:PRIV = 0 : User level privilegePRIV = 1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.word.byte 0x0 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." group.long 0x240++0x3 line.long 0x0 "TPTC01_SAOPT" bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0: Transfer complete chaining is disabled.1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0: Transfer complete interrupt is disabled.1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0: Priority 0 - Highest priority1: Priority 1 ...7: Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0: INCR Dst addressing within an array increments.1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0: INCR Src addressing within an array increments.1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." rgroup.long 0x244++0x3 line.long 0x0 "TPTC01_SASRC" hexmask.long 0x0 0.--31. 1. "SADDR,Source address for Source Active Register Set" rgroup.tbyte 0x248++0x2 line.tbyte 0x0 "TPTC01_SACNT" hexmask.tbyte 0x0 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred in first dimension." rgroup.long 0x24C++0x7 line.long 0x0 "TPTC01_SADST" hexmask.long 0x0 0.--31. 1. "DADDR,Destination address for Source Active Register Set" line.long 0x4 "TPTC01_SABIDX" hexmask.long.word 0x4 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set:B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used.." hexmask.long.word 0x4 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set:B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless.." rgroup.word 0x254++0x1 line.word 0x0 "TPTC01_SAMPPRXY" bitfld.word 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.word 0x0 8. "PRIV,Privilege Level:PRIV = 0 : User level privilegePRIV = 1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.word.byte 0x0 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." rgroup.word 0x258++0x1 line.word 0x0 "TPTC01_SACNTRLD" hexmask.word 0x0 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the Src.." rgroup.long 0x25C++0x7 line.long 0x0 "TPTC01_SASRCBREF" hexmask.long 0x0 0.--31. 1. "SADDRBREF,Source address reference for Source Active Register Set:Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." line.long 0x4 "TPTC01_SADSTBREF" hexmask.long 0x4 0.--31. 1. "DADDRBREF,Dst address reference is not applicable for Src Active Register Set. Reads return 0x0." rgroup.word 0x264++0x1 line.word 0x0 "TPTC01_SABCNT" hexmask.word 0x0 0.--15. 1. "BCNT,B-Dimension count:Number of arrays to be transferred where each array is ACNT in length.Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT.." rgroup.word 0x280++0x1 line.word 0x0 "TPTC01_DFCNTRLD" hexmask.word 0x0 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the.." rgroup.long 0x284++0x3 line.long 0x0 "TPTC01_DFSRCBREF" hexmask.long 0x0 0.--31. 1. "SADDRBREF,Source address reference for Destination FIFO Register Set:Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.long 0x300++0x3 line.long 0x0 "TPTC01_DFOPT0" bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0: Transfer complete chaining is disabled.1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0: Transfer complete interrupt is disabled.1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0: Priority 0 - Highest priority1: Priority 1 ...7: Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0: INCR Dst addressing within an array increments.1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0: INCR Src addressing within an array increments.1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." rgroup.long 0x304++0x3 line.long 0x0 "TPTC01_DFSRC0" hexmask.long 0x0 0.--31. 1. "SADDR,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." rgroup.tbyte 0x308++0x2 line.tbyte 0x0 "TPTC01_DFACNT0" hexmask.tbyte 0x0 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred infirst dimension." rgroup.long 0x30C++0x7 line.long 0x0 "TPTC01_DFDST0" hexmask.long 0x0 0.--31. 1. "DADDR,Destination address for Dst FIFO Register Set:Initial value is copied from PDST.DADDR.TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.When a TR is complete.." line.long 0x4 "TPTC01_DFBIDX0" hexmask.long.word 0x4 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].DBIDX.." hexmask.long.word 0x4 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].SBIDX is always.." rgroup.word 0x314++0x1 line.word 0x0 "TPTC01_DFMPPRXY0" bitfld.word 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.word 0x0 8. "PRIV,Privilege Level:PRIV = 0 : User level privilegePRIV = 1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.word.byte 0x0 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." rgroup.word 0x318++0x1 line.word 0x0 "TPTC01_DFBCNT0" hexmask.word 0x0 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set:Number of arrays to be transferred where each array is ACNT in length.Represents the amount of data remaining to be written.Initial value is copied from PCNT.TC decrements ACNT and BCNT as necessary after each.." group.long 0x340++0x3 line.long 0x0 "TPTC01_DFOPT1" bitfld.long 0x0 28.--29. "DBG_ID,Debug IDValue driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.Used at system level for trace/profiling of user selected transfers in systems that include this feature." "0,1,2,3" bitfld.long 0x0 22. "TCCHEN,Transfer complete chaining enable:0: Transfer complete chaining is disabled.1: Transfer complete chaining is enabled." "0: Transfer complete chaining is disabled,1: Transfer complete chaining is enabled" newline bitfld.long 0x0 20. "TCINTEN,Transfer complete interrupt enable:0: Transfer complete interrupt is disabled.1: Transfer complete interrupt is enabled." "0: Transfer complete interrupt is disabled,1: Transfer complete interrupt is enabled" hexmask.long.byte 0x0 12.--17. 1. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module." newline bitfld.long 0x0 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--6. "PRI,Transfer Priority:0: Priority 0 - Highest priority1: Priority 1 ...7: Priority 7 - Lowest priority" "0: Priority 0,?,?,?,?,?,?,7: Priority 7" newline bitfld.long 0x0 1. "DAM,Destination Address Mode within an array:0: INCR Dst addressing within an array increments.1: FIFO Dst addressing within an array wraps around upon reaching FIFO width." "0: INCR Dst addressing within an array increments,1: FIFO Dst addressing within an array wraps around.." bitfld.long 0x0 0. "SAM,Source Address Mode within an array:0: INCR Src addressing within an array increments.1: FIFO Src addressing within an array wraps around upon reaching FIFO width." "0: INCR Src addressing within an array increments,1: FIFO Src addressing within an array wraps around.." rgroup.long 0x344++0x3 line.long 0x0 "TPTC01_DFSRC1" hexmask.long 0x0 0.--31. 1. "SADDR,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." rgroup.tbyte 0x348++0x2 line.tbyte 0x0 "TPTC01_DFACNT1" hexmask.tbyte 0x0 0.--22. 1. "ACNT,A-Dimension count. Number of bytes to be transferred infirst dimension." rgroup.long 0x34C++0x7 line.long 0x0 "TPTC01_DFDST1" hexmask.long 0x0 0.--31. 1. "DADDR,Destination address for Dst FIFO Register Set:Initial value is copied from PDST.DADDR.TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.When a TR is complete.." line.long 0x4 "TPTC01_DFBIDX1" hexmask.long.word 0x4 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].DBIDX.." hexmask.long.word 0x4 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set.Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].SBIDX is always.." rgroup.word 0x354++0x1 line.word 0x0 "TPTC01_DFMPPRXY1" bitfld.word 0x0 9. "SECURE,Secure Level: Deprecated always read as 0." "0,1" bitfld.word 0x0 8. "PRIV,Privilege Level:PRIV = 0 : User level privilegePRIV = 1 : Supervisor level privilegePMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].The PRIV.." "0: User level privilegePRIV =,1: Supervisor level privilegePMPPRXY" newline hexmask.word.byte 0x0 0.--3. 1. "PRIVID,Privilege ID:PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].The PRIVID value for the SA Set and DF Set are copied from the value in the.." rgroup.word 0x358++0x1 line.word 0x0 "TPTC01_DFBCNT1" hexmask.word 0x0 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set:Number of arrays to be transferred where each array is ACNT in length.Represents the amount of data remaining to be written.Initial value is copied from PCNT.TC decrements ACNT and BCNT as necessary after each.." tree.end tree.end tree "UART" base ad:0x0 tree "UART0" base ad:0x52300000 group.byte 0x0++0x0 line.byte 0x0 "UART0_DLL" hexmask.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART0_RHR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x3 line.long 0x0 "UART0_THR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" group.byte 0x4++0x0 line.byte 0x0 "UART0_DLH" hexmask.byte 0x0 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.byte 0x4++0x0 line.byte 0x0 "UART0_IER_CIR" bitfld.byte 0x0 6.--7. "NOT_USED2,Not Defined" "0,1,2,3" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined 0 | TX_STATUS_IT_VALUE_0Disables the TX status interrupt. 1 | TX_STATUS_IT_VALUE_1Enables the TX status interrupt." "0,1" newline bitfld.byte 0x0 4. "NOT_USED1,Not Defined" "0,1" newline bitfld.byte 0x0 3. "RX_OVERRUN_IT,Not Defined 0 | RX_OVERRUN_IT_VALUE_0Disables the RX overrun interrupt. 1 | RX_OVERRUN_IT_VALUE_1Enables the RX overrun interrupt." "0,1" newline bitfld.byte 0x0 2. "RX_STOP_IT,Not Defined 0 | RX_STOP_IT_VALUE_0Disables the receive stop interrupt. 1 | RX_STOP_IT_VALUE_1Enables the receive stop interrupt." "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt. 1 | THR_IT_VALUE_1Enables the THR interrupt." "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt." "0,1" group.byte 0x4++0x0 line.byte 0x0 "UART0_IER_IRDA" bitfld.byte 0x0 7. "EOF_IT,Not Defined 0 | EOF_IT_VALUE_0Disables the received EOF interrupt. 1 | EOF_IT_VALUE_1Enables the received EOF interrupt." "0,1" newline bitfld.byte 0x0 6. "LINE_STS_IT,Not Defined 0 | LINE_STS_IT_VALUE_0Disables the receiver line status interrupt. 1 | LINE_STS_IT_VALUE_1Enables the receiver line status interrupt." "0,1" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined 0 | TX_STATUS_IT_VALUE_0Disables the TX status interrupt. 1 | TX_STATUS_IT_VALUE_1Enables the TX status interrupt." "0,1" newline bitfld.byte 0x0 4. "STS_FIFO_TRIG_IT,Not Defined 0 | STS_FIFO_TRIG_IT_VALUE_0Disables the status FIFO trigger level interrupt. 1 | STS_FIFO_TRIG_IT_VALUE_1Enables the status FIFO trigger level interrupt." "0,1" newline bitfld.byte 0x0 3. "RX_OVERRUN_IT,Not Defined 0 | RX_OVERRUN_IT_VALUE_0Disables the RX overrun interrupt. 1 | RX_OVERRUN_IT_VALUE_1Enables the RX overrun interrupt." "0,1" newline bitfld.byte 0x0 2. "LAST_RX_BYTE_IT,Not Defined 0 | LAST_RX_BYTE_IT_VALUE_0Disables the last byte of frame in RX FIFO interrupt. 1 | LAST_RX_BYTE_IT_VALUE_1Enables the last byte of frame in RX FIFO interrupt." "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt. 1 | THR_IT_VALUE_1Enables the THR interrupt." "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt." "0,1" group.long 0x4++0x3 line.long 0x0 "UART0_IER_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "CTS_IT,Not Defined 0 | CTS_IT_VALUE_0Disables the CTS* interrupt 1 | CTS_IT_VALUE_1Enables the CTS* interrupt" "0,1" newline bitfld.long 0x0 6. "RTS_IT,Not Defined 0 | RTS_IT_VALUE_0Disables the RTS* interrupt 1 | RTS_IT_VALUE_1Enables the RTS* interrupt" "0,1" newline bitfld.long 0x0 5. "XOFF_IT,Not Defined 0 | XOFF_IT_VALUE_0Disables the XOFF interrupt 1 | XOFF_IT_VALUE_1Enables the XOFF interrupt" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE,Not Defined 0 | SLEEP_MODE_VALUE_0Disables sleep mode 1 | SLEEP_MODE_VALUE_1Enables sleep mode (stop baud rate clock when the module is inactive)" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT,Not Defined 0 | MODEM_STS_IT_VALUE_0Disables the modem status register interrupt 1 | MODEM_STS_IT_VALUE_1Enables the modem status register interrupt" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT,Not Defined 0 | LINE_STS_IT_U_VALUE_0Disables the receiver line status interrupt 1 | LINE_STS_IT_U_VALUE_1Enables the receiver line status interrupt" "0,1" newline bitfld.long 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt 1 | THR_IT_VALUE_1Enables the THR interrupt" "0,1" newline bitfld.long 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt and time out interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt and time out interrupt." "0,1" group.byte 0x8++0x0 line.byte 0x0 "UART0_EFR" bitfld.byte 0x0 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.byte 0x0 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.byte 0x0 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.byte 0x0 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.byte 0x0 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" group.long 0x8++0x3 line.long 0x0 "UART0_FCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO:If SCR[7] = 0 and TLR[7:4] = 0000:00: 8 characters01: 16 characters10: 56 characters11: 60 charactersIf SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered.If SCR[7]=1 RX_FIFO_TRIG is 2.." "0: 8 characters01: 16 characters10: 56..,?,?,?" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO:If SCR[6] = 0 and TLR[3:0] = 0000:00: 8 spaces01: 16 spaces10: 32 spaces11: 56 spacesIf SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered.If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of the.." "0: 8 spaces01: 16 spaces10: 32 spaces11: 56..,?,?,?" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0. Write0 | DMA_MODE_VALUE_0DMA_MODE 0 (No DMA) Write1 | DMA_MODE_VALUE_1DMA_MODE 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR,Not Defined Write0 | TX_FIFO_CLEAR_VALUE_0No change Write1 | TX_FIFO_CLEAR_VALUE_1Clears the transmit FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR,Not Defined Write0 | RX_FIFO_CLEAR_VALUE_0No change Write1 | RX_FIFO_CLEAR_VALUE_1Clears the receive FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 0. "FIFO_EN,Not Defined Write0 | FIFO_EN_VALUE_0Disables the transmit and receive FIFOs. The transmit and receive holding registers are one byte FIFOs. Write1 | FIFO_EN_VALUE_1: Enables the transmit and receive FIFOs.The transmit and receive.." "0,1" rgroup.byte 0x8++0x0 line.byte 0x0 "UART0_IIR_CIR" bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined Read0 | TX_STATUS_IT_VALUE_0TX status interrupt inactive Read1 | TX_STATUS_IT_VALUE_1TX status interrupt active" "0,1" newline bitfld.byte 0x0 3. "RX_OE_IT,Not Defined Read0 | RX_OE_IT_VALUE_0RX overrun interrupt inactive Read1 | RX_OE_IT_VALUE_1RX overrun interrupt active" "0,1" newline bitfld.byte 0x0 2. "RX_STOP_IT,Not Defined Read0 | RX_STOP_IT_VALUE_0Receive stop interrupt inactive Read1 | RX_STOP_IT_VALUE_1Receive stop interrupt active" "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined Read0 | THR_IT_VALUE_0THR interrupt inactive Read1 | THR_IT_VALUE_1THR interrupt active" "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined Read0 | RHR_IT_VALUE_0RHR interrupt inactive Read1 | RHR_IT_VALUE_1RHR interrupt active" "0,1" rgroup.byte 0x8++0x0 line.byte 0x0 "UART0_IIR_IRDA" bitfld.byte 0x0 7. "EOF_IT,Not Defined Read0 | EOF_IT_VALUE_0Received EOF interrupt inactive Read1 | EOF_IT_VALUE_1Received EOF interrupt active" "0,1" newline bitfld.byte 0x0 6. "LINE_STS_IT,Not Defined Read0 | LINE_STS_IT_VALUE_0Receiver line status interrupt inactive Read1 | LINE_STS_IT_VALUE_1Receiver line status interrupt active" "0,1" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined Read0 | TX_STATUS_IT_VALUE_0TX status interrupt inactive Read1 | TX_STATUS_IT_VALUE_1TX status interrupt active" "0,1" newline bitfld.byte 0x0 4. "STS_FIFO_IT,Not Defined Read0 | STS_FIFO_IT_VALUE_0Status FIFO trigger level interrupt inactive Read1 | STS_FIFO_IT_VALUE_1Status FIFO trigger level interrupt active" "0,1" newline bitfld.byte 0x0 3. "RX_OE_IT,Not Defined Read0 | RX_OE_IT_VALUE_0RX overrun interrupt inactive Read1 | RX_OE_IT_VALUE_1RX overrun interrupt active" "0,1" newline bitfld.byte 0x0 2. "RX_FIFO_LAST_BYTE_IT,Not Defined Read0 | RX_FIFO_LAST_BYTE_IT_VALUE_0Last byte of frame in RX FIFO interrupt inactive Read1 | RX_FIFO_LAST_BYTE_IT_VALUE_1Last byte of frame in RX FIFO interrupt active" "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined Read0 | THR_IT_VALUE_0THR interrupt inactive Read1 | THR_IT_VALUE_1THR interrupt active" "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined Read0 | RHR_IT_VALUE_0RHR interrupt inactive Read1 | RHR_IT_VALUE_1RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART0_IIR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Not Defined Read0x00 | IT_TYPE_VALUE_0Modem Interrupt. Priority=4 Read0x01 | IT_TYPE_VALUE_1THR interrupt. Priority=3 Read0x02 | IT_TYPE_VALUE_2RHR interrupt. Priority=2 Read0x03 | IT_TYPE_VALUE_3Receiver line.." newline bitfld.long 0x0 0. "IT_PENDING,Not Defined Read0 | IT_PENDING_VALUE_0An interrupt is pending Read1 | IT_PENDING_VALUE_1No interrupt is pending" "0,1" group.long 0xC++0x3 line.long 0x0 "UART0_LCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "DIV_EN,Not Defined 0 | DIV_EN_VALUE_0Normal operating condition 1 | DIV_EN_VALUE_1Divisor latch enable. Allows to access to DLL DLH and other registers (refer to the registers mapping)" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit. 0 | BREAK_EN_VALUE_0Normal operating condition. 1 | BREAK_EN_VALUE_1Forces the transmitter output to go low to alert the communication terminal" "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1,Not Defined 0 | PARITY_TYPE1_VALUE_0Odd parity is generated (if LCR[3] = 1) 1 | PARITY_TYPE1_VALUE_1Even parity is generated (if LCR[3] = 1)" "0,1" newline bitfld.long 0x0 3. "PARITY_EN,Not Defined 0 | PARITY_EN_VALUE_0No parity 1 | PARITY_EN_VALUE_1A parity bit is generated during transmission and the receiver checks for received parity." "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits: 0 | NB_STOP_VALUE_01 stop bits (word length = 5 6 7 8) 1 | NB_STOP_VALUE_11.5 stop bits (word length = 5) in USART mode. 2 stop bits (word length = 6 7 8)" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received. 0x0 | CHAR_LENGTH_VALUE_05 bits 0x1 | CHAR_LENGTH_VALUE_16 bits 0x2 | CHAR_LENGTH_VALUE_27 bits 0x3 | CHAR_LENGTH_VALUE_38 bits" "0,1,2,3" group.byte 0x10++0x0 line.byte 0x0 "UART0_XON1_ADDR1" hexmask.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." group.long 0x10++0x3 line.long 0x0 "UART0_MCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 7. "RESERVED,Not Defined" "0,1" newline bitfld.long 0x0 6. "TCR_TLR,Not Defined 0 | TCR_TLR_VALUE_0No action 1 | TCR_TLR_VALUE_1Enables access to the TCR and TLR registers." "0,1" newline bitfld.long 0x0 5. "XON_EN,Not Defined 0 | XON_EN_VALUE_0Disable 'XON any' function 1 | XON_EN_VALUE_1Enable 'XON any' function" "0,1" newline bitfld.long 0x0 4. "LOOPBACK_EN,Not Defined 0 | LOOPBACK_EN_VALUE_0Normal operating mode 1 | LOOPBACK_EN_VALUE_1Enable local loopback mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4]. The transmit output is looped back to the.." "0,1" newline bitfld.long 0x0 3. "CD_STS_CH,Not Defined 0 | CD_STS_CH_VALUE_0In loopback forces DCD* input high and IRQ outputs to inactive state. 1 | CD_STS_CH_VALUE_1In loopback forces DCD* input low and IRQ outputs to inactive state." "0,1" newline bitfld.long 0x0 2. "RI_STS_CH,Not Defined 0 | RI_STS_CH_VALUE_0In loopback forces RI* input high. 1 | RI_STS_CH_VALUE_1In loopback forces RI* input low." "0,1" newline bitfld.long 0x0 1. "RTS,In loop back controls MSR[4].If auto-RTS is enabled the RTS* output is controlled by hardware flow control. 0 | RTS_VALUE_0Force RTS* output to inactive (high). 1 | RTS_VALUE_1Force RTS* output to active (low)." "0,1" newline bitfld.long 0x0 0. "DTR,Not Defined 0 | DTR_VALUE_0Force DTR* output to inactive (high). 1 | DTR_VALUE_1Force DTR* output to active (low)." "0,1" group.byte 0x14++0x0 line.byte 0x0 "UART0_XON2_ADDR2" hexmask.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.byte 0x14++0x0 line.byte 0x0 "UART0_LSR_CIR" bitfld.byte 0x0 7. "THR_EMPTY,Not Defined Read0 | THR_EMPTY_VALUE_0Transmit holding register (TX FIFO) is not empty Read1 | THR_EMPTY_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.byte 0x0 6. "RESERVED,Not Defined" "0,1" newline bitfld.byte 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register Read0 | RX_STOP_VALUE_0Reception is on going or waiting for a new frame Read1 |.." "0,1" newline bitfld.byte 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" rgroup.byte 0x14++0x0 line.byte 0x0 "UART0_LSR_IRDA" bitfld.byte 0x0 7. "THR_EMPTY,Not Defined Read0 | THR_EMPTY_VALUE_0Transmit holding register (TX FIFO) is not empty Read1 | THR_EMPTY_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.byte 0x0 6. "STS_FIFO_FULL,Not Defined Read0 | STS_FIFO_FULL_VALUE_0Status FIFO not full Read1 | STS_FIFO_FULL_VALUE_1Status FIFO full" "0,1" newline bitfld.byte 0x0 5. "RX_LAST_BYTE,Not Defined Read0 | RX_LAST_BYTE_VALUE_0The RX FIFO (RHR) does not contain the last byte of the frame to be read Read1 | RX_LAST_BYTE_VALUE_1The RX FIFO (RHR) contains the last byte of the frame to be read.This bit is only.." "0,1" newline bitfld.byte 0x0 4. "FRAME_TOO_LONG,Not Defined Read0 | FRAME_TOO_LONG_VALUE_0No frame-too-long error in frame Read1 | FRAME_TOO_LONG_VALUE_1Frame-too-long error in the frame at the top of the STATUS FIFO [next character to be read]. This bit is set to 1.." "0,1" newline bitfld.byte 0x0 3. "ABORT,Not Defined Read0 | ABORT_VALUE_0No abort pattern error in frame Read1 | ABORT_VALUE_1Abort pattern is received. SIR MIR: Abort pattern. FIR: Illegal symbol" "0,1" newline bitfld.byte 0x0 2. "CRC,Not Defined Read0 | CRC_VALUE_0No CRC error in frame Read1 | CRC_VALUE_1CRC error in the frame at the top of the STATUS FIFO (next character to be read)" "0,1" newline bitfld.byte 0x0 1. "STS_FIFO_E,Not Defined Read0 | STS_FIFO_E_VALUE_0Status FIFO not empty Read1 | STS_FIFO_E_VALUE_1Status FIFO empty" "0,1" newline bitfld.byte 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART0_LSR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "RX_FIFO_STS,Not Defined Read0 | RX_FIFO_STS_VALUE_0Normal operation Read1 | RX_FIFO_STS_VALUE_1At least one parity error framing error or break indication in the RX FIFO. Bit 7 is cleared when no more errors are present in the RX FIFO." "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Not Defined Read0 | TX_SR_E_VALUE_0Transmitter hold (TX FIFO) and shift registers are not empty. Read1 | TX_SR_E_VALUE_1Transmitter hold (TX FIFO) and shift registers are empty" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E,Not Defined Read0 | TX_FIFO_E_VALUE_0Transmit hold register (TX FIFO) is not empty Read1 | TX_FIFO_E_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed." "0,1" newline bitfld.long 0x0 4. "RX_BI,Not Defined Read0 | RX_BI_VALUE_0No break condition Read1 | RX_BI_VALUE_1A break was detected while the data being read from the RX FIFO was being received. (i.e. RX input was low for one character + 1 bit time frame)." "0,1" newline bitfld.long 0x0 3. "RX_FE,Not Defined Read0 | RX_FE_VALUE_0No framing error in data being read from RX FIFO. Read1 | RX_FE_VALUE_1Framing error occurred in data being read from RX FIFO.(received data did not have a valid stop bit)" "0,1" newline bitfld.long 0x0 2. "RX_PE,Not Defined Read0 | RX_PE_VALUE_0No parity error in data being read from RX FIFO. Read1 | RX_PE_VALUE_1Parity error in data being read from RX FIFO" "0,1" newline bitfld.long 0x0 1. "RX_OE,Not Defined Read0 | RX_OE_VALUE_0No overrun error Read1 | RX_OE_VALUE_1Overrun error has occurred. Set when the character held in the receive shift register is not transferred to the RX FIFO. This case can occurs only when receive.." "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" group.byte 0x18++0x0 line.byte 0x0 "UART0_TCR" hexmask.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.byte 0x18++0x0 line.byte 0x0 "UART0_XOFF1" hexmask.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." rgroup.long 0x18++0x3 line.long 0x0 "UART0_MSR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS,Not Defined Read1 | DSR_STS_VALUE_1Indicates that DSR* input (or MCR[0] in loop back) has changed state. Cleared on a read" "0,1" newline bitfld.long 0x0 0. "CTS_STS,Not Defined Read1 | CTS_STS_VALUE_1Indicates that CTS* input (or MCR[1] in loop back) has changed state. Cleared on a read." "0,1" group.byte 0x1C++0x0 line.byte 0x0 "UART0_TLR" hexmask.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.byte 0x1C++0x0 line.byte 0x0 "UART0_XOFF2" hexmask.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." group.long 0x1C++0xF line.long 0x0 "UART0_SPR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "SPR_WORD,Scratchpad register" line.long 0x4 "UART0_MDR1" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only. 0 | FRAME_END_MODE_VALUE_0Frame-length method 1 | FRAME_END_MODE_VALUE_1Set EOT bit method" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only. 0 | SIP_MODE_VALUE_0Manual SIP mode: SIP is generated with the control of ACREG[3] 1 | SIP_MODE_VALUE_1Automatic SIP mode: SIP is generated after each transmission." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission 0 | SCT_VALUE_0Starts the Infrared transmission as soon as a value is written to THR 1 | SCT_VALUE_1Starts the Infrared transmission with the control of ACREG[2]. Note: before starting any.." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver. 0 | SET_TXIR_VALUE_0No action if MDR2[7]=0. TXIR pin output is forced low if MDR2[7]=1 1 | SET_TXIR_VALUE_1TXIR pin output is forced high (not dependant of MDR2[7] value)." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP,Not Defined 0 | IR_SLEEP_VALUE_0IrDA/CIR sleep mode disabled 1 | IR_SLEEP_VALUE_1IrDA/CIR sleep mode enabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,Not Defined 0x0 | MODE_SELECT_VALUE_0UART 16x mode 0x1 | MODE_SELECT_VALUE_1SIR mode 0x2 | MODE_SELECT_VALUE_2UART 16x auto-baud 0x3 | MODE_SELECT_VALUE_3UART 13x mode 0x4 | MODE_SELECT_VALUE_4MIR.." "0,1,2,3,4,5,6,7" line.long 0x8 "UART0_MDR2" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR] 0 | SET_TXIR_ALT_VALUE_0Normal mode 1 | SET_TXIR_ALT_VALUE_1Alternate mode for SET_TXIR" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes. 0 | IRRXINVERT_VALUE_0inversion is performed 1.." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit: 0x0 | CIR_PULSE_MODE_VALUE_0Pulse width of 3 from 12 cycles 0x1 | CIR_PULSE_MODE_VALUE_1Pulse width of 4 from 12 cycles.." "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode. 0 | UART_PULSE_VALUE_0normal UART mode 1 | UART_PULSE_VALUE_1UART mode with a pulse shaping" "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode.Frame Status FIFO Threshold select: 0x0 | STS_FIFO_TRIG_VALUE_01 entry 0x1 | STS_FIFO_TRIG_VALUE_14 entries 0x2 | STS_FIFO_TRIG_VALUE_27 entries 0x3 | STS_FIFO_TRIG_VALUE_38 entries" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is : Read0 | IRTX_UNDERRUN_VALUE_0the last bit of the frame has been transmitted successfully without error. Read1 |.." "0,1" line.long 0xC "UART0_TXFLL" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0xC 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x28++0x3 line.long 0x0 "UART0_SFLSR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 5.--7. "RESERVED5,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Not Defined Read1 | OE_ERROR_VALUE_1Overrun error in RX FIFO when frame at top of RX FIFO was received." "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Not Defined Read1 | FRAME_TOO_LONG_ERROR_VALUE_1Frame-length too long error in frame at top of RX FIFO." "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Not Defined Read1 | ABORT_DETECT_VALUE_1Abort pattern detected in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR,Not Defined Read1 | CRC_ERROR_VALUE_1CRC error in frame at top of RX FIFO. top of RX FIFO = Next frame to be read from RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED0,Not Defined" "0,1" group.long 0x2C++0x3 line.long 0x0 "UART0_TXFLH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 5.--7. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART0_RESUME" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x30++0x3 line.long 0x0 "UART0_RXFLL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART0_SFREGL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART0_RXFLH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART0_SFREGH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.byte 0x38++0x0 line.byte 0x0 "UART0_UASR" bitfld.byte 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.byte 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." group.long 0x38++0x13 line.long 0x0 "UART0_BLR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select. 0 | XBOF_TYPE_VALUE_00xFF 1 | XBOF_TYPE_VALUE_10xC0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED,Not Defined" line.long 0x4 "UART0_ACREG" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 7. "PULSE_TYPE,SIR pulse width select: 0 | PULSE_TYPE_VALUE_03/16 of baud-rate pulse width 1 | PULSE_TYPE_VALUE_11.6us" "0,1" newline bitfld.long 0x4 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. 0 | SD_MOD_VALUE_0SD pin is set to high 1 | SD_MOD_VALUE_1SD pin is set to low" "0,1" newline bitfld.long 0x4 5. "DIS_IR_RX,Not Defined 0 | DIS_IR_RX_VALUE_0Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation). 1 | DIS_IR_RX_VALUE_1Disables RX input (permanent state - independent of transmit)." "0,1" newline bitfld.long 0x4 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line. 0 | DIS_TX_UNDERRUN_VALUE_0Long stop bits.." "0,1" newline bitfld.long 0x4 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP]If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission. 0 |.." "0,1" newline bitfld.long 0x4 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x4 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x4 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x8 "UART0_SCR" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x8 7. "RX_TRIG_GRANU1,Not Defined 0 | RX_TRIG_GRANU1_VALUE_0DISABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL. 1 | RX_TRIG_GRANU1_VALUE_1ENABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL." "0,1" newline bitfld.long 0x8 6. "TX_TRIG_GRANU1,Not Defined 0 | TX_TRIG_GRANU1_VALUE_0DISABLES THE GRANULARITY OF 1 FOR TRIGGER TX LEVEL. 1 | TX_TRIG_GRANU1_VALUE_1Enables the granularity of 1 for trigger TX level." "0,1" newline bitfld.long 0x8 5. "DSR_IT,Not Defined 0 | DSR_IT_VALUE_0DISABLES DSR* INTERRUPT. 1 | DSR_IT_VALUE_1ENABLES DSR* INTERRUPT." "0,1" newline bitfld.long 0x8 4. "RX_CTS_DSR_WAKE_UP_ENABLE,Not Defined 0 | RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_0DISABLES THE WAKE UP INTERRUPT AND CLEARS SSR[1]. 1 | RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_1Waits for a falling edge of pins RX CTS* or DSR* to generate an interrupt" "0,1" newline bitfld.long 0x8 3. "TX_EMPTY_CTL_IT,Not Defined 0 | TX_EMPTY_CTL_IT_VALUE_0Normal mode for THR interrupt (See UART mode interrupts table). 1 | TX_EMPTY_CTL_IT_VALUE_1THE THR INTERRUPT IS GENERATED WHEN TX FIFO AND TX SHIFT REGISTER ARE EMPTY." "0,1" newline bitfld.long 0x8 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1 0x0 | DMA_MODE_2_VALUE_0DMA mode 0 (no DMA) 0x1 | DMA_MODE_2_VALUE_1DMA mode 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX) 0x2 | DMA_MODE_2_VALUE_2DMA mode 2.." "0,1,2,3" newline bitfld.long 0x8 0. "DMA_MODE_CTL,Not Defined 0 | DMA_MODE_CTL_VALUE_0The DMA_MODE is set with FCR[3] 1 | DMA_MODE_CTL_VALUE_1The DMA_MODE is set with SCR[2:1]" "0,1" line.long 0xC "UART0_SSR" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0xC 3.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0xC 2. "DMA_COUNTER_RST,Not Defined 0 | DMA_COUNTER_RST_VALUE_0The DMA counter will not be reset if the corresponding FIFO is reset (via FCR[1] or FCR[2]) 1 | DMA_COUNTER_RST_VALUE_1The DMA counter will be reset if corresponding FIFO is reset.." "0,1" newline rbitfld.long 0xC 1. "RX_CTS_DSR_WAKE_UP_STS,Not Defined Read0 | RX_CTS_DSR_WAKE_UP_STS_VALUE_0No falling edge event on RX CTS* and DSR* Read1 | RX_CTS_DSR_WAKE_UP_STS_VALUE_1A falling edge occurred on RX CTS* or DSR*" "0,1" newline rbitfld.long 0xC 0. "TX_FIFO_FULL,Not Defined Read0 | TX_FIFO_FULL_VALUE_0TX FIFO is not full Read1 | TX_FIFO_FULL_VALUE_1TX FIFO is full." "0,1" line.long 0x10 "UART0_EBLR" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x10 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification.IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]].0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "UART0_MVR" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED,Not Defined" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "UART0_SYSC" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 5.--7. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROLREF: OCP DESIGN GUIDELINES VERSION 1.1 0x0 | IDLEMODE_VALUE_0Force idle. An idle request is acknowledged unconditionally 0x1 | IDLEMODE_VALUE_1No-idle. An idle request is never acknowledged." "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL 0 | ENAWAKEUP_VALUE_0Wake up is disabled 1 | ENAWAKEUP_VALUE_1Wake up capability is enabled" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0. Write0 | SOFTRESET_VALUE_0Normal mode Write1 | SOFTRESET_VALUE_1The module is reset" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy 0 | AUTOIDLE_VALUE_0Clock is running 1 | AUTOIDLE_VALUE_1Automatic OCP clock gating strategy is applied based on the OCP interface activity" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART0_SYSS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring Read0 | RESETDONE_VALUE_0Internal Module Reset is ongoing Read1 | RESETDONE_VALUE_1Reset completed" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART0_WER" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,Not Defined 0 | EVENT_7_TX_WAKEUP_EN_VALUE_0Event is not allowed to wake up the system 1 | EVENT_7_TX_WAKEUP_EN_VALUE_1EVENT CAN WAKE UP THE SYSTEM: Event can be: THR_IT or TX_DMA request and/or TX_SATUS_IT" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,Not Defined 0 | EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_VALUE_0Event is not allowed to wake up the system 1 | EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,Not Defined 0 | EVENT_5_RHR_INTERRUPT_VALUE_0Event is not allowed to wake up the system 1 | EVENT_5_RHR_INTERRUPT_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,Not Defined 0 | EVENT_4_RX_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_4_RX_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,Not Defined 0 | EVENT_3_DCD_CD_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_3_DCD_CD_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,Not Defined 0 | EVENT_2_RI_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_2_RI_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,Not Defined 0 | EVENT_1_DSR_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_1_DSR_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,Not Defined 0 | EVENT_0_CTS_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_0_CTS_ACTIVITY_VALUE_1Event can wake up the system" "0,1" line.long 0x4 "UART0_CFPS" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below.Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1 40 100.." rgroup.long 0x64++0x7 line.long 0x0 "UART0_RXFIFO_LVL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Not Defined" line.long 0x4 "UART0_TXFIFO_LVL" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24,Not Defined" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Not Defined" group.long 0x6C++0xB line.long 0x0 "UART0_IER2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 2. "RHR_IT_DIS,Not Defined 0 | RHR_IT_DIS_VALUE_0Enables the RHR interrupt. 1 | RHR_IT_DIS_VALUE_1Disables the RHR interrupt." "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "UART0_ISR2" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending 0 | TXFIFO_EMPTY_STS_VALUE_0TXFIFO_EMPTY interrupt not pending. 1 | TXFIFO_EMPTY_STS_VALUE_1TXFIFO_EMPTY interrupt pending." "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending 0 | RXFIFO_EMPTY_STS_VALUE_0RXFIFO_EMPTY interrupt not pending. 1 | RXFIFO_EMPTY_STS_VALUE_1RXFIFO_EMPTY interrupt pending." "0,1" line.long 0x8 "UART0_FREQ_SEL" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "UART0_ABAUD_1ST_CHAR" hexmask.long 0x0 0.--31. 1. "RESERVED,Not Defined" line.long 0x4 "UART0_BAUD_2ND_CHAR" hexmask.long 0x4 0.--31. 1. "RESERVED,Not Defined" group.long 0x80++0x27 line.long 0x0 "UART0_MDR3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2,Not Defined" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation 0 | DISABLE_CIR_RX_DEMOD_VALUE_0Enables CIR RX demodulation 1 | DISABLE_CIR_RX_DEMOD_VALUE_1Disables CIR RX demodulation" "0,1" line.long 0x4 "UART0_TX_DMA_THRESHOLD" hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "UART0_MDR4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,Not Defined" newline rbitfld.long 0x8 7. "RESERVED,Not Defined" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes] 0x0 | DISABLEDdisabled (no override) 0x1 | RESERVEDreserved 0x2 | SYNCH_EXTSynchronous mode with external clock 0x3 | SYNCH_GENSynchronous mode with generated clock.." "0,1,2,3,4,5,6,7" line.long 0xC "UART0_EFR2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1,Not Defined" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured 0 | _0timeout after at least one character has been received 1 | _1periodic timeout even when no character has been received" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full 0 | DEFAULTdata in RHR is not overwritten (standard) 1 | ATMELdata in RHR is overwritten when buffer full (and FIFO disabled)" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness 0 | LOW_ENDIANLittle Endian (LSB First) 1 | BIG_ENDIANBig Endian (MSB First)" "0,1" line.long 0x10 "UART0_ECR" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1,Not Defined" newline rbitfld.long 0x10 6.--7. "RESERVED,Not Defined" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter 0 | DISABLEDTransmitter is shut down 1 | ENABLEDTransmitter is working" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver 0 | DISABLEDReceiver is shut down 1 | ENABLEDReceiver is operating" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "UART0_TIMEGUARD" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART0_TIMEOUTL" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "UART0_TIMEOUTH" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "UART0_SCCR" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,Not Defined" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" line.long 0x24 "UART0_ETHR" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED,Not Defined" newline hexmask.long.word 0x24 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" rgroup.long 0xA4++0x3 line.long 0x0 "UART0_ERHR" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Not Defined" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.byte 0xA8++0x0 line.byte 0x0 "UART0_MAR" hexmask.byte 0x0 0.--7. 1. "ADDRESS,Multidrop match address value" group.byte 0xAC++0x0 line.byte 0x0 "UART0_MMR" hexmask.byte 0x0 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" group.byte 0xB0++0x0 line.byte 0x0 "UART0_MBR" hexmask.byte 0x0 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART1" base ad:0x52301000 group.byte 0x0++0x0 line.byte 0x0 "UART1_DLL" hexmask.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART1_RHR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x3 line.long 0x0 "UART1_THR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" group.byte 0x4++0x0 line.byte 0x0 "UART1_DLH" hexmask.byte 0x0 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.byte 0x4++0x0 line.byte 0x0 "UART1_IER_CIR" bitfld.byte 0x0 6.--7. "NOT_USED2,Not Defined" "0,1,2,3" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined 0 | TX_STATUS_IT_VALUE_0Disables the TX status interrupt. 1 | TX_STATUS_IT_VALUE_1Enables the TX status interrupt." "0,1" newline bitfld.byte 0x0 4. "NOT_USED1,Not Defined" "0,1" newline bitfld.byte 0x0 3. "RX_OVERRUN_IT,Not Defined 0 | RX_OVERRUN_IT_VALUE_0Disables the RX overrun interrupt. 1 | RX_OVERRUN_IT_VALUE_1Enables the RX overrun interrupt." "0,1" newline bitfld.byte 0x0 2. "RX_STOP_IT,Not Defined 0 | RX_STOP_IT_VALUE_0Disables the receive stop interrupt. 1 | RX_STOP_IT_VALUE_1Enables the receive stop interrupt." "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt. 1 | THR_IT_VALUE_1Enables the THR interrupt." "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt." "0,1" group.byte 0x4++0x0 line.byte 0x0 "UART1_IER_IRDA" bitfld.byte 0x0 7. "EOF_IT,Not Defined 0 | EOF_IT_VALUE_0Disables the received EOF interrupt. 1 | EOF_IT_VALUE_1Enables the received EOF interrupt." "0,1" newline bitfld.byte 0x0 6. "LINE_STS_IT,Not Defined 0 | LINE_STS_IT_VALUE_0Disables the receiver line status interrupt. 1 | LINE_STS_IT_VALUE_1Enables the receiver line status interrupt." "0,1" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined 0 | TX_STATUS_IT_VALUE_0Disables the TX status interrupt. 1 | TX_STATUS_IT_VALUE_1Enables the TX status interrupt." "0,1" newline bitfld.byte 0x0 4. "STS_FIFO_TRIG_IT,Not Defined 0 | STS_FIFO_TRIG_IT_VALUE_0Disables the status FIFO trigger level interrupt. 1 | STS_FIFO_TRIG_IT_VALUE_1Enables the status FIFO trigger level interrupt." "0,1" newline bitfld.byte 0x0 3. "RX_OVERRUN_IT,Not Defined 0 | RX_OVERRUN_IT_VALUE_0Disables the RX overrun interrupt. 1 | RX_OVERRUN_IT_VALUE_1Enables the RX overrun interrupt." "0,1" newline bitfld.byte 0x0 2. "LAST_RX_BYTE_IT,Not Defined 0 | LAST_RX_BYTE_IT_VALUE_0Disables the last byte of frame in RX FIFO interrupt. 1 | LAST_RX_BYTE_IT_VALUE_1Enables the last byte of frame in RX FIFO interrupt." "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt. 1 | THR_IT_VALUE_1Enables the THR interrupt." "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt." "0,1" group.long 0x4++0x3 line.long 0x0 "UART1_IER_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "CTS_IT,Not Defined 0 | CTS_IT_VALUE_0Disables the CTS* interrupt 1 | CTS_IT_VALUE_1Enables the CTS* interrupt" "0,1" newline bitfld.long 0x0 6. "RTS_IT,Not Defined 0 | RTS_IT_VALUE_0Disables the RTS* interrupt 1 | RTS_IT_VALUE_1Enables the RTS* interrupt" "0,1" newline bitfld.long 0x0 5. "XOFF_IT,Not Defined 0 | XOFF_IT_VALUE_0Disables the XOFF interrupt 1 | XOFF_IT_VALUE_1Enables the XOFF interrupt" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE,Not Defined 0 | SLEEP_MODE_VALUE_0Disables sleep mode 1 | SLEEP_MODE_VALUE_1Enables sleep mode (stop baud rate clock when the module is inactive)" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT,Not Defined 0 | MODEM_STS_IT_VALUE_0Disables the modem status register interrupt 1 | MODEM_STS_IT_VALUE_1Enables the modem status register interrupt" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT,Not Defined 0 | LINE_STS_IT_U_VALUE_0Disables the receiver line status interrupt 1 | LINE_STS_IT_U_VALUE_1Enables the receiver line status interrupt" "0,1" newline bitfld.long 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt 1 | THR_IT_VALUE_1Enables the THR interrupt" "0,1" newline bitfld.long 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt and time out interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt and time out interrupt." "0,1" group.byte 0x8++0x0 line.byte 0x0 "UART1_EFR" bitfld.byte 0x0 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.byte 0x0 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.byte 0x0 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.byte 0x0 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.byte 0x0 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" group.long 0x8++0x3 line.long 0x0 "UART1_FCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO:If SCR[7] = 0 and TLR[7:4] = 0000:00: 8 characters01: 16 characters10: 56 characters11: 60 charactersIf SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered.If SCR[7]=1 RX_FIFO_TRIG is 2.." "0: 8 characters01: 16 characters10: 56..,?,?,?" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO:If SCR[6] = 0 and TLR[3:0] = 0000:00: 8 spaces01: 16 spaces10: 32 spaces11: 56 spacesIf SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered.If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of the.." "0: 8 spaces01: 16 spaces10: 32 spaces11: 56..,?,?,?" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0. Write0 | DMA_MODE_VALUE_0DMA_MODE 0 (No DMA) Write1 | DMA_MODE_VALUE_1DMA_MODE 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR,Not Defined Write0 | TX_FIFO_CLEAR_VALUE_0No change Write1 | TX_FIFO_CLEAR_VALUE_1Clears the transmit FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR,Not Defined Write0 | RX_FIFO_CLEAR_VALUE_0No change Write1 | RX_FIFO_CLEAR_VALUE_1Clears the receive FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 0. "FIFO_EN,Not Defined Write0 | FIFO_EN_VALUE_0Disables the transmit and receive FIFOs. The transmit and receive holding registers are one byte FIFOs. Write1 | FIFO_EN_VALUE_1: Enables the transmit and receive FIFOs.The transmit and receive.." "0,1" rgroup.byte 0x8++0x0 line.byte 0x0 "UART1_IIR_CIR" bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined Read0 | TX_STATUS_IT_VALUE_0TX status interrupt inactive Read1 | TX_STATUS_IT_VALUE_1TX status interrupt active" "0,1" newline bitfld.byte 0x0 3. "RX_OE_IT,Not Defined Read0 | RX_OE_IT_VALUE_0RX overrun interrupt inactive Read1 | RX_OE_IT_VALUE_1RX overrun interrupt active" "0,1" newline bitfld.byte 0x0 2. "RX_STOP_IT,Not Defined Read0 | RX_STOP_IT_VALUE_0Receive stop interrupt inactive Read1 | RX_STOP_IT_VALUE_1Receive stop interrupt active" "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined Read0 | THR_IT_VALUE_0THR interrupt inactive Read1 | THR_IT_VALUE_1THR interrupt active" "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined Read0 | RHR_IT_VALUE_0RHR interrupt inactive Read1 | RHR_IT_VALUE_1RHR interrupt active" "0,1" rgroup.byte 0x8++0x0 line.byte 0x0 "UART1_IIR_IRDA" bitfld.byte 0x0 7. "EOF_IT,Not Defined Read0 | EOF_IT_VALUE_0Received EOF interrupt inactive Read1 | EOF_IT_VALUE_1Received EOF interrupt active" "0,1" newline bitfld.byte 0x0 6. "LINE_STS_IT,Not Defined Read0 | LINE_STS_IT_VALUE_0Receiver line status interrupt inactive Read1 | LINE_STS_IT_VALUE_1Receiver line status interrupt active" "0,1" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined Read0 | TX_STATUS_IT_VALUE_0TX status interrupt inactive Read1 | TX_STATUS_IT_VALUE_1TX status interrupt active" "0,1" newline bitfld.byte 0x0 4. "STS_FIFO_IT,Not Defined Read0 | STS_FIFO_IT_VALUE_0Status FIFO trigger level interrupt inactive Read1 | STS_FIFO_IT_VALUE_1Status FIFO trigger level interrupt active" "0,1" newline bitfld.byte 0x0 3. "RX_OE_IT,Not Defined Read0 | RX_OE_IT_VALUE_0RX overrun interrupt inactive Read1 | RX_OE_IT_VALUE_1RX overrun interrupt active" "0,1" newline bitfld.byte 0x0 2. "RX_FIFO_LAST_BYTE_IT,Not Defined Read0 | RX_FIFO_LAST_BYTE_IT_VALUE_0Last byte of frame in RX FIFO interrupt inactive Read1 | RX_FIFO_LAST_BYTE_IT_VALUE_1Last byte of frame in RX FIFO interrupt active" "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined Read0 | THR_IT_VALUE_0THR interrupt inactive Read1 | THR_IT_VALUE_1THR interrupt active" "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined Read0 | RHR_IT_VALUE_0RHR interrupt inactive Read1 | RHR_IT_VALUE_1RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART1_IIR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Not Defined Read0x00 | IT_TYPE_VALUE_0Modem Interrupt. Priority=4 Read0x01 | IT_TYPE_VALUE_1THR interrupt. Priority=3 Read0x02 | IT_TYPE_VALUE_2RHR interrupt. Priority=2 Read0x03 | IT_TYPE_VALUE_3Receiver line.." newline bitfld.long 0x0 0. "IT_PENDING,Not Defined Read0 | IT_PENDING_VALUE_0An interrupt is pending Read1 | IT_PENDING_VALUE_1No interrupt is pending" "0,1" group.long 0xC++0x3 line.long 0x0 "UART1_LCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "DIV_EN,Not Defined 0 | DIV_EN_VALUE_0Normal operating condition 1 | DIV_EN_VALUE_1Divisor latch enable. Allows to access to DLL DLH and other registers (refer to the registers mapping)" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit. 0 | BREAK_EN_VALUE_0Normal operating condition. 1 | BREAK_EN_VALUE_1Forces the transmitter output to go low to alert the communication terminal" "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1,Not Defined 0 | PARITY_TYPE1_VALUE_0Odd parity is generated (if LCR[3] = 1) 1 | PARITY_TYPE1_VALUE_1Even parity is generated (if LCR[3] = 1)" "0,1" newline bitfld.long 0x0 3. "PARITY_EN,Not Defined 0 | PARITY_EN_VALUE_0No parity 1 | PARITY_EN_VALUE_1A parity bit is generated during transmission and the receiver checks for received parity." "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits: 0 | NB_STOP_VALUE_01 stop bits (word length = 5 6 7 8) 1 | NB_STOP_VALUE_11.5 stop bits (word length = 5) in USART mode. 2 stop bits (word length = 6 7 8)" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received. 0x0 | CHAR_LENGTH_VALUE_05 bits 0x1 | CHAR_LENGTH_VALUE_16 bits 0x2 | CHAR_LENGTH_VALUE_27 bits 0x3 | CHAR_LENGTH_VALUE_38 bits" "0,1,2,3" group.byte 0x10++0x0 line.byte 0x0 "UART1_XON1_ADDR1" hexmask.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." group.long 0x10++0x3 line.long 0x0 "UART1_MCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 7. "RESERVED,Not Defined" "0,1" newline bitfld.long 0x0 6. "TCR_TLR,Not Defined 0 | TCR_TLR_VALUE_0No action 1 | TCR_TLR_VALUE_1Enables access to the TCR and TLR registers." "0,1" newline bitfld.long 0x0 5. "XON_EN,Not Defined 0 | XON_EN_VALUE_0Disable 'XON any' function 1 | XON_EN_VALUE_1Enable 'XON any' function" "0,1" newline bitfld.long 0x0 4. "LOOPBACK_EN,Not Defined 0 | LOOPBACK_EN_VALUE_0Normal operating mode 1 | LOOPBACK_EN_VALUE_1Enable local loopback mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4]. The transmit output is looped back to the.." "0,1" newline bitfld.long 0x0 3. "CD_STS_CH,Not Defined 0 | CD_STS_CH_VALUE_0In loopback forces DCD* input high and IRQ outputs to inactive state. 1 | CD_STS_CH_VALUE_1In loopback forces DCD* input low and IRQ outputs to inactive state." "0,1" newline bitfld.long 0x0 2. "RI_STS_CH,Not Defined 0 | RI_STS_CH_VALUE_0In loopback forces RI* input high. 1 | RI_STS_CH_VALUE_1In loopback forces RI* input low." "0,1" newline bitfld.long 0x0 1. "RTS,In loop back controls MSR[4].If auto-RTS is enabled the RTS* output is controlled by hardware flow control. 0 | RTS_VALUE_0Force RTS* output to inactive (high). 1 | RTS_VALUE_1Force RTS* output to active (low)." "0,1" newline bitfld.long 0x0 0. "DTR,Not Defined 0 | DTR_VALUE_0Force DTR* output to inactive (high). 1 | DTR_VALUE_1Force DTR* output to active (low)." "0,1" group.byte 0x14++0x0 line.byte 0x0 "UART1_XON2_ADDR2" hexmask.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.byte 0x14++0x0 line.byte 0x0 "UART1_LSR_CIR" bitfld.byte 0x0 7. "THR_EMPTY,Not Defined Read0 | THR_EMPTY_VALUE_0Transmit holding register (TX FIFO) is not empty Read1 | THR_EMPTY_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.byte 0x0 6. "RESERVED,Not Defined" "0,1" newline bitfld.byte 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register Read0 | RX_STOP_VALUE_0Reception is on going or waiting for a new frame Read1 |.." "0,1" newline bitfld.byte 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" rgroup.byte 0x14++0x0 line.byte 0x0 "UART1_LSR_IRDA" bitfld.byte 0x0 7. "THR_EMPTY,Not Defined Read0 | THR_EMPTY_VALUE_0Transmit holding register (TX FIFO) is not empty Read1 | THR_EMPTY_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.byte 0x0 6. "STS_FIFO_FULL,Not Defined Read0 | STS_FIFO_FULL_VALUE_0Status FIFO not full Read1 | STS_FIFO_FULL_VALUE_1Status FIFO full" "0,1" newline bitfld.byte 0x0 5. "RX_LAST_BYTE,Not Defined Read0 | RX_LAST_BYTE_VALUE_0The RX FIFO (RHR) does not contain the last byte of the frame to be read Read1 | RX_LAST_BYTE_VALUE_1The RX FIFO (RHR) contains the last byte of the frame to be read.This bit is only.." "0,1" newline bitfld.byte 0x0 4. "FRAME_TOO_LONG,Not Defined Read0 | FRAME_TOO_LONG_VALUE_0No frame-too-long error in frame Read1 | FRAME_TOO_LONG_VALUE_1Frame-too-long error in the frame at the top of the STATUS FIFO [next character to be read]. This bit is set to 1.." "0,1" newline bitfld.byte 0x0 3. "ABORT,Not Defined Read0 | ABORT_VALUE_0No abort pattern error in frame Read1 | ABORT_VALUE_1Abort pattern is received. SIR MIR: Abort pattern. FIR: Illegal symbol" "0,1" newline bitfld.byte 0x0 2. "CRC,Not Defined Read0 | CRC_VALUE_0No CRC error in frame Read1 | CRC_VALUE_1CRC error in the frame at the top of the STATUS FIFO (next character to be read)" "0,1" newline bitfld.byte 0x0 1. "STS_FIFO_E,Not Defined Read0 | STS_FIFO_E_VALUE_0Status FIFO not empty Read1 | STS_FIFO_E_VALUE_1Status FIFO empty" "0,1" newline bitfld.byte 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART1_LSR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "RX_FIFO_STS,Not Defined Read0 | RX_FIFO_STS_VALUE_0Normal operation Read1 | RX_FIFO_STS_VALUE_1At least one parity error framing error or break indication in the RX FIFO. Bit 7 is cleared when no more errors are present in the RX FIFO." "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Not Defined Read0 | TX_SR_E_VALUE_0Transmitter hold (TX FIFO) and shift registers are not empty. Read1 | TX_SR_E_VALUE_1Transmitter hold (TX FIFO) and shift registers are empty" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E,Not Defined Read0 | TX_FIFO_E_VALUE_0Transmit hold register (TX FIFO) is not empty Read1 | TX_FIFO_E_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed." "0,1" newline bitfld.long 0x0 4. "RX_BI,Not Defined Read0 | RX_BI_VALUE_0No break condition Read1 | RX_BI_VALUE_1A break was detected while the data being read from the RX FIFO was being received. (i.e. RX input was low for one character + 1 bit time frame)." "0,1" newline bitfld.long 0x0 3. "RX_FE,Not Defined Read0 | RX_FE_VALUE_0No framing error in data being read from RX FIFO. Read1 | RX_FE_VALUE_1Framing error occurred in data being read from RX FIFO.(received data did not have a valid stop bit)" "0,1" newline bitfld.long 0x0 2. "RX_PE,Not Defined Read0 | RX_PE_VALUE_0No parity error in data being read from RX FIFO. Read1 | RX_PE_VALUE_1Parity error in data being read from RX FIFO" "0,1" newline bitfld.long 0x0 1. "RX_OE,Not Defined Read0 | RX_OE_VALUE_0No overrun error Read1 | RX_OE_VALUE_1Overrun error has occurred. Set when the character held in the receive shift register is not transferred to the RX FIFO. This case can occurs only when receive.." "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" group.byte 0x18++0x0 line.byte 0x0 "UART1_TCR" hexmask.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.byte 0x18++0x0 line.byte 0x0 "UART1_XOFF1" hexmask.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." rgroup.long 0x18++0x3 line.long 0x0 "UART1_MSR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS,Not Defined Read1 | DSR_STS_VALUE_1Indicates that DSR* input (or MCR[0] in loop back) has changed state. Cleared on a read" "0,1" newline bitfld.long 0x0 0. "CTS_STS,Not Defined Read1 | CTS_STS_VALUE_1Indicates that CTS* input (or MCR[1] in loop back) has changed state. Cleared on a read." "0,1" group.byte 0x1C++0x0 line.byte 0x0 "UART1_TLR" hexmask.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.byte 0x1C++0x0 line.byte 0x0 "UART1_XOFF2" hexmask.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." group.long 0x1C++0xF line.long 0x0 "UART1_SPR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "SPR_WORD,Scratchpad register" line.long 0x4 "UART1_MDR1" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only. 0 | FRAME_END_MODE_VALUE_0Frame-length method 1 | FRAME_END_MODE_VALUE_1Set EOT bit method" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only. 0 | SIP_MODE_VALUE_0Manual SIP mode: SIP is generated with the control of ACREG[3] 1 | SIP_MODE_VALUE_1Automatic SIP mode: SIP is generated after each transmission." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission 0 | SCT_VALUE_0Starts the Infrared transmission as soon as a value is written to THR 1 | SCT_VALUE_1Starts the Infrared transmission with the control of ACREG[2]. Note: before starting any.." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver. 0 | SET_TXIR_VALUE_0No action if MDR2[7]=0. TXIR pin output is forced low if MDR2[7]=1 1 | SET_TXIR_VALUE_1TXIR pin output is forced high (not dependant of MDR2[7] value)." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP,Not Defined 0 | IR_SLEEP_VALUE_0IrDA/CIR sleep mode disabled 1 | IR_SLEEP_VALUE_1IrDA/CIR sleep mode enabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,Not Defined 0x0 | MODE_SELECT_VALUE_0UART 16x mode 0x1 | MODE_SELECT_VALUE_1SIR mode 0x2 | MODE_SELECT_VALUE_2UART 16x auto-baud 0x3 | MODE_SELECT_VALUE_3UART 13x mode 0x4 | MODE_SELECT_VALUE_4MIR.." "0,1,2,3,4,5,6,7" line.long 0x8 "UART1_MDR2" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR] 0 | SET_TXIR_ALT_VALUE_0Normal mode 1 | SET_TXIR_ALT_VALUE_1Alternate mode for SET_TXIR" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes. 0 | IRRXINVERT_VALUE_0inversion is performed 1.." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit: 0x0 | CIR_PULSE_MODE_VALUE_0Pulse width of 3 from 12 cycles 0x1 | CIR_PULSE_MODE_VALUE_1Pulse width of 4 from 12 cycles.." "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode. 0 | UART_PULSE_VALUE_0normal UART mode 1 | UART_PULSE_VALUE_1UART mode with a pulse shaping" "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode.Frame Status FIFO Threshold select: 0x0 | STS_FIFO_TRIG_VALUE_01 entry 0x1 | STS_FIFO_TRIG_VALUE_14 entries 0x2 | STS_FIFO_TRIG_VALUE_27 entries 0x3 | STS_FIFO_TRIG_VALUE_38 entries" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is : Read0 | IRTX_UNDERRUN_VALUE_0the last bit of the frame has been transmitted successfully without error. Read1 |.." "0,1" line.long 0xC "UART1_TXFLL" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0xC 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x28++0x3 line.long 0x0 "UART1_SFLSR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 5.--7. "RESERVED5,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Not Defined Read1 | OE_ERROR_VALUE_1Overrun error in RX FIFO when frame at top of RX FIFO was received." "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Not Defined Read1 | FRAME_TOO_LONG_ERROR_VALUE_1Frame-length too long error in frame at top of RX FIFO." "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Not Defined Read1 | ABORT_DETECT_VALUE_1Abort pattern detected in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR,Not Defined Read1 | CRC_ERROR_VALUE_1CRC error in frame at top of RX FIFO. top of RX FIFO = Next frame to be read from RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED0,Not Defined" "0,1" group.long 0x2C++0x3 line.long 0x0 "UART1_TXFLH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 5.--7. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART1_RESUME" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x30++0x3 line.long 0x0 "UART1_RXFLL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART1_SFREGL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART1_RXFLH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART1_SFREGH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.byte 0x38++0x0 line.byte 0x0 "UART1_UASR" bitfld.byte 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.byte 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." group.long 0x38++0x13 line.long 0x0 "UART1_BLR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select. 0 | XBOF_TYPE_VALUE_00xFF 1 | XBOF_TYPE_VALUE_10xC0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED,Not Defined" line.long 0x4 "UART1_ACREG" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 7. "PULSE_TYPE,SIR pulse width select: 0 | PULSE_TYPE_VALUE_03/16 of baud-rate pulse width 1 | PULSE_TYPE_VALUE_11.6us" "0,1" newline bitfld.long 0x4 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. 0 | SD_MOD_VALUE_0SD pin is set to high 1 | SD_MOD_VALUE_1SD pin is set to low" "0,1" newline bitfld.long 0x4 5. "DIS_IR_RX,Not Defined 0 | DIS_IR_RX_VALUE_0Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation). 1 | DIS_IR_RX_VALUE_1Disables RX input (permanent state - independent of transmit)." "0,1" newline bitfld.long 0x4 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line. 0 | DIS_TX_UNDERRUN_VALUE_0Long stop bits.." "0,1" newline bitfld.long 0x4 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP]If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission. 0 |.." "0,1" newline bitfld.long 0x4 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x4 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x4 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x8 "UART1_SCR" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x8 7. "RX_TRIG_GRANU1,Not Defined 0 | RX_TRIG_GRANU1_VALUE_0DISABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL. 1 | RX_TRIG_GRANU1_VALUE_1ENABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL." "0,1" newline bitfld.long 0x8 6. "TX_TRIG_GRANU1,Not Defined 0 | TX_TRIG_GRANU1_VALUE_0DISABLES THE GRANULARITY OF 1 FOR TRIGGER TX LEVEL. 1 | TX_TRIG_GRANU1_VALUE_1Enables the granularity of 1 for trigger TX level." "0,1" newline bitfld.long 0x8 5. "DSR_IT,Not Defined 0 | DSR_IT_VALUE_0DISABLES DSR* INTERRUPT. 1 | DSR_IT_VALUE_1ENABLES DSR* INTERRUPT." "0,1" newline bitfld.long 0x8 4. "RX_CTS_DSR_WAKE_UP_ENABLE,Not Defined 0 | RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_0DISABLES THE WAKE UP INTERRUPT AND CLEARS SSR[1]. 1 | RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_1Waits for a falling edge of pins RX CTS* or DSR* to generate an interrupt" "0,1" newline bitfld.long 0x8 3. "TX_EMPTY_CTL_IT,Not Defined 0 | TX_EMPTY_CTL_IT_VALUE_0Normal mode for THR interrupt (See UART mode interrupts table). 1 | TX_EMPTY_CTL_IT_VALUE_1THE THR INTERRUPT IS GENERATED WHEN TX FIFO AND TX SHIFT REGISTER ARE EMPTY." "0,1" newline bitfld.long 0x8 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1 0x0 | DMA_MODE_2_VALUE_0DMA mode 0 (no DMA) 0x1 | DMA_MODE_2_VALUE_1DMA mode 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX) 0x2 | DMA_MODE_2_VALUE_2DMA mode 2.." "0,1,2,3" newline bitfld.long 0x8 0. "DMA_MODE_CTL,Not Defined 0 | DMA_MODE_CTL_VALUE_0The DMA_MODE is set with FCR[3] 1 | DMA_MODE_CTL_VALUE_1The DMA_MODE is set with SCR[2:1]" "0,1" line.long 0xC "UART1_SSR" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0xC 3.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0xC 2. "DMA_COUNTER_RST,Not Defined 0 | DMA_COUNTER_RST_VALUE_0The DMA counter will not be reset if the corresponding FIFO is reset (via FCR[1] or FCR[2]) 1 | DMA_COUNTER_RST_VALUE_1The DMA counter will be reset if corresponding FIFO is reset.." "0,1" newline rbitfld.long 0xC 1. "RX_CTS_DSR_WAKE_UP_STS,Not Defined Read0 | RX_CTS_DSR_WAKE_UP_STS_VALUE_0No falling edge event on RX CTS* and DSR* Read1 | RX_CTS_DSR_WAKE_UP_STS_VALUE_1A falling edge occurred on RX CTS* or DSR*" "0,1" newline rbitfld.long 0xC 0. "TX_FIFO_FULL,Not Defined Read0 | TX_FIFO_FULL_VALUE_0TX FIFO is not full Read1 | TX_FIFO_FULL_VALUE_1TX FIFO is full." "0,1" line.long 0x10 "UART1_EBLR" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x10 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification.IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]].0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "UART1_MVR" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED,Not Defined" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "UART1_SYSC" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 5.--7. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROLREF: OCP DESIGN GUIDELINES VERSION 1.1 0x0 | IDLEMODE_VALUE_0Force idle. An idle request is acknowledged unconditionally 0x1 | IDLEMODE_VALUE_1No-idle. An idle request is never acknowledged." "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL 0 | ENAWAKEUP_VALUE_0Wake up is disabled 1 | ENAWAKEUP_VALUE_1Wake up capability is enabled" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0. Write0 | SOFTRESET_VALUE_0Normal mode Write1 | SOFTRESET_VALUE_1The module is reset" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy 0 | AUTOIDLE_VALUE_0Clock is running 1 | AUTOIDLE_VALUE_1Automatic OCP clock gating strategy is applied based on the OCP interface activity" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART1_SYSS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring Read0 | RESETDONE_VALUE_0Internal Module Reset is ongoing Read1 | RESETDONE_VALUE_1Reset completed" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART1_WER" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,Not Defined 0 | EVENT_7_TX_WAKEUP_EN_VALUE_0Event is not allowed to wake up the system 1 | EVENT_7_TX_WAKEUP_EN_VALUE_1EVENT CAN WAKE UP THE SYSTEM: Event can be: THR_IT or TX_DMA request and/or TX_SATUS_IT" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,Not Defined 0 | EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_VALUE_0Event is not allowed to wake up the system 1 | EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,Not Defined 0 | EVENT_5_RHR_INTERRUPT_VALUE_0Event is not allowed to wake up the system 1 | EVENT_5_RHR_INTERRUPT_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,Not Defined 0 | EVENT_4_RX_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_4_RX_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,Not Defined 0 | EVENT_3_DCD_CD_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_3_DCD_CD_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,Not Defined 0 | EVENT_2_RI_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_2_RI_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,Not Defined 0 | EVENT_1_DSR_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_1_DSR_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,Not Defined 0 | EVENT_0_CTS_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_0_CTS_ACTIVITY_VALUE_1Event can wake up the system" "0,1" line.long 0x4 "UART1_CFPS" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below.Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1 40 100.." rgroup.long 0x64++0x7 line.long 0x0 "UART1_RXFIFO_LVL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Not Defined" line.long 0x4 "UART1_TXFIFO_LVL" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24,Not Defined" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Not Defined" group.long 0x6C++0xB line.long 0x0 "UART1_IER2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 2. "RHR_IT_DIS,Not Defined 0 | RHR_IT_DIS_VALUE_0Enables the RHR interrupt. 1 | RHR_IT_DIS_VALUE_1Disables the RHR interrupt." "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "UART1_ISR2" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending 0 | TXFIFO_EMPTY_STS_VALUE_0TXFIFO_EMPTY interrupt not pending. 1 | TXFIFO_EMPTY_STS_VALUE_1TXFIFO_EMPTY interrupt pending." "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending 0 | RXFIFO_EMPTY_STS_VALUE_0RXFIFO_EMPTY interrupt not pending. 1 | RXFIFO_EMPTY_STS_VALUE_1RXFIFO_EMPTY interrupt pending." "0,1" line.long 0x8 "UART1_FREQ_SEL" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "UART1_ABAUD_1ST_CHAR" hexmask.long 0x0 0.--31. 1. "RESERVED,Not Defined" line.long 0x4 "UART1_BAUD_2ND_CHAR" hexmask.long 0x4 0.--31. 1. "RESERVED,Not Defined" group.long 0x80++0x27 line.long 0x0 "UART1_MDR3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2,Not Defined" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation 0 | DISABLE_CIR_RX_DEMOD_VALUE_0Enables CIR RX demodulation 1 | DISABLE_CIR_RX_DEMOD_VALUE_1Disables CIR RX demodulation" "0,1" line.long 0x4 "UART1_TX_DMA_THRESHOLD" hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "UART1_MDR4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,Not Defined" newline rbitfld.long 0x8 7. "RESERVED,Not Defined" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes] 0x0 | DISABLEDdisabled (no override) 0x1 | RESERVEDreserved 0x2 | SYNCH_EXTSynchronous mode with external clock 0x3 | SYNCH_GENSynchronous mode with generated clock.." "0,1,2,3,4,5,6,7" line.long 0xC "UART1_EFR2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1,Not Defined" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured 0 | _0timeout after at least one character has been received 1 | _1periodic timeout even when no character has been received" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full 0 | DEFAULTdata in RHR is not overwritten (standard) 1 | ATMELdata in RHR is overwritten when buffer full (and FIFO disabled)" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness 0 | LOW_ENDIANLittle Endian (LSB First) 1 | BIG_ENDIANBig Endian (MSB First)" "0,1" line.long 0x10 "UART1_ECR" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1,Not Defined" newline rbitfld.long 0x10 6.--7. "RESERVED,Not Defined" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter 0 | DISABLEDTransmitter is shut down 1 | ENABLEDTransmitter is working" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver 0 | DISABLEDReceiver is shut down 1 | ENABLEDReceiver is operating" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "UART1_TIMEGUARD" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART1_TIMEOUTL" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "UART1_TIMEOUTH" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "UART1_SCCR" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,Not Defined" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" line.long 0x24 "UART1_ETHR" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED,Not Defined" newline hexmask.long.word 0x24 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" rgroup.long 0xA4++0x3 line.long 0x0 "UART1_ERHR" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Not Defined" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.byte 0xA8++0x0 line.byte 0x0 "UART1_MAR" hexmask.byte 0x0 0.--7. 1. "ADDRESS,Multidrop match address value" group.byte 0xAC++0x0 line.byte 0x0 "UART1_MMR" hexmask.byte 0x0 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" group.byte 0xB0++0x0 line.byte 0x0 "UART1_MBR" hexmask.byte 0x0 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART2" base ad:0x52302000 group.byte 0x0++0x0 line.byte 0x0 "UART2_DLL" hexmask.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART2_RHR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x3 line.long 0x0 "UART2_THR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" group.byte 0x4++0x0 line.byte 0x0 "UART2_DLH" hexmask.byte 0x0 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.byte 0x4++0x0 line.byte 0x0 "UART2_IER_CIR" bitfld.byte 0x0 6.--7. "NOT_USED2,Not Defined" "0,1,2,3" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined 0 | TX_STATUS_IT_VALUE_0Disables the TX status interrupt. 1 | TX_STATUS_IT_VALUE_1Enables the TX status interrupt." "0,1" newline bitfld.byte 0x0 4. "NOT_USED1,Not Defined" "0,1" newline bitfld.byte 0x0 3. "RX_OVERRUN_IT,Not Defined 0 | RX_OVERRUN_IT_VALUE_0Disables the RX overrun interrupt. 1 | RX_OVERRUN_IT_VALUE_1Enables the RX overrun interrupt." "0,1" newline bitfld.byte 0x0 2. "RX_STOP_IT,Not Defined 0 | RX_STOP_IT_VALUE_0Disables the receive stop interrupt. 1 | RX_STOP_IT_VALUE_1Enables the receive stop interrupt." "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt. 1 | THR_IT_VALUE_1Enables the THR interrupt." "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt." "0,1" group.byte 0x4++0x0 line.byte 0x0 "UART2_IER_IRDA" bitfld.byte 0x0 7. "EOF_IT,Not Defined 0 | EOF_IT_VALUE_0Disables the received EOF interrupt. 1 | EOF_IT_VALUE_1Enables the received EOF interrupt." "0,1" newline bitfld.byte 0x0 6. "LINE_STS_IT,Not Defined 0 | LINE_STS_IT_VALUE_0Disables the receiver line status interrupt. 1 | LINE_STS_IT_VALUE_1Enables the receiver line status interrupt." "0,1" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined 0 | TX_STATUS_IT_VALUE_0Disables the TX status interrupt. 1 | TX_STATUS_IT_VALUE_1Enables the TX status interrupt." "0,1" newline bitfld.byte 0x0 4. "STS_FIFO_TRIG_IT,Not Defined 0 | STS_FIFO_TRIG_IT_VALUE_0Disables the status FIFO trigger level interrupt. 1 | STS_FIFO_TRIG_IT_VALUE_1Enables the status FIFO trigger level interrupt." "0,1" newline bitfld.byte 0x0 3. "RX_OVERRUN_IT,Not Defined 0 | RX_OVERRUN_IT_VALUE_0Disables the RX overrun interrupt. 1 | RX_OVERRUN_IT_VALUE_1Enables the RX overrun interrupt." "0,1" newline bitfld.byte 0x0 2. "LAST_RX_BYTE_IT,Not Defined 0 | LAST_RX_BYTE_IT_VALUE_0Disables the last byte of frame in RX FIFO interrupt. 1 | LAST_RX_BYTE_IT_VALUE_1Enables the last byte of frame in RX FIFO interrupt." "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt. 1 | THR_IT_VALUE_1Enables the THR interrupt." "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt." "0,1" group.long 0x4++0x3 line.long 0x0 "UART2_IER_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "CTS_IT,Not Defined 0 | CTS_IT_VALUE_0Disables the CTS* interrupt 1 | CTS_IT_VALUE_1Enables the CTS* interrupt" "0,1" newline bitfld.long 0x0 6. "RTS_IT,Not Defined 0 | RTS_IT_VALUE_0Disables the RTS* interrupt 1 | RTS_IT_VALUE_1Enables the RTS* interrupt" "0,1" newline bitfld.long 0x0 5. "XOFF_IT,Not Defined 0 | XOFF_IT_VALUE_0Disables the XOFF interrupt 1 | XOFF_IT_VALUE_1Enables the XOFF interrupt" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE,Not Defined 0 | SLEEP_MODE_VALUE_0Disables sleep mode 1 | SLEEP_MODE_VALUE_1Enables sleep mode (stop baud rate clock when the module is inactive)" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT,Not Defined 0 | MODEM_STS_IT_VALUE_0Disables the modem status register interrupt 1 | MODEM_STS_IT_VALUE_1Enables the modem status register interrupt" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT,Not Defined 0 | LINE_STS_IT_U_VALUE_0Disables the receiver line status interrupt 1 | LINE_STS_IT_U_VALUE_1Enables the receiver line status interrupt" "0,1" newline bitfld.long 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt 1 | THR_IT_VALUE_1Enables the THR interrupt" "0,1" newline bitfld.long 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt and time out interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt and time out interrupt." "0,1" group.byte 0x8++0x0 line.byte 0x0 "UART2_EFR" bitfld.byte 0x0 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.byte 0x0 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.byte 0x0 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.byte 0x0 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.byte 0x0 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" group.long 0x8++0x3 line.long 0x0 "UART2_FCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO:If SCR[7] = 0 and TLR[7:4] = 0000:00: 8 characters01: 16 characters10: 56 characters11: 60 charactersIf SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered.If SCR[7]=1 RX_FIFO_TRIG is 2.." "0: 8 characters01: 16 characters10: 56..,?,?,?" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO:If SCR[6] = 0 and TLR[3:0] = 0000:00: 8 spaces01: 16 spaces10: 32 spaces11: 56 spacesIf SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered.If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of the.." "0: 8 spaces01: 16 spaces10: 32 spaces11: 56..,?,?,?" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0. Write0 | DMA_MODE_VALUE_0DMA_MODE 0 (No DMA) Write1 | DMA_MODE_VALUE_1DMA_MODE 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR,Not Defined Write0 | TX_FIFO_CLEAR_VALUE_0No change Write1 | TX_FIFO_CLEAR_VALUE_1Clears the transmit FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR,Not Defined Write0 | RX_FIFO_CLEAR_VALUE_0No change Write1 | RX_FIFO_CLEAR_VALUE_1Clears the receive FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 0. "FIFO_EN,Not Defined Write0 | FIFO_EN_VALUE_0Disables the transmit and receive FIFOs. The transmit and receive holding registers are one byte FIFOs. Write1 | FIFO_EN_VALUE_1: Enables the transmit and receive FIFOs.The transmit and receive.." "0,1" rgroup.byte 0x8++0x0 line.byte 0x0 "UART2_IIR_CIR" bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined Read0 | TX_STATUS_IT_VALUE_0TX status interrupt inactive Read1 | TX_STATUS_IT_VALUE_1TX status interrupt active" "0,1" newline bitfld.byte 0x0 3. "RX_OE_IT,Not Defined Read0 | RX_OE_IT_VALUE_0RX overrun interrupt inactive Read1 | RX_OE_IT_VALUE_1RX overrun interrupt active" "0,1" newline bitfld.byte 0x0 2. "RX_STOP_IT,Not Defined Read0 | RX_STOP_IT_VALUE_0Receive stop interrupt inactive Read1 | RX_STOP_IT_VALUE_1Receive stop interrupt active" "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined Read0 | THR_IT_VALUE_0THR interrupt inactive Read1 | THR_IT_VALUE_1THR interrupt active" "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined Read0 | RHR_IT_VALUE_0RHR interrupt inactive Read1 | RHR_IT_VALUE_1RHR interrupt active" "0,1" rgroup.byte 0x8++0x0 line.byte 0x0 "UART2_IIR_IRDA" bitfld.byte 0x0 7. "EOF_IT,Not Defined Read0 | EOF_IT_VALUE_0Received EOF interrupt inactive Read1 | EOF_IT_VALUE_1Received EOF interrupt active" "0,1" newline bitfld.byte 0x0 6. "LINE_STS_IT,Not Defined Read0 | LINE_STS_IT_VALUE_0Receiver line status interrupt inactive Read1 | LINE_STS_IT_VALUE_1Receiver line status interrupt active" "0,1" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined Read0 | TX_STATUS_IT_VALUE_0TX status interrupt inactive Read1 | TX_STATUS_IT_VALUE_1TX status interrupt active" "0,1" newline bitfld.byte 0x0 4. "STS_FIFO_IT,Not Defined Read0 | STS_FIFO_IT_VALUE_0Status FIFO trigger level interrupt inactive Read1 | STS_FIFO_IT_VALUE_1Status FIFO trigger level interrupt active" "0,1" newline bitfld.byte 0x0 3. "RX_OE_IT,Not Defined Read0 | RX_OE_IT_VALUE_0RX overrun interrupt inactive Read1 | RX_OE_IT_VALUE_1RX overrun interrupt active" "0,1" newline bitfld.byte 0x0 2. "RX_FIFO_LAST_BYTE_IT,Not Defined Read0 | RX_FIFO_LAST_BYTE_IT_VALUE_0Last byte of frame in RX FIFO interrupt inactive Read1 | RX_FIFO_LAST_BYTE_IT_VALUE_1Last byte of frame in RX FIFO interrupt active" "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined Read0 | THR_IT_VALUE_0THR interrupt inactive Read1 | THR_IT_VALUE_1THR interrupt active" "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined Read0 | RHR_IT_VALUE_0RHR interrupt inactive Read1 | RHR_IT_VALUE_1RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART2_IIR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Not Defined Read0x00 | IT_TYPE_VALUE_0Modem Interrupt. Priority=4 Read0x01 | IT_TYPE_VALUE_1THR interrupt. Priority=3 Read0x02 | IT_TYPE_VALUE_2RHR interrupt. Priority=2 Read0x03 | IT_TYPE_VALUE_3Receiver line.." newline bitfld.long 0x0 0. "IT_PENDING,Not Defined Read0 | IT_PENDING_VALUE_0An interrupt is pending Read1 | IT_PENDING_VALUE_1No interrupt is pending" "0,1" group.long 0xC++0x3 line.long 0x0 "UART2_LCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "DIV_EN,Not Defined 0 | DIV_EN_VALUE_0Normal operating condition 1 | DIV_EN_VALUE_1Divisor latch enable. Allows to access to DLL DLH and other registers (refer to the registers mapping)" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit. 0 | BREAK_EN_VALUE_0Normal operating condition. 1 | BREAK_EN_VALUE_1Forces the transmitter output to go low to alert the communication terminal" "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1,Not Defined 0 | PARITY_TYPE1_VALUE_0Odd parity is generated (if LCR[3] = 1) 1 | PARITY_TYPE1_VALUE_1Even parity is generated (if LCR[3] = 1)" "0,1" newline bitfld.long 0x0 3. "PARITY_EN,Not Defined 0 | PARITY_EN_VALUE_0No parity 1 | PARITY_EN_VALUE_1A parity bit is generated during transmission and the receiver checks for received parity." "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits: 0 | NB_STOP_VALUE_01 stop bits (word length = 5 6 7 8) 1 | NB_STOP_VALUE_11.5 stop bits (word length = 5) in USART mode. 2 stop bits (word length = 6 7 8)" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received. 0x0 | CHAR_LENGTH_VALUE_05 bits 0x1 | CHAR_LENGTH_VALUE_16 bits 0x2 | CHAR_LENGTH_VALUE_27 bits 0x3 | CHAR_LENGTH_VALUE_38 bits" "0,1,2,3" group.byte 0x10++0x0 line.byte 0x0 "UART2_XON1_ADDR1" hexmask.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." group.long 0x10++0x3 line.long 0x0 "UART2_MCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 7. "RESERVED,Not Defined" "0,1" newline bitfld.long 0x0 6. "TCR_TLR,Not Defined 0 | TCR_TLR_VALUE_0No action 1 | TCR_TLR_VALUE_1Enables access to the TCR and TLR registers." "0,1" newline bitfld.long 0x0 5. "XON_EN,Not Defined 0 | XON_EN_VALUE_0Disable 'XON any' function 1 | XON_EN_VALUE_1Enable 'XON any' function" "0,1" newline bitfld.long 0x0 4. "LOOPBACK_EN,Not Defined 0 | LOOPBACK_EN_VALUE_0Normal operating mode 1 | LOOPBACK_EN_VALUE_1Enable local loopback mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4]. The transmit output is looped back to the.." "0,1" newline bitfld.long 0x0 3. "CD_STS_CH,Not Defined 0 | CD_STS_CH_VALUE_0In loopback forces DCD* input high and IRQ outputs to inactive state. 1 | CD_STS_CH_VALUE_1In loopback forces DCD* input low and IRQ outputs to inactive state." "0,1" newline bitfld.long 0x0 2. "RI_STS_CH,Not Defined 0 | RI_STS_CH_VALUE_0In loopback forces RI* input high. 1 | RI_STS_CH_VALUE_1In loopback forces RI* input low." "0,1" newline bitfld.long 0x0 1. "RTS,In loop back controls MSR[4].If auto-RTS is enabled the RTS* output is controlled by hardware flow control. 0 | RTS_VALUE_0Force RTS* output to inactive (high). 1 | RTS_VALUE_1Force RTS* output to active (low)." "0,1" newline bitfld.long 0x0 0. "DTR,Not Defined 0 | DTR_VALUE_0Force DTR* output to inactive (high). 1 | DTR_VALUE_1Force DTR* output to active (low)." "0,1" group.byte 0x14++0x0 line.byte 0x0 "UART2_XON2_ADDR2" hexmask.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.byte 0x14++0x0 line.byte 0x0 "UART2_LSR_CIR" bitfld.byte 0x0 7. "THR_EMPTY,Not Defined Read0 | THR_EMPTY_VALUE_0Transmit holding register (TX FIFO) is not empty Read1 | THR_EMPTY_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.byte 0x0 6. "RESERVED,Not Defined" "0,1" newline bitfld.byte 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register Read0 | RX_STOP_VALUE_0Reception is on going or waiting for a new frame Read1 |.." "0,1" newline bitfld.byte 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" rgroup.byte 0x14++0x0 line.byte 0x0 "UART2_LSR_IRDA" bitfld.byte 0x0 7. "THR_EMPTY,Not Defined Read0 | THR_EMPTY_VALUE_0Transmit holding register (TX FIFO) is not empty Read1 | THR_EMPTY_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.byte 0x0 6. "STS_FIFO_FULL,Not Defined Read0 | STS_FIFO_FULL_VALUE_0Status FIFO not full Read1 | STS_FIFO_FULL_VALUE_1Status FIFO full" "0,1" newline bitfld.byte 0x0 5. "RX_LAST_BYTE,Not Defined Read0 | RX_LAST_BYTE_VALUE_0The RX FIFO (RHR) does not contain the last byte of the frame to be read Read1 | RX_LAST_BYTE_VALUE_1The RX FIFO (RHR) contains the last byte of the frame to be read.This bit is only.." "0,1" newline bitfld.byte 0x0 4. "FRAME_TOO_LONG,Not Defined Read0 | FRAME_TOO_LONG_VALUE_0No frame-too-long error in frame Read1 | FRAME_TOO_LONG_VALUE_1Frame-too-long error in the frame at the top of the STATUS FIFO [next character to be read]. This bit is set to 1.." "0,1" newline bitfld.byte 0x0 3. "ABORT,Not Defined Read0 | ABORT_VALUE_0No abort pattern error in frame Read1 | ABORT_VALUE_1Abort pattern is received. SIR MIR: Abort pattern. FIR: Illegal symbol" "0,1" newline bitfld.byte 0x0 2. "CRC,Not Defined Read0 | CRC_VALUE_0No CRC error in frame Read1 | CRC_VALUE_1CRC error in the frame at the top of the STATUS FIFO (next character to be read)" "0,1" newline bitfld.byte 0x0 1. "STS_FIFO_E,Not Defined Read0 | STS_FIFO_E_VALUE_0Status FIFO not empty Read1 | STS_FIFO_E_VALUE_1Status FIFO empty" "0,1" newline bitfld.byte 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART2_LSR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "RX_FIFO_STS,Not Defined Read0 | RX_FIFO_STS_VALUE_0Normal operation Read1 | RX_FIFO_STS_VALUE_1At least one parity error framing error or break indication in the RX FIFO. Bit 7 is cleared when no more errors are present in the RX FIFO." "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Not Defined Read0 | TX_SR_E_VALUE_0Transmitter hold (TX FIFO) and shift registers are not empty. Read1 | TX_SR_E_VALUE_1Transmitter hold (TX FIFO) and shift registers are empty" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E,Not Defined Read0 | TX_FIFO_E_VALUE_0Transmit hold register (TX FIFO) is not empty Read1 | TX_FIFO_E_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed." "0,1" newline bitfld.long 0x0 4. "RX_BI,Not Defined Read0 | RX_BI_VALUE_0No break condition Read1 | RX_BI_VALUE_1A break was detected while the data being read from the RX FIFO was being received. (i.e. RX input was low for one character + 1 bit time frame)." "0,1" newline bitfld.long 0x0 3. "RX_FE,Not Defined Read0 | RX_FE_VALUE_0No framing error in data being read from RX FIFO. Read1 | RX_FE_VALUE_1Framing error occurred in data being read from RX FIFO.(received data did not have a valid stop bit)" "0,1" newline bitfld.long 0x0 2. "RX_PE,Not Defined Read0 | RX_PE_VALUE_0No parity error in data being read from RX FIFO. Read1 | RX_PE_VALUE_1Parity error in data being read from RX FIFO" "0,1" newline bitfld.long 0x0 1. "RX_OE,Not Defined Read0 | RX_OE_VALUE_0No overrun error Read1 | RX_OE_VALUE_1Overrun error has occurred. Set when the character held in the receive shift register is not transferred to the RX FIFO. This case can occurs only when receive.." "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" group.byte 0x18++0x0 line.byte 0x0 "UART2_TCR" hexmask.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.byte 0x18++0x0 line.byte 0x0 "UART2_XOFF1" hexmask.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." rgroup.long 0x18++0x3 line.long 0x0 "UART2_MSR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS,Not Defined Read1 | DSR_STS_VALUE_1Indicates that DSR* input (or MCR[0] in loop back) has changed state. Cleared on a read" "0,1" newline bitfld.long 0x0 0. "CTS_STS,Not Defined Read1 | CTS_STS_VALUE_1Indicates that CTS* input (or MCR[1] in loop back) has changed state. Cleared on a read." "0,1" group.byte 0x1C++0x0 line.byte 0x0 "UART2_TLR" hexmask.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.byte 0x1C++0x0 line.byte 0x0 "UART2_XOFF2" hexmask.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." group.long 0x1C++0xF line.long 0x0 "UART2_SPR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "SPR_WORD,Scratchpad register" line.long 0x4 "UART2_MDR1" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only. 0 | FRAME_END_MODE_VALUE_0Frame-length method 1 | FRAME_END_MODE_VALUE_1Set EOT bit method" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only. 0 | SIP_MODE_VALUE_0Manual SIP mode: SIP is generated with the control of ACREG[3] 1 | SIP_MODE_VALUE_1Automatic SIP mode: SIP is generated after each transmission." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission 0 | SCT_VALUE_0Starts the Infrared transmission as soon as a value is written to THR 1 | SCT_VALUE_1Starts the Infrared transmission with the control of ACREG[2]. Note: before starting any.." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver. 0 | SET_TXIR_VALUE_0No action if MDR2[7]=0. TXIR pin output is forced low if MDR2[7]=1 1 | SET_TXIR_VALUE_1TXIR pin output is forced high (not dependant of MDR2[7] value)." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP,Not Defined 0 | IR_SLEEP_VALUE_0IrDA/CIR sleep mode disabled 1 | IR_SLEEP_VALUE_1IrDA/CIR sleep mode enabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,Not Defined 0x0 | MODE_SELECT_VALUE_0UART 16x mode 0x1 | MODE_SELECT_VALUE_1SIR mode 0x2 | MODE_SELECT_VALUE_2UART 16x auto-baud 0x3 | MODE_SELECT_VALUE_3UART 13x mode 0x4 | MODE_SELECT_VALUE_4MIR.." "0,1,2,3,4,5,6,7" line.long 0x8 "UART2_MDR2" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR] 0 | SET_TXIR_ALT_VALUE_0Normal mode 1 | SET_TXIR_ALT_VALUE_1Alternate mode for SET_TXIR" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes. 0 | IRRXINVERT_VALUE_0inversion is performed 1.." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit: 0x0 | CIR_PULSE_MODE_VALUE_0Pulse width of 3 from 12 cycles 0x1 | CIR_PULSE_MODE_VALUE_1Pulse width of 4 from 12 cycles.." "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode. 0 | UART_PULSE_VALUE_0normal UART mode 1 | UART_PULSE_VALUE_1UART mode with a pulse shaping" "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode.Frame Status FIFO Threshold select: 0x0 | STS_FIFO_TRIG_VALUE_01 entry 0x1 | STS_FIFO_TRIG_VALUE_14 entries 0x2 | STS_FIFO_TRIG_VALUE_27 entries 0x3 | STS_FIFO_TRIG_VALUE_38 entries" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is : Read0 | IRTX_UNDERRUN_VALUE_0the last bit of the frame has been transmitted successfully without error. Read1 |.." "0,1" line.long 0xC "UART2_TXFLL" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0xC 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x28++0x3 line.long 0x0 "UART2_SFLSR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 5.--7. "RESERVED5,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Not Defined Read1 | OE_ERROR_VALUE_1Overrun error in RX FIFO when frame at top of RX FIFO was received." "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Not Defined Read1 | FRAME_TOO_LONG_ERROR_VALUE_1Frame-length too long error in frame at top of RX FIFO." "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Not Defined Read1 | ABORT_DETECT_VALUE_1Abort pattern detected in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR,Not Defined Read1 | CRC_ERROR_VALUE_1CRC error in frame at top of RX FIFO. top of RX FIFO = Next frame to be read from RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED0,Not Defined" "0,1" group.long 0x2C++0x3 line.long 0x0 "UART2_TXFLH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 5.--7. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART2_RESUME" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x30++0x3 line.long 0x0 "UART2_RXFLL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART2_SFREGL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART2_RXFLH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART2_SFREGH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.byte 0x38++0x0 line.byte 0x0 "UART2_UASR" bitfld.byte 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.byte 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." group.long 0x38++0x13 line.long 0x0 "UART2_BLR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select. 0 | XBOF_TYPE_VALUE_00xFF 1 | XBOF_TYPE_VALUE_10xC0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED,Not Defined" line.long 0x4 "UART2_ACREG" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 7. "PULSE_TYPE,SIR pulse width select: 0 | PULSE_TYPE_VALUE_03/16 of baud-rate pulse width 1 | PULSE_TYPE_VALUE_11.6us" "0,1" newline bitfld.long 0x4 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. 0 | SD_MOD_VALUE_0SD pin is set to high 1 | SD_MOD_VALUE_1SD pin is set to low" "0,1" newline bitfld.long 0x4 5. "DIS_IR_RX,Not Defined 0 | DIS_IR_RX_VALUE_0Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation). 1 | DIS_IR_RX_VALUE_1Disables RX input (permanent state - independent of transmit)." "0,1" newline bitfld.long 0x4 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line. 0 | DIS_TX_UNDERRUN_VALUE_0Long stop bits.." "0,1" newline bitfld.long 0x4 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP]If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission. 0 |.." "0,1" newline bitfld.long 0x4 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x4 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x4 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x8 "UART2_SCR" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x8 7. "RX_TRIG_GRANU1,Not Defined 0 | RX_TRIG_GRANU1_VALUE_0DISABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL. 1 | RX_TRIG_GRANU1_VALUE_1ENABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL." "0,1" newline bitfld.long 0x8 6. "TX_TRIG_GRANU1,Not Defined 0 | TX_TRIG_GRANU1_VALUE_0DISABLES THE GRANULARITY OF 1 FOR TRIGGER TX LEVEL. 1 | TX_TRIG_GRANU1_VALUE_1Enables the granularity of 1 for trigger TX level." "0,1" newline bitfld.long 0x8 5. "DSR_IT,Not Defined 0 | DSR_IT_VALUE_0DISABLES DSR* INTERRUPT. 1 | DSR_IT_VALUE_1ENABLES DSR* INTERRUPT." "0,1" newline bitfld.long 0x8 4. "RX_CTS_DSR_WAKE_UP_ENABLE,Not Defined 0 | RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_0DISABLES THE WAKE UP INTERRUPT AND CLEARS SSR[1]. 1 | RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_1Waits for a falling edge of pins RX CTS* or DSR* to generate an interrupt" "0,1" newline bitfld.long 0x8 3. "TX_EMPTY_CTL_IT,Not Defined 0 | TX_EMPTY_CTL_IT_VALUE_0Normal mode for THR interrupt (See UART mode interrupts table). 1 | TX_EMPTY_CTL_IT_VALUE_1THE THR INTERRUPT IS GENERATED WHEN TX FIFO AND TX SHIFT REGISTER ARE EMPTY." "0,1" newline bitfld.long 0x8 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1 0x0 | DMA_MODE_2_VALUE_0DMA mode 0 (no DMA) 0x1 | DMA_MODE_2_VALUE_1DMA mode 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX) 0x2 | DMA_MODE_2_VALUE_2DMA mode 2.." "0,1,2,3" newline bitfld.long 0x8 0. "DMA_MODE_CTL,Not Defined 0 | DMA_MODE_CTL_VALUE_0The DMA_MODE is set with FCR[3] 1 | DMA_MODE_CTL_VALUE_1The DMA_MODE is set with SCR[2:1]" "0,1" line.long 0xC "UART2_SSR" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0xC 3.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0xC 2. "DMA_COUNTER_RST,Not Defined 0 | DMA_COUNTER_RST_VALUE_0The DMA counter will not be reset if the corresponding FIFO is reset (via FCR[1] or FCR[2]) 1 | DMA_COUNTER_RST_VALUE_1The DMA counter will be reset if corresponding FIFO is reset.." "0,1" newline rbitfld.long 0xC 1. "RX_CTS_DSR_WAKE_UP_STS,Not Defined Read0 | RX_CTS_DSR_WAKE_UP_STS_VALUE_0No falling edge event on RX CTS* and DSR* Read1 | RX_CTS_DSR_WAKE_UP_STS_VALUE_1A falling edge occurred on RX CTS* or DSR*" "0,1" newline rbitfld.long 0xC 0. "TX_FIFO_FULL,Not Defined Read0 | TX_FIFO_FULL_VALUE_0TX FIFO is not full Read1 | TX_FIFO_FULL_VALUE_1TX FIFO is full." "0,1" line.long 0x10 "UART2_EBLR" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x10 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification.IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]].0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "UART2_MVR" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED,Not Defined" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "UART2_SYSC" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 5.--7. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROLREF: OCP DESIGN GUIDELINES VERSION 1.1 0x0 | IDLEMODE_VALUE_0Force idle. An idle request is acknowledged unconditionally 0x1 | IDLEMODE_VALUE_1No-idle. An idle request is never acknowledged." "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL 0 | ENAWAKEUP_VALUE_0Wake up is disabled 1 | ENAWAKEUP_VALUE_1Wake up capability is enabled" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0. Write0 | SOFTRESET_VALUE_0Normal mode Write1 | SOFTRESET_VALUE_1The module is reset" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy 0 | AUTOIDLE_VALUE_0Clock is running 1 | AUTOIDLE_VALUE_1Automatic OCP clock gating strategy is applied based on the OCP interface activity" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART2_SYSS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring Read0 | RESETDONE_VALUE_0Internal Module Reset is ongoing Read1 | RESETDONE_VALUE_1Reset completed" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART2_WER" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,Not Defined 0 | EVENT_7_TX_WAKEUP_EN_VALUE_0Event is not allowed to wake up the system 1 | EVENT_7_TX_WAKEUP_EN_VALUE_1EVENT CAN WAKE UP THE SYSTEM: Event can be: THR_IT or TX_DMA request and/or TX_SATUS_IT" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,Not Defined 0 | EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_VALUE_0Event is not allowed to wake up the system 1 | EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,Not Defined 0 | EVENT_5_RHR_INTERRUPT_VALUE_0Event is not allowed to wake up the system 1 | EVENT_5_RHR_INTERRUPT_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,Not Defined 0 | EVENT_4_RX_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_4_RX_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,Not Defined 0 | EVENT_3_DCD_CD_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_3_DCD_CD_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,Not Defined 0 | EVENT_2_RI_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_2_RI_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,Not Defined 0 | EVENT_1_DSR_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_1_DSR_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,Not Defined 0 | EVENT_0_CTS_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_0_CTS_ACTIVITY_VALUE_1Event can wake up the system" "0,1" line.long 0x4 "UART2_CFPS" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below.Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1 40 100.." rgroup.long 0x64++0x7 line.long 0x0 "UART2_RXFIFO_LVL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Not Defined" line.long 0x4 "UART2_TXFIFO_LVL" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24,Not Defined" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Not Defined" group.long 0x6C++0xB line.long 0x0 "UART2_IER2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 2. "RHR_IT_DIS,Not Defined 0 | RHR_IT_DIS_VALUE_0Enables the RHR interrupt. 1 | RHR_IT_DIS_VALUE_1Disables the RHR interrupt." "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "UART2_ISR2" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending 0 | TXFIFO_EMPTY_STS_VALUE_0TXFIFO_EMPTY interrupt not pending. 1 | TXFIFO_EMPTY_STS_VALUE_1TXFIFO_EMPTY interrupt pending." "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending 0 | RXFIFO_EMPTY_STS_VALUE_0RXFIFO_EMPTY interrupt not pending. 1 | RXFIFO_EMPTY_STS_VALUE_1RXFIFO_EMPTY interrupt pending." "0,1" line.long 0x8 "UART2_FREQ_SEL" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "UART2_ABAUD_1ST_CHAR" hexmask.long 0x0 0.--31. 1. "RESERVED,Not Defined" line.long 0x4 "UART2_BAUD_2ND_CHAR" hexmask.long 0x4 0.--31. 1. "RESERVED,Not Defined" group.long 0x80++0x27 line.long 0x0 "UART2_MDR3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2,Not Defined" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation 0 | DISABLE_CIR_RX_DEMOD_VALUE_0Enables CIR RX demodulation 1 | DISABLE_CIR_RX_DEMOD_VALUE_1Disables CIR RX demodulation" "0,1" line.long 0x4 "UART2_TX_DMA_THRESHOLD" hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "UART2_MDR4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,Not Defined" newline rbitfld.long 0x8 7. "RESERVED,Not Defined" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes] 0x0 | DISABLEDdisabled (no override) 0x1 | RESERVEDreserved 0x2 | SYNCH_EXTSynchronous mode with external clock 0x3 | SYNCH_GENSynchronous mode with generated clock.." "0,1,2,3,4,5,6,7" line.long 0xC "UART2_EFR2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1,Not Defined" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured 0 | _0timeout after at least one character has been received 1 | _1periodic timeout even when no character has been received" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full 0 | DEFAULTdata in RHR is not overwritten (standard) 1 | ATMELdata in RHR is overwritten when buffer full (and FIFO disabled)" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness 0 | LOW_ENDIANLittle Endian (LSB First) 1 | BIG_ENDIANBig Endian (MSB First)" "0,1" line.long 0x10 "UART2_ECR" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1,Not Defined" newline rbitfld.long 0x10 6.--7. "RESERVED,Not Defined" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter 0 | DISABLEDTransmitter is shut down 1 | ENABLEDTransmitter is working" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver 0 | DISABLEDReceiver is shut down 1 | ENABLEDReceiver is operating" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "UART2_TIMEGUARD" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART2_TIMEOUTL" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "UART2_TIMEOUTH" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "UART2_SCCR" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,Not Defined" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" line.long 0x24 "UART2_ETHR" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED,Not Defined" newline hexmask.long.word 0x24 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" rgroup.long 0xA4++0x3 line.long 0x0 "UART2_ERHR" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Not Defined" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.byte 0xA8++0x0 line.byte 0x0 "UART2_MAR" hexmask.byte 0x0 0.--7. 1. "ADDRESS,Multidrop match address value" group.byte 0xAC++0x0 line.byte 0x0 "UART2_MMR" hexmask.byte 0x0 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" group.byte 0xB0++0x0 line.byte 0x0 "UART2_MBR" hexmask.byte 0x0 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART3" base ad:0x52303000 group.byte 0x0++0x0 line.byte 0x0 "UART3_DLL" hexmask.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART3_RHR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x3 line.long 0x0 "UART3_THR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" group.byte 0x4++0x0 line.byte 0x0 "UART3_DLH" hexmask.byte 0x0 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.byte 0x4++0x0 line.byte 0x0 "UART3_IER_CIR" bitfld.byte 0x0 6.--7. "NOT_USED2,Not Defined" "0,1,2,3" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined 0 | TX_STATUS_IT_VALUE_0Disables the TX status interrupt. 1 | TX_STATUS_IT_VALUE_1Enables the TX status interrupt." "0,1" newline bitfld.byte 0x0 4. "NOT_USED1,Not Defined" "0,1" newline bitfld.byte 0x0 3. "RX_OVERRUN_IT,Not Defined 0 | RX_OVERRUN_IT_VALUE_0Disables the RX overrun interrupt. 1 | RX_OVERRUN_IT_VALUE_1Enables the RX overrun interrupt." "0,1" newline bitfld.byte 0x0 2. "RX_STOP_IT,Not Defined 0 | RX_STOP_IT_VALUE_0Disables the receive stop interrupt. 1 | RX_STOP_IT_VALUE_1Enables the receive stop interrupt." "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt. 1 | THR_IT_VALUE_1Enables the THR interrupt." "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt." "0,1" group.byte 0x4++0x0 line.byte 0x0 "UART3_IER_IRDA" bitfld.byte 0x0 7. "EOF_IT,Not Defined 0 | EOF_IT_VALUE_0Disables the received EOF interrupt. 1 | EOF_IT_VALUE_1Enables the received EOF interrupt." "0,1" newline bitfld.byte 0x0 6. "LINE_STS_IT,Not Defined 0 | LINE_STS_IT_VALUE_0Disables the receiver line status interrupt. 1 | LINE_STS_IT_VALUE_1Enables the receiver line status interrupt." "0,1" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined 0 | TX_STATUS_IT_VALUE_0Disables the TX status interrupt. 1 | TX_STATUS_IT_VALUE_1Enables the TX status interrupt." "0,1" newline bitfld.byte 0x0 4. "STS_FIFO_TRIG_IT,Not Defined 0 | STS_FIFO_TRIG_IT_VALUE_0Disables the status FIFO trigger level interrupt. 1 | STS_FIFO_TRIG_IT_VALUE_1Enables the status FIFO trigger level interrupt." "0,1" newline bitfld.byte 0x0 3. "RX_OVERRUN_IT,Not Defined 0 | RX_OVERRUN_IT_VALUE_0Disables the RX overrun interrupt. 1 | RX_OVERRUN_IT_VALUE_1Enables the RX overrun interrupt." "0,1" newline bitfld.byte 0x0 2. "LAST_RX_BYTE_IT,Not Defined 0 | LAST_RX_BYTE_IT_VALUE_0Disables the last byte of frame in RX FIFO interrupt. 1 | LAST_RX_BYTE_IT_VALUE_1Enables the last byte of frame in RX FIFO interrupt." "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt. 1 | THR_IT_VALUE_1Enables the THR interrupt." "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt." "0,1" group.long 0x4++0x3 line.long 0x0 "UART3_IER_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "CTS_IT,Not Defined 0 | CTS_IT_VALUE_0Disables the CTS* interrupt 1 | CTS_IT_VALUE_1Enables the CTS* interrupt" "0,1" newline bitfld.long 0x0 6. "RTS_IT,Not Defined 0 | RTS_IT_VALUE_0Disables the RTS* interrupt 1 | RTS_IT_VALUE_1Enables the RTS* interrupt" "0,1" newline bitfld.long 0x0 5. "XOFF_IT,Not Defined 0 | XOFF_IT_VALUE_0Disables the XOFF interrupt 1 | XOFF_IT_VALUE_1Enables the XOFF interrupt" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE,Not Defined 0 | SLEEP_MODE_VALUE_0Disables sleep mode 1 | SLEEP_MODE_VALUE_1Enables sleep mode (stop baud rate clock when the module is inactive)" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT,Not Defined 0 | MODEM_STS_IT_VALUE_0Disables the modem status register interrupt 1 | MODEM_STS_IT_VALUE_1Enables the modem status register interrupt" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT,Not Defined 0 | LINE_STS_IT_U_VALUE_0Disables the receiver line status interrupt 1 | LINE_STS_IT_U_VALUE_1Enables the receiver line status interrupt" "0,1" newline bitfld.long 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt 1 | THR_IT_VALUE_1Enables the THR interrupt" "0,1" newline bitfld.long 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt and time out interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt and time out interrupt." "0,1" group.byte 0x8++0x0 line.byte 0x0 "UART3_EFR" bitfld.byte 0x0 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.byte 0x0 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.byte 0x0 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.byte 0x0 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.byte 0x0 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" group.long 0x8++0x3 line.long 0x0 "UART3_FCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO:If SCR[7] = 0 and TLR[7:4] = 0000:00: 8 characters01: 16 characters10: 56 characters11: 60 charactersIf SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered.If SCR[7]=1 RX_FIFO_TRIG is 2.." "0: 8 characters01: 16 characters10: 56..,?,?,?" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO:If SCR[6] = 0 and TLR[3:0] = 0000:00: 8 spaces01: 16 spaces10: 32 spaces11: 56 spacesIf SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered.If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of the.." "0: 8 spaces01: 16 spaces10: 32 spaces11: 56..,?,?,?" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0. Write0 | DMA_MODE_VALUE_0DMA_MODE 0 (No DMA) Write1 | DMA_MODE_VALUE_1DMA_MODE 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR,Not Defined Write0 | TX_FIFO_CLEAR_VALUE_0No change Write1 | TX_FIFO_CLEAR_VALUE_1Clears the transmit FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR,Not Defined Write0 | RX_FIFO_CLEAR_VALUE_0No change Write1 | RX_FIFO_CLEAR_VALUE_1Clears the receive FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 0. "FIFO_EN,Not Defined Write0 | FIFO_EN_VALUE_0Disables the transmit and receive FIFOs. The transmit and receive holding registers are one byte FIFOs. Write1 | FIFO_EN_VALUE_1: Enables the transmit and receive FIFOs.The transmit and receive.." "0,1" rgroup.byte 0x8++0x0 line.byte 0x0 "UART3_IIR_CIR" bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined Read0 | TX_STATUS_IT_VALUE_0TX status interrupt inactive Read1 | TX_STATUS_IT_VALUE_1TX status interrupt active" "0,1" newline bitfld.byte 0x0 3. "RX_OE_IT,Not Defined Read0 | RX_OE_IT_VALUE_0RX overrun interrupt inactive Read1 | RX_OE_IT_VALUE_1RX overrun interrupt active" "0,1" newline bitfld.byte 0x0 2. "RX_STOP_IT,Not Defined Read0 | RX_STOP_IT_VALUE_0Receive stop interrupt inactive Read1 | RX_STOP_IT_VALUE_1Receive stop interrupt active" "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined Read0 | THR_IT_VALUE_0THR interrupt inactive Read1 | THR_IT_VALUE_1THR interrupt active" "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined Read0 | RHR_IT_VALUE_0RHR interrupt inactive Read1 | RHR_IT_VALUE_1RHR interrupt active" "0,1" rgroup.byte 0x8++0x0 line.byte 0x0 "UART3_IIR_IRDA" bitfld.byte 0x0 7. "EOF_IT,Not Defined Read0 | EOF_IT_VALUE_0Received EOF interrupt inactive Read1 | EOF_IT_VALUE_1Received EOF interrupt active" "0,1" newline bitfld.byte 0x0 6. "LINE_STS_IT,Not Defined Read0 | LINE_STS_IT_VALUE_0Receiver line status interrupt inactive Read1 | LINE_STS_IT_VALUE_1Receiver line status interrupt active" "0,1" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined Read0 | TX_STATUS_IT_VALUE_0TX status interrupt inactive Read1 | TX_STATUS_IT_VALUE_1TX status interrupt active" "0,1" newline bitfld.byte 0x0 4. "STS_FIFO_IT,Not Defined Read0 | STS_FIFO_IT_VALUE_0Status FIFO trigger level interrupt inactive Read1 | STS_FIFO_IT_VALUE_1Status FIFO trigger level interrupt active" "0,1" newline bitfld.byte 0x0 3. "RX_OE_IT,Not Defined Read0 | RX_OE_IT_VALUE_0RX overrun interrupt inactive Read1 | RX_OE_IT_VALUE_1RX overrun interrupt active" "0,1" newline bitfld.byte 0x0 2. "RX_FIFO_LAST_BYTE_IT,Not Defined Read0 | RX_FIFO_LAST_BYTE_IT_VALUE_0Last byte of frame in RX FIFO interrupt inactive Read1 | RX_FIFO_LAST_BYTE_IT_VALUE_1Last byte of frame in RX FIFO interrupt active" "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined Read0 | THR_IT_VALUE_0THR interrupt inactive Read1 | THR_IT_VALUE_1THR interrupt active" "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined Read0 | RHR_IT_VALUE_0RHR interrupt inactive Read1 | RHR_IT_VALUE_1RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART3_IIR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Not Defined Read0x00 | IT_TYPE_VALUE_0Modem Interrupt. Priority=4 Read0x01 | IT_TYPE_VALUE_1THR interrupt. Priority=3 Read0x02 | IT_TYPE_VALUE_2RHR interrupt. Priority=2 Read0x03 | IT_TYPE_VALUE_3Receiver line.." newline bitfld.long 0x0 0. "IT_PENDING,Not Defined Read0 | IT_PENDING_VALUE_0An interrupt is pending Read1 | IT_PENDING_VALUE_1No interrupt is pending" "0,1" group.long 0xC++0x3 line.long 0x0 "UART3_LCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "DIV_EN,Not Defined 0 | DIV_EN_VALUE_0Normal operating condition 1 | DIV_EN_VALUE_1Divisor latch enable. Allows to access to DLL DLH and other registers (refer to the registers mapping)" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit. 0 | BREAK_EN_VALUE_0Normal operating condition. 1 | BREAK_EN_VALUE_1Forces the transmitter output to go low to alert the communication terminal" "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1,Not Defined 0 | PARITY_TYPE1_VALUE_0Odd parity is generated (if LCR[3] = 1) 1 | PARITY_TYPE1_VALUE_1Even parity is generated (if LCR[3] = 1)" "0,1" newline bitfld.long 0x0 3. "PARITY_EN,Not Defined 0 | PARITY_EN_VALUE_0No parity 1 | PARITY_EN_VALUE_1A parity bit is generated during transmission and the receiver checks for received parity." "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits: 0 | NB_STOP_VALUE_01 stop bits (word length = 5 6 7 8) 1 | NB_STOP_VALUE_11.5 stop bits (word length = 5) in USART mode. 2 stop bits (word length = 6 7 8)" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received. 0x0 | CHAR_LENGTH_VALUE_05 bits 0x1 | CHAR_LENGTH_VALUE_16 bits 0x2 | CHAR_LENGTH_VALUE_27 bits 0x3 | CHAR_LENGTH_VALUE_38 bits" "0,1,2,3" group.byte 0x10++0x0 line.byte 0x0 "UART3_XON1_ADDR1" hexmask.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." group.long 0x10++0x3 line.long 0x0 "UART3_MCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 7. "RESERVED,Not Defined" "0,1" newline bitfld.long 0x0 6. "TCR_TLR,Not Defined 0 | TCR_TLR_VALUE_0No action 1 | TCR_TLR_VALUE_1Enables access to the TCR and TLR registers." "0,1" newline bitfld.long 0x0 5. "XON_EN,Not Defined 0 | XON_EN_VALUE_0Disable 'XON any' function 1 | XON_EN_VALUE_1Enable 'XON any' function" "0,1" newline bitfld.long 0x0 4. "LOOPBACK_EN,Not Defined 0 | LOOPBACK_EN_VALUE_0Normal operating mode 1 | LOOPBACK_EN_VALUE_1Enable local loopback mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4]. The transmit output is looped back to the.." "0,1" newline bitfld.long 0x0 3. "CD_STS_CH,Not Defined 0 | CD_STS_CH_VALUE_0In loopback forces DCD* input high and IRQ outputs to inactive state. 1 | CD_STS_CH_VALUE_1In loopback forces DCD* input low and IRQ outputs to inactive state." "0,1" newline bitfld.long 0x0 2. "RI_STS_CH,Not Defined 0 | RI_STS_CH_VALUE_0In loopback forces RI* input high. 1 | RI_STS_CH_VALUE_1In loopback forces RI* input low." "0,1" newline bitfld.long 0x0 1. "RTS,In loop back controls MSR[4].If auto-RTS is enabled the RTS* output is controlled by hardware flow control. 0 | RTS_VALUE_0Force RTS* output to inactive (high). 1 | RTS_VALUE_1Force RTS* output to active (low)." "0,1" newline bitfld.long 0x0 0. "DTR,Not Defined 0 | DTR_VALUE_0Force DTR* output to inactive (high). 1 | DTR_VALUE_1Force DTR* output to active (low)." "0,1" group.byte 0x14++0x0 line.byte 0x0 "UART3_XON2_ADDR2" hexmask.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.byte 0x14++0x0 line.byte 0x0 "UART3_LSR_CIR" bitfld.byte 0x0 7. "THR_EMPTY,Not Defined Read0 | THR_EMPTY_VALUE_0Transmit holding register (TX FIFO) is not empty Read1 | THR_EMPTY_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.byte 0x0 6. "RESERVED,Not Defined" "0,1" newline bitfld.byte 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register Read0 | RX_STOP_VALUE_0Reception is on going or waiting for a new frame Read1 |.." "0,1" newline bitfld.byte 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" rgroup.byte 0x14++0x0 line.byte 0x0 "UART3_LSR_IRDA" bitfld.byte 0x0 7. "THR_EMPTY,Not Defined Read0 | THR_EMPTY_VALUE_0Transmit holding register (TX FIFO) is not empty Read1 | THR_EMPTY_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.byte 0x0 6. "STS_FIFO_FULL,Not Defined Read0 | STS_FIFO_FULL_VALUE_0Status FIFO not full Read1 | STS_FIFO_FULL_VALUE_1Status FIFO full" "0,1" newline bitfld.byte 0x0 5. "RX_LAST_BYTE,Not Defined Read0 | RX_LAST_BYTE_VALUE_0The RX FIFO (RHR) does not contain the last byte of the frame to be read Read1 | RX_LAST_BYTE_VALUE_1The RX FIFO (RHR) contains the last byte of the frame to be read.This bit is only.." "0,1" newline bitfld.byte 0x0 4. "FRAME_TOO_LONG,Not Defined Read0 | FRAME_TOO_LONG_VALUE_0No frame-too-long error in frame Read1 | FRAME_TOO_LONG_VALUE_1Frame-too-long error in the frame at the top of the STATUS FIFO [next character to be read]. This bit is set to 1.." "0,1" newline bitfld.byte 0x0 3. "ABORT,Not Defined Read0 | ABORT_VALUE_0No abort pattern error in frame Read1 | ABORT_VALUE_1Abort pattern is received. SIR MIR: Abort pattern. FIR: Illegal symbol" "0,1" newline bitfld.byte 0x0 2. "CRC,Not Defined Read0 | CRC_VALUE_0No CRC error in frame Read1 | CRC_VALUE_1CRC error in the frame at the top of the STATUS FIFO (next character to be read)" "0,1" newline bitfld.byte 0x0 1. "STS_FIFO_E,Not Defined Read0 | STS_FIFO_E_VALUE_0Status FIFO not empty Read1 | STS_FIFO_E_VALUE_1Status FIFO empty" "0,1" newline bitfld.byte 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART3_LSR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "RX_FIFO_STS,Not Defined Read0 | RX_FIFO_STS_VALUE_0Normal operation Read1 | RX_FIFO_STS_VALUE_1At least one parity error framing error or break indication in the RX FIFO. Bit 7 is cleared when no more errors are present in the RX FIFO." "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Not Defined Read0 | TX_SR_E_VALUE_0Transmitter hold (TX FIFO) and shift registers are not empty. Read1 | TX_SR_E_VALUE_1Transmitter hold (TX FIFO) and shift registers are empty" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E,Not Defined Read0 | TX_FIFO_E_VALUE_0Transmit hold register (TX FIFO) is not empty Read1 | TX_FIFO_E_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed." "0,1" newline bitfld.long 0x0 4. "RX_BI,Not Defined Read0 | RX_BI_VALUE_0No break condition Read1 | RX_BI_VALUE_1A break was detected while the data being read from the RX FIFO was being received. (i.e. RX input was low for one character + 1 bit time frame)." "0,1" newline bitfld.long 0x0 3. "RX_FE,Not Defined Read0 | RX_FE_VALUE_0No framing error in data being read from RX FIFO. Read1 | RX_FE_VALUE_1Framing error occurred in data being read from RX FIFO.(received data did not have a valid stop bit)" "0,1" newline bitfld.long 0x0 2. "RX_PE,Not Defined Read0 | RX_PE_VALUE_0No parity error in data being read from RX FIFO. Read1 | RX_PE_VALUE_1Parity error in data being read from RX FIFO" "0,1" newline bitfld.long 0x0 1. "RX_OE,Not Defined Read0 | RX_OE_VALUE_0No overrun error Read1 | RX_OE_VALUE_1Overrun error has occurred. Set when the character held in the receive shift register is not transferred to the RX FIFO. This case can occurs only when receive.." "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" group.byte 0x18++0x0 line.byte 0x0 "UART3_TCR" hexmask.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.byte 0x18++0x0 line.byte 0x0 "UART3_XOFF1" hexmask.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." rgroup.long 0x18++0x3 line.long 0x0 "UART3_MSR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS,Not Defined Read1 | DSR_STS_VALUE_1Indicates that DSR* input (or MCR[0] in loop back) has changed state. Cleared on a read" "0,1" newline bitfld.long 0x0 0. "CTS_STS,Not Defined Read1 | CTS_STS_VALUE_1Indicates that CTS* input (or MCR[1] in loop back) has changed state. Cleared on a read." "0,1" group.byte 0x1C++0x0 line.byte 0x0 "UART3_TLR" hexmask.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.byte 0x1C++0x0 line.byte 0x0 "UART3_XOFF2" hexmask.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." group.long 0x1C++0xF line.long 0x0 "UART3_SPR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "SPR_WORD,Scratchpad register" line.long 0x4 "UART3_MDR1" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only. 0 | FRAME_END_MODE_VALUE_0Frame-length method 1 | FRAME_END_MODE_VALUE_1Set EOT bit method" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only. 0 | SIP_MODE_VALUE_0Manual SIP mode: SIP is generated with the control of ACREG[3] 1 | SIP_MODE_VALUE_1Automatic SIP mode: SIP is generated after each transmission." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission 0 | SCT_VALUE_0Starts the Infrared transmission as soon as a value is written to THR 1 | SCT_VALUE_1Starts the Infrared transmission with the control of ACREG[2]. Note: before starting any.." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver. 0 | SET_TXIR_VALUE_0No action if MDR2[7]=0. TXIR pin output is forced low if MDR2[7]=1 1 | SET_TXIR_VALUE_1TXIR pin output is forced high (not dependant of MDR2[7] value)." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP,Not Defined 0 | IR_SLEEP_VALUE_0IrDA/CIR sleep mode disabled 1 | IR_SLEEP_VALUE_1IrDA/CIR sleep mode enabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,Not Defined 0x0 | MODE_SELECT_VALUE_0UART 16x mode 0x1 | MODE_SELECT_VALUE_1SIR mode 0x2 | MODE_SELECT_VALUE_2UART 16x auto-baud 0x3 | MODE_SELECT_VALUE_3UART 13x mode 0x4 | MODE_SELECT_VALUE_4MIR.." "0,1,2,3,4,5,6,7" line.long 0x8 "UART3_MDR2" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR] 0 | SET_TXIR_ALT_VALUE_0Normal mode 1 | SET_TXIR_ALT_VALUE_1Alternate mode for SET_TXIR" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes. 0 | IRRXINVERT_VALUE_0inversion is performed 1.." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit: 0x0 | CIR_PULSE_MODE_VALUE_0Pulse width of 3 from 12 cycles 0x1 | CIR_PULSE_MODE_VALUE_1Pulse width of 4 from 12 cycles.." "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode. 0 | UART_PULSE_VALUE_0normal UART mode 1 | UART_PULSE_VALUE_1UART mode with a pulse shaping" "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode.Frame Status FIFO Threshold select: 0x0 | STS_FIFO_TRIG_VALUE_01 entry 0x1 | STS_FIFO_TRIG_VALUE_14 entries 0x2 | STS_FIFO_TRIG_VALUE_27 entries 0x3 | STS_FIFO_TRIG_VALUE_38 entries" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is : Read0 | IRTX_UNDERRUN_VALUE_0the last bit of the frame has been transmitted successfully without error. Read1 |.." "0,1" line.long 0xC "UART3_TXFLL" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0xC 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x28++0x3 line.long 0x0 "UART3_SFLSR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 5.--7. "RESERVED5,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Not Defined Read1 | OE_ERROR_VALUE_1Overrun error in RX FIFO when frame at top of RX FIFO was received." "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Not Defined Read1 | FRAME_TOO_LONG_ERROR_VALUE_1Frame-length too long error in frame at top of RX FIFO." "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Not Defined Read1 | ABORT_DETECT_VALUE_1Abort pattern detected in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR,Not Defined Read1 | CRC_ERROR_VALUE_1CRC error in frame at top of RX FIFO. top of RX FIFO = Next frame to be read from RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED0,Not Defined" "0,1" group.long 0x2C++0x3 line.long 0x0 "UART3_TXFLH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 5.--7. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART3_RESUME" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x30++0x3 line.long 0x0 "UART3_RXFLL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART3_SFREGL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART3_RXFLH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART3_SFREGH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.byte 0x38++0x0 line.byte 0x0 "UART3_UASR" bitfld.byte 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.byte 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." group.long 0x38++0x13 line.long 0x0 "UART3_BLR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select. 0 | XBOF_TYPE_VALUE_00xFF 1 | XBOF_TYPE_VALUE_10xC0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED,Not Defined" line.long 0x4 "UART3_ACREG" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 7. "PULSE_TYPE,SIR pulse width select: 0 | PULSE_TYPE_VALUE_03/16 of baud-rate pulse width 1 | PULSE_TYPE_VALUE_11.6us" "0,1" newline bitfld.long 0x4 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. 0 | SD_MOD_VALUE_0SD pin is set to high 1 | SD_MOD_VALUE_1SD pin is set to low" "0,1" newline bitfld.long 0x4 5. "DIS_IR_RX,Not Defined 0 | DIS_IR_RX_VALUE_0Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation). 1 | DIS_IR_RX_VALUE_1Disables RX input (permanent state - independent of transmit)." "0,1" newline bitfld.long 0x4 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line. 0 | DIS_TX_UNDERRUN_VALUE_0Long stop bits.." "0,1" newline bitfld.long 0x4 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP]If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission. 0 |.." "0,1" newline bitfld.long 0x4 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x4 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x4 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x8 "UART3_SCR" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x8 7. "RX_TRIG_GRANU1,Not Defined 0 | RX_TRIG_GRANU1_VALUE_0DISABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL. 1 | RX_TRIG_GRANU1_VALUE_1ENABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL." "0,1" newline bitfld.long 0x8 6. "TX_TRIG_GRANU1,Not Defined 0 | TX_TRIG_GRANU1_VALUE_0DISABLES THE GRANULARITY OF 1 FOR TRIGGER TX LEVEL. 1 | TX_TRIG_GRANU1_VALUE_1Enables the granularity of 1 for trigger TX level." "0,1" newline bitfld.long 0x8 5. "DSR_IT,Not Defined 0 | DSR_IT_VALUE_0DISABLES DSR* INTERRUPT. 1 | DSR_IT_VALUE_1ENABLES DSR* INTERRUPT." "0,1" newline bitfld.long 0x8 4. "RX_CTS_DSR_WAKE_UP_ENABLE,Not Defined 0 | RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_0DISABLES THE WAKE UP INTERRUPT AND CLEARS SSR[1]. 1 | RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_1Waits for a falling edge of pins RX CTS* or DSR* to generate an interrupt" "0,1" newline bitfld.long 0x8 3. "TX_EMPTY_CTL_IT,Not Defined 0 | TX_EMPTY_CTL_IT_VALUE_0Normal mode for THR interrupt (See UART mode interrupts table). 1 | TX_EMPTY_CTL_IT_VALUE_1THE THR INTERRUPT IS GENERATED WHEN TX FIFO AND TX SHIFT REGISTER ARE EMPTY." "0,1" newline bitfld.long 0x8 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1 0x0 | DMA_MODE_2_VALUE_0DMA mode 0 (no DMA) 0x1 | DMA_MODE_2_VALUE_1DMA mode 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX) 0x2 | DMA_MODE_2_VALUE_2DMA mode 2.." "0,1,2,3" newline bitfld.long 0x8 0. "DMA_MODE_CTL,Not Defined 0 | DMA_MODE_CTL_VALUE_0The DMA_MODE is set with FCR[3] 1 | DMA_MODE_CTL_VALUE_1The DMA_MODE is set with SCR[2:1]" "0,1" line.long 0xC "UART3_SSR" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0xC 3.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0xC 2. "DMA_COUNTER_RST,Not Defined 0 | DMA_COUNTER_RST_VALUE_0The DMA counter will not be reset if the corresponding FIFO is reset (via FCR[1] or FCR[2]) 1 | DMA_COUNTER_RST_VALUE_1The DMA counter will be reset if corresponding FIFO is reset.." "0,1" newline rbitfld.long 0xC 1. "RX_CTS_DSR_WAKE_UP_STS,Not Defined Read0 | RX_CTS_DSR_WAKE_UP_STS_VALUE_0No falling edge event on RX CTS* and DSR* Read1 | RX_CTS_DSR_WAKE_UP_STS_VALUE_1A falling edge occurred on RX CTS* or DSR*" "0,1" newline rbitfld.long 0xC 0. "TX_FIFO_FULL,Not Defined Read0 | TX_FIFO_FULL_VALUE_0TX FIFO is not full Read1 | TX_FIFO_FULL_VALUE_1TX FIFO is full." "0,1" line.long 0x10 "UART3_EBLR" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x10 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification.IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]].0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "UART3_MVR" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED,Not Defined" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "UART3_SYSC" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 5.--7. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROLREF: OCP DESIGN GUIDELINES VERSION 1.1 0x0 | IDLEMODE_VALUE_0Force idle. An idle request is acknowledged unconditionally 0x1 | IDLEMODE_VALUE_1No-idle. An idle request is never acknowledged." "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL 0 | ENAWAKEUP_VALUE_0Wake up is disabled 1 | ENAWAKEUP_VALUE_1Wake up capability is enabled" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0. Write0 | SOFTRESET_VALUE_0Normal mode Write1 | SOFTRESET_VALUE_1The module is reset" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy 0 | AUTOIDLE_VALUE_0Clock is running 1 | AUTOIDLE_VALUE_1Automatic OCP clock gating strategy is applied based on the OCP interface activity" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART3_SYSS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring Read0 | RESETDONE_VALUE_0Internal Module Reset is ongoing Read1 | RESETDONE_VALUE_1Reset completed" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART3_WER" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,Not Defined 0 | EVENT_7_TX_WAKEUP_EN_VALUE_0Event is not allowed to wake up the system 1 | EVENT_7_TX_WAKEUP_EN_VALUE_1EVENT CAN WAKE UP THE SYSTEM: Event can be: THR_IT or TX_DMA request and/or TX_SATUS_IT" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,Not Defined 0 | EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_VALUE_0Event is not allowed to wake up the system 1 | EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,Not Defined 0 | EVENT_5_RHR_INTERRUPT_VALUE_0Event is not allowed to wake up the system 1 | EVENT_5_RHR_INTERRUPT_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,Not Defined 0 | EVENT_4_RX_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_4_RX_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,Not Defined 0 | EVENT_3_DCD_CD_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_3_DCD_CD_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,Not Defined 0 | EVENT_2_RI_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_2_RI_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,Not Defined 0 | EVENT_1_DSR_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_1_DSR_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,Not Defined 0 | EVENT_0_CTS_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_0_CTS_ACTIVITY_VALUE_1Event can wake up the system" "0,1" line.long 0x4 "UART3_CFPS" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below.Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1 40 100.." rgroup.long 0x64++0x7 line.long 0x0 "UART3_RXFIFO_LVL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Not Defined" line.long 0x4 "UART3_TXFIFO_LVL" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24,Not Defined" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Not Defined" group.long 0x6C++0xB line.long 0x0 "UART3_IER2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 2. "RHR_IT_DIS,Not Defined 0 | RHR_IT_DIS_VALUE_0Enables the RHR interrupt. 1 | RHR_IT_DIS_VALUE_1Disables the RHR interrupt." "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "UART3_ISR2" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending 0 | TXFIFO_EMPTY_STS_VALUE_0TXFIFO_EMPTY interrupt not pending. 1 | TXFIFO_EMPTY_STS_VALUE_1TXFIFO_EMPTY interrupt pending." "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending 0 | RXFIFO_EMPTY_STS_VALUE_0RXFIFO_EMPTY interrupt not pending. 1 | RXFIFO_EMPTY_STS_VALUE_1RXFIFO_EMPTY interrupt pending." "0,1" line.long 0x8 "UART3_FREQ_SEL" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "UART3_ABAUD_1ST_CHAR" hexmask.long 0x0 0.--31. 1. "RESERVED,Not Defined" line.long 0x4 "UART3_BAUD_2ND_CHAR" hexmask.long 0x4 0.--31. 1. "RESERVED,Not Defined" group.long 0x80++0x27 line.long 0x0 "UART3_MDR3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2,Not Defined" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation 0 | DISABLE_CIR_RX_DEMOD_VALUE_0Enables CIR RX demodulation 1 | DISABLE_CIR_RX_DEMOD_VALUE_1Disables CIR RX demodulation" "0,1" line.long 0x4 "UART3_TX_DMA_THRESHOLD" hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "UART3_MDR4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,Not Defined" newline rbitfld.long 0x8 7. "RESERVED,Not Defined" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes] 0x0 | DISABLEDdisabled (no override) 0x1 | RESERVEDreserved 0x2 | SYNCH_EXTSynchronous mode with external clock 0x3 | SYNCH_GENSynchronous mode with generated clock.." "0,1,2,3,4,5,6,7" line.long 0xC "UART3_EFR2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1,Not Defined" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured 0 | _0timeout after at least one character has been received 1 | _1periodic timeout even when no character has been received" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full 0 | DEFAULTdata in RHR is not overwritten (standard) 1 | ATMELdata in RHR is overwritten when buffer full (and FIFO disabled)" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness 0 | LOW_ENDIANLittle Endian (LSB First) 1 | BIG_ENDIANBig Endian (MSB First)" "0,1" line.long 0x10 "UART3_ECR" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1,Not Defined" newline rbitfld.long 0x10 6.--7. "RESERVED,Not Defined" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter 0 | DISABLEDTransmitter is shut down 1 | ENABLEDTransmitter is working" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver 0 | DISABLEDReceiver is shut down 1 | ENABLEDReceiver is operating" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "UART3_TIMEGUARD" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART3_TIMEOUTL" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "UART3_TIMEOUTH" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "UART3_SCCR" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,Not Defined" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" line.long 0x24 "UART3_ETHR" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED,Not Defined" newline hexmask.long.word 0x24 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" rgroup.long 0xA4++0x3 line.long 0x0 "UART3_ERHR" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Not Defined" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.byte 0xA8++0x0 line.byte 0x0 "UART3_MAR" hexmask.byte 0x0 0.--7. 1. "ADDRESS,Multidrop match address value" group.byte 0xAC++0x0 line.byte 0x0 "UART3_MMR" hexmask.byte 0x0 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" group.byte 0xB0++0x0 line.byte 0x0 "UART3_MBR" hexmask.byte 0x0 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART4" base ad:0x52304000 group.byte 0x0++0x0 line.byte 0x0 "UART4_DLL" hexmask.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART4_RHR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x3 line.long 0x0 "UART4_THR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" group.byte 0x4++0x0 line.byte 0x0 "UART4_DLH" hexmask.byte 0x0 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.byte 0x4++0x0 line.byte 0x0 "UART4_IER_CIR" bitfld.byte 0x0 6.--7. "NOT_USED2,Not Defined" "0,1,2,3" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined 0 | TX_STATUS_IT_VALUE_0Disables the TX status interrupt. 1 | TX_STATUS_IT_VALUE_1Enables the TX status interrupt." "0,1" newline bitfld.byte 0x0 4. "NOT_USED1,Not Defined" "0,1" newline bitfld.byte 0x0 3. "RX_OVERRUN_IT,Not Defined 0 | RX_OVERRUN_IT_VALUE_0Disables the RX overrun interrupt. 1 | RX_OVERRUN_IT_VALUE_1Enables the RX overrun interrupt." "0,1" newline bitfld.byte 0x0 2. "RX_STOP_IT,Not Defined 0 | RX_STOP_IT_VALUE_0Disables the receive stop interrupt. 1 | RX_STOP_IT_VALUE_1Enables the receive stop interrupt." "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt. 1 | THR_IT_VALUE_1Enables the THR interrupt." "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt." "0,1" group.byte 0x4++0x0 line.byte 0x0 "UART4_IER_IRDA" bitfld.byte 0x0 7. "EOF_IT,Not Defined 0 | EOF_IT_VALUE_0Disables the received EOF interrupt. 1 | EOF_IT_VALUE_1Enables the received EOF interrupt." "0,1" newline bitfld.byte 0x0 6. "LINE_STS_IT,Not Defined 0 | LINE_STS_IT_VALUE_0Disables the receiver line status interrupt. 1 | LINE_STS_IT_VALUE_1Enables the receiver line status interrupt." "0,1" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined 0 | TX_STATUS_IT_VALUE_0Disables the TX status interrupt. 1 | TX_STATUS_IT_VALUE_1Enables the TX status interrupt." "0,1" newline bitfld.byte 0x0 4. "STS_FIFO_TRIG_IT,Not Defined 0 | STS_FIFO_TRIG_IT_VALUE_0Disables the status FIFO trigger level interrupt. 1 | STS_FIFO_TRIG_IT_VALUE_1Enables the status FIFO trigger level interrupt." "0,1" newline bitfld.byte 0x0 3. "RX_OVERRUN_IT,Not Defined 0 | RX_OVERRUN_IT_VALUE_0Disables the RX overrun interrupt. 1 | RX_OVERRUN_IT_VALUE_1Enables the RX overrun interrupt." "0,1" newline bitfld.byte 0x0 2. "LAST_RX_BYTE_IT,Not Defined 0 | LAST_RX_BYTE_IT_VALUE_0Disables the last byte of frame in RX FIFO interrupt. 1 | LAST_RX_BYTE_IT_VALUE_1Enables the last byte of frame in RX FIFO interrupt." "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt. 1 | THR_IT_VALUE_1Enables the THR interrupt." "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt." "0,1" group.long 0x4++0x3 line.long 0x0 "UART4_IER_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "CTS_IT,Not Defined 0 | CTS_IT_VALUE_0Disables the CTS* interrupt 1 | CTS_IT_VALUE_1Enables the CTS* interrupt" "0,1" newline bitfld.long 0x0 6. "RTS_IT,Not Defined 0 | RTS_IT_VALUE_0Disables the RTS* interrupt 1 | RTS_IT_VALUE_1Enables the RTS* interrupt" "0,1" newline bitfld.long 0x0 5. "XOFF_IT,Not Defined 0 | XOFF_IT_VALUE_0Disables the XOFF interrupt 1 | XOFF_IT_VALUE_1Enables the XOFF interrupt" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE,Not Defined 0 | SLEEP_MODE_VALUE_0Disables sleep mode 1 | SLEEP_MODE_VALUE_1Enables sleep mode (stop baud rate clock when the module is inactive)" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT,Not Defined 0 | MODEM_STS_IT_VALUE_0Disables the modem status register interrupt 1 | MODEM_STS_IT_VALUE_1Enables the modem status register interrupt" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT,Not Defined 0 | LINE_STS_IT_U_VALUE_0Disables the receiver line status interrupt 1 | LINE_STS_IT_U_VALUE_1Enables the receiver line status interrupt" "0,1" newline bitfld.long 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt 1 | THR_IT_VALUE_1Enables the THR interrupt" "0,1" newline bitfld.long 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt and time out interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt and time out interrupt." "0,1" group.byte 0x8++0x0 line.byte 0x0 "UART4_EFR" bitfld.byte 0x0 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.byte 0x0 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.byte 0x0 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.byte 0x0 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.byte 0x0 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" group.long 0x8++0x3 line.long 0x0 "UART4_FCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO:If SCR[7] = 0 and TLR[7:4] = 0000:00: 8 characters01: 16 characters10: 56 characters11: 60 charactersIf SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered.If SCR[7]=1 RX_FIFO_TRIG is 2.." "0: 8 characters01: 16 characters10: 56..,?,?,?" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO:If SCR[6] = 0 and TLR[3:0] = 0000:00: 8 spaces01: 16 spaces10: 32 spaces11: 56 spacesIf SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered.If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of the.." "0: 8 spaces01: 16 spaces10: 32 spaces11: 56..,?,?,?" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0. Write0 | DMA_MODE_VALUE_0DMA_MODE 0 (No DMA) Write1 | DMA_MODE_VALUE_1DMA_MODE 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR,Not Defined Write0 | TX_FIFO_CLEAR_VALUE_0No change Write1 | TX_FIFO_CLEAR_VALUE_1Clears the transmit FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR,Not Defined Write0 | RX_FIFO_CLEAR_VALUE_0No change Write1 | RX_FIFO_CLEAR_VALUE_1Clears the receive FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 0. "FIFO_EN,Not Defined Write0 | FIFO_EN_VALUE_0Disables the transmit and receive FIFOs. The transmit and receive holding registers are one byte FIFOs. Write1 | FIFO_EN_VALUE_1: Enables the transmit and receive FIFOs.The transmit and receive.." "0,1" rgroup.byte 0x8++0x0 line.byte 0x0 "UART4_IIR_CIR" bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined Read0 | TX_STATUS_IT_VALUE_0TX status interrupt inactive Read1 | TX_STATUS_IT_VALUE_1TX status interrupt active" "0,1" newline bitfld.byte 0x0 3. "RX_OE_IT,Not Defined Read0 | RX_OE_IT_VALUE_0RX overrun interrupt inactive Read1 | RX_OE_IT_VALUE_1RX overrun interrupt active" "0,1" newline bitfld.byte 0x0 2. "RX_STOP_IT,Not Defined Read0 | RX_STOP_IT_VALUE_0Receive stop interrupt inactive Read1 | RX_STOP_IT_VALUE_1Receive stop interrupt active" "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined Read0 | THR_IT_VALUE_0THR interrupt inactive Read1 | THR_IT_VALUE_1THR interrupt active" "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined Read0 | RHR_IT_VALUE_0RHR interrupt inactive Read1 | RHR_IT_VALUE_1RHR interrupt active" "0,1" rgroup.byte 0x8++0x0 line.byte 0x0 "UART4_IIR_IRDA" bitfld.byte 0x0 7. "EOF_IT,Not Defined Read0 | EOF_IT_VALUE_0Received EOF interrupt inactive Read1 | EOF_IT_VALUE_1Received EOF interrupt active" "0,1" newline bitfld.byte 0x0 6. "LINE_STS_IT,Not Defined Read0 | LINE_STS_IT_VALUE_0Receiver line status interrupt inactive Read1 | LINE_STS_IT_VALUE_1Receiver line status interrupt active" "0,1" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined Read0 | TX_STATUS_IT_VALUE_0TX status interrupt inactive Read1 | TX_STATUS_IT_VALUE_1TX status interrupt active" "0,1" newline bitfld.byte 0x0 4. "STS_FIFO_IT,Not Defined Read0 | STS_FIFO_IT_VALUE_0Status FIFO trigger level interrupt inactive Read1 | STS_FIFO_IT_VALUE_1Status FIFO trigger level interrupt active" "0,1" newline bitfld.byte 0x0 3. "RX_OE_IT,Not Defined Read0 | RX_OE_IT_VALUE_0RX overrun interrupt inactive Read1 | RX_OE_IT_VALUE_1RX overrun interrupt active" "0,1" newline bitfld.byte 0x0 2. "RX_FIFO_LAST_BYTE_IT,Not Defined Read0 | RX_FIFO_LAST_BYTE_IT_VALUE_0Last byte of frame in RX FIFO interrupt inactive Read1 | RX_FIFO_LAST_BYTE_IT_VALUE_1Last byte of frame in RX FIFO interrupt active" "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined Read0 | THR_IT_VALUE_0THR interrupt inactive Read1 | THR_IT_VALUE_1THR interrupt active" "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined Read0 | RHR_IT_VALUE_0RHR interrupt inactive Read1 | RHR_IT_VALUE_1RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART4_IIR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Not Defined Read0x00 | IT_TYPE_VALUE_0Modem Interrupt. Priority=4 Read0x01 | IT_TYPE_VALUE_1THR interrupt. Priority=3 Read0x02 | IT_TYPE_VALUE_2RHR interrupt. Priority=2 Read0x03 | IT_TYPE_VALUE_3Receiver line.." newline bitfld.long 0x0 0. "IT_PENDING,Not Defined Read0 | IT_PENDING_VALUE_0An interrupt is pending Read1 | IT_PENDING_VALUE_1No interrupt is pending" "0,1" group.long 0xC++0x3 line.long 0x0 "UART4_LCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "DIV_EN,Not Defined 0 | DIV_EN_VALUE_0Normal operating condition 1 | DIV_EN_VALUE_1Divisor latch enable. Allows to access to DLL DLH and other registers (refer to the registers mapping)" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit. 0 | BREAK_EN_VALUE_0Normal operating condition. 1 | BREAK_EN_VALUE_1Forces the transmitter output to go low to alert the communication terminal" "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1,Not Defined 0 | PARITY_TYPE1_VALUE_0Odd parity is generated (if LCR[3] = 1) 1 | PARITY_TYPE1_VALUE_1Even parity is generated (if LCR[3] = 1)" "0,1" newline bitfld.long 0x0 3. "PARITY_EN,Not Defined 0 | PARITY_EN_VALUE_0No parity 1 | PARITY_EN_VALUE_1A parity bit is generated during transmission and the receiver checks for received parity." "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits: 0 | NB_STOP_VALUE_01 stop bits (word length = 5 6 7 8) 1 | NB_STOP_VALUE_11.5 stop bits (word length = 5) in USART mode. 2 stop bits (word length = 6 7 8)" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received. 0x0 | CHAR_LENGTH_VALUE_05 bits 0x1 | CHAR_LENGTH_VALUE_16 bits 0x2 | CHAR_LENGTH_VALUE_27 bits 0x3 | CHAR_LENGTH_VALUE_38 bits" "0,1,2,3" group.byte 0x10++0x0 line.byte 0x0 "UART4_XON1_ADDR1" hexmask.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." group.long 0x10++0x3 line.long 0x0 "UART4_MCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 7. "RESERVED,Not Defined" "0,1" newline bitfld.long 0x0 6. "TCR_TLR,Not Defined 0 | TCR_TLR_VALUE_0No action 1 | TCR_TLR_VALUE_1Enables access to the TCR and TLR registers." "0,1" newline bitfld.long 0x0 5. "XON_EN,Not Defined 0 | XON_EN_VALUE_0Disable 'XON any' function 1 | XON_EN_VALUE_1Enable 'XON any' function" "0,1" newline bitfld.long 0x0 4. "LOOPBACK_EN,Not Defined 0 | LOOPBACK_EN_VALUE_0Normal operating mode 1 | LOOPBACK_EN_VALUE_1Enable local loopback mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4]. The transmit output is looped back to the.." "0,1" newline bitfld.long 0x0 3. "CD_STS_CH,Not Defined 0 | CD_STS_CH_VALUE_0In loopback forces DCD* input high and IRQ outputs to inactive state. 1 | CD_STS_CH_VALUE_1In loopback forces DCD* input low and IRQ outputs to inactive state." "0,1" newline bitfld.long 0x0 2. "RI_STS_CH,Not Defined 0 | RI_STS_CH_VALUE_0In loopback forces RI* input high. 1 | RI_STS_CH_VALUE_1In loopback forces RI* input low." "0,1" newline bitfld.long 0x0 1. "RTS,In loop back controls MSR[4].If auto-RTS is enabled the RTS* output is controlled by hardware flow control. 0 | RTS_VALUE_0Force RTS* output to inactive (high). 1 | RTS_VALUE_1Force RTS* output to active (low)." "0,1" newline bitfld.long 0x0 0. "DTR,Not Defined 0 | DTR_VALUE_0Force DTR* output to inactive (high). 1 | DTR_VALUE_1Force DTR* output to active (low)." "0,1" group.byte 0x14++0x0 line.byte 0x0 "UART4_XON2_ADDR2" hexmask.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.byte 0x14++0x0 line.byte 0x0 "UART4_LSR_CIR" bitfld.byte 0x0 7. "THR_EMPTY,Not Defined Read0 | THR_EMPTY_VALUE_0Transmit holding register (TX FIFO) is not empty Read1 | THR_EMPTY_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.byte 0x0 6. "RESERVED,Not Defined" "0,1" newline bitfld.byte 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register Read0 | RX_STOP_VALUE_0Reception is on going or waiting for a new frame Read1 |.." "0,1" newline bitfld.byte 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" rgroup.byte 0x14++0x0 line.byte 0x0 "UART4_LSR_IRDA" bitfld.byte 0x0 7. "THR_EMPTY,Not Defined Read0 | THR_EMPTY_VALUE_0Transmit holding register (TX FIFO) is not empty Read1 | THR_EMPTY_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.byte 0x0 6. "STS_FIFO_FULL,Not Defined Read0 | STS_FIFO_FULL_VALUE_0Status FIFO not full Read1 | STS_FIFO_FULL_VALUE_1Status FIFO full" "0,1" newline bitfld.byte 0x0 5. "RX_LAST_BYTE,Not Defined Read0 | RX_LAST_BYTE_VALUE_0The RX FIFO (RHR) does not contain the last byte of the frame to be read Read1 | RX_LAST_BYTE_VALUE_1The RX FIFO (RHR) contains the last byte of the frame to be read.This bit is only.." "0,1" newline bitfld.byte 0x0 4. "FRAME_TOO_LONG,Not Defined Read0 | FRAME_TOO_LONG_VALUE_0No frame-too-long error in frame Read1 | FRAME_TOO_LONG_VALUE_1Frame-too-long error in the frame at the top of the STATUS FIFO [next character to be read]. This bit is set to 1.." "0,1" newline bitfld.byte 0x0 3. "ABORT,Not Defined Read0 | ABORT_VALUE_0No abort pattern error in frame Read1 | ABORT_VALUE_1Abort pattern is received. SIR MIR: Abort pattern. FIR: Illegal symbol" "0,1" newline bitfld.byte 0x0 2. "CRC,Not Defined Read0 | CRC_VALUE_0No CRC error in frame Read1 | CRC_VALUE_1CRC error in the frame at the top of the STATUS FIFO (next character to be read)" "0,1" newline bitfld.byte 0x0 1. "STS_FIFO_E,Not Defined Read0 | STS_FIFO_E_VALUE_0Status FIFO not empty Read1 | STS_FIFO_E_VALUE_1Status FIFO empty" "0,1" newline bitfld.byte 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART4_LSR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "RX_FIFO_STS,Not Defined Read0 | RX_FIFO_STS_VALUE_0Normal operation Read1 | RX_FIFO_STS_VALUE_1At least one parity error framing error or break indication in the RX FIFO. Bit 7 is cleared when no more errors are present in the RX FIFO." "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Not Defined Read0 | TX_SR_E_VALUE_0Transmitter hold (TX FIFO) and shift registers are not empty. Read1 | TX_SR_E_VALUE_1Transmitter hold (TX FIFO) and shift registers are empty" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E,Not Defined Read0 | TX_FIFO_E_VALUE_0Transmit hold register (TX FIFO) is not empty Read1 | TX_FIFO_E_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed." "0,1" newline bitfld.long 0x0 4. "RX_BI,Not Defined Read0 | RX_BI_VALUE_0No break condition Read1 | RX_BI_VALUE_1A break was detected while the data being read from the RX FIFO was being received. (i.e. RX input was low for one character + 1 bit time frame)." "0,1" newline bitfld.long 0x0 3. "RX_FE,Not Defined Read0 | RX_FE_VALUE_0No framing error in data being read from RX FIFO. Read1 | RX_FE_VALUE_1Framing error occurred in data being read from RX FIFO.(received data did not have a valid stop bit)" "0,1" newline bitfld.long 0x0 2. "RX_PE,Not Defined Read0 | RX_PE_VALUE_0No parity error in data being read from RX FIFO. Read1 | RX_PE_VALUE_1Parity error in data being read from RX FIFO" "0,1" newline bitfld.long 0x0 1. "RX_OE,Not Defined Read0 | RX_OE_VALUE_0No overrun error Read1 | RX_OE_VALUE_1Overrun error has occurred. Set when the character held in the receive shift register is not transferred to the RX FIFO. This case can occurs only when receive.." "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" group.byte 0x18++0x0 line.byte 0x0 "UART4_TCR" hexmask.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.byte 0x18++0x0 line.byte 0x0 "UART4_XOFF1" hexmask.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." rgroup.long 0x18++0x3 line.long 0x0 "UART4_MSR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS,Not Defined Read1 | DSR_STS_VALUE_1Indicates that DSR* input (or MCR[0] in loop back) has changed state. Cleared on a read" "0,1" newline bitfld.long 0x0 0. "CTS_STS,Not Defined Read1 | CTS_STS_VALUE_1Indicates that CTS* input (or MCR[1] in loop back) has changed state. Cleared on a read." "0,1" group.byte 0x1C++0x0 line.byte 0x0 "UART4_TLR" hexmask.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.byte 0x1C++0x0 line.byte 0x0 "UART4_XOFF2" hexmask.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." group.long 0x1C++0xF line.long 0x0 "UART4_SPR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "SPR_WORD,Scratchpad register" line.long 0x4 "UART4_MDR1" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only. 0 | FRAME_END_MODE_VALUE_0Frame-length method 1 | FRAME_END_MODE_VALUE_1Set EOT bit method" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only. 0 | SIP_MODE_VALUE_0Manual SIP mode: SIP is generated with the control of ACREG[3] 1 | SIP_MODE_VALUE_1Automatic SIP mode: SIP is generated after each transmission." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission 0 | SCT_VALUE_0Starts the Infrared transmission as soon as a value is written to THR 1 | SCT_VALUE_1Starts the Infrared transmission with the control of ACREG[2]. Note: before starting any.." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver. 0 | SET_TXIR_VALUE_0No action if MDR2[7]=0. TXIR pin output is forced low if MDR2[7]=1 1 | SET_TXIR_VALUE_1TXIR pin output is forced high (not dependant of MDR2[7] value)." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP,Not Defined 0 | IR_SLEEP_VALUE_0IrDA/CIR sleep mode disabled 1 | IR_SLEEP_VALUE_1IrDA/CIR sleep mode enabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,Not Defined 0x0 | MODE_SELECT_VALUE_0UART 16x mode 0x1 | MODE_SELECT_VALUE_1SIR mode 0x2 | MODE_SELECT_VALUE_2UART 16x auto-baud 0x3 | MODE_SELECT_VALUE_3UART 13x mode 0x4 | MODE_SELECT_VALUE_4MIR.." "0,1,2,3,4,5,6,7" line.long 0x8 "UART4_MDR2" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR] 0 | SET_TXIR_ALT_VALUE_0Normal mode 1 | SET_TXIR_ALT_VALUE_1Alternate mode for SET_TXIR" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes. 0 | IRRXINVERT_VALUE_0inversion is performed 1.." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit: 0x0 | CIR_PULSE_MODE_VALUE_0Pulse width of 3 from 12 cycles 0x1 | CIR_PULSE_MODE_VALUE_1Pulse width of 4 from 12 cycles.." "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode. 0 | UART_PULSE_VALUE_0normal UART mode 1 | UART_PULSE_VALUE_1UART mode with a pulse shaping" "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode.Frame Status FIFO Threshold select: 0x0 | STS_FIFO_TRIG_VALUE_01 entry 0x1 | STS_FIFO_TRIG_VALUE_14 entries 0x2 | STS_FIFO_TRIG_VALUE_27 entries 0x3 | STS_FIFO_TRIG_VALUE_38 entries" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is : Read0 | IRTX_UNDERRUN_VALUE_0the last bit of the frame has been transmitted successfully without error. Read1 |.." "0,1" line.long 0xC "UART4_TXFLL" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0xC 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x28++0x3 line.long 0x0 "UART4_SFLSR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 5.--7. "RESERVED5,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Not Defined Read1 | OE_ERROR_VALUE_1Overrun error in RX FIFO when frame at top of RX FIFO was received." "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Not Defined Read1 | FRAME_TOO_LONG_ERROR_VALUE_1Frame-length too long error in frame at top of RX FIFO." "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Not Defined Read1 | ABORT_DETECT_VALUE_1Abort pattern detected in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR,Not Defined Read1 | CRC_ERROR_VALUE_1CRC error in frame at top of RX FIFO. top of RX FIFO = Next frame to be read from RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED0,Not Defined" "0,1" group.long 0x2C++0x3 line.long 0x0 "UART4_TXFLH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 5.--7. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART4_RESUME" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x30++0x3 line.long 0x0 "UART4_RXFLL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART4_SFREGL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART4_RXFLH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART4_SFREGH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.byte 0x38++0x0 line.byte 0x0 "UART4_UASR" bitfld.byte 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.byte 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." group.long 0x38++0x13 line.long 0x0 "UART4_BLR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select. 0 | XBOF_TYPE_VALUE_00xFF 1 | XBOF_TYPE_VALUE_10xC0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED,Not Defined" line.long 0x4 "UART4_ACREG" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 7. "PULSE_TYPE,SIR pulse width select: 0 | PULSE_TYPE_VALUE_03/16 of baud-rate pulse width 1 | PULSE_TYPE_VALUE_11.6us" "0,1" newline bitfld.long 0x4 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. 0 | SD_MOD_VALUE_0SD pin is set to high 1 | SD_MOD_VALUE_1SD pin is set to low" "0,1" newline bitfld.long 0x4 5. "DIS_IR_RX,Not Defined 0 | DIS_IR_RX_VALUE_0Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation). 1 | DIS_IR_RX_VALUE_1Disables RX input (permanent state - independent of transmit)." "0,1" newline bitfld.long 0x4 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line. 0 | DIS_TX_UNDERRUN_VALUE_0Long stop bits.." "0,1" newline bitfld.long 0x4 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP]If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission. 0 |.." "0,1" newline bitfld.long 0x4 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x4 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x4 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x8 "UART4_SCR" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x8 7. "RX_TRIG_GRANU1,Not Defined 0 | RX_TRIG_GRANU1_VALUE_0DISABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL. 1 | RX_TRIG_GRANU1_VALUE_1ENABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL." "0,1" newline bitfld.long 0x8 6. "TX_TRIG_GRANU1,Not Defined 0 | TX_TRIG_GRANU1_VALUE_0DISABLES THE GRANULARITY OF 1 FOR TRIGGER TX LEVEL. 1 | TX_TRIG_GRANU1_VALUE_1Enables the granularity of 1 for trigger TX level." "0,1" newline bitfld.long 0x8 5. "DSR_IT,Not Defined 0 | DSR_IT_VALUE_0DISABLES DSR* INTERRUPT. 1 | DSR_IT_VALUE_1ENABLES DSR* INTERRUPT." "0,1" newline bitfld.long 0x8 4. "RX_CTS_DSR_WAKE_UP_ENABLE,Not Defined 0 | RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_0DISABLES THE WAKE UP INTERRUPT AND CLEARS SSR[1]. 1 | RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_1Waits for a falling edge of pins RX CTS* or DSR* to generate an interrupt" "0,1" newline bitfld.long 0x8 3. "TX_EMPTY_CTL_IT,Not Defined 0 | TX_EMPTY_CTL_IT_VALUE_0Normal mode for THR interrupt (See UART mode interrupts table). 1 | TX_EMPTY_CTL_IT_VALUE_1THE THR INTERRUPT IS GENERATED WHEN TX FIFO AND TX SHIFT REGISTER ARE EMPTY." "0,1" newline bitfld.long 0x8 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1 0x0 | DMA_MODE_2_VALUE_0DMA mode 0 (no DMA) 0x1 | DMA_MODE_2_VALUE_1DMA mode 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX) 0x2 | DMA_MODE_2_VALUE_2DMA mode 2.." "0,1,2,3" newline bitfld.long 0x8 0. "DMA_MODE_CTL,Not Defined 0 | DMA_MODE_CTL_VALUE_0The DMA_MODE is set with FCR[3] 1 | DMA_MODE_CTL_VALUE_1The DMA_MODE is set with SCR[2:1]" "0,1" line.long 0xC "UART4_SSR" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0xC 3.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0xC 2. "DMA_COUNTER_RST,Not Defined 0 | DMA_COUNTER_RST_VALUE_0The DMA counter will not be reset if the corresponding FIFO is reset (via FCR[1] or FCR[2]) 1 | DMA_COUNTER_RST_VALUE_1The DMA counter will be reset if corresponding FIFO is reset.." "0,1" newline rbitfld.long 0xC 1. "RX_CTS_DSR_WAKE_UP_STS,Not Defined Read0 | RX_CTS_DSR_WAKE_UP_STS_VALUE_0No falling edge event on RX CTS* and DSR* Read1 | RX_CTS_DSR_WAKE_UP_STS_VALUE_1A falling edge occurred on RX CTS* or DSR*" "0,1" newline rbitfld.long 0xC 0. "TX_FIFO_FULL,Not Defined Read0 | TX_FIFO_FULL_VALUE_0TX FIFO is not full Read1 | TX_FIFO_FULL_VALUE_1TX FIFO is full." "0,1" line.long 0x10 "UART4_EBLR" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x10 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification.IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]].0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "UART4_MVR" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED,Not Defined" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "UART4_SYSC" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 5.--7. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROLREF: OCP DESIGN GUIDELINES VERSION 1.1 0x0 | IDLEMODE_VALUE_0Force idle. An idle request is acknowledged unconditionally 0x1 | IDLEMODE_VALUE_1No-idle. An idle request is never acknowledged." "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL 0 | ENAWAKEUP_VALUE_0Wake up is disabled 1 | ENAWAKEUP_VALUE_1Wake up capability is enabled" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0. Write0 | SOFTRESET_VALUE_0Normal mode Write1 | SOFTRESET_VALUE_1The module is reset" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy 0 | AUTOIDLE_VALUE_0Clock is running 1 | AUTOIDLE_VALUE_1Automatic OCP clock gating strategy is applied based on the OCP interface activity" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART4_SYSS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring Read0 | RESETDONE_VALUE_0Internal Module Reset is ongoing Read1 | RESETDONE_VALUE_1Reset completed" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART4_WER" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,Not Defined 0 | EVENT_7_TX_WAKEUP_EN_VALUE_0Event is not allowed to wake up the system 1 | EVENT_7_TX_WAKEUP_EN_VALUE_1EVENT CAN WAKE UP THE SYSTEM: Event can be: THR_IT or TX_DMA request and/or TX_SATUS_IT" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,Not Defined 0 | EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_VALUE_0Event is not allowed to wake up the system 1 | EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,Not Defined 0 | EVENT_5_RHR_INTERRUPT_VALUE_0Event is not allowed to wake up the system 1 | EVENT_5_RHR_INTERRUPT_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,Not Defined 0 | EVENT_4_RX_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_4_RX_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,Not Defined 0 | EVENT_3_DCD_CD_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_3_DCD_CD_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,Not Defined 0 | EVENT_2_RI_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_2_RI_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,Not Defined 0 | EVENT_1_DSR_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_1_DSR_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,Not Defined 0 | EVENT_0_CTS_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_0_CTS_ACTIVITY_VALUE_1Event can wake up the system" "0,1" line.long 0x4 "UART4_CFPS" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below.Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1 40 100.." rgroup.long 0x64++0x7 line.long 0x0 "UART4_RXFIFO_LVL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Not Defined" line.long 0x4 "UART4_TXFIFO_LVL" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24,Not Defined" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Not Defined" group.long 0x6C++0xB line.long 0x0 "UART4_IER2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 2. "RHR_IT_DIS,Not Defined 0 | RHR_IT_DIS_VALUE_0Enables the RHR interrupt. 1 | RHR_IT_DIS_VALUE_1Disables the RHR interrupt." "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "UART4_ISR2" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending 0 | TXFIFO_EMPTY_STS_VALUE_0TXFIFO_EMPTY interrupt not pending. 1 | TXFIFO_EMPTY_STS_VALUE_1TXFIFO_EMPTY interrupt pending." "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending 0 | RXFIFO_EMPTY_STS_VALUE_0RXFIFO_EMPTY interrupt not pending. 1 | RXFIFO_EMPTY_STS_VALUE_1RXFIFO_EMPTY interrupt pending." "0,1" line.long 0x8 "UART4_FREQ_SEL" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "UART4_ABAUD_1ST_CHAR" hexmask.long 0x0 0.--31. 1. "RESERVED,Not Defined" line.long 0x4 "UART4_BAUD_2ND_CHAR" hexmask.long 0x4 0.--31. 1. "RESERVED,Not Defined" group.long 0x80++0x27 line.long 0x0 "UART4_MDR3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2,Not Defined" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation 0 | DISABLE_CIR_RX_DEMOD_VALUE_0Enables CIR RX demodulation 1 | DISABLE_CIR_RX_DEMOD_VALUE_1Disables CIR RX demodulation" "0,1" line.long 0x4 "UART4_TX_DMA_THRESHOLD" hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "UART4_MDR4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,Not Defined" newline rbitfld.long 0x8 7. "RESERVED,Not Defined" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes] 0x0 | DISABLEDdisabled (no override) 0x1 | RESERVEDreserved 0x2 | SYNCH_EXTSynchronous mode with external clock 0x3 | SYNCH_GENSynchronous mode with generated clock.." "0,1,2,3,4,5,6,7" line.long 0xC "UART4_EFR2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1,Not Defined" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured 0 | _0timeout after at least one character has been received 1 | _1periodic timeout even when no character has been received" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full 0 | DEFAULTdata in RHR is not overwritten (standard) 1 | ATMELdata in RHR is overwritten when buffer full (and FIFO disabled)" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness 0 | LOW_ENDIANLittle Endian (LSB First) 1 | BIG_ENDIANBig Endian (MSB First)" "0,1" line.long 0x10 "UART4_ECR" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1,Not Defined" newline rbitfld.long 0x10 6.--7. "RESERVED,Not Defined" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter 0 | DISABLEDTransmitter is shut down 1 | ENABLEDTransmitter is working" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver 0 | DISABLEDReceiver is shut down 1 | ENABLEDReceiver is operating" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "UART4_TIMEGUARD" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART4_TIMEOUTL" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "UART4_TIMEOUTH" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "UART4_SCCR" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,Not Defined" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" line.long 0x24 "UART4_ETHR" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED,Not Defined" newline hexmask.long.word 0x24 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" rgroup.long 0xA4++0x3 line.long 0x0 "UART4_ERHR" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Not Defined" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.byte 0xA8++0x0 line.byte 0x0 "UART4_MAR" hexmask.byte 0x0 0.--7. 1. "ADDRESS,Multidrop match address value" group.byte 0xAC++0x0 line.byte 0x0 "UART4_MMR" hexmask.byte 0x0 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" group.byte 0xB0++0x0 line.byte 0x0 "UART4_MBR" hexmask.byte 0x0 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree "UART5" base ad:0x52305000 group.byte 0x0++0x0 line.byte 0x0 "UART5_DLL" hexmask.byte 0x0 0.--7. 1. "CLOCK_LSB,Used to store the 8-bit LSB divisor value" rgroup.long 0x0++0x3 line.long 0x0 "UART5_RHR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RHR,Receive holding register" group.long 0x0++0x3 line.long 0x0 "UART5_THR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "THR,TRANSMIT HOLDING REGISTER" group.byte 0x4++0x0 line.byte 0x0 "UART5_DLH" hexmask.byte 0x0 0.--7. 1. "CLOCK_MSB,Used to store the 8-bit MSB divisor value" group.byte 0x4++0x0 line.byte 0x0 "UART5_IER_CIR" bitfld.byte 0x0 6.--7. "NOT_USED2,Not Defined" "0,1,2,3" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined 0 | TX_STATUS_IT_VALUE_0Disables the TX status interrupt. 1 | TX_STATUS_IT_VALUE_1Enables the TX status interrupt." "0,1" newline bitfld.byte 0x0 4. "NOT_USED1,Not Defined" "0,1" newline bitfld.byte 0x0 3. "RX_OVERRUN_IT,Not Defined 0 | RX_OVERRUN_IT_VALUE_0Disables the RX overrun interrupt. 1 | RX_OVERRUN_IT_VALUE_1Enables the RX overrun interrupt." "0,1" newline bitfld.byte 0x0 2. "RX_STOP_IT,Not Defined 0 | RX_STOP_IT_VALUE_0Disables the receive stop interrupt. 1 | RX_STOP_IT_VALUE_1Enables the receive stop interrupt." "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt. 1 | THR_IT_VALUE_1Enables the THR interrupt." "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt." "0,1" group.byte 0x4++0x0 line.byte 0x0 "UART5_IER_IRDA" bitfld.byte 0x0 7. "EOF_IT,Not Defined 0 | EOF_IT_VALUE_0Disables the received EOF interrupt. 1 | EOF_IT_VALUE_1Enables the received EOF interrupt." "0,1" newline bitfld.byte 0x0 6. "LINE_STS_IT,Not Defined 0 | LINE_STS_IT_VALUE_0Disables the receiver line status interrupt. 1 | LINE_STS_IT_VALUE_1Enables the receiver line status interrupt." "0,1" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined 0 | TX_STATUS_IT_VALUE_0Disables the TX status interrupt. 1 | TX_STATUS_IT_VALUE_1Enables the TX status interrupt." "0,1" newline bitfld.byte 0x0 4. "STS_FIFO_TRIG_IT,Not Defined 0 | STS_FIFO_TRIG_IT_VALUE_0Disables the status FIFO trigger level interrupt. 1 | STS_FIFO_TRIG_IT_VALUE_1Enables the status FIFO trigger level interrupt." "0,1" newline bitfld.byte 0x0 3. "RX_OVERRUN_IT,Not Defined 0 | RX_OVERRUN_IT_VALUE_0Disables the RX overrun interrupt. 1 | RX_OVERRUN_IT_VALUE_1Enables the RX overrun interrupt." "0,1" newline bitfld.byte 0x0 2. "LAST_RX_BYTE_IT,Not Defined 0 | LAST_RX_BYTE_IT_VALUE_0Disables the last byte of frame in RX FIFO interrupt. 1 | LAST_RX_BYTE_IT_VALUE_1Enables the last byte of frame in RX FIFO interrupt." "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt. 1 | THR_IT_VALUE_1Enables the THR interrupt." "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt." "0,1" group.long 0x4++0x3 line.long 0x0 "UART5_IER_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "CTS_IT,Not Defined 0 | CTS_IT_VALUE_0Disables the CTS* interrupt 1 | CTS_IT_VALUE_1Enables the CTS* interrupt" "0,1" newline bitfld.long 0x0 6. "RTS_IT,Not Defined 0 | RTS_IT_VALUE_0Disables the RTS* interrupt 1 | RTS_IT_VALUE_1Enables the RTS* interrupt" "0,1" newline bitfld.long 0x0 5. "XOFF_IT,Not Defined 0 | XOFF_IT_VALUE_0Disables the XOFF interrupt 1 | XOFF_IT_VALUE_1Enables the XOFF interrupt" "0,1" newline bitfld.long 0x0 4. "SLEEP_MODE,Not Defined 0 | SLEEP_MODE_VALUE_0Disables sleep mode 1 | SLEEP_MODE_VALUE_1Enables sleep mode (stop baud rate clock when the module is inactive)" "0,1" newline bitfld.long 0x0 3. "MODEM_STS_IT,Not Defined 0 | MODEM_STS_IT_VALUE_0Disables the modem status register interrupt 1 | MODEM_STS_IT_VALUE_1Enables the modem status register interrupt" "0,1" newline bitfld.long 0x0 2. "LINE_STS_IT,Not Defined 0 | LINE_STS_IT_U_VALUE_0Disables the receiver line status interrupt 1 | LINE_STS_IT_U_VALUE_1Enables the receiver line status interrupt" "0,1" newline bitfld.long 0x0 1. "THR_IT,Not Defined 0 | THR_IT_VALUE_0Disables the THR interrupt 1 | THR_IT_VALUE_1Enables the THR interrupt" "0,1" newline bitfld.long 0x0 0. "RHR_IT,Not Defined 0 | RHR_IT_VALUE_0Disables the RHR interrupt and time out interrupt. 1 | RHR_IT_VALUE_1Enables the RHR interrupt and time out interrupt." "0,1" group.byte 0x8++0x0 line.byte 0x0 "UART5_EFR" bitfld.byte 0x0 7. "AUTO_CTS_EN,Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive)." "0: Normal operation,1: Auto-CTS flow control is enabled i" newline bitfld.byte 0x0 6. "AUTO_RTS_EN,Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level TCR[3:0] is reached and goes low (active) when the receiver FIFO RESTORE.." "0: Normal operation,1: Auto- RTS flow control is enabled i" newline bitfld.byte 0x0 5. "SPECIAL_CHAR_DETECT,0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been.." "0: Normal operation,1: Special character detect enable" newline bitfld.byte 0x0 4. "ENHANCED_EN,Enhanced functions write enable bit. 0: Disables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7. 1: Enables writing to IER bits 4-7 FCR bits 4-5 and MCR bits 5-7." "0: Disables writing to IER bits 4-7,1: Enables writing to IER bits 4-7" newline hexmask.byte 0x0 0.--3. 1. "SW_FLOW_CONTROL,Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options" group.long 0x8++0x3 line.long 0x0 "UART5_FCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 6.--7. "RX_FIFO_TRIG,Sets the trigger level for the RX FIFO:If SCR[7] = 0 and TLR[7:4] = 0000:00: 8 characters01: 16 characters10: 56 characters11: 60 charactersIf SCR[7] = 0 and TLR[7:4] != 0000 RX_FIFO_TRIG is not considered.If SCR[7]=1 RX_FIFO_TRIG is 2.." "0: 8 characters01: 16 characters10: 56..,?,?,?" newline bitfld.long 0x0 4.--5. "TX_FIFO_TRIG,Sets the trigger level for the TX FIFO:If SCR[6] = 0 and TLR[3:0] = 0000:00: 8 spaces01: 16 spaces10: 32 spaces11: 56 spacesIf SCR[6] = 0 and TLR[3:0] != 0000 TX_FIFO_TRIG is not considered.If SCR[6]=1 TX_FIFO_TRIG is 2 LSB of the.." "0: 8 spaces01: 16 spaces10: 32 spaces11: 56..,?,?,?" newline bitfld.long 0x0 3. "DMA_MODE,This register is considered if SCR[0] = 0. Write0 | DMA_MODE_VALUE_0DMA_MODE 0 (No DMA) Write1 | DMA_MODE_VALUE_1DMA_MODE 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX)" "0,1" newline bitfld.long 0x0 2. "TX_FIFO_CLEAR,Not Defined Write0 | TX_FIFO_CLEAR_VALUE_0No change Write1 | TX_FIFO_CLEAR_VALUE_1Clears the transmit FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 1. "RX_FIFO_CLEAR,Not Defined Write0 | RX_FIFO_CLEAR_VALUE_0No change Write1 | RX_FIFO_CLEAR_VALUE_1Clears the receive FIFO and resets its counter logic to zero. Returns to zero after clearing FIFO." "0,1" newline bitfld.long 0x0 0. "FIFO_EN,Not Defined Write0 | FIFO_EN_VALUE_0Disables the transmit and receive FIFOs. The transmit and receive holding registers are one byte FIFOs. Write1 | FIFO_EN_VALUE_1: Enables the transmit and receive FIFOs.The transmit and receive.." "0,1" rgroup.byte 0x8++0x0 line.byte 0x0 "UART5_IIR_CIR" bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined Read0 | TX_STATUS_IT_VALUE_0TX status interrupt inactive Read1 | TX_STATUS_IT_VALUE_1TX status interrupt active" "0,1" newline bitfld.byte 0x0 3. "RX_OE_IT,Not Defined Read0 | RX_OE_IT_VALUE_0RX overrun interrupt inactive Read1 | RX_OE_IT_VALUE_1RX overrun interrupt active" "0,1" newline bitfld.byte 0x0 2. "RX_STOP_IT,Not Defined Read0 | RX_STOP_IT_VALUE_0Receive stop interrupt inactive Read1 | RX_STOP_IT_VALUE_1Receive stop interrupt active" "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined Read0 | THR_IT_VALUE_0THR interrupt inactive Read1 | THR_IT_VALUE_1THR interrupt active" "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined Read0 | RHR_IT_VALUE_0RHR interrupt inactive Read1 | RHR_IT_VALUE_1RHR interrupt active" "0,1" rgroup.byte 0x8++0x0 line.byte 0x0 "UART5_IIR_IRDA" bitfld.byte 0x0 7. "EOF_IT,Not Defined Read0 | EOF_IT_VALUE_0Received EOF interrupt inactive Read1 | EOF_IT_VALUE_1Received EOF interrupt active" "0,1" newline bitfld.byte 0x0 6. "LINE_STS_IT,Not Defined Read0 | LINE_STS_IT_VALUE_0Receiver line status interrupt inactive Read1 | LINE_STS_IT_VALUE_1Receiver line status interrupt active" "0,1" newline bitfld.byte 0x0 5. "TX_STATUS_IT,Not Defined Read0 | TX_STATUS_IT_VALUE_0TX status interrupt inactive Read1 | TX_STATUS_IT_VALUE_1TX status interrupt active" "0,1" newline bitfld.byte 0x0 4. "STS_FIFO_IT,Not Defined Read0 | STS_FIFO_IT_VALUE_0Status FIFO trigger level interrupt inactive Read1 | STS_FIFO_IT_VALUE_1Status FIFO trigger level interrupt active" "0,1" newline bitfld.byte 0x0 3. "RX_OE_IT,Not Defined Read0 | RX_OE_IT_VALUE_0RX overrun interrupt inactive Read1 | RX_OE_IT_VALUE_1RX overrun interrupt active" "0,1" newline bitfld.byte 0x0 2. "RX_FIFO_LAST_BYTE_IT,Not Defined Read0 | RX_FIFO_LAST_BYTE_IT_VALUE_0Last byte of frame in RX FIFO interrupt inactive Read1 | RX_FIFO_LAST_BYTE_IT_VALUE_1Last byte of frame in RX FIFO interrupt active" "0,1" newline bitfld.byte 0x0 1. "THR_IT,Not Defined Read0 | THR_IT_VALUE_0THR interrupt inactive Read1 | THR_IT_VALUE_1THR interrupt active" "0,1" newline bitfld.byte 0x0 0. "RHR_IT,Not Defined Read0 | RHR_IT_VALUE_0RHR interrupt inactive Read1 | RHR_IT_VALUE_1RHR interrupt active" "0,1" rgroup.long 0x8++0x3 line.long 0x0 "UART5_IIR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 6.--7. "FCR_MIRROR,Mirror the contents of FCR[0] on both bits." "0,1,2,3" newline hexmask.long.byte 0x0 1.--5. 1. "IT_TYPE,Not Defined Read0x00 | IT_TYPE_VALUE_0Modem Interrupt. Priority=4 Read0x01 | IT_TYPE_VALUE_1THR interrupt. Priority=3 Read0x02 | IT_TYPE_VALUE_2RHR interrupt. Priority=2 Read0x03 | IT_TYPE_VALUE_3Receiver line.." newline bitfld.long 0x0 0. "IT_PENDING,Not Defined Read0 | IT_PENDING_VALUE_0An interrupt is pending Read1 | IT_PENDING_VALUE_1No interrupt is pending" "0,1" group.long 0xC++0x3 line.long 0x0 "UART5_LCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "DIV_EN,Not Defined 0 | DIV_EN_VALUE_0Normal operating condition 1 | DIV_EN_VALUE_1Divisor latch enable. Allows to access to DLL DLH and other registers (refer to the registers mapping)" "0,1" newline bitfld.long 0x0 6. "BREAK_EN,Break control bit. 0 | BREAK_EN_VALUE_0Normal operating condition. 1 | BREAK_EN_VALUE_1Forces the transmitter output to go low to alert the communication terminal" "0,1" newline bitfld.long 0x0 5. "PARITY_TYPE2,Selects the forced parity format [if LCR[3] = 1]. If LCR[5] = 1 and LCR[4] = 0 the parity bit is forced to 1 in the transmitted and received data. If LCR[5] = 1 and LCR[4] = 1 the parity bit is forced to 0 in the transmitted and received.." "0,1" newline bitfld.long 0x0 4. "PARITY_TYPE1,Not Defined 0 | PARITY_TYPE1_VALUE_0Odd parity is generated (if LCR[3] = 1) 1 | PARITY_TYPE1_VALUE_1Even parity is generated (if LCR[3] = 1)" "0,1" newline bitfld.long 0x0 3. "PARITY_EN,Not Defined 0 | PARITY_EN_VALUE_0No parity 1 | PARITY_EN_VALUE_1A parity bit is generated during transmission and the receiver checks for received parity." "0,1" newline bitfld.long 0x0 2. "NB_STOP,Specifies the number of stop bits: 0 | NB_STOP_VALUE_01 stop bits (word length = 5 6 7 8) 1 | NB_STOP_VALUE_11.5 stop bits (word length = 5) in USART mode. 2 stop bits (word length = 6 7 8)" "0,1" newline bitfld.long 0x0 0.--1. "CHAR_LENGTH,Specifies the word length to be transmitted or received. 0x0 | CHAR_LENGTH_VALUE_05 bits 0x1 | CHAR_LENGTH_VALUE_16 bits 0x2 | CHAR_LENGTH_VALUE_27 bits 0x3 | CHAR_LENGTH_VALUE_38 bits" "0,1,2,3" group.byte 0x10++0x0 line.byte 0x0 "UART5_XON1_ADDR1" hexmask.byte 0x0 0.--7. 1. "XON_WORD1,Used to store the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes." group.long 0x10++0x3 line.long 0x0 "UART5_MCR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 7. "RESERVED,Not Defined" "0,1" newline bitfld.long 0x0 6. "TCR_TLR,Not Defined 0 | TCR_TLR_VALUE_0No action 1 | TCR_TLR_VALUE_1Enables access to the TCR and TLR registers." "0,1" newline bitfld.long 0x0 5. "XON_EN,Not Defined 0 | XON_EN_VALUE_0Disable 'XON any' function 1 | XON_EN_VALUE_1Enable 'XON any' function" "0,1" newline bitfld.long 0x0 4. "LOOPBACK_EN,Not Defined 0 | LOOPBACK_EN_VALUE_0Normal operating mode 1 | LOOPBACK_EN_VALUE_1Enable local loopback mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4]. The transmit output is looped back to the.." "0,1" newline bitfld.long 0x0 3. "CD_STS_CH,Not Defined 0 | CD_STS_CH_VALUE_0In loopback forces DCD* input high and IRQ outputs to inactive state. 1 | CD_STS_CH_VALUE_1In loopback forces DCD* input low and IRQ outputs to inactive state." "0,1" newline bitfld.long 0x0 2. "RI_STS_CH,Not Defined 0 | RI_STS_CH_VALUE_0In loopback forces RI* input high. 1 | RI_STS_CH_VALUE_1In loopback forces RI* input low." "0,1" newline bitfld.long 0x0 1. "RTS,In loop back controls MSR[4].If auto-RTS is enabled the RTS* output is controlled by hardware flow control. 0 | RTS_VALUE_0Force RTS* output to inactive (high). 1 | RTS_VALUE_1Force RTS* output to active (low)." "0,1" newline bitfld.long 0x0 0. "DTR,Not Defined 0 | DTR_VALUE_0Force DTR* output to inactive (high). 1 | DTR_VALUE_1Force DTR* output to active (low)." "0,1" group.byte 0x14++0x0 line.byte 0x0 "UART5_XON2_ADDR2" hexmask.byte 0x0 0.--7. 1. "XON_WORD2,Used to store the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes." rgroup.byte 0x14++0x0 line.byte 0x0 "UART5_LSR_CIR" bitfld.byte 0x0 7. "THR_EMPTY,Not Defined Read0 | THR_EMPTY_VALUE_0Transmit holding register (TX FIFO) is not empty Read1 | THR_EMPTY_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.byte 0x0 6. "RESERVED,Not Defined" "0,1" newline bitfld.byte 0x0 5. "RX_STOP,The RX_STOP is generated based on the value set in the BOF Length register (EBLR). It is cleared on a single read of the LSR register Read0 | RX_STOP_VALUE_0Reception is on going or waiting for a new frame Read1 |.." "0,1" newline bitfld.byte 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" rgroup.byte 0x14++0x0 line.byte 0x0 "UART5_LSR_IRDA" bitfld.byte 0x0 7. "THR_EMPTY,Not Defined Read0 | THR_EMPTY_VALUE_0Transmit holding register (TX FIFO) is not empty Read1 | THR_EMPTY_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed" "0,1" newline bitfld.byte 0x0 6. "STS_FIFO_FULL,Not Defined Read0 | STS_FIFO_FULL_VALUE_0Status FIFO not full Read1 | STS_FIFO_FULL_VALUE_1Status FIFO full" "0,1" newline bitfld.byte 0x0 5. "RX_LAST_BYTE,Not Defined Read0 | RX_LAST_BYTE_VALUE_0The RX FIFO (RHR) does not contain the last byte of the frame to be read Read1 | RX_LAST_BYTE_VALUE_1The RX FIFO (RHR) contains the last byte of the frame to be read.This bit is only.." "0,1" newline bitfld.byte 0x0 4. "FRAME_TOO_LONG,Not Defined Read0 | FRAME_TOO_LONG_VALUE_0No frame-too-long error in frame Read1 | FRAME_TOO_LONG_VALUE_1Frame-too-long error in the frame at the top of the STATUS FIFO [next character to be read]. This bit is set to 1.." "0,1" newline bitfld.byte 0x0 3. "ABORT,Not Defined Read0 | ABORT_VALUE_0No abort pattern error in frame Read1 | ABORT_VALUE_1Abort pattern is received. SIR MIR: Abort pattern. FIR: Illegal symbol" "0,1" newline bitfld.byte 0x0 2. "CRC,Not Defined Read0 | CRC_VALUE_0No CRC error in frame Read1 | CRC_VALUE_1CRC error in the frame at the top of the STATUS FIFO (next character to be read)" "0,1" newline bitfld.byte 0x0 1. "STS_FIFO_E,Not Defined Read0 | STS_FIFO_E_VALUE_0Status FIFO not empty Read1 | STS_FIFO_E_VALUE_1Status FIFO empty" "0,1" newline bitfld.byte 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" rgroup.long 0x14++0x3 line.long 0x0 "UART5_LSR_UART" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "RX_FIFO_STS,Not Defined Read0 | RX_FIFO_STS_VALUE_0Normal operation Read1 | RX_FIFO_STS_VALUE_1At least one parity error framing error or break indication in the RX FIFO. Bit 7 is cleared when no more errors are present in the RX FIFO." "0,1" newline bitfld.long 0x0 6. "TX_SR_E,Not Defined Read0 | TX_SR_E_VALUE_0Transmitter hold (TX FIFO) and shift registers are not empty. Read1 | TX_SR_E_VALUE_1Transmitter hold (TX FIFO) and shift registers are empty" "0,1" newline bitfld.long 0x0 5. "TX_FIFO_E,Not Defined Read0 | TX_FIFO_E_VALUE_0Transmit hold register (TX FIFO) is not empty Read1 | TX_FIFO_E_VALUE_1Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed." "0,1" newline bitfld.long 0x0 4. "RX_BI,Not Defined Read0 | RX_BI_VALUE_0No break condition Read1 | RX_BI_VALUE_1A break was detected while the data being read from the RX FIFO was being received. (i.e. RX input was low for one character + 1 bit time frame)." "0,1" newline bitfld.long 0x0 3. "RX_FE,Not Defined Read0 | RX_FE_VALUE_0No framing error in data being read from RX FIFO. Read1 | RX_FE_VALUE_1Framing error occurred in data being read from RX FIFO.(received data did not have a valid stop bit)" "0,1" newline bitfld.long 0x0 2. "RX_PE,Not Defined Read0 | RX_PE_VALUE_0No parity error in data being read from RX FIFO. Read1 | RX_PE_VALUE_1Parity error in data being read from RX FIFO" "0,1" newline bitfld.long 0x0 1. "RX_OE,Not Defined Read0 | RX_OE_VALUE_0No overrun error Read1 | RX_OE_VALUE_1Overrun error has occurred. Set when the character held in the receive shift register is not transferred to the RX FIFO. This case can occurs only when receive.." "0,1" newline bitfld.long 0x0 0. "RX_FIFO_E,Not Defined Read0 | RX_FIFO_E_VALUE_0No data in the receive FIFO Read1 | RX_FIFO_E_VALUE_1At least one data character in the RX FIFO" "0,1" group.byte 0x18++0x0 line.byte 0x0 "UART5_TCR" hexmask.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_START,RX FIFO trigger level to RESTORE transmission (0 - 60)" newline hexmask.byte 0x0 0.--3. 1. "RX_FIFO_TRIG_HALT,RX FIFO trigger level to HALT transmission (0 - 60)" group.byte 0x18++0x0 line.byte 0x0 "UART5_XOFF1" hexmask.byte 0x0 0.--7. 1. "XOFF_WORD1,Used to store the 8-bit XOFF1 character in used in UART modes." rgroup.long 0x18++0x3 line.long 0x0 "UART5_MSR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "NCD_STS,This bit is the complement of the DCD* input. In loop-back mode it is equivalent to MCR[3]" "0,1" newline bitfld.long 0x0 6. "NRI_STS,This bit is the complement of the RI* input. In loop-back mode it is equivalent to MCR[2]" "0,1" newline bitfld.long 0x0 5. "NDSR_STS,This bit is the complement of the DSR* input. In loop-back mode it is equivalent to MCR[0]" "0,1" newline bitfld.long 0x0 4. "NCTS_STS,This bit is the complement of the CTS* input. In loop-back mode it is equivalent to MCR[1]" "0,1" newline bitfld.long 0x0 3. "DCD_STS,Indicates that DCD* input [or MCR[3] in loop back] has changed. Cleared on a read." "0,1" newline bitfld.long 0x0 2. "RI_STS,Indicates that RI* input [or MCR[2] in loop back] has changed state from low to high. Cleared on a read." "0,1" newline bitfld.long 0x0 1. "DSR_STS,Not Defined Read1 | DSR_STS_VALUE_1Indicates that DSR* input (or MCR[0] in loop back) has changed state. Cleared on a read" "0,1" newline bitfld.long 0x0 0. "CTS_STS,Not Defined Read1 | CTS_STS_VALUE_1Indicates that CTS* input (or MCR[1] in loop back) has changed state. Cleared on a read." "0,1" group.byte 0x1C++0x0 line.byte 0x0 "UART5_TLR" hexmask.byte 0x0 4.--7. 1. "RX_FIFO_TRIG_DMA,Receive FIFO trigger level" newline hexmask.byte 0x0 0.--3. 1. "TX_FIFO_TRIG_DMA,Transmit FIFO trigger level" group.byte 0x1C++0x0 line.byte 0x0 "UART5_XOFF2" hexmask.byte 0x0 0.--7. 1. "XOFF_WORD2,Used to store the 8-bit XOFF2 character in used in UART modes." group.long 0x1C++0xF line.long 0x0 "UART5_SPR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "SPR_WORD,Scratchpad register" line.long 0x4 "UART5_MDR1" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 7. "FRAME_END_MODE,IrDA mode only. 0 | FRAME_END_MODE_VALUE_0Frame-length method 1 | FRAME_END_MODE_VALUE_1Set EOT bit method" "0,1" newline bitfld.long 0x4 6. "SIP_MODE,MIR/FIR modes only. 0 | SIP_MODE_VALUE_0Manual SIP mode: SIP is generated with the control of ACREG[3] 1 | SIP_MODE_VALUE_1Automatic SIP mode: SIP is generated after each transmission." "0,1" newline bitfld.long 0x4 5. "SCT,Store and control the transmission 0 | SCT_VALUE_0Starts the Infrared transmission as soon as a value is written to THR 1 | SCT_VALUE_1Starts the Infrared transmission with the control of ACREG[2]. Note: before starting any.." "0,1" newline bitfld.long 0x4 4. "SET_TXIR,Used to configure the infrared transceiver. 0 | SET_TXIR_VALUE_0No action if MDR2[7]=0. TXIR pin output is forced low if MDR2[7]=1 1 | SET_TXIR_VALUE_1TXIR pin output is forced high (not dependant of MDR2[7] value)." "0,1" newline bitfld.long 0x4 3. "IR_SLEEP,Not Defined 0 | IR_SLEEP_VALUE_0IrDA/CIR sleep mode disabled 1 | IR_SLEEP_VALUE_1IrDA/CIR sleep mode enabled" "0,1" newline bitfld.long 0x4 0.--2. "MODE_SELECT,Not Defined 0x0 | MODE_SELECT_VALUE_0UART 16x mode 0x1 | MODE_SELECT_VALUE_1SIR mode 0x2 | MODE_SELECT_VALUE_2UART 16x auto-baud 0x3 | MODE_SELECT_VALUE_3UART 13x mode 0x4 | MODE_SELECT_VALUE_4MIR.." "0,1,2,3,4,5,6,7" line.long 0x8 "UART5_MDR2" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x8 7. "SET_TXIR_ALT,Provide alternate functionnality for MDR1[4] [SET_TXIR] 0 | SET_TXIR_ALT_VALUE_0Normal mode 1 | SET_TXIR_ALT_VALUE_1Alternate mode for SET_TXIR" "0,1" newline bitfld.long 0x8 6. "IRRXINVERT,Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes. 0 | IRRXINVERT_VALUE_0inversion is performed 1.." "0,1" newline bitfld.long 0x8 4.--5. "CIR_PULSE_MODE,CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit: 0x0 | CIR_PULSE_MODE_VALUE_0Pulse width of 3 from 12 cycles 0x1 | CIR_PULSE_MODE_VALUE_1Pulse width of 4 from 12 cycles.." "0,1,2,3" newline bitfld.long 0x8 3. "UART_PULSE,UART mode only. Used to allow pulse shaping in UART mode. 0 | UART_PULSE_VALUE_0normal UART mode 1 | UART_PULSE_VALUE_1UART mode with a pulse shaping" "0,1" newline bitfld.long 0x8 1.--2. "STS_FIFO_TRIG,Only for IR-IRDA mode.Frame Status FIFO Threshold select: 0x0 | STS_FIFO_TRIG_VALUE_01 entry 0x1 | STS_FIFO_TRIG_VALUE_14 entries 0x2 | STS_FIFO_TRIG_VALUE_27 entries 0x3 | STS_FIFO_TRIG_VALUE_38 entries" "0,1,2,3" newline rbitfld.long 0x8 0. "IRTX_UNDERRUN,IRDA Transmission status interrupt.When the IIR[5] interrupt occurs the meaning of the interrupt is : Read0 | IRTX_UNDERRUN_VALUE_0the last bit of the frame has been transmitted successfully without error. Read1 |.." "0,1" line.long 0xC "UART5_TXFLL" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0xC 0.--7. 1. "TXFLL,LSB register used to specify the frame length" rgroup.long 0x28++0x3 line.long 0x0 "UART5_SFLSR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 5.--7. "RESERVED5,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "OE_ERROR,Not Defined Read1 | OE_ERROR_VALUE_1Overrun error in RX FIFO when frame at top of RX FIFO was received." "0,1" newline bitfld.long 0x0 3. "FRAME_TOO_LONG_ERROR,Not Defined Read1 | FRAME_TOO_LONG_ERROR_VALUE_1Frame-length too long error in frame at top of RX FIFO." "0,1" newline bitfld.long 0x0 2. "ABORT_DETECT,Not Defined Read1 | ABORT_DETECT_VALUE_1Abort pattern detected in frame at top of RX FIFO" "0,1" newline bitfld.long 0x0 1. "CRC_ERROR,Not Defined Read1 | CRC_ERROR_VALUE_1CRC error in frame at top of RX FIFO. top of RX FIFO = Next frame to be read from RX FIFO" "0,1" newline bitfld.long 0x0 0. "RESERVED0,Not Defined" "0,1" group.long 0x2C++0x3 line.long 0x0 "UART5_TXFLH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 5.--7. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TXFLH,MSB register used to specify the frame length" rgroup.long 0x2C++0x3 line.long 0x0 "UART5_RESUME" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RESUME,Dummy read to restart the TX or RX" group.long 0x30++0x3 line.long 0x0 "UART5_RXFLL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RXFLL,LSB register used to specify the frame length in reception" rgroup.long 0x30++0x3 line.long 0x0 "UART5_SFREGL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "SFREGL,LSB part of the frame length" group.long 0x34++0x3 line.long 0x0 "UART5_RXFLH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--3. 1. "RXFLH,MSB register used to specify the frame length in reception" rgroup.long 0x34++0x3 line.long 0x0 "UART5_SFREGH" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 0.--3. 1. "SFREGH,MSB part of the frame length" rgroup.byte 0x38++0x0 line.byte 0x0 "UART5_UASR" bitfld.byte 0x0 6.--7. "PARITY_TYPE,00 => No Parity identified. 01 => Parity space. 10 => Even Parity. 11 => Odd Parity" "0: No Parity identified,1: Parity space,?,?" newline bitfld.byte 0x0 5. "BIT_BY_CHAR,0 => 7 bits character identified. 1 => 8 bits character identified" "0: 7 bits character identified,1: 8 bits character identified" newline hexmask.byte 0x0 0.--4. 1. "SPEED,Used to report the speed identified. 00000 => No speed identified. 00001 => 115200 bauds. 00010 => 57600 bauds. 00011 => 38400 bauds. 00100 => 28800 bauds. 00101 => 19200 bauds. 00110 => 14400 bauds. 00111 => 9600 bauds. 01000 => 4800 bauds. 01001.." group.long 0x38++0x13 line.long 0x0 "UART5_BLR" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "STS_FIFO_RESET,Status FIFO reset. This bit is self-clearing" "0,1" newline bitfld.long 0x0 6. "XBOF_TYPE,SIR xBOF select. 0 | XBOF_TYPE_VALUE_00xFF 1 | XBOF_TYPE_VALUE_10xC0" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "RESERVED,Not Defined" line.long 0x4 "UART5_ACREG" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 7. "PULSE_TYPE,SIR pulse width select: 0 | PULSE_TYPE_VALUE_03/16 of baud-rate pulse width 1 | PULSE_TYPE_VALUE_11.6us" "0,1" newline bitfld.long 0x4 6. "SD_MOD,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers. 0 | SD_MOD_VALUE_0SD pin is set to high 1 | SD_MOD_VALUE_1SD pin is set to low" "0,1" newline bitfld.long 0x4 5. "DIS_IR_RX,Not Defined 0 | DIS_IR_RX_VALUE_0Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation). 1 | DIS_IR_RX_VALUE_1Disables RX input (permanent state - independent of transmit)." "0,1" newline bitfld.long 0x4 4. "DIS_TX_UNDERRUN,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by setting ACREG[4]=1 garbage data is sent over TX line. 0 | DIS_TX_UNDERRUN_VALUE_0Long stop bits.." "0,1" newline bitfld.long 0x4 3. "SEND_SIP,MIR/FIR Modes only.Send Serial Infrared Interaction Pulse [SIP]If this bit is set during a MIR/FIR transmission the SIP will be send at the end of it.This bit automatically gets cleared at the end of the SIP transmission. 0 |.." "0,1" newline bitfld.long 0x4 2. "SCTX_EN,Store and controlled TX start. When MDR1[5] = 1 and the LH writes 1 to this bit the TX state machine starts frame transmission. This bit is self-clearing." "0,1" newline bitfld.long 0x4 1. "ABORT_EN,Frame Abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If transmit FIFO is not empty and MDR1[5]=1 UART IrDA will start a new transfer.." "0,1" newline bitfld.long 0x4 0. "EOT_EN,EOT [end of transmission] bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit automatically gets cleared when the LH writes to the THR [TX FIFO]." "0,1" line.long 0x8 "UART5_SCR" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x8 7. "RX_TRIG_GRANU1,Not Defined 0 | RX_TRIG_GRANU1_VALUE_0DISABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL. 1 | RX_TRIG_GRANU1_VALUE_1ENABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL." "0,1" newline bitfld.long 0x8 6. "TX_TRIG_GRANU1,Not Defined 0 | TX_TRIG_GRANU1_VALUE_0DISABLES THE GRANULARITY OF 1 FOR TRIGGER TX LEVEL. 1 | TX_TRIG_GRANU1_VALUE_1Enables the granularity of 1 for trigger TX level." "0,1" newline bitfld.long 0x8 5. "DSR_IT,Not Defined 0 | DSR_IT_VALUE_0DISABLES DSR* INTERRUPT. 1 | DSR_IT_VALUE_1ENABLES DSR* INTERRUPT." "0,1" newline bitfld.long 0x8 4. "RX_CTS_DSR_WAKE_UP_ENABLE,Not Defined 0 | RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_0DISABLES THE WAKE UP INTERRUPT AND CLEARS SSR[1]. 1 | RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_1Waits for a falling edge of pins RX CTS* or DSR* to generate an interrupt" "0,1" newline bitfld.long 0x8 3. "TX_EMPTY_CTL_IT,Not Defined 0 | TX_EMPTY_CTL_IT_VALUE_0Normal mode for THR interrupt (See UART mode interrupts table). 1 | TX_EMPTY_CTL_IT_VALUE_1THE THR INTERRUPT IS GENERATED WHEN TX FIFO AND TX SHIFT REGISTER ARE EMPTY." "0,1" newline bitfld.long 0x8 1.--2. "DMA_MODE_2,Used to specify the DMA mode valid if SCR[0] = 1 0x0 | DMA_MODE_2_VALUE_0DMA mode 0 (no DMA) 0x1 | DMA_MODE_2_VALUE_1DMA mode 1 (UART_nDMA_REQ[0] in TX UART_nDMA_REQ[1] in RX) 0x2 | DMA_MODE_2_VALUE_2DMA mode 2.." "0,1,2,3" newline bitfld.long 0x8 0. "DMA_MODE_CTL,Not Defined 0 | DMA_MODE_CTL_VALUE_0The DMA_MODE is set with FCR[3] 1 | DMA_MODE_CTL_VALUE_1The DMA_MODE is set with SCR[2:1]" "0,1" line.long 0xC "UART5_SSR" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0xC 3.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0xC 2. "DMA_COUNTER_RST,Not Defined 0 | DMA_COUNTER_RST_VALUE_0The DMA counter will not be reset if the corresponding FIFO is reset (via FCR[1] or FCR[2]) 1 | DMA_COUNTER_RST_VALUE_1The DMA counter will be reset if corresponding FIFO is reset.." "0,1" newline rbitfld.long 0xC 1. "RX_CTS_DSR_WAKE_UP_STS,Not Defined Read0 | RX_CTS_DSR_WAKE_UP_STS_VALUE_0No falling edge event on RX CTS* and DSR* Read1 | RX_CTS_DSR_WAKE_UP_STS_VALUE_1A falling edge occurred on RX CTS* or DSR*" "0,1" newline rbitfld.long 0xC 0. "TX_FIFO_FULL,Not Defined Read0 | TX_FIFO_FULL_VALUE_0TX FIFO is not full Read1 | TX_FIFO_FULL_VALUE_1TX FIFO is full." "0,1" line.long 0x10 "UART5_EBLR" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x10 0.--7. 1. "EBLR,IR-IRDA mode: This register allows to define up to 176 xBOFs the maximum required by IrDA specification.IR-CIR mode: This register specifies the number of consecutive zeros to be received before generating the RX_STOP interrupt [IIR[2]].0x00:.." rgroup.long 0x50++0x3 line.long 0x0 "UART5_MVR" bitfld.long 0x0 30.--31. "SCHEME,Scheme revision number of module" "0,1,2,3" newline bitfld.long 0x0 28.--29. "RESERVED,Not Defined" "0,1,2,3" newline hexmask.long.word 0x0 16.--27. 1. "FUNC,Function revision number of module" newline hexmask.long.byte 0x0 11.--15. 1. "RTL,Rtl revision number of module" newline bitfld.long 0x0 8.--10. "MAJOR,Major revision number of the module." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--7. "CUSTOM,Custom revision number of the module." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision number of the module." group.long 0x54++0x3 line.long 0x0 "UART5_SYSC" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline rbitfld.long 0x0 5.--7. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 3.--4. "IDLEMODE,POWER MANAGEMENT REQ/ACK CONTROLREF: OCP DESIGN GUIDELINES VERSION 1.1 0x0 | IDLEMODE_VALUE_0Force idle. An idle request is acknowledged unconditionally 0x1 | IDLEMODE_VALUE_1No-idle. An idle request is never acknowledged." "0,1,2,3" newline bitfld.long 0x0 2. "ENAWAKEUP,WAKE UP FEATURE CONTROL 0 | ENAWAKEUP_VALUE_0Wake up is disabled 1 | ENAWAKEUP_VALUE_1Wake up capability is enabled" "0,1" newline bitfld.long 0x0 1. "SOFTRESET,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. During reads it always returns a 0. Write0 | SOFTRESET_VALUE_0Normal mode Write1 | SOFTRESET_VALUE_1The module is reset" "0,1" newline bitfld.long 0x0 0. "AUTOIDLE,Internal OCP clock gating strategy 0 | AUTOIDLE_VALUE_0Clock is running 1 | AUTOIDLE_VALUE_1Automatic OCP clock gating strategy is applied based on the OCP interface activity" "0,1" rgroup.long 0x58++0x3 line.long 0x0 "UART5_SYSS" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 0. "RESETDONE,Internal Reset Monitoring Read0 | RESETDONE_VALUE_0Internal Module Reset is ongoing Read1 | RESETDONE_VALUE_1Reset completed" "0,1" group.long 0x5C++0x7 line.long 0x0 "UART5_WER" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 7. "EVENT_7_TX_WAKEUP_EN,Not Defined 0 | EVENT_7_TX_WAKEUP_EN_VALUE_0Event is not allowed to wake up the system 1 | EVENT_7_TX_WAKEUP_EN_VALUE_1EVENT CAN WAKE UP THE SYSTEM: Event can be: THR_IT or TX_DMA request and/or TX_SATUS_IT" "0,1" newline bitfld.long 0x0 6. "EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT,Not Defined 0 | EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_VALUE_0Event is not allowed to wake up the system 1 | EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 5. "EVENT_5_RHR_INTERRUPT,Not Defined 0 | EVENT_5_RHR_INTERRUPT_VALUE_0Event is not allowed to wake up the system 1 | EVENT_5_RHR_INTERRUPT_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 4. "EVENT_4_RX_ACTIVITY,Not Defined 0 | EVENT_4_RX_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_4_RX_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 3. "EVENT_3_DCD_CD_ACTIVITY,Not Defined 0 | EVENT_3_DCD_CD_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_3_DCD_CD_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 2. "EVENT_2_RI_ACTIVITY,Not Defined 0 | EVENT_2_RI_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_2_RI_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 1. "EVENT_1_DSR_ACTIVITY,Not Defined 0 | EVENT_1_DSR_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_1_DSR_ACTIVITY_VALUE_1Event can wake up the system" "0,1" newline bitfld.long 0x0 0. "EVENT_0_CTS_ACTIVITY,Not Defined 0 | EVENT_0_CTS_ACTIVITY_VALUE_0Event is not allowed to wake up the system 1 | EVENT_0_CTS_ACTIVITY_VALUE_1Event can wake up the system" "0,1" line.long 0x4 "UART5_CFPS" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x4 0.--7. 1. "CFPS,System clock frequency prescaler at [12x multiple]. Examples for CFPS values are given in the table below.Target Freq [KHz] CFPS [decimal] Actual Freq[KHz] 30 133 30.08 32.75 122 32.79 36 111 36.04 36.7 109 36.69 38* 105 38.1 40 100.." rgroup.long 0x64++0x7 line.long 0x0 "UART5_RXFIFO_LVL" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED24,Not Defined" newline hexmask.long.byte 0x0 0.--7. 1. "RXFIFO_LVL,Not Defined" line.long 0x4 "UART5_TXFIFO_LVL" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED24,Not Defined" newline hexmask.long.byte 0x4 0.--7. 1. "TXFIFO_LVL,Not Defined" group.long 0x6C++0xB line.long 0x0 "UART5_IER2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x0 2. "RHR_IT_DIS,Not Defined 0 | RHR_IT_DIS_VALUE_0Enables the RHR interrupt. 1 | RHR_IT_DIS_VALUE_1Disables the RHR interrupt." "0,1" newline bitfld.long 0x0 1. "EN_TXFIFO_EMPTY,Enables[1]/DISABLES[00 EN_TXFIFO_EMPTY interrupt." "0,1" newline bitfld.long 0x0 0. "EN_RXFIFO_EMPTY,Enables[1]/disables[0] EN_RXFIFO_EMPTY interrupt." "0,1" line.long 0x4 "UART5_ISR2" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED1,Not Defined" newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED,Not Defined" newline bitfld.long 0x4 1. "TXFIFO_EMPTY_STS,TXFIFO interrupt pending 0 | TXFIFO_EMPTY_STS_VALUE_0TXFIFO_EMPTY interrupt not pending. 1 | TXFIFO_EMPTY_STS_VALUE_1TXFIFO_EMPTY interrupt pending." "0,1" newline bitfld.long 0x4 0. "RXFIFO_EMPTY_STS,RXFIFO interrupt pending 0 | RXFIFO_EMPTY_STS_VALUE_0RXFIFO_EMPTY interrupt not pending. 1 | RXFIFO_EMPTY_STS_VALUE_1RXFIFO_EMPTY interrupt pending." "0,1" line.long 0x8 "UART5_FREQ_SEL" hexmask.long.byte 0x8 0.--7. 1. "FREQ_SEL,Sets the sample per bit if non default frequency is used. MDR3[1] must be set to 1 after this value is set. Must be equal or higher then 6." rgroup.long 0x78++0x7 line.long 0x0 "UART5_ABAUD_1ST_CHAR" hexmask.long 0x0 0.--31. 1. "RESERVED,Not Defined" line.long 0x4 "UART5_BAUD_2ND_CHAR" hexmask.long 0x4 0.--31. 1. "RESERVED,Not Defined" group.long 0x80++0x27 line.long 0x0 "UART5_MDR3" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED2,Not Defined" newline bitfld.long 0x0 4. "DIR_EN,RS-485 External Transceiver Direction Enable" "0,1" newline bitfld.long 0x0 3. "DIR_POL,RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0 RX: RTS=1. 1 => TX: RTS=1 RX: RTS=0" "0: TX: RTS=0,1: TX: RTS=1" newline bitfld.long 0x0 2. "SET_DMA_TX_THRESHOLD,Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD]" "0,1" newline bitfld.long 0x0 1. "NONDEFAULT_FREQ,Enables[1]/Disables[0] using NONDEFAULT fclk frequencies" "0,1" newline bitfld.long 0x0 0. "DISABLE_CIR_RX_DEMOD,Disables[1]/Enables[0] CIR RX demodulation 0 | DISABLE_CIR_RX_DEMOD_VALUE_0Enables CIR RX demodulation 1 | DISABLE_CIR_RX_DEMOD_VALUE_1Disables CIR RX demodulation" "0,1" line.long 0x4 "UART5_TX_DMA_THRESHOLD" hexmask.long.byte 0x4 0.--5. 1. "TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level." line.long 0x8 "UART5_MDR4" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED1,Not Defined" newline rbitfld.long 0x8 7. "RESERVED,Not Defined" "0,1" newline bitfld.long 0x8 6. "MODE9,9-bit character length. When '1' overrides character length setting in LCR" "0,1" newline bitfld.long 0x8 3.--5. "FREQ_SEL_H,Upper 3 bits of FREQ_SEL register for higher division values as required for example for FI/Di in ISO7816 mode" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0.--2. "MODE,New modes [when set overrides MDR1 modes] 0x0 | DISABLEDdisabled (no override) 0x1 | RESERVEDreserved 0x2 | SYNCH_EXTSynchronous mode with external clock 0x3 | SYNCH_GENSynchronous mode with generated clock.." "0,1,2,3,4,5,6,7" line.long 0xC "UART5_EFR2" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED1,Not Defined" newline bitfld.long 0xC 7. "BROADCAST,Enables broadcast address matching in multi-drop address match mode" "0,1" newline bitfld.long 0xC 6. "TIMEOUT_BEHAVE,Specifies how timeout is measured 0 | _0timeout after at least one character has been received 1 | _1periodic timeout even when no character has been received" "0,1" newline bitfld.long 0xC 5. "C8,Value for ISO 7816 C8 pin for software control" "0,1" newline bitfld.long 0xC 4. "C4,Value for ISO 7816 C4 pin for software control" "0,1" newline bitfld.long 0xC 3. "C2,Value for ISO 7816 reset pin [software controllable]" "0,1" newline bitfld.long 0xC 2. "MULTIDROP,Enables parity Multi-drop mode [overrides LCR[5..3]] when '1'" "0,1" newline bitfld.long 0xC 1. "RHR_OVERRUN,RHR Overrun behaviour when buffer full 0 | DEFAULTdata in RHR is not overwritten (standard) 1 | ATMELdata in RHR is overwritten when buffer full (and FIFO disabled)" "0,1" newline bitfld.long 0xC 0. "ENDIAN,Endianness 0 | LOW_ENDIANLittle Endian (LSB First) 1 | BIG_ENDIANBig Endian (MSB First)" "0,1" line.long 0x10 "UART5_ECR" hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED1,Not Defined" newline rbitfld.long 0x10 6.--7. "RESERVED,Not Defined" "0,1,2,3" newline bitfld.long 0x10 5. "CLEAR_TX_PE,Write 1 to clear parity error from the Transmitter to allow it to continue to try sending data [ISO7816 transmit only]" "0,1" newline bitfld.long 0x10 4. "TX_EN,Enables/Disables the transmitter 0 | DISABLEDTransmitter is shut down 1 | ENABLEDTransmitter is working" "0,1" newline bitfld.long 0x10 3. "RX_EN,Enables/Disables the receiver 0 | DISABLEDReceiver is shut down 1 | ENABLEDReceiver is operating" "0,1" newline bitfld.long 0x10 2. "TX_RST,Writing '1' resets the transmitter" "0,1" newline bitfld.long 0x10 1. "RX_RST,Writing '1' resets the receiver" "0,1" newline bitfld.long 0x10 0. "A_MULTIDROP,In multi-drop mode when written with the value '1' causes the next byte written into THR to be transmitted with the parity bit set signaling an address" "0,1" line.long 0x14 "UART5_TIMEGUARD" hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x14 0.--7. 1. "TIMEGUARD,Specifies the amount of idle baud clocks [transmitter bit period] to insert between transmitted bytes useful when comunicating with slower devices" line.long 0x18 "UART5_TIMEOUTL" hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x18 0.--7. 1. "TIMEOUT_L,Custom timeout period in baud clocks to override the internal value when different from 0. [Lower byte of the 16 bit value]" line.long 0x1C "UART5_TIMEOUTH" hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED,Not Defined" newline hexmask.long.byte 0x1C 0.--7. 1. "TIMEOUT_H,Custom timeout period in baud clocks to override the internal value when different from 0. [Higher byte of the 16 bit value]" line.long 0x20 "UART5_SCCR" hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED1,Not Defined" newline bitfld.long 0x20 7. "DSNACK,Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline bitfld.long 0x20 6. "INACK,Inhibit NACK when receiving even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when reading it." "0,1" newline rbitfld.long 0x20 3.--5. "RESERVED,Not Defined" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0.--2. "MAX_ITERATION,Number of times to repeat transmitted character if the receiver did not acknowledge. If not acknowledged after the max value is reached the USART transmitter will set parity error stop and not continue until it is cleared." "0,1,2,3,4,5,6,7" line.long 0x24 "UART5_ETHR" hexmask.long.tbyte 0x24 9.--31. 1. "RESERVED,Not Defined" newline hexmask.long.word 0x24 0.--8. 1. "ETHR,Extended Transmit Holding Register - allows writing the full 9bit RHR" rgroup.long 0xA4++0x3 line.long 0x0 "UART5_ERHR" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Not Defined" newline hexmask.long.word 0x0 0.--8. 1. "ERHR,Extended Receive Holding Register - allows accessing the full 9bit RHR" group.byte 0xA8++0x0 line.byte 0x0 "UART5_MAR" hexmask.byte 0x0 0.--7. 1. "ADDRESS,Multidrop match address value" group.byte 0xAC++0x0 line.byte 0x0 "UART5_MMR" hexmask.byte 0x0 0.--7. 1. "MASK,Address match masking value ? writing a 0 to a bit means that the corresponding address bit will be ignored in matching" group.byte 0xB0++0x0 line.byte 0x0 "UART5_MBR" hexmask.byte 0x0 0.--7. 1. "BROADCAST_ADDRESS,Broadcast address for address matching" tree.end tree.end tree "VIM" base ad:0x50F00000 rgroup.long 0x0++0x17 line.long 0x0 "VIM_PID" bitfld.long 0x0 30.--31. "SCHEME,PID register scheme" "0,1,2,3" bitfld.long 0x0 28.--29. "BU,Business Unit: 10 = Processors" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. "FUNC,Module ID" hexmask.long.byte 0x0 11.--15. 1. "RTL,RTL revision. Will vary depending on release." bitfld.long 0x0 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. "CUSTOM,Custom" "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "MINOR,Minor revision" line.long 0x4 "VIM_INFO" hexmask.long.tbyte 0x4 11.--31. 1. "RES1,RESERVE FIELD" hexmask.long.word 0x4 0.--10. 1. "INTERRUPTS,Total number of Interrupts" line.long 0x8 "VIM_PRIIRQ" bitfld.long 0x8 31. "VALID,Indicates that the num field is valid." "0,1" hexmask.long.word 0x8 20.--30. 1. "RES2,RESERVE FIELD" hexmask.long.byte 0x8 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set." hexmask.long.byte 0x8 10.--15. 1. "RES3,RESERVE FIELD" hexmask.long.word 0x8 0.--9. 1. "NUM,Number of the highest priority pending IRQ. valid only if the valid flag is set." line.long 0xC "VIM_PRIFIQ" bitfld.long 0xC 31. "VALID,Indicates that the num field is valid." "0,1" hexmask.long.word 0xC 20.--30. 1. "RES4,RESERVE FIELD" hexmask.long.byte 0xC 16.--19. 1. "PRI,Priority of the highest priority pending FIQ. valid only if the valid flag is set." hexmask.long.byte 0xC 10.--15. 1. "RES5,RESERVE FIELD" hexmask.long.word 0xC 0.--9. 1. "NUM,Number of the highest priority pending FIQ. valid only if the valid flag is set." line.long 0x10 "VIM_IRQGSTS" hexmask.long 0x10 0.--31. 1. "STS,Indicates that the num field is valid." line.long 0x14 "VIM_FIQGSTS" hexmask.long 0x14 0.--31. 1. "STS,Indicates that the num field is valid." group.long 0x18++0x7 line.long 0x0 "VIM_IRQVEC" hexmask.long 0x0 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized IRQ Register valid flag is true." rbitfld.long 0x0 0.--1. "RES21,RESERVE FIELD" "0,1,2,3" line.long 0x4 "VIM_FIQVEC" hexmask.long 0x4 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address. Only valid if the Prioritized FIQ Register valid flag is true." rbitfld.long 0x4 0.--1. "RES22,RESERVE FIELD" "0,1,2,3" rgroup.long 0x20++0x7 line.long 0x0 "VIM_ACTIRQ" bitfld.long 0x0 31. "VALID,Indicates that the num field is valid. Set when the IRQ Vector Address Register is read and cleared whenever the IRQ Vector Address Register is written." "0,1" hexmask.long.word 0x0 20.--30. 1. "RES6,RESERVE FIELD" hexmask.long.byte 0x0 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set." hexmask.long.byte 0x0 10.--15. 1. "RES7,RESERVE FIELD" hexmask.long.word 0x0 0.--9. 1. "NUM,Number of the currently active IRQ. Loaded from teh Prioritized IRQ Register whenever the IRQ Vector Address is read. Valid only if the valid flag is set." line.long 0x4 "VIM_ACTFIQ" bitfld.long 0x4 31. "VALID,Indicates that the num field is valid. Set when the FIQ Vector Address Register is read and cleared whenever the FIQ Vector Address Register is written." "0,1" hexmask.long.word 0x4 20.--30. 1. "RES8,RESERVE FIELD" hexmask.long.byte 0x4 16.--19. 1. "PRI,Priority of the highest priority pending IRQ. valid only if the valid flag is set." hexmask.long.byte 0x4 10.--15. 1. "RES9,RESERVE FIELD" hexmask.long.word 0x4 0.--9. 1. "NUM,Number of the currently active FIQ. Loaded from teh Prioritized FIQ Register whenever the FIQ Vector Address is read. Valid only if the valid flag is set." group.long 0x28++0xB line.long 0x0 "VIM_IRQPRIMSK" hexmask.long.word 0x0 16.--31. 1. "RES24,RESERVE FIELD" hexmask.long.word 0x0 0.--15. 1. "MSK,Each bit corresponds to the given priority. 1 - IRQs of this priority are enabled. 0 - IRQs of this priority are disabled." line.long 0x4 "VIM_FIQPRIMSK" hexmask.long.word 0x4 16.--31. 1. "RES24,RESERVE FIELD" hexmask.long.word 0x4 0.--15. 1. "MSK,Each bit corresponds to the given priority. 1 - FIQs of this priority are enabled. 0 - FIQs of this priority are disabled." line.long 0x8 "VIM_DEDVEC" hexmask.long 0x8 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address." rbitfld.long 0x8 0.--1. "RES23,RESERVE FIELD" "0,1,2,3" group.long 0x400++0xFF line.long 0x0 "VIM_RAW" hexmask.long 0x0 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 InactiveRead 1 Active/PendingWrite 0 No effectWrite 1 Set to Interrupt Raw Status" line.long 0x4 "VIM_STS" hexmask.long 0x4 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or DisabledRead 1 Active/Pending and EnabledWrite 0 No effectWrite 1 Clear Interrupt Raw Status" line.long 0x8 "VIM_INTR_EN_SET" hexmask.long 0x8 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Set Enable" line.long 0xC "VIM_INTER_EN_CLR" hexmask.long 0xC 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Clear Enable" line.long 0x10 "VIM_IRQSTS" hexmask.long 0x10 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an IRQRead 1 Active/Pending Enabled and IRQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x14 "VIM_FIQSTS" hexmask.long 0x14 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an FIQRead 1 Active/Pending Enabled and FIQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x18 "VIM_INTMAP" hexmask.long 0x18 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt (default)1 FIQ Interrupt" line.long 0x1C "VIM_INTTYPE" hexmask.long 0x1C 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event (see.." line.long 0x20 "VIM_RAW_1" hexmask.long 0x20 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 InactiveRead 1 Active/PendingWrite 0 No effectWrite 1 Set to Interrupt Raw Status" line.long 0x24 "VIM_STS_1" hexmask.long 0x24 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or DisabledRead 1 Active/Pending and EnabledWrite 0 No effectWrite 1 Clear Interrupt Raw Status" line.long 0x28 "VIM_INTR_EN_SET_1" hexmask.long 0x28 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Set Enable" line.long 0x2C "VIM_INTER_EN_CLR_1" hexmask.long 0x2C 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Clear Enable" line.long 0x30 "VIM_IRQSTS_1" hexmask.long 0x30 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an IRQRead 1 Active/Pending Enabled and IRQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x34 "VIM_FIQSTS_1" hexmask.long 0x34 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an FIQRead 1 Active/Pending Enabled and FIQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x38 "VIM_INTMAP_1" hexmask.long 0x38 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt (default)1 FIQ Interrupt" line.long 0x3C "VIM_INTTYPE_1" hexmask.long 0x3C 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event (see.." line.long 0x40 "VIM_RAW_2" hexmask.long 0x40 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 InactiveRead 1 Active/PendingWrite 0 No effectWrite 1 Set to Interrupt Raw Status" line.long 0x44 "VIM_STS_2" hexmask.long 0x44 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or DisabledRead 1 Active/Pending and EnabledWrite 0 No effectWrite 1 Clear Interrupt Raw Status" line.long 0x48 "VIM_INTR_EN_SET_2" hexmask.long 0x48 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Set Enable" line.long 0x4C "VIM_INTER_EN_CLR_2" hexmask.long 0x4C 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Clear Enable" line.long 0x50 "VIM_IRQSTS_2" hexmask.long 0x50 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an IRQRead 1 Active/Pending Enabled and IRQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x54 "VIM_FIQSTS_2" hexmask.long 0x54 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an FIQRead 1 Active/Pending Enabled and FIQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x58 "VIM_INTMAP_2" hexmask.long 0x58 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt (default)1 FIQ Interrupt" line.long 0x5C "VIM_INTTYPE_2" hexmask.long 0x5C 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event (see.." line.long 0x60 "VIM_RAW_3" hexmask.long 0x60 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 InactiveRead 1 Active/PendingWrite 0 No effectWrite 1 Set to Interrupt Raw Status" line.long 0x64 "VIM_STS_3" hexmask.long 0x64 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or DisabledRead 1 Active/Pending and EnabledWrite 0 No effectWrite 1 Clear Interrupt Raw Status" line.long 0x68 "VIM_INTR_EN_SET_3" hexmask.long 0x68 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Set Enable" line.long 0x6C "VIM_INTER_EN_CLR_3" hexmask.long 0x6C 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Clear Enable" line.long 0x70 "VIM_IRQSTS_3" hexmask.long 0x70 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an IRQRead 1 Active/Pending Enabled and IRQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x74 "VIM_FIQSTS_3" hexmask.long 0x74 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an FIQRead 1 Active/Pending Enabled and FIQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x78 "VIM_INTMAP_3" hexmask.long 0x78 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt (default)1 FIQ Interrupt" line.long 0x7C "VIM_INTTYPE_3" hexmask.long 0x7C 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event (see.." line.long 0x80 "VIM_RAW_4" hexmask.long 0x80 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 InactiveRead 1 Active/PendingWrite 0 No effectWrite 1 Set to Interrupt Raw Status" line.long 0x84 "VIM_STS_4" hexmask.long 0x84 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or DisabledRead 1 Active/Pending and EnabledWrite 0 No effectWrite 1 Clear Interrupt Raw Status" line.long 0x88 "VIM_INTR_EN_SET_4" hexmask.long 0x88 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Set Enable" line.long 0x8C "VIM_INTER_EN_CLR_4" hexmask.long 0x8C 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Clear Enable" line.long 0x90 "VIM_IRQSTS_4" hexmask.long 0x90 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an IRQRead 1 Active/Pending Enabled and IRQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x94 "VIM_FIQSTS_4" hexmask.long 0x94 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an FIQRead 1 Active/Pending Enabled and FIQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0x98 "VIM_INTMAP_4" hexmask.long 0x98 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt (default)1 FIQ Interrupt" line.long 0x9C "VIM_INTTYPE_4" hexmask.long 0x9C 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event (see.." line.long 0xA0 "VIM_RAW_5" hexmask.long 0xA0 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 InactiveRead 1 Active/PendingWrite 0 No effectWrite 1 Set to Interrupt Raw Status" line.long 0xA4 "VIM_STS_5" hexmask.long 0xA4 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or DisabledRead 1 Active/Pending and EnabledWrite 0 No effectWrite 1 Clear Interrupt Raw Status" line.long 0xA8 "VIM_INTR_EN_SET_5" hexmask.long 0xA8 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Set Enable" line.long 0xAC "VIM_INTER_EN_CLR_5" hexmask.long 0xAC 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Clear Enable" line.long 0xB0 "VIM_IRQSTS_5" hexmask.long 0xB0 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an IRQRead 1 Active/Pending Enabled and IRQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0xB4 "VIM_FIQSTS_5" hexmask.long 0xB4 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an FIQRead 1 Active/Pending Enabled and FIQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0xB8 "VIM_INTMAP_5" hexmask.long 0xB8 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt (default)1 FIQ Interrupt" line.long 0xBC "VIM_INTTYPE_5" hexmask.long 0xBC 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event (see.." line.long 0xC0 "VIM_RAW_6" hexmask.long 0xC0 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 InactiveRead 1 Active/PendingWrite 0 No effectWrite 1 Set to Interrupt Raw Status" line.long 0xC4 "VIM_STS_6" hexmask.long 0xC4 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or DisabledRead 1 Active/Pending and EnabledWrite 0 No effectWrite 1 Clear Interrupt Raw Status" line.long 0xC8 "VIM_INTR_EN_SET_6" hexmask.long 0xC8 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Set Enable" line.long 0xCC "VIM_INTER_EN_CLR_6" hexmask.long 0xCC 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Clear Enable" line.long 0xD0 "VIM_IRQSTS_6" hexmask.long 0xD0 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an IRQRead 1 Active/Pending Enabled and IRQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0xD4 "VIM_FIQSTS_6" hexmask.long 0xD4 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an FIQRead 1 Active/Pending Enabled and FIQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0xD8 "VIM_INTMAP_6" hexmask.long 0xD8 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt (default)1 FIQ Interrupt" line.long 0xDC "VIM_INTTYPE_6" hexmask.long 0xDC 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event (see.." line.long 0xE0 "VIM_RAW_7" hexmask.long 0xE0 0.--31. 1. "STS,This is the raw status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 InactiveRead 1 Active/PendingWrite 0 No effectWrite 1 Set to Interrupt Raw Status" line.long 0xE4 "VIM_STS_7" hexmask.long 0xE4 0.--31. 1. "MASK,This is the masked status of the events in Group M Each bit corresponds to event Q where Q = Mx32+Bit Read 0 Inactive or DisabledRead 1 Active/Pending and EnabledWrite 0 No effectWrite 1 Clear Interrupt Raw Status" line.long 0xE8 "VIM_INTR_EN_SET_7" hexmask.long 0xE8 0.--31. 1. "MASK,This field is used to enable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Set Enable" line.long 0xEC "VIM_INTER_EN_CLR_7" hexmask.long 0xEC 0.--31. 1. "MASK,This field is used to disable the mask of events in Group M Each bit corresponds to event Q where Q = Mx32+BitRead 0 DisabledRead 1 EnabledWrite 0 No effectWrite 1 Clear Enable" line.long 0xF0 "VIM_IRQSTS_7" hexmask.long 0xF0 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to IRQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an IRQRead 1 Active/Pending Enabled and IRQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0xF4 "VIM_FIQSTS_7" hexmask.long 0xF4 0.--31. 1. "MASK,This is the masked status of the events in group M that are mapped to FIQ Each bit corresponds to event Q where Q = Mx32+BitRead 0 Inactive Disabled or not an FIQRead 1 Active/Pending Enabled and FIQWrite 0 No effectWrite 1 Clear Interrupt.." line.long 0xF8 "VIM_INTMAP_7" hexmask.long 0xF8 0.--31. 1. "MASK,This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q where Q = Mx32+Bit 0 IRQ Interrupt (default)1 FIQ Interrupt" line.long 0xFC "VIM_INTTYPE_7" hexmask.long 0xFC 0.--31. 1. "VAL,This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. This is informational so that an ISR may query this register and know whether it has to clear a pulse event or a level event (see.." group.long 0x1000++0x3FF line.long 0x0 "VIM_INTPRIORITY" hexmask.long 0x0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x4 "VIM_INTPRIORITY_1" hexmask.long 0x4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x8 "VIM_INTPRIORITY_2" hexmask.long 0x8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xC "VIM_INTPRIORITY_3" hexmask.long 0xC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x10 "VIM_INTPRIORITY_4" hexmask.long 0x10 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x10 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x14 "VIM_INTPRIORITY_5" hexmask.long 0x14 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x14 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x18 "VIM_INTPRIORITY_6" hexmask.long 0x18 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x18 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1C "VIM_INTPRIORITY_7" hexmask.long 0x1C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x20 "VIM_INTPRIORITY_8" hexmask.long 0x20 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x20 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x24 "VIM_INTPRIORITY_9" hexmask.long 0x24 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x24 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x28 "VIM_INTPRIORITY_10" hexmask.long 0x28 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x28 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2C "VIM_INTPRIORITY_11" hexmask.long 0x2C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x30 "VIM_INTPRIORITY_12" hexmask.long 0x30 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x30 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x34 "VIM_INTPRIORITY_13" hexmask.long 0x34 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x34 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x38 "VIM_INTPRIORITY_14" hexmask.long 0x38 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x38 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3C "VIM_INTPRIORITY_15" hexmask.long 0x3C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x40 "VIM_INTPRIORITY_16" hexmask.long 0x40 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x40 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x44 "VIM_INTPRIORITY_17" hexmask.long 0x44 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x44 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x48 "VIM_INTPRIORITY_18" hexmask.long 0x48 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x48 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x4C "VIM_INTPRIORITY_19" hexmask.long 0x4C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x4C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x50 "VIM_INTPRIORITY_20" hexmask.long 0x50 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x50 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x54 "VIM_INTPRIORITY_21" hexmask.long 0x54 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x54 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x58 "VIM_INTPRIORITY_22" hexmask.long 0x58 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x58 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x5C "VIM_INTPRIORITY_23" hexmask.long 0x5C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x5C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x60 "VIM_INTPRIORITY_24" hexmask.long 0x60 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x60 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x64 "VIM_INTPRIORITY_25" hexmask.long 0x64 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x64 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x68 "VIM_INTPRIORITY_26" hexmask.long 0x68 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x68 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x6C "VIM_INTPRIORITY_27" hexmask.long 0x6C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x6C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x70 "VIM_INTPRIORITY_28" hexmask.long 0x70 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x70 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x74 "VIM_INTPRIORITY_29" hexmask.long 0x74 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x74 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x78 "VIM_INTPRIORITY_30" hexmask.long 0x78 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x78 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x7C "VIM_INTPRIORITY_31" hexmask.long 0x7C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x7C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x80 "VIM_INTPRIORITY_32" hexmask.long 0x80 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x80 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x84 "VIM_INTPRIORITY_33" hexmask.long 0x84 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x84 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x88 "VIM_INTPRIORITY_34" hexmask.long 0x88 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x88 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x8C "VIM_INTPRIORITY_35" hexmask.long 0x8C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x8C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x90 "VIM_INTPRIORITY_36" hexmask.long 0x90 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x90 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x94 "VIM_INTPRIORITY_37" hexmask.long 0x94 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x94 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x98 "VIM_INTPRIORITY_38" hexmask.long 0x98 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x98 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x9C "VIM_INTPRIORITY_39" hexmask.long 0x9C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x9C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xA0 "VIM_INTPRIORITY_40" hexmask.long 0xA0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xA0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xA4 "VIM_INTPRIORITY_41" hexmask.long 0xA4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xA4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xA8 "VIM_INTPRIORITY_42" hexmask.long 0xA8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xA8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xAC "VIM_INTPRIORITY_43" hexmask.long 0xAC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xAC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xB0 "VIM_INTPRIORITY_44" hexmask.long 0xB0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xB0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xB4 "VIM_INTPRIORITY_45" hexmask.long 0xB4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xB4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xB8 "VIM_INTPRIORITY_46" hexmask.long 0xB8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xB8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xBC "VIM_INTPRIORITY_47" hexmask.long 0xBC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xBC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xC0 "VIM_INTPRIORITY_48" hexmask.long 0xC0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xC0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xC4 "VIM_INTPRIORITY_49" hexmask.long 0xC4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xC4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xC8 "VIM_INTPRIORITY_50" hexmask.long 0xC8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xC8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xCC "VIM_INTPRIORITY_51" hexmask.long 0xCC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xCC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xD0 "VIM_INTPRIORITY_52" hexmask.long 0xD0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xD0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xD4 "VIM_INTPRIORITY_53" hexmask.long 0xD4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xD4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xD8 "VIM_INTPRIORITY_54" hexmask.long 0xD8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xD8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xDC "VIM_INTPRIORITY_55" hexmask.long 0xDC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xDC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xE0 "VIM_INTPRIORITY_56" hexmask.long 0xE0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xE0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xE4 "VIM_INTPRIORITY_57" hexmask.long 0xE4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xE4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xE8 "VIM_INTPRIORITY_58" hexmask.long 0xE8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xE8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xEC "VIM_INTPRIORITY_59" hexmask.long 0xEC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xEC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xF0 "VIM_INTPRIORITY_60" hexmask.long 0xF0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xF0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xF4 "VIM_INTPRIORITY_61" hexmask.long 0xF4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xF4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xF8 "VIM_INTPRIORITY_62" hexmask.long 0xF8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xF8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0xFC "VIM_INTPRIORITY_63" hexmask.long 0xFC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0xFC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x100 "VIM_INTPRIORITY_64" hexmask.long 0x100 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x100 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x104 "VIM_INTPRIORITY_65" hexmask.long 0x104 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x104 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x108 "VIM_INTPRIORITY_66" hexmask.long 0x108 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x108 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x10C "VIM_INTPRIORITY_67" hexmask.long 0x10C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x10C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x110 "VIM_INTPRIORITY_68" hexmask.long 0x110 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x110 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x114 "VIM_INTPRIORITY_69" hexmask.long 0x114 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x114 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x118 "VIM_INTPRIORITY_70" hexmask.long 0x118 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x118 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x11C "VIM_INTPRIORITY_71" hexmask.long 0x11C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x11C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x120 "VIM_INTPRIORITY_72" hexmask.long 0x120 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x120 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x124 "VIM_INTPRIORITY_73" hexmask.long 0x124 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x124 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x128 "VIM_INTPRIORITY_74" hexmask.long 0x128 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x128 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x12C "VIM_INTPRIORITY_75" hexmask.long 0x12C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x12C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x130 "VIM_INTPRIORITY_76" hexmask.long 0x130 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x130 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x134 "VIM_INTPRIORITY_77" hexmask.long 0x134 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x134 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x138 "VIM_INTPRIORITY_78" hexmask.long 0x138 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x138 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x13C "VIM_INTPRIORITY_79" hexmask.long 0x13C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x13C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x140 "VIM_INTPRIORITY_80" hexmask.long 0x140 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x140 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x144 "VIM_INTPRIORITY_81" hexmask.long 0x144 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x144 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x148 "VIM_INTPRIORITY_82" hexmask.long 0x148 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x148 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x14C "VIM_INTPRIORITY_83" hexmask.long 0x14C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x14C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x150 "VIM_INTPRIORITY_84" hexmask.long 0x150 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x150 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x154 "VIM_INTPRIORITY_85" hexmask.long 0x154 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x154 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x158 "VIM_INTPRIORITY_86" hexmask.long 0x158 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x158 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x15C "VIM_INTPRIORITY_87" hexmask.long 0x15C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x15C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x160 "VIM_INTPRIORITY_88" hexmask.long 0x160 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x160 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x164 "VIM_INTPRIORITY_89" hexmask.long 0x164 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x164 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x168 "VIM_INTPRIORITY_90" hexmask.long 0x168 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x168 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x16C "VIM_INTPRIORITY_91" hexmask.long 0x16C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x16C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x170 "VIM_INTPRIORITY_92" hexmask.long 0x170 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x170 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x174 "VIM_INTPRIORITY_93" hexmask.long 0x174 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x174 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x178 "VIM_INTPRIORITY_94" hexmask.long 0x178 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x178 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x17C "VIM_INTPRIORITY_95" hexmask.long 0x17C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x17C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x180 "VIM_INTPRIORITY_96" hexmask.long 0x180 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x180 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x184 "VIM_INTPRIORITY_97" hexmask.long 0x184 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x184 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x188 "VIM_INTPRIORITY_98" hexmask.long 0x188 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x188 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x18C "VIM_INTPRIORITY_99" hexmask.long 0x18C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x18C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x190 "VIM_INTPRIORITY_100" hexmask.long 0x190 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x190 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x194 "VIM_INTPRIORITY_101" hexmask.long 0x194 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x194 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x198 "VIM_INTPRIORITY_102" hexmask.long 0x198 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x198 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x19C "VIM_INTPRIORITY_103" hexmask.long 0x19C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x19C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1A0 "VIM_INTPRIORITY_104" hexmask.long 0x1A0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1A0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1A4 "VIM_INTPRIORITY_105" hexmask.long 0x1A4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1A4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1A8 "VIM_INTPRIORITY_106" hexmask.long 0x1A8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1A8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1AC "VIM_INTPRIORITY_107" hexmask.long 0x1AC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1AC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1B0 "VIM_INTPRIORITY_108" hexmask.long 0x1B0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1B0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1B4 "VIM_INTPRIORITY_109" hexmask.long 0x1B4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1B4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1B8 "VIM_INTPRIORITY_110" hexmask.long 0x1B8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1B8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1BC "VIM_INTPRIORITY_111" hexmask.long 0x1BC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1BC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1C0 "VIM_INTPRIORITY_112" hexmask.long 0x1C0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1C0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1C4 "VIM_INTPRIORITY_113" hexmask.long 0x1C4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1C4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1C8 "VIM_INTPRIORITY_114" hexmask.long 0x1C8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1C8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1CC "VIM_INTPRIORITY_115" hexmask.long 0x1CC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1CC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1D0 "VIM_INTPRIORITY_116" hexmask.long 0x1D0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1D0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1D4 "VIM_INTPRIORITY_117" hexmask.long 0x1D4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1D4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1D8 "VIM_INTPRIORITY_118" hexmask.long 0x1D8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1D8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1DC "VIM_INTPRIORITY_119" hexmask.long 0x1DC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1DC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1E0 "VIM_INTPRIORITY_120" hexmask.long 0x1E0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1E0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1E4 "VIM_INTPRIORITY_121" hexmask.long 0x1E4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1E4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1E8 "VIM_INTPRIORITY_122" hexmask.long 0x1E8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1E8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1EC "VIM_INTPRIORITY_123" hexmask.long 0x1EC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1EC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1F0 "VIM_INTPRIORITY_124" hexmask.long 0x1F0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1F0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1F4 "VIM_INTPRIORITY_125" hexmask.long 0x1F4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1F4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1F8 "VIM_INTPRIORITY_126" hexmask.long 0x1F8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1F8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x1FC "VIM_INTPRIORITY_127" hexmask.long 0x1FC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x1FC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x200 "VIM_INTPRIORITY_128" hexmask.long 0x200 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x200 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x204 "VIM_INTPRIORITY_129" hexmask.long 0x204 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x204 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x208 "VIM_INTPRIORITY_130" hexmask.long 0x208 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x208 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x20C "VIM_INTPRIORITY_131" hexmask.long 0x20C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x20C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x210 "VIM_INTPRIORITY_132" hexmask.long 0x210 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x210 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x214 "VIM_INTPRIORITY_133" hexmask.long 0x214 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x214 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x218 "VIM_INTPRIORITY_134" hexmask.long 0x218 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x218 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x21C "VIM_INTPRIORITY_135" hexmask.long 0x21C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x21C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x220 "VIM_INTPRIORITY_136" hexmask.long 0x220 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x220 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x224 "VIM_INTPRIORITY_137" hexmask.long 0x224 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x224 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x228 "VIM_INTPRIORITY_138" hexmask.long 0x228 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x228 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x22C "VIM_INTPRIORITY_139" hexmask.long 0x22C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x22C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x230 "VIM_INTPRIORITY_140" hexmask.long 0x230 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x230 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x234 "VIM_INTPRIORITY_141" hexmask.long 0x234 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x234 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x238 "VIM_INTPRIORITY_142" hexmask.long 0x238 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x238 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x23C "VIM_INTPRIORITY_143" hexmask.long 0x23C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x23C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x240 "VIM_INTPRIORITY_144" hexmask.long 0x240 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x240 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x244 "VIM_INTPRIORITY_145" hexmask.long 0x244 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x244 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x248 "VIM_INTPRIORITY_146" hexmask.long 0x248 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x248 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x24C "VIM_INTPRIORITY_147" hexmask.long 0x24C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x24C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x250 "VIM_INTPRIORITY_148" hexmask.long 0x250 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x250 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x254 "VIM_INTPRIORITY_149" hexmask.long 0x254 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x254 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x258 "VIM_INTPRIORITY_150" hexmask.long 0x258 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x258 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x25C "VIM_INTPRIORITY_151" hexmask.long 0x25C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x25C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x260 "VIM_INTPRIORITY_152" hexmask.long 0x260 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x260 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x264 "VIM_INTPRIORITY_153" hexmask.long 0x264 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x264 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x268 "VIM_INTPRIORITY_154" hexmask.long 0x268 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x268 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x26C "VIM_INTPRIORITY_155" hexmask.long 0x26C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x26C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x270 "VIM_INTPRIORITY_156" hexmask.long 0x270 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x270 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x274 "VIM_INTPRIORITY_157" hexmask.long 0x274 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x274 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x278 "VIM_INTPRIORITY_158" hexmask.long 0x278 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x278 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x27C "VIM_INTPRIORITY_159" hexmask.long 0x27C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x27C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x280 "VIM_INTPRIORITY_160" hexmask.long 0x280 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x280 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x284 "VIM_INTPRIORITY_161" hexmask.long 0x284 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x284 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x288 "VIM_INTPRIORITY_162" hexmask.long 0x288 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x288 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x28C "VIM_INTPRIORITY_163" hexmask.long 0x28C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x28C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x290 "VIM_INTPRIORITY_164" hexmask.long 0x290 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x290 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x294 "VIM_INTPRIORITY_165" hexmask.long 0x294 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x294 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x298 "VIM_INTPRIORITY_166" hexmask.long 0x298 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x298 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x29C "VIM_INTPRIORITY_167" hexmask.long 0x29C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x29C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2A0 "VIM_INTPRIORITY_168" hexmask.long 0x2A0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2A0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2A4 "VIM_INTPRIORITY_169" hexmask.long 0x2A4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2A4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2A8 "VIM_INTPRIORITY_170" hexmask.long 0x2A8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2A8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2AC "VIM_INTPRIORITY_171" hexmask.long 0x2AC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2AC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2B0 "VIM_INTPRIORITY_172" hexmask.long 0x2B0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2B0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2B4 "VIM_INTPRIORITY_173" hexmask.long 0x2B4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2B4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2B8 "VIM_INTPRIORITY_174" hexmask.long 0x2B8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2B8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2BC "VIM_INTPRIORITY_175" hexmask.long 0x2BC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2BC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2C0 "VIM_INTPRIORITY_176" hexmask.long 0x2C0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2C0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2C4 "VIM_INTPRIORITY_177" hexmask.long 0x2C4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2C4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2C8 "VIM_INTPRIORITY_178" hexmask.long 0x2C8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2C8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2CC "VIM_INTPRIORITY_179" hexmask.long 0x2CC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2CC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2D0 "VIM_INTPRIORITY_180" hexmask.long 0x2D0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2D0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2D4 "VIM_INTPRIORITY_181" hexmask.long 0x2D4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2D4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2D8 "VIM_INTPRIORITY_182" hexmask.long 0x2D8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2D8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2DC "VIM_INTPRIORITY_183" hexmask.long 0x2DC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2DC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2E0 "VIM_INTPRIORITY_184" hexmask.long 0x2E0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2E0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2E4 "VIM_INTPRIORITY_185" hexmask.long 0x2E4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2E4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2E8 "VIM_INTPRIORITY_186" hexmask.long 0x2E8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2E8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2EC "VIM_INTPRIORITY_187" hexmask.long 0x2EC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2EC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2F0 "VIM_INTPRIORITY_188" hexmask.long 0x2F0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2F0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2F4 "VIM_INTPRIORITY_189" hexmask.long 0x2F4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2F4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2F8 "VIM_INTPRIORITY_190" hexmask.long 0x2F8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2F8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x2FC "VIM_INTPRIORITY_191" hexmask.long 0x2FC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x2FC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x300 "VIM_INTPRIORITY_192" hexmask.long 0x300 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x300 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x304 "VIM_INTPRIORITY_193" hexmask.long 0x304 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x304 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x308 "VIM_INTPRIORITY_194" hexmask.long 0x308 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x308 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x30C "VIM_INTPRIORITY_195" hexmask.long 0x30C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x30C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x310 "VIM_INTPRIORITY_196" hexmask.long 0x310 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x310 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x314 "VIM_INTPRIORITY_197" hexmask.long 0x314 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x314 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x318 "VIM_INTPRIORITY_198" hexmask.long 0x318 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x318 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x31C "VIM_INTPRIORITY_199" hexmask.long 0x31C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x31C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x320 "VIM_INTPRIORITY_200" hexmask.long 0x320 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x320 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x324 "VIM_INTPRIORITY_201" hexmask.long 0x324 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x324 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x328 "VIM_INTPRIORITY_202" hexmask.long 0x328 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x328 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x32C "VIM_INTPRIORITY_203" hexmask.long 0x32C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x32C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x330 "VIM_INTPRIORITY_204" hexmask.long 0x330 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x330 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x334 "VIM_INTPRIORITY_205" hexmask.long 0x334 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x334 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x338 "VIM_INTPRIORITY_206" hexmask.long 0x338 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x338 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x33C "VIM_INTPRIORITY_207" hexmask.long 0x33C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x33C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x340 "VIM_INTPRIORITY_208" hexmask.long 0x340 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x340 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x344 "VIM_INTPRIORITY_209" hexmask.long 0x344 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x344 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x348 "VIM_INTPRIORITY_210" hexmask.long 0x348 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x348 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x34C "VIM_INTPRIORITY_211" hexmask.long 0x34C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x34C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x350 "VIM_INTPRIORITY_212" hexmask.long 0x350 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x350 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x354 "VIM_INTPRIORITY_213" hexmask.long 0x354 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x354 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x358 "VIM_INTPRIORITY_214" hexmask.long 0x358 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x358 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x35C "VIM_INTPRIORITY_215" hexmask.long 0x35C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x35C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x360 "VIM_INTPRIORITY_216" hexmask.long 0x360 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x360 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x364 "VIM_INTPRIORITY_217" hexmask.long 0x364 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x364 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x368 "VIM_INTPRIORITY_218" hexmask.long 0x368 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x368 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x36C "VIM_INTPRIORITY_219" hexmask.long 0x36C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x36C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x370 "VIM_INTPRIORITY_220" hexmask.long 0x370 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x370 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x374 "VIM_INTPRIORITY_221" hexmask.long 0x374 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x374 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x378 "VIM_INTPRIORITY_222" hexmask.long 0x378 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x378 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x37C "VIM_INTPRIORITY_223" hexmask.long 0x37C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x37C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x380 "VIM_INTPRIORITY_224" hexmask.long 0x380 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x380 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x384 "VIM_INTPRIORITY_225" hexmask.long 0x384 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x384 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x388 "VIM_INTPRIORITY_226" hexmask.long 0x388 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x388 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x38C "VIM_INTPRIORITY_227" hexmask.long 0x38C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x38C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x390 "VIM_INTPRIORITY_228" hexmask.long 0x390 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x390 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x394 "VIM_INTPRIORITY_229" hexmask.long 0x394 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x394 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x398 "VIM_INTPRIORITY_230" hexmask.long 0x398 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x398 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x39C "VIM_INTPRIORITY_231" hexmask.long 0x39C 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x39C 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3A0 "VIM_INTPRIORITY_232" hexmask.long 0x3A0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3A0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3A4 "VIM_INTPRIORITY_233" hexmask.long 0x3A4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3A4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3A8 "VIM_INTPRIORITY_234" hexmask.long 0x3A8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3A8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3AC "VIM_INTPRIORITY_235" hexmask.long 0x3AC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3AC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3B0 "VIM_INTPRIORITY_236" hexmask.long 0x3B0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3B0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3B4 "VIM_INTPRIORITY_237" hexmask.long 0x3B4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3B4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3B8 "VIM_INTPRIORITY_238" hexmask.long 0x3B8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3B8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3BC "VIM_INTPRIORITY_239" hexmask.long 0x3BC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3BC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3C0 "VIM_INTPRIORITY_240" hexmask.long 0x3C0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3C0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3C4 "VIM_INTPRIORITY_241" hexmask.long 0x3C4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3C4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3C8 "VIM_INTPRIORITY_242" hexmask.long 0x3C8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3C8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3CC "VIM_INTPRIORITY_243" hexmask.long 0x3CC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3CC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3D0 "VIM_INTPRIORITY_244" hexmask.long 0x3D0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3D0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3D4 "VIM_INTPRIORITY_245" hexmask.long 0x3D4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3D4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3D8 "VIM_INTPRIORITY_246" hexmask.long 0x3D8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3D8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3DC "VIM_INTPRIORITY_247" hexmask.long 0x3DC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3DC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3E0 "VIM_INTPRIORITY_248" hexmask.long 0x3E0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3E0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3E4 "VIM_INTPRIORITY_249" hexmask.long 0x3E4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3E4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3E8 "VIM_INTPRIORITY_250" hexmask.long 0x3E8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3E8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3EC "VIM_INTPRIORITY_251" hexmask.long 0x3EC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3EC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3F0 "VIM_INTPRIORITY_252" hexmask.long 0x3F0 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3F0 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3F4 "VIM_INTPRIORITY_253" hexmask.long 0x3F4 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3F4 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3F8 "VIM_INTPRIORITY_254" hexmask.long 0x3F8 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3F8 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" line.long 0x3FC "VIM_INTPRIORITY_255" hexmask.long 0x3FC 4.--31. 1. "RES19,RESERVE FIELD" hexmask.long.byte 0x3FC 0.--3. 1. "PRI,This is the priority for interrupt Q. If two interrupts have the same priority then whichever interrupt has the lower number Q wins arbitration 0 Highest Priority 15 Lowest Priority (Default)" group.long 0x2000++0x3FF line.long 0x0 "VIM_INTVECTOR" hexmask.long 0x0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x4 "VIM_INTVECTOR_1" hexmask.long 0x4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x8 "VIM_INTVECTOR_2" hexmask.long 0x8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xC "VIM_INTVECTOR_3" hexmask.long 0xC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x10 "VIM_INTVECTOR_4" hexmask.long 0x10 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x10 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x14 "VIM_INTVECTOR_5" hexmask.long 0x14 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x14 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x18 "VIM_INTVECTOR_6" hexmask.long 0x18 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x18 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1C "VIM_INTVECTOR_7" hexmask.long 0x1C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x20 "VIM_INTVECTOR_8" hexmask.long 0x20 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x20 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x24 "VIM_INTVECTOR_9" hexmask.long 0x24 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x24 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x28 "VIM_INTVECTOR_10" hexmask.long 0x28 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x28 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2C "VIM_INTVECTOR_11" hexmask.long 0x2C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x30 "VIM_INTVECTOR_12" hexmask.long 0x30 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x30 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x34 "VIM_INTVECTOR_13" hexmask.long 0x34 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x34 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x38 "VIM_INTVECTOR_14" hexmask.long 0x38 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x38 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3C "VIM_INTVECTOR_15" hexmask.long 0x3C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x40 "VIM_INTVECTOR_16" hexmask.long 0x40 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x40 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x44 "VIM_INTVECTOR_17" hexmask.long 0x44 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x44 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x48 "VIM_INTVECTOR_18" hexmask.long 0x48 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x48 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x4C "VIM_INTVECTOR_19" hexmask.long 0x4C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x4C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x50 "VIM_INTVECTOR_20" hexmask.long 0x50 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x50 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x54 "VIM_INTVECTOR_21" hexmask.long 0x54 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x54 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x58 "VIM_INTVECTOR_22" hexmask.long 0x58 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x58 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x5C "VIM_INTVECTOR_23" hexmask.long 0x5C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x5C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x60 "VIM_INTVECTOR_24" hexmask.long 0x60 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x60 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x64 "VIM_INTVECTOR_25" hexmask.long 0x64 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x64 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x68 "VIM_INTVECTOR_26" hexmask.long 0x68 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x68 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x6C "VIM_INTVECTOR_27" hexmask.long 0x6C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x6C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x70 "VIM_INTVECTOR_28" hexmask.long 0x70 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x70 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x74 "VIM_INTVECTOR_29" hexmask.long 0x74 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x74 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x78 "VIM_INTVECTOR_30" hexmask.long 0x78 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x78 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x7C "VIM_INTVECTOR_31" hexmask.long 0x7C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x7C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x80 "VIM_INTVECTOR_32" hexmask.long 0x80 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x80 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x84 "VIM_INTVECTOR_33" hexmask.long 0x84 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x84 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x88 "VIM_INTVECTOR_34" hexmask.long 0x88 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x88 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x8C "VIM_INTVECTOR_35" hexmask.long 0x8C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x8C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x90 "VIM_INTVECTOR_36" hexmask.long 0x90 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x90 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x94 "VIM_INTVECTOR_37" hexmask.long 0x94 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x94 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x98 "VIM_INTVECTOR_38" hexmask.long 0x98 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x98 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x9C "VIM_INTVECTOR_39" hexmask.long 0x9C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x9C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xA0 "VIM_INTVECTOR_40" hexmask.long 0xA0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xA0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xA4 "VIM_INTVECTOR_41" hexmask.long 0xA4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xA4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xA8 "VIM_INTVECTOR_42" hexmask.long 0xA8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xA8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xAC "VIM_INTVECTOR_43" hexmask.long 0xAC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xAC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xB0 "VIM_INTVECTOR_44" hexmask.long 0xB0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xB0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xB4 "VIM_INTVECTOR_45" hexmask.long 0xB4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xB4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xB8 "VIM_INTVECTOR_46" hexmask.long 0xB8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xB8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xBC "VIM_INTVECTOR_47" hexmask.long 0xBC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xBC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xC0 "VIM_INTVECTOR_48" hexmask.long 0xC0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xC0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xC4 "VIM_INTVECTOR_49" hexmask.long 0xC4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xC4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xC8 "VIM_INTVECTOR_50" hexmask.long 0xC8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xC8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xCC "VIM_INTVECTOR_51" hexmask.long 0xCC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xCC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xD0 "VIM_INTVECTOR_52" hexmask.long 0xD0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xD0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xD4 "VIM_INTVECTOR_53" hexmask.long 0xD4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xD4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xD8 "VIM_INTVECTOR_54" hexmask.long 0xD8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xD8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xDC "VIM_INTVECTOR_55" hexmask.long 0xDC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xDC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xE0 "VIM_INTVECTOR_56" hexmask.long 0xE0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xE0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xE4 "VIM_INTVECTOR_57" hexmask.long 0xE4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xE4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xE8 "VIM_INTVECTOR_58" hexmask.long 0xE8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xE8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xEC "VIM_INTVECTOR_59" hexmask.long 0xEC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xEC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xF0 "VIM_INTVECTOR_60" hexmask.long 0xF0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xF0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xF4 "VIM_INTVECTOR_61" hexmask.long 0xF4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xF4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xF8 "VIM_INTVECTOR_62" hexmask.long 0xF8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xF8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0xFC "VIM_INTVECTOR_63" hexmask.long 0xFC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0xFC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x100 "VIM_INTVECTOR_64" hexmask.long 0x100 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x100 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x104 "VIM_INTVECTOR_65" hexmask.long 0x104 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x104 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x108 "VIM_INTVECTOR_66" hexmask.long 0x108 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x108 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x10C "VIM_INTVECTOR_67" hexmask.long 0x10C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x10C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x110 "VIM_INTVECTOR_68" hexmask.long 0x110 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x110 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x114 "VIM_INTVECTOR_69" hexmask.long 0x114 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x114 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x118 "VIM_INTVECTOR_70" hexmask.long 0x118 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x118 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x11C "VIM_INTVECTOR_71" hexmask.long 0x11C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x11C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x120 "VIM_INTVECTOR_72" hexmask.long 0x120 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x120 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x124 "VIM_INTVECTOR_73" hexmask.long 0x124 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x124 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x128 "VIM_INTVECTOR_74" hexmask.long 0x128 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x128 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x12C "VIM_INTVECTOR_75" hexmask.long 0x12C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x12C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x130 "VIM_INTVECTOR_76" hexmask.long 0x130 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x130 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x134 "VIM_INTVECTOR_77" hexmask.long 0x134 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x134 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x138 "VIM_INTVECTOR_78" hexmask.long 0x138 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x138 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x13C "VIM_INTVECTOR_79" hexmask.long 0x13C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x13C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x140 "VIM_INTVECTOR_80" hexmask.long 0x140 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x140 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x144 "VIM_INTVECTOR_81" hexmask.long 0x144 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x144 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x148 "VIM_INTVECTOR_82" hexmask.long 0x148 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x148 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x14C "VIM_INTVECTOR_83" hexmask.long 0x14C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x14C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x150 "VIM_INTVECTOR_84" hexmask.long 0x150 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x150 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x154 "VIM_INTVECTOR_85" hexmask.long 0x154 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x154 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x158 "VIM_INTVECTOR_86" hexmask.long 0x158 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x158 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x15C "VIM_INTVECTOR_87" hexmask.long 0x15C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x15C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x160 "VIM_INTVECTOR_88" hexmask.long 0x160 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x160 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x164 "VIM_INTVECTOR_89" hexmask.long 0x164 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x164 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x168 "VIM_INTVECTOR_90" hexmask.long 0x168 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x168 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x16C "VIM_INTVECTOR_91" hexmask.long 0x16C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x16C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x170 "VIM_INTVECTOR_92" hexmask.long 0x170 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x170 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x174 "VIM_INTVECTOR_93" hexmask.long 0x174 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x174 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x178 "VIM_INTVECTOR_94" hexmask.long 0x178 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x178 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x17C "VIM_INTVECTOR_95" hexmask.long 0x17C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x17C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x180 "VIM_INTVECTOR_96" hexmask.long 0x180 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x180 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x184 "VIM_INTVECTOR_97" hexmask.long 0x184 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x184 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x188 "VIM_INTVECTOR_98" hexmask.long 0x188 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x188 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x18C "VIM_INTVECTOR_99" hexmask.long 0x18C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x18C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x190 "VIM_INTVECTOR_100" hexmask.long 0x190 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x190 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x194 "VIM_INTVECTOR_101" hexmask.long 0x194 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x194 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x198 "VIM_INTVECTOR_102" hexmask.long 0x198 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x198 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x19C "VIM_INTVECTOR_103" hexmask.long 0x19C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x19C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1A0 "VIM_INTVECTOR_104" hexmask.long 0x1A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1A0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1A4 "VIM_INTVECTOR_105" hexmask.long 0x1A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1A4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1A8 "VIM_INTVECTOR_106" hexmask.long 0x1A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1A8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1AC "VIM_INTVECTOR_107" hexmask.long 0x1AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1AC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1B0 "VIM_INTVECTOR_108" hexmask.long 0x1B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1B0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1B4 "VIM_INTVECTOR_109" hexmask.long 0x1B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1B4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1B8 "VIM_INTVECTOR_110" hexmask.long 0x1B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1B8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1BC "VIM_INTVECTOR_111" hexmask.long 0x1BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1BC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1C0 "VIM_INTVECTOR_112" hexmask.long 0x1C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1C0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1C4 "VIM_INTVECTOR_113" hexmask.long 0x1C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1C4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1C8 "VIM_INTVECTOR_114" hexmask.long 0x1C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1C8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1CC "VIM_INTVECTOR_115" hexmask.long 0x1CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1CC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1D0 "VIM_INTVECTOR_116" hexmask.long 0x1D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1D0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1D4 "VIM_INTVECTOR_117" hexmask.long 0x1D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1D4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1D8 "VIM_INTVECTOR_118" hexmask.long 0x1D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1D8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1DC "VIM_INTVECTOR_119" hexmask.long 0x1DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1DC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1E0 "VIM_INTVECTOR_120" hexmask.long 0x1E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1E0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1E4 "VIM_INTVECTOR_121" hexmask.long 0x1E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1E4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1E8 "VIM_INTVECTOR_122" hexmask.long 0x1E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1E8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1EC "VIM_INTVECTOR_123" hexmask.long 0x1EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1EC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1F0 "VIM_INTVECTOR_124" hexmask.long 0x1F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1F0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1F4 "VIM_INTVECTOR_125" hexmask.long 0x1F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1F4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1F8 "VIM_INTVECTOR_126" hexmask.long 0x1F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1F8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x1FC "VIM_INTVECTOR_127" hexmask.long 0x1FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x1FC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x200 "VIM_INTVECTOR_128" hexmask.long 0x200 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x200 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x204 "VIM_INTVECTOR_129" hexmask.long 0x204 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x204 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x208 "VIM_INTVECTOR_130" hexmask.long 0x208 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x208 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x20C "VIM_INTVECTOR_131" hexmask.long 0x20C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x20C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x210 "VIM_INTVECTOR_132" hexmask.long 0x210 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x210 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x214 "VIM_INTVECTOR_133" hexmask.long 0x214 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x214 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x218 "VIM_INTVECTOR_134" hexmask.long 0x218 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x218 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x21C "VIM_INTVECTOR_135" hexmask.long 0x21C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x21C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x220 "VIM_INTVECTOR_136" hexmask.long 0x220 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x220 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x224 "VIM_INTVECTOR_137" hexmask.long 0x224 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x224 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x228 "VIM_INTVECTOR_138" hexmask.long 0x228 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x228 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x22C "VIM_INTVECTOR_139" hexmask.long 0x22C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x22C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x230 "VIM_INTVECTOR_140" hexmask.long 0x230 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x230 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x234 "VIM_INTVECTOR_141" hexmask.long 0x234 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x234 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x238 "VIM_INTVECTOR_142" hexmask.long 0x238 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x238 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x23C "VIM_INTVECTOR_143" hexmask.long 0x23C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x23C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x240 "VIM_INTVECTOR_144" hexmask.long 0x240 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x240 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x244 "VIM_INTVECTOR_145" hexmask.long 0x244 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x244 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x248 "VIM_INTVECTOR_146" hexmask.long 0x248 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x248 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x24C "VIM_INTVECTOR_147" hexmask.long 0x24C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x24C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x250 "VIM_INTVECTOR_148" hexmask.long 0x250 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x250 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x254 "VIM_INTVECTOR_149" hexmask.long 0x254 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x254 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x258 "VIM_INTVECTOR_150" hexmask.long 0x258 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x258 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x25C "VIM_INTVECTOR_151" hexmask.long 0x25C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x25C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x260 "VIM_INTVECTOR_152" hexmask.long 0x260 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x260 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x264 "VIM_INTVECTOR_153" hexmask.long 0x264 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x264 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x268 "VIM_INTVECTOR_154" hexmask.long 0x268 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x268 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x26C "VIM_INTVECTOR_155" hexmask.long 0x26C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x26C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x270 "VIM_INTVECTOR_156" hexmask.long 0x270 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x270 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x274 "VIM_INTVECTOR_157" hexmask.long 0x274 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x274 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x278 "VIM_INTVECTOR_158" hexmask.long 0x278 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x278 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x27C "VIM_INTVECTOR_159" hexmask.long 0x27C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x27C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x280 "VIM_INTVECTOR_160" hexmask.long 0x280 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x280 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x284 "VIM_INTVECTOR_161" hexmask.long 0x284 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x284 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x288 "VIM_INTVECTOR_162" hexmask.long 0x288 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x288 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x28C "VIM_INTVECTOR_163" hexmask.long 0x28C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x28C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x290 "VIM_INTVECTOR_164" hexmask.long 0x290 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x290 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x294 "VIM_INTVECTOR_165" hexmask.long 0x294 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x294 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x298 "VIM_INTVECTOR_166" hexmask.long 0x298 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x298 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x29C "VIM_INTVECTOR_167" hexmask.long 0x29C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x29C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2A0 "VIM_INTVECTOR_168" hexmask.long 0x2A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2A0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2A4 "VIM_INTVECTOR_169" hexmask.long 0x2A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2A4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2A8 "VIM_INTVECTOR_170" hexmask.long 0x2A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2A8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2AC "VIM_INTVECTOR_171" hexmask.long 0x2AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2AC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2B0 "VIM_INTVECTOR_172" hexmask.long 0x2B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2B0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2B4 "VIM_INTVECTOR_173" hexmask.long 0x2B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2B4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2B8 "VIM_INTVECTOR_174" hexmask.long 0x2B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2B8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2BC "VIM_INTVECTOR_175" hexmask.long 0x2BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2BC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2C0 "VIM_INTVECTOR_176" hexmask.long 0x2C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2C0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2C4 "VIM_INTVECTOR_177" hexmask.long 0x2C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2C4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2C8 "VIM_INTVECTOR_178" hexmask.long 0x2C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2C8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2CC "VIM_INTVECTOR_179" hexmask.long 0x2CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2CC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2D0 "VIM_INTVECTOR_180" hexmask.long 0x2D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2D0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2D4 "VIM_INTVECTOR_181" hexmask.long 0x2D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2D4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2D8 "VIM_INTVECTOR_182" hexmask.long 0x2D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2D8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2DC "VIM_INTVECTOR_183" hexmask.long 0x2DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2DC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2E0 "VIM_INTVECTOR_184" hexmask.long 0x2E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2E0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2E4 "VIM_INTVECTOR_185" hexmask.long 0x2E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2E4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2E8 "VIM_INTVECTOR_186" hexmask.long 0x2E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2E8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2EC "VIM_INTVECTOR_187" hexmask.long 0x2EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2EC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2F0 "VIM_INTVECTOR_188" hexmask.long 0x2F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2F0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2F4 "VIM_INTVECTOR_189" hexmask.long 0x2F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2F4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2F8 "VIM_INTVECTOR_190" hexmask.long 0x2F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2F8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x2FC "VIM_INTVECTOR_191" hexmask.long 0x2FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x2FC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x300 "VIM_INTVECTOR_192" hexmask.long 0x300 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x300 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x304 "VIM_INTVECTOR_193" hexmask.long 0x304 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x304 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x308 "VIM_INTVECTOR_194" hexmask.long 0x308 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x308 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x30C "VIM_INTVECTOR_195" hexmask.long 0x30C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x30C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x310 "VIM_INTVECTOR_196" hexmask.long 0x310 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x310 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x314 "VIM_INTVECTOR_197" hexmask.long 0x314 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x314 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x318 "VIM_INTVECTOR_198" hexmask.long 0x318 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x318 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x31C "VIM_INTVECTOR_199" hexmask.long 0x31C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x31C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x320 "VIM_INTVECTOR_200" hexmask.long 0x320 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x320 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x324 "VIM_INTVECTOR_201" hexmask.long 0x324 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x324 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x328 "VIM_INTVECTOR_202" hexmask.long 0x328 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x328 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x32C "VIM_INTVECTOR_203" hexmask.long 0x32C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x32C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x330 "VIM_INTVECTOR_204" hexmask.long 0x330 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x330 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x334 "VIM_INTVECTOR_205" hexmask.long 0x334 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x334 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x338 "VIM_INTVECTOR_206" hexmask.long 0x338 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x338 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x33C "VIM_INTVECTOR_207" hexmask.long 0x33C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x33C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x340 "VIM_INTVECTOR_208" hexmask.long 0x340 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x340 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x344 "VIM_INTVECTOR_209" hexmask.long 0x344 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x344 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x348 "VIM_INTVECTOR_210" hexmask.long 0x348 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x348 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x34C "VIM_INTVECTOR_211" hexmask.long 0x34C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x34C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x350 "VIM_INTVECTOR_212" hexmask.long 0x350 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x350 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x354 "VIM_INTVECTOR_213" hexmask.long 0x354 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x354 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x358 "VIM_INTVECTOR_214" hexmask.long 0x358 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x358 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x35C "VIM_INTVECTOR_215" hexmask.long 0x35C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x35C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x360 "VIM_INTVECTOR_216" hexmask.long 0x360 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x360 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x364 "VIM_INTVECTOR_217" hexmask.long 0x364 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x364 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x368 "VIM_INTVECTOR_218" hexmask.long 0x368 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x368 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x36C "VIM_INTVECTOR_219" hexmask.long 0x36C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x36C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x370 "VIM_INTVECTOR_220" hexmask.long 0x370 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x370 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x374 "VIM_INTVECTOR_221" hexmask.long 0x374 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x374 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x378 "VIM_INTVECTOR_222" hexmask.long 0x378 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x378 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x37C "VIM_INTVECTOR_223" hexmask.long 0x37C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x37C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x380 "VIM_INTVECTOR_224" hexmask.long 0x380 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x380 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x384 "VIM_INTVECTOR_225" hexmask.long 0x384 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x384 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x388 "VIM_INTVECTOR_226" hexmask.long 0x388 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x388 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x38C "VIM_INTVECTOR_227" hexmask.long 0x38C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x38C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x390 "VIM_INTVECTOR_228" hexmask.long 0x390 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x390 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x394 "VIM_INTVECTOR_229" hexmask.long 0x394 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x394 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x398 "VIM_INTVECTOR_230" hexmask.long 0x398 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x398 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x39C "VIM_INTVECTOR_231" hexmask.long 0x39C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x39C 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3A0 "VIM_INTVECTOR_232" hexmask.long 0x3A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3A0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3A4 "VIM_INTVECTOR_233" hexmask.long 0x3A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3A4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3A8 "VIM_INTVECTOR_234" hexmask.long 0x3A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3A8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3AC "VIM_INTVECTOR_235" hexmask.long 0x3AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3AC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3B0 "VIM_INTVECTOR_236" hexmask.long 0x3B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3B0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3B4 "VIM_INTVECTOR_237" hexmask.long 0x3B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3B4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3B8 "VIM_INTVECTOR_238" hexmask.long 0x3B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3B8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3BC "VIM_INTVECTOR_239" hexmask.long 0x3BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3BC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3C0 "VIM_INTVECTOR_240" hexmask.long 0x3C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3C0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3C4 "VIM_INTVECTOR_241" hexmask.long 0x3C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3C4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3C8 "VIM_INTVECTOR_242" hexmask.long 0x3C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3C8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3CC "VIM_INTVECTOR_243" hexmask.long 0x3CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3CC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3D0 "VIM_INTVECTOR_244" hexmask.long 0x3D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3D0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3D4 "VIM_INTVECTOR_245" hexmask.long 0x3D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3D4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3D8 "VIM_INTVECTOR_246" hexmask.long 0x3D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3D8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3DC "VIM_INTVECTOR_247" hexmask.long 0x3DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3DC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3E0 "VIM_INTVECTOR_248" hexmask.long 0x3E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3E0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3E4 "VIM_INTVECTOR_249" hexmask.long 0x3E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3E4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3E8 "VIM_INTVECTOR_250" hexmask.long 0x3E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3E8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3EC "VIM_INTVECTOR_251" hexmask.long 0x3EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3EC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3F0 "VIM_INTVECTOR_252" hexmask.long 0x3F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3F0 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3F4 "VIM_INTVECTOR_253" hexmask.long 0x3F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3F4 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3F8 "VIM_INTVECTOR_254" hexmask.long 0x3F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3F8 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" line.long 0x3FC "VIM_INTVECTOR_255" hexmask.long 0x3FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address (Base Address + 0x18) or FIQ Vector Address (Base Address + 0x1C) and the VECADDR pin when interrupt Q is the active.." rbitfld.long 0x3FC 0.--1. "RES20,Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned." "0,1,2,3" tree.end tree "WDT" base ad:0x0 tree "WDT0" base ad:0x52100000 group.long 0x0++0x1B line.long 0x0 "WDT0_RTIGCTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode (read):0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "WDT0_RTITBCTRL" bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode (read):0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "WDT0_RTICAPCTRL" hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "WDT0_RTICOMPCTRL" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "WDT0_RTIFRC0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x14 "WDT0_RTIUC0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "WDT0_RTICPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "WDT0_RTICAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 0 on.." line.long 0x4 "WDT0_RTICAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "WDT0_RTIFRC1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x4 "WDT0_RTIUC1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "WDT0_RTICPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "WDT0_RTICAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 1 on.." line.long 0x4 "WDT0_RTICAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "WDT0_RTICOMP0" hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "WDT0_RTIUDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "WDT0_RTICOMP1" hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "WDT0_RTIUDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "WDT0_RTICOMP2" hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "WDT0_RTIUDCP2" hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "WDT0_RTICOMP3" hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "WDT0_RTIUDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "WDT0_RTITBLCOMP" hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode (read):current compare valuePrivilege mode (write when.." line.long 0x24 "WDT0_RTITBHCOMP" hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "WDT0_RTISETINT" hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "WDT0_RTICLEARINT" hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "WDT0_RTIINTFLAG" hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read):this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "WDT0_RTIDWDCTRL" hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode (read):0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged (enabled or disabled)Priviledge.." line.long 0x4 "WDT0_RTIDWDPRLD" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode (read):A read from this register in any CPU mode returns the current preload value.Priviledge mode (write):If the DWD is always enabled after reset is released:The DWD starts.." line.long 0x8 "WDT0_RTIWDSTATUS" hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode (read):0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode (read):0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode (read):0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode (read):0 = AWD pin 0 ?> 1 threshold not exceeded1 = AWD pin 0 ?> 1 threshold exceededPriviledge mode (write):0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "WDT0_RTIWDKEY" hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode (write):A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "WDT0_RTIDWDCNTR" hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "WDT0_RTIWWDRXNCTRL" hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode (read) privileged mode (write):0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "WDT0_RTIWWDSIZECTRL" hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode (read) privileged mode (write):Value written to WWDSIZE Window Size0x00000005 100% (Functionality same as the time-out digital.." line.long 0x1C "WDT0_RTIINTCLRENABLE" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "WDT0_RTICOMP0CLR" hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "WDT0_RTICOMP1CLR" hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "WDT0_RTICOMP2CLR" hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "WDT0_RTICOMP3CLR" hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "WDT1" base ad:0x52101000 group.long 0x0++0x1B line.long 0x0 "WDT1_RTIGCTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode (read):0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "WDT1_RTITBCTRL" bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode (read):0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "WDT1_RTICAPCTRL" hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "WDT1_RTICOMPCTRL" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "WDT1_RTIFRC0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x14 "WDT1_RTIUC0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "WDT1_RTICPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "WDT1_RTICAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 0 on.." line.long 0x4 "WDT1_RTICAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "WDT1_RTIFRC1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x4 "WDT1_RTIUC1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "WDT1_RTICPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "WDT1_RTICAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 1 on.." line.long 0x4 "WDT1_RTICAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "WDT1_RTICOMP0" hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "WDT1_RTIUDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "WDT1_RTICOMP1" hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "WDT1_RTIUDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "WDT1_RTICOMP2" hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "WDT1_RTIUDCP2" hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "WDT1_RTICOMP3" hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "WDT1_RTIUDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "WDT1_RTITBLCOMP" hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode (read):current compare valuePrivilege mode (write when.." line.long 0x24 "WDT1_RTITBHCOMP" hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "WDT1_RTISETINT" hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "WDT1_RTICLEARINT" hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "WDT1_RTIINTFLAG" hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read):this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "WDT1_RTIDWDCTRL" hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode (read):0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged (enabled or disabled)Priviledge.." line.long 0x4 "WDT1_RTIDWDPRLD" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode (read):A read from this register in any CPU mode returns the current preload value.Priviledge mode (write):If the DWD is always enabled after reset is released:The DWD starts.." line.long 0x8 "WDT1_RTIWDSTATUS" hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode (read):0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode (read):0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode (read):0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode (read):0 = AWD pin 0 ?> 1 threshold not exceeded1 = AWD pin 0 ?> 1 threshold exceededPriviledge mode (write):0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "WDT1_RTIWDKEY" hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode (write):A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "WDT1_RTIDWDCNTR" hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "WDT1_RTIWWDRXNCTRL" hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode (read) privileged mode (write):0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "WDT1_RTIWWDSIZECTRL" hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode (read) privileged mode (write):Value written to WWDSIZE Window Size0x00000005 100% (Functionality same as the time-out digital.." line.long 0x1C "WDT1_RTIINTCLRENABLE" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "WDT1_RTICOMP0CLR" hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "WDT1_RTICOMP1CLR" hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "WDT1_RTICOMP2CLR" hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "WDT1_RTICOMP3CLR" hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "WDT2" base ad:0x52102000 group.long 0x0++0x1B line.long 0x0 "WDT2_RTIGCTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode (read):0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "WDT2_RTITBCTRL" bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode (read):0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "WDT2_RTICAPCTRL" hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "WDT2_RTICOMPCTRL" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "WDT2_RTIFRC0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x14 "WDT2_RTIUC0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "WDT2_RTICPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "WDT2_RTICAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 0 on.." line.long 0x4 "WDT2_RTICAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "WDT2_RTIFRC1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x4 "WDT2_RTIUC1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "WDT2_RTICPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "WDT2_RTICAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 1 on.." line.long 0x4 "WDT2_RTICAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "WDT2_RTICOMP0" hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "WDT2_RTIUDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "WDT2_RTICOMP1" hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "WDT2_RTIUDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "WDT2_RTICOMP2" hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "WDT2_RTIUDCP2" hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "WDT2_RTICOMP3" hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "WDT2_RTIUDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "WDT2_RTITBLCOMP" hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode (read):current compare valuePrivilege mode (write when.." line.long 0x24 "WDT2_RTITBHCOMP" hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "WDT2_RTISETINT" hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "WDT2_RTICLEARINT" hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "WDT2_RTIINTFLAG" hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read):this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "WDT2_RTIDWDCTRL" hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode (read):0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged (enabled or disabled)Priviledge.." line.long 0x4 "WDT2_RTIDWDPRLD" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode (read):A read from this register in any CPU mode returns the current preload value.Priviledge mode (write):If the DWD is always enabled after reset is released:The DWD starts.." line.long 0x8 "WDT2_RTIWDSTATUS" hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode (read):0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode (read):0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode (read):0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode (read):0 = AWD pin 0 ?> 1 threshold not exceeded1 = AWD pin 0 ?> 1 threshold exceededPriviledge mode (write):0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "WDT2_RTIWDKEY" hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode (write):A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "WDT2_RTIDWDCNTR" hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "WDT2_RTIWWDRXNCTRL" hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode (read) privileged mode (write):0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "WDT2_RTIWWDSIZECTRL" hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode (read) privileged mode (write):Value written to WWDSIZE Window Size0x00000005 100% (Functionality same as the time-out digital.." line.long 0x1C "WDT2_RTIINTCLRENABLE" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "WDT2_RTICOMP0CLR" hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "WDT2_RTICOMP1CLR" hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "WDT2_RTICOMP2CLR" hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "WDT2_RTICOMP3CLR" hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree "WDT3" base ad:0x52103000 group.long 0x0++0x1B line.long 0x0 "WDT3_RTIGCTRL" hexmask.long.word 0x0 20.--31. 1. "RESERVED2,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x0 16.--19. 1. "NTUSEL,NTUSEL: Select NTU signal.These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will.." newline bitfld.long 0x0 15. "COS,COS: Continue On Suspend.This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting.User and privilege mode (read):0 = counters are stopped while in debug mode1 = counters are running while in.." "0: stop counters in debug mode1 = continue counting..,?" newline hexmask.long.word 0x0 2.--14. 1. "RESERVED1,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 1. "CNT1EN,CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start.." "0: stop counters1 = start countersGives the..,?" newline bitfld.long 0x0 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0).User and privilege mode (read):0 = counters are stopped1 = counters are runningPrivilege mode (write):0 = stop counters1 = start countersGives.." "0: stop counters1 = start countersGives the..,?" line.long 0x4 "WDT3_RTITBCTRL" bitfld.long 0x4 1. "INC,INC: Increment Free Running Counter 0.This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected.User and privilege mode (read):0 = FRC0 will not be incremented1 = FRC0 will be.." "0: Do not increment FRC0 on failing external clock1..,?" newline bitfld.long 0x4 0. "TBEXT,TBEXT: Timebase External.The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0 Free Running Counter 0.." "0: MUX is switched to internal UC0 clocking scheme1..,?" line.long 0x8 "WDT3_RTICAPCTRL" hexmask.long 0x8 2.--31. 1. "RESERVED4,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1.This bit determines which external interrupt source triggers a capture event of both UC1 and FRC1.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." newline bitfld.long 0x8 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0.This bit determines which external interrupt source triggers a capture event of both UC0 and FRC0.User and privilege mode (read):0 = capture event is triggered by Capture Event Source 01 = capture event is triggered.." "0: enable capture event triggered by Capture Event..,1: enable capture event triggered by Capture Event.." line.long 0xC "WDT3_RTICOMPCTRL" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED8,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0xC 12. "COMP3SEL,COMPSEL3: Compare Select 3.This bit determines the counter with which the compare value hold in compare register 3 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 9.--11. "RESERVED7,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 8. "COMP2SEL,COMPSEL2: Compare Select 2.This bit determines the counter with which the compare value hold in compare register 2 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 5.--7. "RESERVED6,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 4. "COMP1SEL,COMPSEL1: Compare Select 1.This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" newline bitfld.long 0xC 1.--3. "RESERVED5,Reserved.Reads return 0 and writes have no effect" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "COMP0SEL,COMPSEL0: Compare Select 0.This bit determines the counter with which the compare value hold in compare register 0 is compared.User and privilege mode (read):0 = value will be compared with FRC 01 = value will be compared with FRC 1Privilege.." "0: enable compare with FRC,1: enable compare with FRC 1" line.long 0x10 "WDT3_RTIFRC0" hexmask.long 0x10 0.--31. 1. "FRC0,FRC0: Free Running Counter 0.This registers holds the current value of the Free Running Counter 0 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x14 "WDT3_RTIUC0" hexmask.long 0x14 0.--31. 1. "UC0,UC0: Up Counter 0.This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters without having the.." line.long 0x18 "WDT3_RTICPUC0" hexmask.long 0x18 0.--31. 1. "CPUC0,This registers holds the compare value which is compared with the Up Counter 0. When the compare matches Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this.." group.long 0x20++0x7 line.long 0x0 "WDT3_RTICAFRC0" hexmask.long 0x0 0.--31. 1. "CAFRC0,CAFRC0: Capture Free Running Counter 0.This registers captures the current value of the Free Running Counter 0 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 0 on.." line.long 0x4 "WDT3_RTICAUC0" hexmask.long 0x4 0.--31. 1. "CAUC0,CAUC0: Capture Up Counter 0.This registers captures the current value of the Up Counter 0 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0." group.long 0x30++0xB line.long 0x0 "WDT3_RTIFRC1" hexmask.long 0x0 0.--31. 1. "FRC1,FRC1: Free Running Counter 1.This registers holds the current value of the Free Running Counter 1 and will be updated continuously.User and privilege mode (read):current value of the counterPrivilege mode (write):The counter can be preset by writing.." line.long 0x4 "WDT3_RTIUC1" hexmask.long 0x4 0.--31. 1. "UC1,UC1: Up Counter 1.This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters without having the.." line.long 0x8 "WDT3_RTICPUC1" hexmask.long 0x8 0.--31. 1. "CPUC1,This registers holds the compare value which is compared with the Up Counter 1. When the compare matches Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this.." group.long 0x40++0x7 line.long 0x0 "WDT3_RTICAFRC1" hexmask.long 0x0 0.--31. 1. "CAFRC1,CAFRC1: Capture Free Running Counter 1.This registers captures the current value of the Free Running Counter 1 when a event occurs controlled by the external capture control block.User and privilege mode (read):value of Free Running Counter 1 on.." line.long 0x4 "WDT3_RTICAUC1" hexmask.long 0x4 0.--31. 1. "CAUC1,CAUC1: Capture Up Counter 1.This registers captures the current value of the Up Counter 1 when a event occurs controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1." group.long 0x50++0x27 line.long 0x0 "WDT3_RTICOMP0" hexmask.long 0x0 0.--31. 1. "COMP0,COMP0: Compare 0.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x4 "WDT3_RTIUDCP0" hexmask.long 0x4 0.--31. 1. "UDCP0,UDCP0: Update Compare 0 Register.This registers holds a value which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x8 "WDT3_RTICOMP1" hexmask.long 0x8 0.--31. 1. "COMP1,COMP1: compare1.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0xC "WDT3_RTIUDCP1" hexmask.long 0xC 0.--31. 1. "UDCP1,UDCP1: Update compare1 Register.This registers holds a value which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x10 "WDT3_RTICOMP2" hexmask.long 0x10 0.--31. 1. "COMP2,COMP2: compare 2.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x14 "WDT3_RTIUDCP2" hexmask.long 0x14 0.--31. 1. "UDCP2,UDCP2: Update compare 2 Register.This registers holds a value which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x18 "WDT3_RTICOMP3" hexmask.long 0x18 0.--31. 1. "COMP3,COMP3: compare 3.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value an interrupt is flagged. With this register it is also possible.." line.long 0x1C "WDT3_RTIUDCP3" hexmask.long 0x1C 0.--31. 1. "UDCP3,UDCP3: Update compare 3 Register.This registers holds a value which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention.User and.." line.long 0x20 "WDT3_RTITBLCOMP" hexmask.long 0x20 0.--31. 1. "TBLCOMP,TBLCOMP: Timebase Low Compare Value.This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0.User and privilege mode (read):current compare valuePrivilege mode (write when.." line.long 0x24 "WDT3_RTITBHCOMP" hexmask.long 0x24 0.--31. 1. "TBHCOMP,TBHCOMP: Timebase High Compare Value.This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0.RTITBHCOMP has to be less than RTICPUC0 since RTIUC0 will be reset when.." group.long 0x80++0xB line.long 0x0 "WDT3_RTISETINT" hexmask.long.word 0x0 19.--31. 1. "RESERVED11,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 16. "SETTBINT,SETTBINT: Set Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED10,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable DMA request" "0: leaves the corresponding bit unchanged1 = enable..,?" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED9,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x0 3. "SETINT3,SETINT3: Set Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged" "0: leaves the corresponding bit unchanged,?" newline bitfld.long 0x0 2. "SETINT2,SETINT2: Set Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 1. "SETINT1,SETINT1: Set Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" newline bitfld.long 0x0 0. "SETINT0,SETINT0: Set Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = enable interrupt" "0: leaves the corresponding bit unchanged1 = enable..,?" line.long 0x4 "WDT3_RTICLEARINT" hexmask.long.word 0x4 19.--31. 1. "RESERVED14,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED13,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0.User and privilege mode (read):0 = DMA request is disabled1 = DMA request is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable DMA request" "0: leaves the corresponding bit unchanged1 =..,?" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED12,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x4 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" newline bitfld.long 0x4 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0.User and privilege mode (read):0 = interrupt is disabled1 = interrupt is enabledPrivilege mode (write):0 = leaves the corresponding bit unchanged1 = disable interrupt" "0: leaves the corresponding bit unchanged1 =..,?" line.long 0x8 "WDT3_RTIINTFLAG" hexmask.long.word 0x8 19.--31. 1. "RESERVED16,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag.User and privilege mode (read):determines if an interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 16. "TBINT,User and privilege mode (read):this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software.determines if an interrupt is pending0 = no interrupt pending1 = interrupt.." "0: leaves the bit unchanged1 = set the bit to 0,?" newline hexmask.long.word 0x8 4.--15. 1. "RESERVED15,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 3. "INT3,INT3: Interrupt Flag 3.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 2. "INT2,INT2: Interrupt Flag 2.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 1. "INT1,INT1: Interrupt Flag 1.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" newline bitfld.long 0x8 0. "INT0,INT0: Interrupt Flag 0.User and privilege mode (read):determines if a interrupt is pending0 = no interrupt pending1 = interrupt pendingPrivilege mode (write):0 = leaves the bit unchanged1 = set the bit to 0" "0: leaves the bit unchanged1 = set the bit to 0,?" group.long 0x90++0x2F line.long 0x0 "WDT3_RTIDWDCTRL" hexmask.long 0x0 0.--31. 1. "DWDCTRL,DWDCTRL: Digital Watchdog Control.User and priviledge mode (read):0x5312ACED = DWD counter is disabled. This is the default value.0xA98559DA = DWD counter is enabledAny other value = DWD counter state is unchanged (enabled or disabled)Priviledge.." line.long 0x4 "WDT3_RTIDWDPRLD" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED17,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0x4 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value.User and priviledge mode (read):A read from this register in any CPU mode returns the current preload value.Priviledge mode (write):If the DWD is always enabled after reset is released:The DWD starts.." line.long 0x8 "WDT3_RTIWDSTATUS" hexmask.long 0x8 6.--31. 1. "RESERVED18,Reserved.Reads return 0 and writes have no effect" newline bitfld.long 0x8 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status.This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated or if a wrong key or key sequence was written to service the watchdog.User and priviledge mode (read):0 =.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status.This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag.User and priviledge.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was.." "0: leaves the current value unchanged,1: clears the bit to 0" newline bitfld.long 0x8 2. "KEYST,KEYST: Watchdog KeyStatus.This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register.User and priviledge mode (read):0 = no wrong key or key-sequence written1 = wrong key or key-sequence written to.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 1. "DWDST,DWDST: Digital Watchdog Status.This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons.User and priviledge mode (read):0 = DWD timeout period not expired1 = DWD timeout period has.." "0: leaves the current value unchanged1 = clears the..,?" newline bitfld.long 0x8 0. "AWDST,AWDST: Analog Watchdog Status.User and priviledge mode (read):0 = AWD pin 0 ?> 1 threshold not exceeded1 = AWD pin 0 ?> 1 threshold exceededPriviledge mode (write):0 = leaves the current value unchanged1 = clears the bit to 0" "0: leaves the current value unchanged1 = clears the..,?" line.long 0xC "WDT3_RTIWDKEY" hexmask.long.word 0xC 16.--31. 1. "RESERVED19,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.word 0xC 0.--15. 1. "WDKEY,WDKEY: Watchdog Key.User and privilege mode reads are indeterminate.Privilege mode (write):A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the.." line.long 0x10 "WDT3_RTIDWDCNTR" hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved.Reads return 0 and writes have no effect" newline hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter.The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz a watchdog reset will be.." line.long 0x14 "WDT3_RTIWWDRXNCTRL" hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x14 0.--3. 1. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction.User and privilege mode (read) privileged mode (write):0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the.." line.long 0x18 "WDT3_RTIWWDSIZECTRL" hexmask.long 0x18 0.--31. 1. "WWDSIZE,WWDSIZE: Digital Windowed Watchdog Window Size.User and privilege mode (read) privileged mode (write):Value written to WWDSIZE Window Size0x00000005 100% (Functionality same as the time-out digital.." line.long 0x1C "WDT3_RTIINTCLRENABLE" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED25,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 24.--27. 1. "INTCLRENABLE3,INTCLRENABLE3.Enables the auto-clear functionality on the compare 3 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 3 interrupt is disabled.Any other value = Auto-clear for compare 3 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 20.--23. 1. "RESERVED24,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 16.--19. 1. "INTCLRENABLE2,INTCLRENABLE2.Enables the auto-clear functionality on the compare 2 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 2 interrupt is disabled.Any other value = Auto-clear for compare 2 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 12.--15. 1. "RESERVED23,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 8.--11. 1. "INTCLRENABLE1,INTCLRENABLE1.Enables the auto-clear functionality on the compare 1 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 1 interrupt is disabled.Any other value = Auto-clear for compare 1 interrupt is enabled.Privileged.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED22,Reserved.Reads return 0 and writes have no effect" newline hexmask.long.byte 0x1C 0.--3. 1. "INTCLRENABLE0,INTCLRENABLE0.Enables the auto-clear functionality on the compare 0 interrupt.User and Privileged mode (read):0x5 = Auto-clear for compare 0 interrupt is disabled.Any other value = Auto-clear for compare 0 interrupt is enabled.Privileged.." line.long 0x20 "WDT3_RTICOMP0CLR" hexmask.long 0x20 0.--31. 1. "COMP0CLR,COMP0CLR: Compare 0 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the compare 0 interrupt or DMA request line is.." line.long 0x24 "WDT3_RTICOMP1CLR" hexmask.long 0x24 0.--31. 1. "COMP1CLR,COMP1CLR: Compare 1 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 1 interrupt or DMA request line is.." line.long 0x28 "WDT3_RTICOMP2CLR" hexmask.long 0x28 0.--31. 1. "COMP2CLR,COMP2CLR: Compare 2 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 2 interrupt or DMA request line is.." line.long 0x2C "WDT3_RTICOMP3CLR" hexmask.long 0x2C 0.--31. 1. "COMP3CLR,COMP3CLR: Compare 3 Clear.This registers holds a compare value which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value the Compare 3 interrupt or DMA request line is.." tree.end tree.end newline AUTOINDENT.OFF